1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_uapi.h> 19 #include <drm/drm_crtc.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_probe_helper.h> 24 #ifdef CONFIG_DRM_ANALOGIX_DP 25 #include <drm/bridge/analogix_dp.h> 26 #endif 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/platform_device.h> 31 #include <linux/clk.h> 32 #include <linux/iopoll.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/component.h> 37 #include <linux/overflow.h> 38 39 #include <linux/reset.h> 40 #include <linux/delay.h> 41 42 #include "rockchip_drm_drv.h" 43 #include "rockchip_drm_gem.h" 44 #include "rockchip_drm_fb.h" 45 #include "rockchip_drm_psr.h" 46 #include "rockchip_drm_vop.h" 47 #include "rockchip_rgb.h" 48 49 #define VOP_WIN_SET(vop, win, name, v) \ 50 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 51 #define VOP_SCL_SET(vop, win, name, v) \ 52 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 53 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 54 vop_reg_set(vop, &win->phy->scl->ext->name, \ 55 win->base, ~0, v, #name) 56 57 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 58 do { \ 59 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 60 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 61 } while (0) 62 63 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 64 do { \ 65 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 66 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 67 } while (0) 68 69 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 70 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 71 72 #define VOP_REG_SET(vop, group, name, v) \ 73 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 74 75 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 76 do { \ 77 int i, reg = 0, mask = 0; \ 78 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 79 if (vop->data->intr->intrs[i] & type) { \ 80 reg |= (v) << i; \ 81 mask |= 1 << i; \ 82 } \ 83 } \ 84 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 85 } while (0) 86 #define VOP_INTR_GET_TYPE(vop, name, type) \ 87 vop_get_intr_type(vop, &vop->data->intr->name, type) 88 89 #define VOP_WIN_GET(vop, win, name) \ 90 vop_read_reg(vop, win->offset, win->phy->name) 91 92 #define VOP_WIN_HAS_REG(win, name) \ 93 (!!(win->phy->name.mask)) 94 95 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 96 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 97 98 #define VOP_WIN_TO_INDEX(vop_win) \ 99 ((vop_win) - (vop_win)->vop->win) 100 101 #define to_vop(x) container_of(x, struct vop, crtc) 102 #define to_vop_win(x) container_of(x, struct vop_win, base) 103 104 /* 105 * The coefficients of the following matrix are all fixed points. 106 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 107 * They are all represented in two's complement. 108 */ 109 static const uint32_t bt601_yuv2rgb[] = { 110 0x4A8, 0x0, 0x662, 111 0x4A8, 0x1E6F, 0x1CBF, 112 0x4A8, 0x812, 0x0, 113 0x321168, 0x0877CF, 0x2EB127 114 }; 115 116 enum vop_pending { 117 VOP_PENDING_FB_UNREF, 118 }; 119 120 struct vop_win { 121 struct drm_plane base; 122 const struct vop_win_data *data; 123 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 124 struct vop *vop; 125 }; 126 127 struct rockchip_rgb; 128 struct vop { 129 struct drm_crtc crtc; 130 struct device *dev; 131 struct drm_device *drm_dev; 132 bool is_enabled; 133 134 struct completion dsp_hold_completion; 135 136 /* protected by dev->event_lock */ 137 struct drm_pending_vblank_event *event; 138 139 struct drm_flip_work fb_unref_work; 140 unsigned long pending; 141 142 struct completion line_flag_completion; 143 144 const struct vop_data *data; 145 146 uint32_t *regsbak; 147 void __iomem *regs; 148 149 /* physical map length of vop register */ 150 uint32_t len; 151 152 /* one time only one process allowed to config the register */ 153 spinlock_t reg_lock; 154 /* lock vop irq reg */ 155 spinlock_t irq_lock; 156 /* protects crtc enable/disable */ 157 struct mutex vop_lock; 158 159 unsigned int irq; 160 161 /* vop AHP clk */ 162 struct clk *hclk; 163 /* vop dclk */ 164 struct clk *dclk; 165 /* vop share memory frequency */ 166 struct clk *aclk; 167 168 /* vop dclk reset */ 169 struct reset_control *dclk_rst; 170 171 /* optional internal rgb encoder */ 172 struct rockchip_rgb *rgb; 173 174 struct vop_win win[]; 175 }; 176 177 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 178 { 179 writel(v, vop->regs + offset); 180 vop->regsbak[offset >> 2] = v; 181 } 182 183 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 184 { 185 return readl(vop->regs + offset); 186 } 187 188 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 189 const struct vop_reg *reg) 190 { 191 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 192 } 193 194 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 195 uint32_t _offset, uint32_t _mask, uint32_t v, 196 const char *reg_name) 197 { 198 int offset, mask, shift; 199 200 if (!reg || !reg->mask) { 201 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 202 return; 203 } 204 205 offset = reg->offset + _offset; 206 mask = reg->mask & _mask; 207 shift = reg->shift; 208 209 if (reg->write_mask) { 210 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 211 } else { 212 uint32_t cached_val = vop->regsbak[offset >> 2]; 213 214 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 215 vop->regsbak[offset >> 2] = v; 216 } 217 218 if (reg->relaxed) 219 writel_relaxed(v, vop->regs + offset); 220 else 221 writel(v, vop->regs + offset); 222 } 223 224 static inline uint32_t vop_get_intr_type(struct vop *vop, 225 const struct vop_reg *reg, int type) 226 { 227 uint32_t i, ret = 0; 228 uint32_t regs = vop_read_reg(vop, 0, reg); 229 230 for (i = 0; i < vop->data->intr->nintrs; i++) { 231 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 232 ret |= vop->data->intr->intrs[i]; 233 } 234 235 return ret; 236 } 237 238 static inline void vop_cfg_done(struct vop *vop) 239 { 240 VOP_REG_SET(vop, common, cfg_done, 1); 241 } 242 243 static bool has_rb_swapped(uint32_t format) 244 { 245 switch (format) { 246 case DRM_FORMAT_XBGR8888: 247 case DRM_FORMAT_ABGR8888: 248 case DRM_FORMAT_BGR888: 249 case DRM_FORMAT_BGR565: 250 return true; 251 default: 252 return false; 253 } 254 } 255 256 static enum vop_data_format vop_convert_format(uint32_t format) 257 { 258 switch (format) { 259 case DRM_FORMAT_XRGB8888: 260 case DRM_FORMAT_ARGB8888: 261 case DRM_FORMAT_XBGR8888: 262 case DRM_FORMAT_ABGR8888: 263 return VOP_FMT_ARGB8888; 264 case DRM_FORMAT_RGB888: 265 case DRM_FORMAT_BGR888: 266 return VOP_FMT_RGB888; 267 case DRM_FORMAT_RGB565: 268 case DRM_FORMAT_BGR565: 269 return VOP_FMT_RGB565; 270 case DRM_FORMAT_NV12: 271 return VOP_FMT_YUV420SP; 272 case DRM_FORMAT_NV16: 273 return VOP_FMT_YUV422SP; 274 case DRM_FORMAT_NV24: 275 return VOP_FMT_YUV444SP; 276 default: 277 DRM_ERROR("unsupported format[%08x]\n", format); 278 return -EINVAL; 279 } 280 } 281 282 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 283 uint32_t dst, bool is_horizontal, 284 int vsu_mode, int *vskiplines) 285 { 286 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 287 288 if (vskiplines) 289 *vskiplines = 0; 290 291 if (is_horizontal) { 292 if (mode == SCALE_UP) 293 val = GET_SCL_FT_BIC(src, dst); 294 else if (mode == SCALE_DOWN) 295 val = GET_SCL_FT_BILI_DN(src, dst); 296 } else { 297 if (mode == SCALE_UP) { 298 if (vsu_mode == SCALE_UP_BIL) 299 val = GET_SCL_FT_BILI_UP(src, dst); 300 else 301 val = GET_SCL_FT_BIC(src, dst); 302 } else if (mode == SCALE_DOWN) { 303 if (vskiplines) { 304 *vskiplines = scl_get_vskiplines(src, dst); 305 val = scl_get_bili_dn_vskip(src, dst, 306 *vskiplines); 307 } else { 308 val = GET_SCL_FT_BILI_DN(src, dst); 309 } 310 } 311 } 312 313 return val; 314 } 315 316 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 317 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 318 uint32_t dst_h, uint32_t pixel_format) 319 { 320 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 321 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 322 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 323 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 324 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 325 const struct drm_format_info *info; 326 bool is_yuv = false; 327 uint16_t cbcr_src_w = src_w / hsub; 328 uint16_t cbcr_src_h = src_h / vsub; 329 uint16_t vsu_mode; 330 uint16_t lb_mode; 331 uint32_t val; 332 int vskiplines; 333 334 info = drm_format_info(pixel_format); 335 336 if (info->is_yuv) 337 is_yuv = true; 338 339 if (dst_w > 3840) { 340 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 341 return; 342 } 343 344 if (!win->phy->scl->ext) { 345 VOP_SCL_SET(vop, win, scale_yrgb_x, 346 scl_cal_scale2(src_w, dst_w)); 347 VOP_SCL_SET(vop, win, scale_yrgb_y, 348 scl_cal_scale2(src_h, dst_h)); 349 if (is_yuv) { 350 VOP_SCL_SET(vop, win, scale_cbcr_x, 351 scl_cal_scale2(cbcr_src_w, dst_w)); 352 VOP_SCL_SET(vop, win, scale_cbcr_y, 353 scl_cal_scale2(cbcr_src_h, dst_h)); 354 } 355 return; 356 } 357 358 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 359 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 360 361 if (is_yuv) { 362 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 363 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 364 if (cbcr_hor_scl_mode == SCALE_DOWN) 365 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 366 else 367 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 368 } else { 369 if (yrgb_hor_scl_mode == SCALE_DOWN) 370 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 371 else 372 lb_mode = scl_vop_cal_lb_mode(src_w, false); 373 } 374 375 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 376 if (lb_mode == LB_RGB_3840X2) { 377 if (yrgb_ver_scl_mode != SCALE_NONE) { 378 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 379 return; 380 } 381 if (cbcr_ver_scl_mode != SCALE_NONE) { 382 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 383 return; 384 } 385 vsu_mode = SCALE_UP_BIL; 386 } else if (lb_mode == LB_RGB_2560X4) { 387 vsu_mode = SCALE_UP_BIL; 388 } else { 389 vsu_mode = SCALE_UP_BIC; 390 } 391 392 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 393 true, 0, NULL); 394 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 395 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 396 false, vsu_mode, &vskiplines); 397 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 398 399 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 400 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 401 402 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 403 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 404 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 405 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 406 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 407 if (is_yuv) { 408 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 409 dst_w, true, 0, NULL); 410 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 411 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 412 dst_h, false, vsu_mode, &vskiplines); 413 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 414 415 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 416 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 417 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 418 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 419 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 420 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 421 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 422 } 423 } 424 425 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 426 { 427 unsigned long flags; 428 429 if (WARN_ON(!vop->is_enabled)) 430 return; 431 432 spin_lock_irqsave(&vop->irq_lock, flags); 433 434 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 435 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 436 437 spin_unlock_irqrestore(&vop->irq_lock, flags); 438 } 439 440 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 441 { 442 unsigned long flags; 443 444 if (WARN_ON(!vop->is_enabled)) 445 return; 446 447 spin_lock_irqsave(&vop->irq_lock, flags); 448 449 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 450 451 spin_unlock_irqrestore(&vop->irq_lock, flags); 452 } 453 454 /* 455 * (1) each frame starts at the start of the Vsync pulse which is signaled by 456 * the "FRAME_SYNC" interrupt. 457 * (2) the active data region of each frame ends at dsp_vact_end 458 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 459 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 460 * 461 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 462 * Interrupts 463 * LINE_FLAG -------------------------------+ 464 * FRAME_SYNC ----+ | 465 * | | 466 * v v 467 * | Vsync | Vbp | Vactive | Vfp | 468 * ^ ^ ^ ^ 469 * | | | | 470 * | | | | 471 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 472 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 473 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 474 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 475 */ 476 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 477 { 478 uint32_t line_flag_irq; 479 unsigned long flags; 480 481 spin_lock_irqsave(&vop->irq_lock, flags); 482 483 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 484 485 spin_unlock_irqrestore(&vop->irq_lock, flags); 486 487 return !!line_flag_irq; 488 } 489 490 static void vop_line_flag_irq_enable(struct vop *vop) 491 { 492 unsigned long flags; 493 494 if (WARN_ON(!vop->is_enabled)) 495 return; 496 497 spin_lock_irqsave(&vop->irq_lock, flags); 498 499 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 500 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 501 502 spin_unlock_irqrestore(&vop->irq_lock, flags); 503 } 504 505 static void vop_line_flag_irq_disable(struct vop *vop) 506 { 507 unsigned long flags; 508 509 if (WARN_ON(!vop->is_enabled)) 510 return; 511 512 spin_lock_irqsave(&vop->irq_lock, flags); 513 514 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 515 516 spin_unlock_irqrestore(&vop->irq_lock, flags); 517 } 518 519 static int vop_core_clks_enable(struct vop *vop) 520 { 521 int ret; 522 523 ret = clk_enable(vop->hclk); 524 if (ret < 0) 525 return ret; 526 527 ret = clk_enable(vop->aclk); 528 if (ret < 0) 529 goto err_disable_hclk; 530 531 return 0; 532 533 err_disable_hclk: 534 clk_disable(vop->hclk); 535 return ret; 536 } 537 538 static void vop_core_clks_disable(struct vop *vop) 539 { 540 clk_disable(vop->aclk); 541 clk_disable(vop->hclk); 542 } 543 544 static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) 545 { 546 if (win->phy->scl && win->phy->scl->ext) { 547 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 548 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 549 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 550 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 551 } 552 553 VOP_WIN_SET(vop, win, enable, 0); 554 } 555 556 static int vop_enable(struct drm_crtc *crtc) 557 { 558 struct vop *vop = to_vop(crtc); 559 int ret, i; 560 561 ret = pm_runtime_get_sync(vop->dev); 562 if (ret < 0) { 563 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 564 return ret; 565 } 566 567 ret = vop_core_clks_enable(vop); 568 if (WARN_ON(ret < 0)) 569 goto err_put_pm_runtime; 570 571 ret = clk_enable(vop->dclk); 572 if (WARN_ON(ret < 0)) 573 goto err_disable_core; 574 575 /* 576 * Slave iommu shares power, irq and clock with vop. It was associated 577 * automatically with this master device via common driver code. 578 * Now that we have enabled the clock we attach it to the shared drm 579 * mapping. 580 */ 581 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 582 if (ret) { 583 DRM_DEV_ERROR(vop->dev, 584 "failed to attach dma mapping, %d\n", ret); 585 goto err_disable_dclk; 586 } 587 588 spin_lock(&vop->reg_lock); 589 for (i = 0; i < vop->len; i += 4) 590 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 591 592 /* 593 * We need to make sure that all windows are disabled before we 594 * enable the crtc. Otherwise we might try to scan from a destroyed 595 * buffer later. 596 */ 597 for (i = 0; i < vop->data->win_size; i++) { 598 struct vop_win *vop_win = &vop->win[i]; 599 const struct vop_win_data *win = vop_win->data; 600 601 vop_win_disable(vop, win); 602 } 603 spin_unlock(&vop->reg_lock); 604 605 vop_cfg_done(vop); 606 607 /* 608 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 609 */ 610 vop->is_enabled = true; 611 612 spin_lock(&vop->reg_lock); 613 614 VOP_REG_SET(vop, common, standby, 1); 615 616 spin_unlock(&vop->reg_lock); 617 618 drm_crtc_vblank_on(crtc); 619 620 return 0; 621 622 err_disable_dclk: 623 clk_disable(vop->dclk); 624 err_disable_core: 625 vop_core_clks_disable(vop); 626 err_put_pm_runtime: 627 pm_runtime_put_sync(vop->dev); 628 return ret; 629 } 630 631 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 632 struct drm_crtc_state *old_state) 633 { 634 struct vop *vop = to_vop(crtc); 635 636 WARN_ON(vop->event); 637 638 mutex_lock(&vop->vop_lock); 639 drm_crtc_vblank_off(crtc); 640 641 /* 642 * Vop standby will take effect at end of current frame, 643 * if dsp hold valid irq happen, it means standby complete. 644 * 645 * we must wait standby complete when we want to disable aclk, 646 * if not, memory bus maybe dead. 647 */ 648 reinit_completion(&vop->dsp_hold_completion); 649 vop_dsp_hold_valid_irq_enable(vop); 650 651 spin_lock(&vop->reg_lock); 652 653 VOP_REG_SET(vop, common, standby, 1); 654 655 spin_unlock(&vop->reg_lock); 656 657 wait_for_completion(&vop->dsp_hold_completion); 658 659 vop_dsp_hold_valid_irq_disable(vop); 660 661 vop->is_enabled = false; 662 663 /* 664 * vop standby complete, so iommu detach is safe. 665 */ 666 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 667 668 clk_disable(vop->dclk); 669 vop_core_clks_disable(vop); 670 pm_runtime_put(vop->dev); 671 mutex_unlock(&vop->vop_lock); 672 673 if (crtc->state->event && !crtc->state->active) { 674 spin_lock_irq(&crtc->dev->event_lock); 675 drm_crtc_send_vblank_event(crtc, crtc->state->event); 676 spin_unlock_irq(&crtc->dev->event_lock); 677 678 crtc->state->event = NULL; 679 } 680 } 681 682 static void vop_plane_destroy(struct drm_plane *plane) 683 { 684 drm_plane_cleanup(plane); 685 } 686 687 static int vop_plane_atomic_check(struct drm_plane *plane, 688 struct drm_plane_state *state) 689 { 690 struct drm_crtc *crtc = state->crtc; 691 struct drm_crtc_state *crtc_state; 692 struct drm_framebuffer *fb = state->fb; 693 struct vop_win *vop_win = to_vop_win(plane); 694 const struct vop_win_data *win = vop_win->data; 695 int ret; 696 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 697 DRM_PLANE_HELPER_NO_SCALING; 698 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 699 DRM_PLANE_HELPER_NO_SCALING; 700 701 if (!crtc || !fb) 702 return 0; 703 704 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 705 if (WARN_ON(!crtc_state)) 706 return -EINVAL; 707 708 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 709 min_scale, max_scale, 710 true, true); 711 if (ret) 712 return ret; 713 714 if (!state->visible) 715 return 0; 716 717 ret = vop_convert_format(fb->format->format); 718 if (ret < 0) 719 return ret; 720 721 /* 722 * Src.x1 can be odd when do clip, but yuv plane start point 723 * need align with 2 pixel. 724 */ 725 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 726 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 727 return -EINVAL; 728 } 729 730 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 731 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 732 return -EINVAL; 733 } 734 735 return 0; 736 } 737 738 static void vop_plane_atomic_disable(struct drm_plane *plane, 739 struct drm_plane_state *old_state) 740 { 741 struct vop_win *vop_win = to_vop_win(plane); 742 const struct vop_win_data *win = vop_win->data; 743 struct vop *vop = to_vop(old_state->crtc); 744 745 if (!old_state->crtc) 746 return; 747 748 spin_lock(&vop->reg_lock); 749 750 vop_win_disable(vop, win); 751 752 spin_unlock(&vop->reg_lock); 753 } 754 755 static void vop_plane_atomic_update(struct drm_plane *plane, 756 struct drm_plane_state *old_state) 757 { 758 struct drm_plane_state *state = plane->state; 759 struct drm_crtc *crtc = state->crtc; 760 struct vop_win *vop_win = to_vop_win(plane); 761 const struct vop_win_data *win = vop_win->data; 762 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 763 struct vop *vop = to_vop(state->crtc); 764 struct drm_framebuffer *fb = state->fb; 765 unsigned int actual_w, actual_h; 766 unsigned int dsp_stx, dsp_sty; 767 uint32_t act_info, dsp_info, dsp_st; 768 struct drm_rect *src = &state->src; 769 struct drm_rect *dest = &state->dst; 770 struct drm_gem_object *obj, *uv_obj; 771 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 772 unsigned long offset; 773 dma_addr_t dma_addr; 774 uint32_t val; 775 bool rb_swap; 776 int win_index = VOP_WIN_TO_INDEX(vop_win); 777 int format; 778 int is_yuv = fb->format->is_yuv; 779 int i; 780 781 /* 782 * can't update plane when vop is disabled. 783 */ 784 if (WARN_ON(!crtc)) 785 return; 786 787 if (WARN_ON(!vop->is_enabled)) 788 return; 789 790 if (!state->visible) { 791 vop_plane_atomic_disable(plane, old_state); 792 return; 793 } 794 795 obj = fb->obj[0]; 796 rk_obj = to_rockchip_obj(obj); 797 798 actual_w = drm_rect_width(src) >> 16; 799 actual_h = drm_rect_height(src) >> 16; 800 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 801 802 dsp_info = (drm_rect_height(dest) - 1) << 16; 803 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 804 805 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 806 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 807 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 808 809 offset = (src->x1 >> 16) * fb->format->cpp[0]; 810 offset += (src->y1 >> 16) * fb->pitches[0]; 811 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 812 813 /* 814 * For y-mirroring we need to move address 815 * to the beginning of the last line. 816 */ 817 if (state->rotation & DRM_MODE_REFLECT_Y) 818 dma_addr += (actual_h - 1) * fb->pitches[0]; 819 820 format = vop_convert_format(fb->format->format); 821 822 spin_lock(&vop->reg_lock); 823 824 VOP_WIN_SET(vop, win, format, format); 825 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 826 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 827 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 828 VOP_WIN_SET(vop, win, y_mir_en, 829 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 830 VOP_WIN_SET(vop, win, x_mir_en, 831 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 832 833 if (is_yuv) { 834 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 835 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 836 int bpp = fb->format->cpp[1]; 837 838 uv_obj = fb->obj[1]; 839 rk_uv_obj = to_rockchip_obj(uv_obj); 840 841 offset = (src->x1 >> 16) * bpp / hsub; 842 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 843 844 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 845 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 846 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 847 848 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 849 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 850 win_yuv2yuv, 851 y2r_coefficients[i], 852 bt601_yuv2rgb[i]); 853 } 854 } 855 856 if (win->phy->scl) 857 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 858 drm_rect_width(dest), drm_rect_height(dest), 859 fb->format->format); 860 861 VOP_WIN_SET(vop, win, act_info, act_info); 862 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 863 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 864 865 rb_swap = has_rb_swapped(fb->format->format); 866 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 867 868 /* 869 * Blending win0 with the background color doesn't seem to work 870 * correctly. We only get the background color, no matter the contents 871 * of the win0 framebuffer. However, blending pre-multiplied color 872 * with the default opaque black default background color is a no-op, 873 * so we can just disable blending to get the correct result. 874 */ 875 if (fb->format->has_alpha && win_index > 0) { 876 VOP_WIN_SET(vop, win, dst_alpha_ctl, 877 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 878 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 879 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 880 SRC_BLEND_M0(ALPHA_PER_PIX) | 881 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 882 SRC_FACTOR_M0(ALPHA_ONE); 883 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 884 } else { 885 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 886 } 887 888 VOP_WIN_SET(vop, win, enable, 1); 889 spin_unlock(&vop->reg_lock); 890 } 891 892 static int vop_plane_atomic_async_check(struct drm_plane *plane, 893 struct drm_plane_state *state) 894 { 895 struct vop_win *vop_win = to_vop_win(plane); 896 const struct vop_win_data *win = vop_win->data; 897 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 898 DRM_PLANE_HELPER_NO_SCALING; 899 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 900 DRM_PLANE_HELPER_NO_SCALING; 901 struct drm_crtc_state *crtc_state; 902 903 if (plane != state->crtc->cursor) 904 return -EINVAL; 905 906 if (!plane->state) 907 return -EINVAL; 908 909 if (!plane->state->fb) 910 return -EINVAL; 911 912 if (state->state) 913 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 914 state->crtc); 915 else /* Special case for asynchronous cursor updates. */ 916 crtc_state = plane->crtc->state; 917 918 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 919 min_scale, max_scale, 920 true, true); 921 } 922 923 static void vop_plane_atomic_async_update(struct drm_plane *plane, 924 struct drm_plane_state *new_state) 925 { 926 struct vop *vop = to_vop(plane->state->crtc); 927 struct drm_plane_state *plane_state; 928 929 plane_state = plane->funcs->atomic_duplicate_state(plane); 930 plane_state->crtc_x = new_state->crtc_x; 931 plane_state->crtc_y = new_state->crtc_y; 932 plane_state->crtc_h = new_state->crtc_h; 933 plane_state->crtc_w = new_state->crtc_w; 934 plane_state->src_x = new_state->src_x; 935 plane_state->src_y = new_state->src_y; 936 plane_state->src_h = new_state->src_h; 937 plane_state->src_w = new_state->src_w; 938 939 if (plane_state->fb != new_state->fb) 940 drm_atomic_set_fb_for_plane(plane_state, new_state->fb); 941 942 swap(plane_state, plane->state); 943 944 if (plane->state->fb && plane->state->fb != new_state->fb) { 945 drm_framebuffer_get(plane->state->fb); 946 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 947 drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb); 948 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 949 } 950 951 if (vop->is_enabled) { 952 rockchip_drm_psr_inhibit_get_state(new_state->state); 953 vop_plane_atomic_update(plane, plane->state); 954 spin_lock(&vop->reg_lock); 955 vop_cfg_done(vop); 956 spin_unlock(&vop->reg_lock); 957 rockchip_drm_psr_inhibit_put_state(new_state->state); 958 } 959 960 plane->funcs->atomic_destroy_state(plane, plane_state); 961 } 962 963 static const struct drm_plane_helper_funcs plane_helper_funcs = { 964 .atomic_check = vop_plane_atomic_check, 965 .atomic_update = vop_plane_atomic_update, 966 .atomic_disable = vop_plane_atomic_disable, 967 .atomic_async_check = vop_plane_atomic_async_check, 968 .atomic_async_update = vop_plane_atomic_async_update, 969 .prepare_fb = drm_gem_fb_prepare_fb, 970 }; 971 972 static const struct drm_plane_funcs vop_plane_funcs = { 973 .update_plane = drm_atomic_helper_update_plane, 974 .disable_plane = drm_atomic_helper_disable_plane, 975 .destroy = vop_plane_destroy, 976 .reset = drm_atomic_helper_plane_reset, 977 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 978 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 979 }; 980 981 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 982 { 983 struct vop *vop = to_vop(crtc); 984 unsigned long flags; 985 986 if (WARN_ON(!vop->is_enabled)) 987 return -EPERM; 988 989 spin_lock_irqsave(&vop->irq_lock, flags); 990 991 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 992 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 993 994 spin_unlock_irqrestore(&vop->irq_lock, flags); 995 996 return 0; 997 } 998 999 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1000 { 1001 struct vop *vop = to_vop(crtc); 1002 unsigned long flags; 1003 1004 if (WARN_ON(!vop->is_enabled)) 1005 return; 1006 1007 spin_lock_irqsave(&vop->irq_lock, flags); 1008 1009 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1010 1011 spin_unlock_irqrestore(&vop->irq_lock, flags); 1012 } 1013 1014 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1015 const struct drm_display_mode *mode, 1016 struct drm_display_mode *adjusted_mode) 1017 { 1018 struct vop *vop = to_vop(crtc); 1019 1020 adjusted_mode->clock = 1021 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 1022 1023 return true; 1024 } 1025 1026 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1027 struct drm_crtc_state *old_state) 1028 { 1029 struct vop *vop = to_vop(crtc); 1030 const struct vop_data *vop_data = vop->data; 1031 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1032 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1033 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1034 u16 hdisplay = adjusted_mode->hdisplay; 1035 u16 htotal = adjusted_mode->htotal; 1036 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1037 u16 hact_end = hact_st + hdisplay; 1038 u16 vdisplay = adjusted_mode->vdisplay; 1039 u16 vtotal = adjusted_mode->vtotal; 1040 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1041 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1042 u16 vact_end = vact_st + vdisplay; 1043 uint32_t pin_pol, val; 1044 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1045 int ret; 1046 1047 mutex_lock(&vop->vop_lock); 1048 1049 WARN_ON(vop->event); 1050 1051 ret = vop_enable(crtc); 1052 if (ret) { 1053 mutex_unlock(&vop->vop_lock); 1054 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1055 return; 1056 } 1057 1058 pin_pol = BIT(DCLK_INVERT); 1059 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1060 BIT(HSYNC_POSITIVE) : 0; 1061 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1062 BIT(VSYNC_POSITIVE) : 0; 1063 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1064 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1065 1066 switch (s->output_type) { 1067 case DRM_MODE_CONNECTOR_LVDS: 1068 VOP_REG_SET(vop, output, rgb_en, 1); 1069 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1070 break; 1071 case DRM_MODE_CONNECTOR_eDP: 1072 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1073 VOP_REG_SET(vop, output, edp_en, 1); 1074 break; 1075 case DRM_MODE_CONNECTOR_HDMIA: 1076 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1077 VOP_REG_SET(vop, output, hdmi_en, 1); 1078 break; 1079 case DRM_MODE_CONNECTOR_DSI: 1080 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1081 VOP_REG_SET(vop, output, mipi_en, 1); 1082 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1083 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1084 break; 1085 case DRM_MODE_CONNECTOR_DisplayPort: 1086 pin_pol &= ~BIT(DCLK_INVERT); 1087 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1088 VOP_REG_SET(vop, output, dp_en, 1); 1089 break; 1090 default: 1091 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1092 s->output_type); 1093 } 1094 1095 /* 1096 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1097 */ 1098 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1099 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1100 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1101 1102 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1103 VOP_REG_SET(vop, common, pre_dither_down, 1); 1104 else 1105 VOP_REG_SET(vop, common, pre_dither_down, 0); 1106 1107 if (dither_bpc == 6) { 1108 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1109 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1110 VOP_REG_SET(vop, common, dither_down_en, 1); 1111 } else { 1112 VOP_REG_SET(vop, common, dither_down_en, 0); 1113 } 1114 1115 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1116 1117 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1118 val = hact_st << 16; 1119 val |= hact_end; 1120 VOP_REG_SET(vop, modeset, hact_st_end, val); 1121 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1122 1123 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1124 val = vact_st << 16; 1125 val |= vact_end; 1126 VOP_REG_SET(vop, modeset, vact_st_end, val); 1127 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1128 1129 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1130 1131 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1132 1133 VOP_REG_SET(vop, common, standby, 0); 1134 mutex_unlock(&vop->vop_lock); 1135 } 1136 1137 static bool vop_fs_irq_is_pending(struct vop *vop) 1138 { 1139 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1140 } 1141 1142 static void vop_wait_for_irq_handler(struct vop *vop) 1143 { 1144 bool pending; 1145 int ret; 1146 1147 /* 1148 * Spin until frame start interrupt status bit goes low, which means 1149 * that interrupt handler was invoked and cleared it. The timeout of 1150 * 10 msecs is really too long, but it is just a safety measure if 1151 * something goes really wrong. The wait will only happen in the very 1152 * unlikely case of a vblank happening exactly at the same time and 1153 * shouldn't exceed microseconds range. 1154 */ 1155 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1156 !pending, 0, 10 * 1000); 1157 if (ret) 1158 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1159 1160 synchronize_irq(vop->irq); 1161 } 1162 1163 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1164 struct drm_crtc_state *old_crtc_state) 1165 { 1166 struct drm_atomic_state *old_state = old_crtc_state->state; 1167 struct drm_plane_state *old_plane_state, *new_plane_state; 1168 struct vop *vop = to_vop(crtc); 1169 struct drm_plane *plane; 1170 int i; 1171 1172 if (WARN_ON(!vop->is_enabled)) 1173 return; 1174 1175 spin_lock(&vop->reg_lock); 1176 1177 vop_cfg_done(vop); 1178 1179 spin_unlock(&vop->reg_lock); 1180 1181 /* 1182 * There is a (rather unlikely) possiblity that a vblank interrupt 1183 * fired before we set the cfg_done bit. To avoid spuriously 1184 * signalling flip completion we need to wait for it to finish. 1185 */ 1186 vop_wait_for_irq_handler(vop); 1187 1188 spin_lock_irq(&crtc->dev->event_lock); 1189 if (crtc->state->event) { 1190 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1191 WARN_ON(vop->event); 1192 1193 vop->event = crtc->state->event; 1194 crtc->state->event = NULL; 1195 } 1196 spin_unlock_irq(&crtc->dev->event_lock); 1197 1198 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1199 new_plane_state, i) { 1200 if (!old_plane_state->fb) 1201 continue; 1202 1203 if (old_plane_state->fb == new_plane_state->fb) 1204 continue; 1205 1206 drm_framebuffer_get(old_plane_state->fb); 1207 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1208 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1209 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1210 } 1211 } 1212 1213 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1214 .mode_fixup = vop_crtc_mode_fixup, 1215 .atomic_flush = vop_crtc_atomic_flush, 1216 .atomic_enable = vop_crtc_atomic_enable, 1217 .atomic_disable = vop_crtc_atomic_disable, 1218 }; 1219 1220 static void vop_crtc_destroy(struct drm_crtc *crtc) 1221 { 1222 drm_crtc_cleanup(crtc); 1223 } 1224 1225 static void vop_crtc_reset(struct drm_crtc *crtc) 1226 { 1227 if (crtc->state) 1228 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1229 kfree(crtc->state); 1230 1231 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1232 if (crtc->state) 1233 crtc->state->crtc = crtc; 1234 } 1235 1236 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1237 { 1238 struct rockchip_crtc_state *rockchip_state; 1239 1240 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1241 if (!rockchip_state) 1242 return NULL; 1243 1244 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1245 return &rockchip_state->base; 1246 } 1247 1248 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1249 struct drm_crtc_state *state) 1250 { 1251 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1252 1253 __drm_atomic_helper_crtc_destroy_state(&s->base); 1254 kfree(s); 1255 } 1256 1257 #ifdef CONFIG_DRM_ANALOGIX_DP 1258 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1259 { 1260 struct drm_connector *connector; 1261 struct drm_connector_list_iter conn_iter; 1262 1263 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1264 drm_for_each_connector_iter(connector, &conn_iter) { 1265 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1266 drm_connector_list_iter_end(&conn_iter); 1267 return connector; 1268 } 1269 } 1270 drm_connector_list_iter_end(&conn_iter); 1271 1272 return NULL; 1273 } 1274 1275 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1276 const char *source_name) 1277 { 1278 struct vop *vop = to_vop(crtc); 1279 struct drm_connector *connector; 1280 int ret; 1281 1282 connector = vop_get_edp_connector(vop); 1283 if (!connector) 1284 return -EINVAL; 1285 1286 if (source_name && strcmp(source_name, "auto") == 0) 1287 ret = analogix_dp_start_crc(connector); 1288 else if (!source_name) 1289 ret = analogix_dp_stop_crc(connector); 1290 else 1291 ret = -EINVAL; 1292 1293 return ret; 1294 } 1295 1296 static int 1297 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1298 size_t *values_cnt) 1299 { 1300 if (source_name && strcmp(source_name, "auto") != 0) 1301 return -EINVAL; 1302 1303 *values_cnt = 3; 1304 return 0; 1305 } 1306 1307 #else 1308 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1309 const char *source_name) 1310 { 1311 return -ENODEV; 1312 } 1313 1314 static int 1315 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1316 size_t *values_cnt) 1317 { 1318 return -ENODEV; 1319 } 1320 #endif 1321 1322 static const struct drm_crtc_funcs vop_crtc_funcs = { 1323 .set_config = drm_atomic_helper_set_config, 1324 .page_flip = drm_atomic_helper_page_flip, 1325 .destroy = vop_crtc_destroy, 1326 .reset = vop_crtc_reset, 1327 .atomic_duplicate_state = vop_crtc_duplicate_state, 1328 .atomic_destroy_state = vop_crtc_destroy_state, 1329 .enable_vblank = vop_crtc_enable_vblank, 1330 .disable_vblank = vop_crtc_disable_vblank, 1331 .set_crc_source = vop_crtc_set_crc_source, 1332 .verify_crc_source = vop_crtc_verify_crc_source, 1333 }; 1334 1335 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1336 { 1337 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1338 struct drm_framebuffer *fb = val; 1339 1340 drm_crtc_vblank_put(&vop->crtc); 1341 drm_framebuffer_put(fb); 1342 } 1343 1344 static void vop_handle_vblank(struct vop *vop) 1345 { 1346 struct drm_device *drm = vop->drm_dev; 1347 struct drm_crtc *crtc = &vop->crtc; 1348 1349 spin_lock(&drm->event_lock); 1350 if (vop->event) { 1351 drm_crtc_send_vblank_event(crtc, vop->event); 1352 drm_crtc_vblank_put(crtc); 1353 vop->event = NULL; 1354 } 1355 spin_unlock(&drm->event_lock); 1356 1357 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1358 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1359 } 1360 1361 static irqreturn_t vop_isr(int irq, void *data) 1362 { 1363 struct vop *vop = data; 1364 struct drm_crtc *crtc = &vop->crtc; 1365 uint32_t active_irqs; 1366 int ret = IRQ_NONE; 1367 1368 /* 1369 * The irq is shared with the iommu. If the runtime-pm state of the 1370 * vop-device is disabled the irq has to be targeted at the iommu. 1371 */ 1372 if (!pm_runtime_get_if_in_use(vop->dev)) 1373 return IRQ_NONE; 1374 1375 if (vop_core_clks_enable(vop)) { 1376 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1377 goto out; 1378 } 1379 1380 /* 1381 * interrupt register has interrupt status, enable and clear bits, we 1382 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1383 */ 1384 spin_lock(&vop->irq_lock); 1385 1386 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1387 /* Clear all active interrupt sources */ 1388 if (active_irqs) 1389 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1390 1391 spin_unlock(&vop->irq_lock); 1392 1393 /* This is expected for vop iommu irqs, since the irq is shared */ 1394 if (!active_irqs) 1395 goto out_disable; 1396 1397 if (active_irqs & DSP_HOLD_VALID_INTR) { 1398 complete(&vop->dsp_hold_completion); 1399 active_irqs &= ~DSP_HOLD_VALID_INTR; 1400 ret = IRQ_HANDLED; 1401 } 1402 1403 if (active_irqs & LINE_FLAG_INTR) { 1404 complete(&vop->line_flag_completion); 1405 active_irqs &= ~LINE_FLAG_INTR; 1406 ret = IRQ_HANDLED; 1407 } 1408 1409 if (active_irqs & FS_INTR) { 1410 drm_crtc_handle_vblank(crtc); 1411 vop_handle_vblank(vop); 1412 active_irqs &= ~FS_INTR; 1413 ret = IRQ_HANDLED; 1414 } 1415 1416 /* Unhandled irqs are spurious. */ 1417 if (active_irqs) 1418 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1419 active_irqs); 1420 1421 out_disable: 1422 vop_core_clks_disable(vop); 1423 out: 1424 pm_runtime_put(vop->dev); 1425 return ret; 1426 } 1427 1428 static void vop_plane_add_properties(struct drm_plane *plane, 1429 const struct vop_win_data *win_data) 1430 { 1431 unsigned int flags = 0; 1432 1433 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1434 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1435 if (flags) 1436 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1437 DRM_MODE_ROTATE_0 | flags); 1438 } 1439 1440 static int vop_create_crtc(struct vop *vop) 1441 { 1442 const struct vop_data *vop_data = vop->data; 1443 struct device *dev = vop->dev; 1444 struct drm_device *drm_dev = vop->drm_dev; 1445 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1446 struct drm_crtc *crtc = &vop->crtc; 1447 struct device_node *port; 1448 int ret; 1449 int i; 1450 1451 /* 1452 * Create drm_plane for primary and cursor planes first, since we need 1453 * to pass them to drm_crtc_init_with_planes, which sets the 1454 * "possible_crtcs" to the newly initialized crtc. 1455 */ 1456 for (i = 0; i < vop_data->win_size; i++) { 1457 struct vop_win *vop_win = &vop->win[i]; 1458 const struct vop_win_data *win_data = vop_win->data; 1459 1460 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1461 win_data->type != DRM_PLANE_TYPE_CURSOR) 1462 continue; 1463 1464 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1465 0, &vop_plane_funcs, 1466 win_data->phy->data_formats, 1467 win_data->phy->nformats, 1468 NULL, win_data->type, NULL); 1469 if (ret) { 1470 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1471 ret); 1472 goto err_cleanup_planes; 1473 } 1474 1475 plane = &vop_win->base; 1476 drm_plane_helper_add(plane, &plane_helper_funcs); 1477 vop_plane_add_properties(plane, win_data); 1478 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1479 primary = plane; 1480 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1481 cursor = plane; 1482 } 1483 1484 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1485 &vop_crtc_funcs, NULL); 1486 if (ret) 1487 goto err_cleanup_planes; 1488 1489 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1490 1491 /* 1492 * Create drm_planes for overlay windows with possible_crtcs restricted 1493 * to the newly created crtc. 1494 */ 1495 for (i = 0; i < vop_data->win_size; i++) { 1496 struct vop_win *vop_win = &vop->win[i]; 1497 const struct vop_win_data *win_data = vop_win->data; 1498 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1499 1500 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1501 continue; 1502 1503 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1504 possible_crtcs, 1505 &vop_plane_funcs, 1506 win_data->phy->data_formats, 1507 win_data->phy->nformats, 1508 NULL, win_data->type, NULL); 1509 if (ret) { 1510 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1511 ret); 1512 goto err_cleanup_crtc; 1513 } 1514 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1515 vop_plane_add_properties(&vop_win->base, win_data); 1516 } 1517 1518 port = of_get_child_by_name(dev->of_node, "port"); 1519 if (!port) { 1520 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1521 dev->of_node); 1522 ret = -ENOENT; 1523 goto err_cleanup_crtc; 1524 } 1525 1526 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1527 vop_fb_unref_worker); 1528 1529 init_completion(&vop->dsp_hold_completion); 1530 init_completion(&vop->line_flag_completion); 1531 crtc->port = port; 1532 1533 return 0; 1534 1535 err_cleanup_crtc: 1536 drm_crtc_cleanup(crtc); 1537 err_cleanup_planes: 1538 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1539 head) 1540 drm_plane_cleanup(plane); 1541 return ret; 1542 } 1543 1544 static void vop_destroy_crtc(struct vop *vop) 1545 { 1546 struct drm_crtc *crtc = &vop->crtc; 1547 struct drm_device *drm_dev = vop->drm_dev; 1548 struct drm_plane *plane, *tmp; 1549 1550 of_node_put(crtc->port); 1551 1552 /* 1553 * We need to cleanup the planes now. Why? 1554 * 1555 * The planes are "&vop->win[i].base". That means the memory is 1556 * all part of the big "struct vop" chunk of memory. That memory 1557 * was devm allocated and associated with this component. We need to 1558 * free it ourselves before vop_unbind() finishes. 1559 */ 1560 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1561 head) 1562 vop_plane_destroy(plane); 1563 1564 /* 1565 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1566 * references the CRTC. 1567 */ 1568 drm_crtc_cleanup(crtc); 1569 drm_flip_work_cleanup(&vop->fb_unref_work); 1570 } 1571 1572 static int vop_initial(struct vop *vop) 1573 { 1574 const struct vop_data *vop_data = vop->data; 1575 struct reset_control *ahb_rst; 1576 int i, ret; 1577 1578 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1579 if (IS_ERR(vop->hclk)) { 1580 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1581 return PTR_ERR(vop->hclk); 1582 } 1583 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1584 if (IS_ERR(vop->aclk)) { 1585 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1586 return PTR_ERR(vop->aclk); 1587 } 1588 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1589 if (IS_ERR(vop->dclk)) { 1590 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1591 return PTR_ERR(vop->dclk); 1592 } 1593 1594 ret = pm_runtime_get_sync(vop->dev); 1595 if (ret < 0) { 1596 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1597 return ret; 1598 } 1599 1600 ret = clk_prepare(vop->dclk); 1601 if (ret < 0) { 1602 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1603 goto err_put_pm_runtime; 1604 } 1605 1606 /* Enable both the hclk and aclk to setup the vop */ 1607 ret = clk_prepare_enable(vop->hclk); 1608 if (ret < 0) { 1609 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1610 goto err_unprepare_dclk; 1611 } 1612 1613 ret = clk_prepare_enable(vop->aclk); 1614 if (ret < 0) { 1615 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1616 goto err_disable_hclk; 1617 } 1618 1619 /* 1620 * do hclk_reset, reset all vop registers. 1621 */ 1622 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1623 if (IS_ERR(ahb_rst)) { 1624 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1625 ret = PTR_ERR(ahb_rst); 1626 goto err_disable_aclk; 1627 } 1628 reset_control_assert(ahb_rst); 1629 usleep_range(10, 20); 1630 reset_control_deassert(ahb_rst); 1631 1632 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1633 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1634 1635 for (i = 0; i < vop->len; i += sizeof(u32)) 1636 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1637 1638 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1639 VOP_REG_SET(vop, common, dsp_blank, 0); 1640 1641 for (i = 0; i < vop_data->win_size; i++) { 1642 const struct vop_win_data *win = &vop_data->win[i]; 1643 int channel = i * 2 + 1; 1644 1645 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1646 vop_win_disable(vop, win); 1647 VOP_WIN_SET(vop, win, gate, 1); 1648 } 1649 1650 vop_cfg_done(vop); 1651 1652 /* 1653 * do dclk_reset, let all config take affect. 1654 */ 1655 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1656 if (IS_ERR(vop->dclk_rst)) { 1657 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1658 ret = PTR_ERR(vop->dclk_rst); 1659 goto err_disable_aclk; 1660 } 1661 reset_control_assert(vop->dclk_rst); 1662 usleep_range(10, 20); 1663 reset_control_deassert(vop->dclk_rst); 1664 1665 clk_disable(vop->hclk); 1666 clk_disable(vop->aclk); 1667 1668 vop->is_enabled = false; 1669 1670 pm_runtime_put_sync(vop->dev); 1671 1672 return 0; 1673 1674 err_disable_aclk: 1675 clk_disable_unprepare(vop->aclk); 1676 err_disable_hclk: 1677 clk_disable_unprepare(vop->hclk); 1678 err_unprepare_dclk: 1679 clk_unprepare(vop->dclk); 1680 err_put_pm_runtime: 1681 pm_runtime_put_sync(vop->dev); 1682 return ret; 1683 } 1684 1685 /* 1686 * Initialize the vop->win array elements. 1687 */ 1688 static void vop_win_init(struct vop *vop) 1689 { 1690 const struct vop_data *vop_data = vop->data; 1691 unsigned int i; 1692 1693 for (i = 0; i < vop_data->win_size; i++) { 1694 struct vop_win *vop_win = &vop->win[i]; 1695 const struct vop_win_data *win_data = &vop_data->win[i]; 1696 1697 vop_win->data = win_data; 1698 vop_win->vop = vop; 1699 1700 if (vop_data->win_yuv2yuv) 1701 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 1702 } 1703 } 1704 1705 /** 1706 * rockchip_drm_wait_vact_end 1707 * @crtc: CRTC to enable line flag 1708 * @mstimeout: millisecond for timeout 1709 * 1710 * Wait for vact_end line flag irq or timeout. 1711 * 1712 * Returns: 1713 * Zero on success, negative errno on failure. 1714 */ 1715 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1716 { 1717 struct vop *vop = to_vop(crtc); 1718 unsigned long jiffies_left; 1719 int ret = 0; 1720 1721 if (!crtc || !vop->is_enabled) 1722 return -ENODEV; 1723 1724 mutex_lock(&vop->vop_lock); 1725 if (mstimeout <= 0) { 1726 ret = -EINVAL; 1727 goto out; 1728 } 1729 1730 if (vop_line_flag_irq_is_enabled(vop)) { 1731 ret = -EBUSY; 1732 goto out; 1733 } 1734 1735 reinit_completion(&vop->line_flag_completion); 1736 vop_line_flag_irq_enable(vop); 1737 1738 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1739 msecs_to_jiffies(mstimeout)); 1740 vop_line_flag_irq_disable(vop); 1741 1742 if (jiffies_left == 0) { 1743 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1744 ret = -ETIMEDOUT; 1745 goto out; 1746 } 1747 1748 out: 1749 mutex_unlock(&vop->vop_lock); 1750 return ret; 1751 } 1752 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1753 1754 static int vop_bind(struct device *dev, struct device *master, void *data) 1755 { 1756 struct platform_device *pdev = to_platform_device(dev); 1757 const struct vop_data *vop_data; 1758 struct drm_device *drm_dev = data; 1759 struct vop *vop; 1760 struct resource *res; 1761 int ret, irq; 1762 1763 vop_data = of_device_get_match_data(dev); 1764 if (!vop_data) 1765 return -ENODEV; 1766 1767 /* Allocate vop struct and its vop_win array */ 1768 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 1769 GFP_KERNEL); 1770 if (!vop) 1771 return -ENOMEM; 1772 1773 vop->dev = dev; 1774 vop->data = vop_data; 1775 vop->drm_dev = drm_dev; 1776 dev_set_drvdata(dev, vop); 1777 1778 vop_win_init(vop); 1779 1780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1781 vop->len = resource_size(res); 1782 vop->regs = devm_ioremap_resource(dev, res); 1783 if (IS_ERR(vop->regs)) 1784 return PTR_ERR(vop->regs); 1785 1786 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1787 if (!vop->regsbak) 1788 return -ENOMEM; 1789 1790 irq = platform_get_irq(pdev, 0); 1791 if (irq < 0) { 1792 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1793 return irq; 1794 } 1795 vop->irq = (unsigned int)irq; 1796 1797 spin_lock_init(&vop->reg_lock); 1798 spin_lock_init(&vop->irq_lock); 1799 mutex_init(&vop->vop_lock); 1800 1801 ret = vop_create_crtc(vop); 1802 if (ret) 1803 return ret; 1804 1805 pm_runtime_enable(&pdev->dev); 1806 1807 ret = vop_initial(vop); 1808 if (ret < 0) { 1809 DRM_DEV_ERROR(&pdev->dev, 1810 "cannot initial vop dev - err %d\n", ret); 1811 goto err_disable_pm_runtime; 1812 } 1813 1814 ret = devm_request_irq(dev, vop->irq, vop_isr, 1815 IRQF_SHARED, dev_name(dev), vop); 1816 if (ret) 1817 goto err_disable_pm_runtime; 1818 1819 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 1820 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 1821 if (IS_ERR(vop->rgb)) { 1822 ret = PTR_ERR(vop->rgb); 1823 goto err_disable_pm_runtime; 1824 } 1825 } 1826 1827 return 0; 1828 1829 err_disable_pm_runtime: 1830 pm_runtime_disable(&pdev->dev); 1831 vop_destroy_crtc(vop); 1832 return ret; 1833 } 1834 1835 static void vop_unbind(struct device *dev, struct device *master, void *data) 1836 { 1837 struct vop *vop = dev_get_drvdata(dev); 1838 1839 if (vop->rgb) 1840 rockchip_rgb_fini(vop->rgb); 1841 1842 pm_runtime_disable(dev); 1843 vop_destroy_crtc(vop); 1844 1845 clk_unprepare(vop->aclk); 1846 clk_unprepare(vop->hclk); 1847 clk_unprepare(vop->dclk); 1848 } 1849 1850 const struct component_ops vop_component_ops = { 1851 .bind = vop_bind, 1852 .unbind = vop_unbind, 1853 }; 1854 EXPORT_SYMBOL_GPL(vop_component_ops); 1855