1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4  * Author:Mark Yao <mark.yao@rock-chips.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/log2.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/overflow.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19 
20 #include <drm/drm.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_uapi.h>
23 #include <drm/drm_blend.h>
24 #include <drm/drm_crtc.h>
25 #include <drm/drm_flip_work.h>
26 #include <drm/drm_fourcc.h>
27 #include <drm/drm_framebuffer.h>
28 #include <drm/drm_gem_atomic_helper.h>
29 #include <drm/drm_gem_framebuffer_helper.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_self_refresh_helper.h>
32 #include <drm/drm_vblank.h>
33 
34 #ifdef CONFIG_DRM_ANALOGIX_DP
35 #include <drm/bridge/analogix_dp.h>
36 #endif
37 
38 #include "rockchip_drm_drv.h"
39 #include "rockchip_drm_gem.h"
40 #include "rockchip_drm_fb.h"
41 #include "rockchip_drm_vop.h"
42 #include "rockchip_rgb.h"
43 
44 #define VOP_WIN_SET(vop, win, name, v) \
45 		vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
46 #define VOP_SCL_SET(vop, win, name, v) \
47 		vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
48 #define VOP_SCL_SET_EXT(vop, win, name, v) \
49 		vop_reg_set(vop, &win->phy->scl->ext->name, \
50 			    win->base, ~0, v, #name)
51 
52 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
53 	do { \
54 		if (win_yuv2yuv && win_yuv2yuv->name.mask) \
55 			vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
56 	} while (0)
57 
58 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
59 	do { \
60 		if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
61 			vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
62 	} while (0)
63 
64 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
65 		vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
66 
67 #define VOP_REG_SET(vop, group, name, v) \
68 		    vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
69 
70 #define VOP_HAS_REG(vop, group, name) \
71 		(!!(vop->data->group->name.mask))
72 
73 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
74 	do { \
75 		int i, reg = 0, mask = 0; \
76 		for (i = 0; i < vop->data->intr->nintrs; i++) { \
77 			if (vop->data->intr->intrs[i] & type) { \
78 				reg |= (v) << i; \
79 				mask |= 1 << i; \
80 			} \
81 		} \
82 		VOP_INTR_SET_MASK(vop, name, mask, reg); \
83 	} while (0)
84 #define VOP_INTR_GET_TYPE(vop, name, type) \
85 		vop_get_intr_type(vop, &vop->data->intr->name, type)
86 
87 #define VOP_WIN_GET(vop, win, name) \
88 		vop_read_reg(vop, win->base, &win->phy->name)
89 
90 #define VOP_WIN_HAS_REG(win, name) \
91 	(!!(win->phy->name.mask))
92 
93 #define VOP_WIN_GET_YRGBADDR(vop, win) \
94 		vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
95 
96 #define VOP_WIN_TO_INDEX(vop_win) \
97 	((vop_win) - (vop_win)->vop->win)
98 
99 #define VOP_AFBC_SET(vop, name, v) \
100 	do { \
101 		if ((vop)->data->afbc) \
102 			vop_reg_set((vop), &(vop)->data->afbc->name, \
103 				    0, ~0, v, #name); \
104 	} while (0)
105 
106 #define to_vop(x) container_of(x, struct vop, crtc)
107 #define to_vop_win(x) container_of(x, struct vop_win, base)
108 
109 #define AFBC_FMT_RGB565		0x0
110 #define AFBC_FMT_U8U8U8U8	0x5
111 #define AFBC_FMT_U8U8U8		0x4
112 
113 #define AFBC_TILE_16x16		BIT(4)
114 
115 /*
116  * The coefficients of the following matrix are all fixed points.
117  * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
118  * They are all represented in two's complement.
119  */
120 static const uint32_t bt601_yuv2rgb[] = {
121 	0x4A8, 0x0,    0x662,
122 	0x4A8, 0x1E6F, 0x1CBF,
123 	0x4A8, 0x812,  0x0,
124 	0x321168, 0x0877CF, 0x2EB127
125 };
126 
127 enum vop_pending {
128 	VOP_PENDING_FB_UNREF,
129 };
130 
131 struct vop_win {
132 	struct drm_plane base;
133 	const struct vop_win_data *data;
134 	const struct vop_win_yuv2yuv_data *yuv2yuv_data;
135 	struct vop *vop;
136 };
137 
138 struct rockchip_rgb;
139 struct vop {
140 	struct drm_crtc crtc;
141 	struct device *dev;
142 	struct drm_device *drm_dev;
143 	bool is_enabled;
144 
145 	struct completion dsp_hold_completion;
146 	unsigned int win_enabled;
147 
148 	/* protected by dev->event_lock */
149 	struct drm_pending_vblank_event *event;
150 
151 	struct drm_flip_work fb_unref_work;
152 	unsigned long pending;
153 
154 	struct completion line_flag_completion;
155 
156 	const struct vop_data *data;
157 
158 	uint32_t *regsbak;
159 	void __iomem *regs;
160 	void __iomem *lut_regs;
161 
162 	/* physical map length of vop register */
163 	uint32_t len;
164 
165 	/* one time only one process allowed to config the register */
166 	spinlock_t reg_lock;
167 	/* lock vop irq reg */
168 	spinlock_t irq_lock;
169 	/* protects crtc enable/disable */
170 	struct mutex vop_lock;
171 
172 	unsigned int irq;
173 
174 	/* vop AHP clk */
175 	struct clk *hclk;
176 	/* vop dclk */
177 	struct clk *dclk;
178 	/* vop share memory frequency */
179 	struct clk *aclk;
180 
181 	/* vop dclk reset */
182 	struct reset_control *dclk_rst;
183 
184 	/* optional internal rgb encoder */
185 	struct rockchip_rgb *rgb;
186 
187 	struct vop_win win[];
188 };
189 
190 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
191 {
192 	return readl(vop->regs + offset);
193 }
194 
195 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
196 				    const struct vop_reg *reg)
197 {
198 	return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
199 }
200 
201 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
202 			uint32_t _offset, uint32_t _mask, uint32_t v,
203 			const char *reg_name)
204 {
205 	int offset, mask, shift;
206 
207 	if (!reg || !reg->mask) {
208 		DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
209 		return;
210 	}
211 
212 	offset = reg->offset + _offset;
213 	mask = reg->mask & _mask;
214 	shift = reg->shift;
215 
216 	if (reg->write_mask) {
217 		v = ((v << shift) & 0xffff) | (mask << (shift + 16));
218 	} else {
219 		uint32_t cached_val = vop->regsbak[offset >> 2];
220 
221 		v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
222 		vop->regsbak[offset >> 2] = v;
223 	}
224 
225 	if (reg->relaxed)
226 		writel_relaxed(v, vop->regs + offset);
227 	else
228 		writel(v, vop->regs + offset);
229 }
230 
231 static inline uint32_t vop_get_intr_type(struct vop *vop,
232 					 const struct vop_reg *reg, int type)
233 {
234 	uint32_t i, ret = 0;
235 	uint32_t regs = vop_read_reg(vop, 0, reg);
236 
237 	for (i = 0; i < vop->data->intr->nintrs; i++) {
238 		if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
239 			ret |= vop->data->intr->intrs[i];
240 	}
241 
242 	return ret;
243 }
244 
245 static inline void vop_cfg_done(struct vop *vop)
246 {
247 	VOP_REG_SET(vop, common, cfg_done, 1);
248 }
249 
250 static bool has_rb_swapped(uint32_t format)
251 {
252 	switch (format) {
253 	case DRM_FORMAT_XBGR8888:
254 	case DRM_FORMAT_ABGR8888:
255 	case DRM_FORMAT_BGR888:
256 	case DRM_FORMAT_BGR565:
257 		return true;
258 	default:
259 		return false;
260 	}
261 }
262 
263 static bool has_uv_swapped(uint32_t format)
264 {
265 	switch (format) {
266 	case DRM_FORMAT_NV21:
267 	case DRM_FORMAT_NV61:
268 	case DRM_FORMAT_NV42:
269 		return true;
270 	default:
271 		return false;
272 	}
273 }
274 
275 static enum vop_data_format vop_convert_format(uint32_t format)
276 {
277 	switch (format) {
278 	case DRM_FORMAT_XRGB8888:
279 	case DRM_FORMAT_ARGB8888:
280 	case DRM_FORMAT_XBGR8888:
281 	case DRM_FORMAT_ABGR8888:
282 		return VOP_FMT_ARGB8888;
283 	case DRM_FORMAT_RGB888:
284 	case DRM_FORMAT_BGR888:
285 		return VOP_FMT_RGB888;
286 	case DRM_FORMAT_RGB565:
287 	case DRM_FORMAT_BGR565:
288 		return VOP_FMT_RGB565;
289 	case DRM_FORMAT_NV12:
290 	case DRM_FORMAT_NV21:
291 		return VOP_FMT_YUV420SP;
292 	case DRM_FORMAT_NV16:
293 	case DRM_FORMAT_NV61:
294 		return VOP_FMT_YUV422SP;
295 	case DRM_FORMAT_NV24:
296 	case DRM_FORMAT_NV42:
297 		return VOP_FMT_YUV444SP;
298 	default:
299 		DRM_ERROR("unsupported format[%08x]\n", format);
300 		return -EINVAL;
301 	}
302 }
303 
304 static int vop_convert_afbc_format(uint32_t format)
305 {
306 	switch (format) {
307 	case DRM_FORMAT_XRGB8888:
308 	case DRM_FORMAT_ARGB8888:
309 	case DRM_FORMAT_XBGR8888:
310 	case DRM_FORMAT_ABGR8888:
311 		return AFBC_FMT_U8U8U8U8;
312 	case DRM_FORMAT_RGB888:
313 	case DRM_FORMAT_BGR888:
314 		return AFBC_FMT_U8U8U8;
315 	case DRM_FORMAT_RGB565:
316 	case DRM_FORMAT_BGR565:
317 		return AFBC_FMT_RGB565;
318 	default:
319 		DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format);
320 		return -EINVAL;
321 	}
322 }
323 
324 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
325 				  uint32_t dst, bool is_horizontal,
326 				  int vsu_mode, int *vskiplines)
327 {
328 	uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
329 
330 	if (vskiplines)
331 		*vskiplines = 0;
332 
333 	if (is_horizontal) {
334 		if (mode == SCALE_UP)
335 			val = GET_SCL_FT_BIC(src, dst);
336 		else if (mode == SCALE_DOWN)
337 			val = GET_SCL_FT_BILI_DN(src, dst);
338 	} else {
339 		if (mode == SCALE_UP) {
340 			if (vsu_mode == SCALE_UP_BIL)
341 				val = GET_SCL_FT_BILI_UP(src, dst);
342 			else
343 				val = GET_SCL_FT_BIC(src, dst);
344 		} else if (mode == SCALE_DOWN) {
345 			if (vskiplines) {
346 				*vskiplines = scl_get_vskiplines(src, dst);
347 				val = scl_get_bili_dn_vskip(src, dst,
348 							    *vskiplines);
349 			} else {
350 				val = GET_SCL_FT_BILI_DN(src, dst);
351 			}
352 		}
353 	}
354 
355 	return val;
356 }
357 
358 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
359 			     uint32_t src_w, uint32_t src_h, uint32_t dst_w,
360 			     uint32_t dst_h, const struct drm_format_info *info)
361 {
362 	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
363 	uint16_t cbcr_hor_scl_mode = SCALE_NONE;
364 	uint16_t cbcr_ver_scl_mode = SCALE_NONE;
365 	bool is_yuv = false;
366 	uint16_t cbcr_src_w = src_w / info->hsub;
367 	uint16_t cbcr_src_h = src_h / info->vsub;
368 	uint16_t vsu_mode;
369 	uint16_t lb_mode;
370 	uint32_t val;
371 	int vskiplines;
372 
373 	if (info->is_yuv)
374 		is_yuv = true;
375 
376 	if (dst_w > 3840) {
377 		DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
378 		return;
379 	}
380 
381 	if (!win->phy->scl->ext) {
382 		VOP_SCL_SET(vop, win, scale_yrgb_x,
383 			    scl_cal_scale2(src_w, dst_w));
384 		VOP_SCL_SET(vop, win, scale_yrgb_y,
385 			    scl_cal_scale2(src_h, dst_h));
386 		if (is_yuv) {
387 			VOP_SCL_SET(vop, win, scale_cbcr_x,
388 				    scl_cal_scale2(cbcr_src_w, dst_w));
389 			VOP_SCL_SET(vop, win, scale_cbcr_y,
390 				    scl_cal_scale2(cbcr_src_h, dst_h));
391 		}
392 		return;
393 	}
394 
395 	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
396 	yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
397 
398 	if (is_yuv) {
399 		cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
400 		cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
401 		if (cbcr_hor_scl_mode == SCALE_DOWN)
402 			lb_mode = scl_vop_cal_lb_mode(dst_w, true);
403 		else
404 			lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
405 	} else {
406 		if (yrgb_hor_scl_mode == SCALE_DOWN)
407 			lb_mode = scl_vop_cal_lb_mode(dst_w, false);
408 		else
409 			lb_mode = scl_vop_cal_lb_mode(src_w, false);
410 	}
411 
412 	VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
413 	if (lb_mode == LB_RGB_3840X2) {
414 		if (yrgb_ver_scl_mode != SCALE_NONE) {
415 			DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
416 			return;
417 		}
418 		if (cbcr_ver_scl_mode != SCALE_NONE) {
419 			DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
420 			return;
421 		}
422 		vsu_mode = SCALE_UP_BIL;
423 	} else if (lb_mode == LB_RGB_2560X4) {
424 		vsu_mode = SCALE_UP_BIL;
425 	} else {
426 		vsu_mode = SCALE_UP_BIC;
427 	}
428 
429 	val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
430 				true, 0, NULL);
431 	VOP_SCL_SET(vop, win, scale_yrgb_x, val);
432 	val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
433 				false, vsu_mode, &vskiplines);
434 	VOP_SCL_SET(vop, win, scale_yrgb_y, val);
435 
436 	VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
437 	VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
438 
439 	VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
440 	VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
441 	VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
442 	VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
443 	VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
444 	if (is_yuv) {
445 		val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
446 					dst_w, true, 0, NULL);
447 		VOP_SCL_SET(vop, win, scale_cbcr_x, val);
448 		val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
449 					dst_h, false, vsu_mode, &vskiplines);
450 		VOP_SCL_SET(vop, win, scale_cbcr_y, val);
451 
452 		VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
453 		VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
454 		VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
455 		VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
456 		VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
457 		VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
458 		VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
459 	}
460 }
461 
462 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
463 {
464 	unsigned long flags;
465 
466 	if (WARN_ON(!vop->is_enabled))
467 		return;
468 
469 	spin_lock_irqsave(&vop->irq_lock, flags);
470 
471 	VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
472 	VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
473 
474 	spin_unlock_irqrestore(&vop->irq_lock, flags);
475 }
476 
477 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
478 {
479 	unsigned long flags;
480 
481 	if (WARN_ON(!vop->is_enabled))
482 		return;
483 
484 	spin_lock_irqsave(&vop->irq_lock, flags);
485 
486 	VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
487 
488 	spin_unlock_irqrestore(&vop->irq_lock, flags);
489 }
490 
491 /*
492  * (1) each frame starts at the start of the Vsync pulse which is signaled by
493  *     the "FRAME_SYNC" interrupt.
494  * (2) the active data region of each frame ends at dsp_vact_end
495  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
496  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
497  *
498  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
499  * Interrupts
500  * LINE_FLAG -------------------------------+
501  * FRAME_SYNC ----+                         |
502  *                |                         |
503  *                v                         v
504  *                | Vsync | Vbp |  Vactive  | Vfp |
505  *                        ^     ^           ^     ^
506  *                        |     |           |     |
507  *                        |     |           |     |
508  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
509  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
510  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
511  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
512  */
513 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
514 {
515 	uint32_t line_flag_irq;
516 	unsigned long flags;
517 
518 	spin_lock_irqsave(&vop->irq_lock, flags);
519 
520 	line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
521 
522 	spin_unlock_irqrestore(&vop->irq_lock, flags);
523 
524 	return !!line_flag_irq;
525 }
526 
527 static void vop_line_flag_irq_enable(struct vop *vop)
528 {
529 	unsigned long flags;
530 
531 	if (WARN_ON(!vop->is_enabled))
532 		return;
533 
534 	spin_lock_irqsave(&vop->irq_lock, flags);
535 
536 	VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
537 	VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
538 
539 	spin_unlock_irqrestore(&vop->irq_lock, flags);
540 }
541 
542 static void vop_line_flag_irq_disable(struct vop *vop)
543 {
544 	unsigned long flags;
545 
546 	if (WARN_ON(!vop->is_enabled))
547 		return;
548 
549 	spin_lock_irqsave(&vop->irq_lock, flags);
550 
551 	VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
552 
553 	spin_unlock_irqrestore(&vop->irq_lock, flags);
554 }
555 
556 static int vop_core_clks_enable(struct vop *vop)
557 {
558 	int ret;
559 
560 	ret = clk_enable(vop->hclk);
561 	if (ret < 0)
562 		return ret;
563 
564 	ret = clk_enable(vop->aclk);
565 	if (ret < 0)
566 		goto err_disable_hclk;
567 
568 	return 0;
569 
570 err_disable_hclk:
571 	clk_disable(vop->hclk);
572 	return ret;
573 }
574 
575 static void vop_core_clks_disable(struct vop *vop)
576 {
577 	clk_disable(vop->aclk);
578 	clk_disable(vop->hclk);
579 }
580 
581 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
582 {
583 	const struct vop_win_data *win = vop_win->data;
584 
585 	if (win->phy->scl && win->phy->scl->ext) {
586 		VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
587 		VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
588 		VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
589 		VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
590 	}
591 
592 	VOP_WIN_SET(vop, win, enable, 0);
593 	vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
594 }
595 
596 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
597 {
598 	struct vop *vop = to_vop(crtc);
599 	int ret, i;
600 
601 	ret = pm_runtime_resume_and_get(vop->dev);
602 	if (ret < 0) {
603 		DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
604 		return ret;
605 	}
606 
607 	ret = vop_core_clks_enable(vop);
608 	if (WARN_ON(ret < 0))
609 		goto err_put_pm_runtime;
610 
611 	ret = clk_enable(vop->dclk);
612 	if (WARN_ON(ret < 0))
613 		goto err_disable_core;
614 
615 	/*
616 	 * Slave iommu shares power, irq and clock with vop.  It was associated
617 	 * automatically with this master device via common driver code.
618 	 * Now that we have enabled the clock we attach it to the shared drm
619 	 * mapping.
620 	 */
621 	ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
622 	if (ret) {
623 		DRM_DEV_ERROR(vop->dev,
624 			      "failed to attach dma mapping, %d\n", ret);
625 		goto err_disable_dclk;
626 	}
627 
628 	spin_lock(&vop->reg_lock);
629 	for (i = 0; i < vop->len; i += 4)
630 		writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
631 
632 	/*
633 	 * We need to make sure that all windows are disabled before we
634 	 * enable the crtc. Otherwise we might try to scan from a destroyed
635 	 * buffer later.
636 	 *
637 	 * In the case of enable-after-PSR, we don't need to worry about this
638 	 * case since the buffer is guaranteed to be valid and disabling the
639 	 * window will result in screen glitches on PSR exit.
640 	 */
641 	if (!old_state || !old_state->self_refresh_active) {
642 		for (i = 0; i < vop->data->win_size; i++) {
643 			struct vop_win *vop_win = &vop->win[i];
644 
645 			vop_win_disable(vop, vop_win);
646 		}
647 	}
648 
649 	if (vop->data->afbc) {
650 		struct rockchip_crtc_state *s;
651 		/*
652 		 * Disable AFBC and forget there was a vop window with AFBC
653 		 */
654 		VOP_AFBC_SET(vop, enable, 0);
655 		s = to_rockchip_crtc_state(crtc->state);
656 		s->enable_afbc = false;
657 	}
658 
659 	vop_cfg_done(vop);
660 
661 	spin_unlock(&vop->reg_lock);
662 
663 	/*
664 	 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
665 	 */
666 	vop->is_enabled = true;
667 
668 	spin_lock(&vop->reg_lock);
669 
670 	VOP_REG_SET(vop, common, standby, 1);
671 
672 	spin_unlock(&vop->reg_lock);
673 
674 	drm_crtc_vblank_on(crtc);
675 
676 	return 0;
677 
678 err_disable_dclk:
679 	clk_disable(vop->dclk);
680 err_disable_core:
681 	vop_core_clks_disable(vop);
682 err_put_pm_runtime:
683 	pm_runtime_put_sync(vop->dev);
684 	return ret;
685 }
686 
687 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
688 {
689         struct vop *vop = to_vop(crtc);
690         int i;
691 
692         spin_lock(&vop->reg_lock);
693 
694         for (i = 0; i < vop->data->win_size; i++) {
695                 struct vop_win *vop_win = &vop->win[i];
696                 const struct vop_win_data *win = vop_win->data;
697 
698                 VOP_WIN_SET(vop, win, enable,
699                             enabled && (vop->win_enabled & BIT(i)));
700         }
701         vop_cfg_done(vop);
702 
703         spin_unlock(&vop->reg_lock);
704 }
705 
706 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
707 				    struct drm_atomic_state *state)
708 {
709 	struct vop *vop = to_vop(crtc);
710 
711 	WARN_ON(vop->event);
712 
713 	if (crtc->state->self_refresh_active)
714 		rockchip_drm_set_win_enabled(crtc, false);
715 
716 	if (crtc->state->self_refresh_active)
717 		goto out;
718 
719 	mutex_lock(&vop->vop_lock);
720 
721 	drm_crtc_vblank_off(crtc);
722 
723 	/*
724 	 * Vop standby will take effect at end of current frame,
725 	 * if dsp hold valid irq happen, it means standby complete.
726 	 *
727 	 * we must wait standby complete when we want to disable aclk,
728 	 * if not, memory bus maybe dead.
729 	 */
730 	reinit_completion(&vop->dsp_hold_completion);
731 	vop_dsp_hold_valid_irq_enable(vop);
732 
733 	spin_lock(&vop->reg_lock);
734 
735 	VOP_REG_SET(vop, common, standby, 1);
736 
737 	spin_unlock(&vop->reg_lock);
738 
739 	if (!wait_for_completion_timeout(&vop->dsp_hold_completion,
740 					 msecs_to_jiffies(200)))
741 		WARN(1, "%s: timed out waiting for DSP hold", crtc->name);
742 
743 	vop_dsp_hold_valid_irq_disable(vop);
744 
745 	vop->is_enabled = false;
746 
747 	/*
748 	 * vop standby complete, so iommu detach is safe.
749 	 */
750 	rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
751 
752 	clk_disable(vop->dclk);
753 	vop_core_clks_disable(vop);
754 	pm_runtime_put(vop->dev);
755 
756 	mutex_unlock(&vop->vop_lock);
757 
758 out:
759 	if (crtc->state->event && !crtc->state->active) {
760 		spin_lock_irq(&crtc->dev->event_lock);
761 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
762 		spin_unlock_irq(&crtc->dev->event_lock);
763 
764 		crtc->state->event = NULL;
765 	}
766 }
767 
768 static void vop_plane_destroy(struct drm_plane *plane)
769 {
770 	drm_plane_cleanup(plane);
771 }
772 
773 static inline bool rockchip_afbc(u64 modifier)
774 {
775 	return modifier == ROCKCHIP_AFBC_MOD;
776 }
777 
778 static bool rockchip_mod_supported(struct drm_plane *plane,
779 				   u32 format, u64 modifier)
780 {
781 	if (modifier == DRM_FORMAT_MOD_LINEAR)
782 		return true;
783 
784 	if (!rockchip_afbc(modifier)) {
785 		DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
786 
787 		return false;
788 	}
789 
790 	return vop_convert_afbc_format(format) >= 0;
791 }
792 
793 static int vop_plane_atomic_check(struct drm_plane *plane,
794 			   struct drm_atomic_state *state)
795 {
796 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
797 										 plane);
798 	struct drm_crtc *crtc = new_plane_state->crtc;
799 	struct drm_crtc_state *crtc_state;
800 	struct drm_framebuffer *fb = new_plane_state->fb;
801 	struct vop_win *vop_win = to_vop_win(plane);
802 	const struct vop_win_data *win = vop_win->data;
803 	int ret;
804 	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
805 					DRM_PLANE_NO_SCALING;
806 	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
807 					DRM_PLANE_NO_SCALING;
808 
809 	if (!crtc || WARN_ON(!fb))
810 		return 0;
811 
812 	crtc_state = drm_atomic_get_existing_crtc_state(state,
813 							crtc);
814 	if (WARN_ON(!crtc_state))
815 		return -EINVAL;
816 
817 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
818 						  min_scale, max_scale,
819 						  true, true);
820 	if (ret)
821 		return ret;
822 
823 	if (!new_plane_state->visible)
824 		return 0;
825 
826 	ret = vop_convert_format(fb->format->format);
827 	if (ret < 0)
828 		return ret;
829 
830 	/*
831 	 * Src.x1 can be odd when do clip, but yuv plane start point
832 	 * need align with 2 pixel.
833 	 */
834 	if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) {
835 		DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n");
836 		return -EINVAL;
837 	}
838 
839 	if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) {
840 		DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n");
841 		return -EINVAL;
842 	}
843 
844 	if (rockchip_afbc(fb->modifier)) {
845 		struct vop *vop = to_vop(crtc);
846 
847 		if (!vop->data->afbc) {
848 			DRM_DEBUG_KMS("vop does not support AFBC\n");
849 			return -EINVAL;
850 		}
851 
852 		ret = vop_convert_afbc_format(fb->format->format);
853 		if (ret < 0)
854 			return ret;
855 
856 		if (new_plane_state->src.x1 || new_plane_state->src.y1) {
857 			DRM_DEBUG_KMS("AFBC does not support offset display, " \
858 				      "xpos=%d, ypos=%d, offset=%d\n",
859 				      new_plane_state->src.x1, new_plane_state->src.y1,
860 				      fb->offsets[0]);
861 			return -EINVAL;
862 		}
863 
864 		if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) {
865 			DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n",
866 				      new_plane_state->rotation);
867 			return -EINVAL;
868 		}
869 	}
870 
871 	return 0;
872 }
873 
874 static void vop_plane_atomic_disable(struct drm_plane *plane,
875 				     struct drm_atomic_state *state)
876 {
877 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
878 									   plane);
879 	struct vop_win *vop_win = to_vop_win(plane);
880 	struct vop *vop = to_vop(old_state->crtc);
881 
882 	if (!old_state->crtc)
883 		return;
884 
885 	spin_lock(&vop->reg_lock);
886 
887 	vop_win_disable(vop, vop_win);
888 
889 	spin_unlock(&vop->reg_lock);
890 }
891 
892 static void vop_plane_atomic_update(struct drm_plane *plane,
893 		struct drm_atomic_state *state)
894 {
895 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
896 									   plane);
897 	struct drm_crtc *crtc = new_state->crtc;
898 	struct vop_win *vop_win = to_vop_win(plane);
899 	const struct vop_win_data *win = vop_win->data;
900 	const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
901 	struct vop *vop = to_vop(new_state->crtc);
902 	struct drm_framebuffer *fb = new_state->fb;
903 	unsigned int actual_w, actual_h;
904 	unsigned int dsp_stx, dsp_sty;
905 	uint32_t act_info, dsp_info, dsp_st;
906 	struct drm_rect *src = &new_state->src;
907 	struct drm_rect *dest = &new_state->dst;
908 	struct drm_gem_object *obj, *uv_obj;
909 	struct rockchip_gem_object *rk_obj, *rk_uv_obj;
910 	unsigned long offset;
911 	dma_addr_t dma_addr;
912 	uint32_t val;
913 	bool rb_swap, uv_swap;
914 	int win_index = VOP_WIN_TO_INDEX(vop_win);
915 	int format;
916 	int is_yuv = fb->format->is_yuv;
917 	int i;
918 
919 	/*
920 	 * can't update plane when vop is disabled.
921 	 */
922 	if (WARN_ON(!crtc))
923 		return;
924 
925 	if (WARN_ON(!vop->is_enabled))
926 		return;
927 
928 	if (!new_state->visible) {
929 		vop_plane_atomic_disable(plane, state);
930 		return;
931 	}
932 
933 	obj = fb->obj[0];
934 	rk_obj = to_rockchip_obj(obj);
935 
936 	actual_w = drm_rect_width(src) >> 16;
937 	actual_h = drm_rect_height(src) >> 16;
938 	act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
939 
940 	dsp_info = (drm_rect_height(dest) - 1) << 16;
941 	dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
942 
943 	dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
944 	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
945 	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
946 
947 	offset = (src->x1 >> 16) * fb->format->cpp[0];
948 	offset += (src->y1 >> 16) * fb->pitches[0];
949 	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
950 
951 	/*
952 	 * For y-mirroring we need to move address
953 	 * to the beginning of the last line.
954 	 */
955 	if (new_state->rotation & DRM_MODE_REFLECT_Y)
956 		dma_addr += (actual_h - 1) * fb->pitches[0];
957 
958 	format = vop_convert_format(fb->format->format);
959 
960 	spin_lock(&vop->reg_lock);
961 
962 	if (rockchip_afbc(fb->modifier)) {
963 		int afbc_format = vop_convert_afbc_format(fb->format->format);
964 
965 		VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
966 		VOP_AFBC_SET(vop, hreg_block_split, 0);
967 		VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
968 		VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
969 		VOP_AFBC_SET(vop, pic_size, act_info);
970 	}
971 
972 	VOP_WIN_SET(vop, win, format, format);
973 	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
974 	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
975 	VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
976 	VOP_WIN_SET(vop, win, y_mir_en,
977 		    (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
978 	VOP_WIN_SET(vop, win, x_mir_en,
979 		    (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
980 
981 	if (is_yuv) {
982 		int hsub = fb->format->hsub;
983 		int vsub = fb->format->vsub;
984 		int bpp = fb->format->cpp[1];
985 
986 		uv_obj = fb->obj[1];
987 		rk_uv_obj = to_rockchip_obj(uv_obj);
988 
989 		offset = (src->x1 >> 16) * bpp / hsub;
990 		offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
991 
992 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
993 		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
994 		VOP_WIN_SET(vop, win, uv_mst, dma_addr);
995 
996 		for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
997 			VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
998 							win_yuv2yuv,
999 							y2r_coefficients[i],
1000 							bt601_yuv2rgb[i]);
1001 		}
1002 
1003 		uv_swap = has_uv_swapped(fb->format->format);
1004 		VOP_WIN_SET(vop, win, uv_swap, uv_swap);
1005 	}
1006 
1007 	if (win->phy->scl)
1008 		scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1009 				    drm_rect_width(dest), drm_rect_height(dest),
1010 				    fb->format);
1011 
1012 	VOP_WIN_SET(vop, win, act_info, act_info);
1013 	VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1014 	VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1015 
1016 	rb_swap = has_rb_swapped(fb->format->format);
1017 	VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1018 
1019 	/*
1020 	 * Blending win0 with the background color doesn't seem to work
1021 	 * correctly. We only get the background color, no matter the contents
1022 	 * of the win0 framebuffer.  However, blending pre-multiplied color
1023 	 * with the default opaque black default background color is a no-op,
1024 	 * so we can just disable blending to get the correct result.
1025 	 */
1026 	if (fb->format->has_alpha && win_index > 0) {
1027 		VOP_WIN_SET(vop, win, dst_alpha_ctl,
1028 			    DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1029 		val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1030 			SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1031 			SRC_BLEND_M0(ALPHA_PER_PIX) |
1032 			SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1033 			SRC_FACTOR_M0(ALPHA_ONE);
1034 		VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1035 
1036 		VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1037 		VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1038 		VOP_WIN_SET(vop, win, alpha_en, 1);
1039 	} else {
1040 		VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1041 		VOP_WIN_SET(vop, win, alpha_en, 0);
1042 	}
1043 
1044 	VOP_WIN_SET(vop, win, enable, 1);
1045 	vop->win_enabled |= BIT(win_index);
1046 	spin_unlock(&vop->reg_lock);
1047 }
1048 
1049 static int vop_plane_atomic_async_check(struct drm_plane *plane,
1050 					struct drm_atomic_state *state)
1051 {
1052 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1053 										 plane);
1054 	struct vop_win *vop_win = to_vop_win(plane);
1055 	const struct vop_win_data *win = vop_win->data;
1056 	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1057 					DRM_PLANE_NO_SCALING;
1058 	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1059 					DRM_PLANE_NO_SCALING;
1060 	struct drm_crtc_state *crtc_state;
1061 
1062 	if (plane != new_plane_state->crtc->cursor)
1063 		return -EINVAL;
1064 
1065 	if (!plane->state)
1066 		return -EINVAL;
1067 
1068 	if (!plane->state->fb)
1069 		return -EINVAL;
1070 
1071 	if (state)
1072 		crtc_state = drm_atomic_get_existing_crtc_state(state,
1073 								new_plane_state->crtc);
1074 	else /* Special case for asynchronous cursor updates. */
1075 		crtc_state = plane->crtc->state;
1076 
1077 	return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
1078 						   min_scale, max_scale,
1079 						   true, true);
1080 }
1081 
1082 static void vop_plane_atomic_async_update(struct drm_plane *plane,
1083 					  struct drm_atomic_state *state)
1084 {
1085 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1086 									   plane);
1087 	struct vop *vop = to_vop(plane->state->crtc);
1088 	struct drm_framebuffer *old_fb = plane->state->fb;
1089 
1090 	plane->state->crtc_x = new_state->crtc_x;
1091 	plane->state->crtc_y = new_state->crtc_y;
1092 	plane->state->crtc_h = new_state->crtc_h;
1093 	plane->state->crtc_w = new_state->crtc_w;
1094 	plane->state->src_x = new_state->src_x;
1095 	plane->state->src_y = new_state->src_y;
1096 	plane->state->src_h = new_state->src_h;
1097 	plane->state->src_w = new_state->src_w;
1098 	swap(plane->state->fb, new_state->fb);
1099 
1100 	if (vop->is_enabled) {
1101 		vop_plane_atomic_update(plane, state);
1102 		spin_lock(&vop->reg_lock);
1103 		vop_cfg_done(vop);
1104 		spin_unlock(&vop->reg_lock);
1105 
1106 		/*
1107 		 * A scanout can still be occurring, so we can't drop the
1108 		 * reference to the old framebuffer. To solve this we get a
1109 		 * reference to old_fb and set a worker to release it later.
1110 		 * FIXME: if we perform 500 async_update calls before the
1111 		 * vblank, then we can have 500 different framebuffers waiting
1112 		 * to be released.
1113 		 */
1114 		if (old_fb && plane->state->fb != old_fb) {
1115 			drm_framebuffer_get(old_fb);
1116 			WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1117 			drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1118 			set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1119 		}
1120 	}
1121 }
1122 
1123 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1124 	.atomic_check = vop_plane_atomic_check,
1125 	.atomic_update = vop_plane_atomic_update,
1126 	.atomic_disable = vop_plane_atomic_disable,
1127 	.atomic_async_check = vop_plane_atomic_async_check,
1128 	.atomic_async_update = vop_plane_atomic_async_update,
1129 };
1130 
1131 static const struct drm_plane_funcs vop_plane_funcs = {
1132 	.update_plane	= drm_atomic_helper_update_plane,
1133 	.disable_plane	= drm_atomic_helper_disable_plane,
1134 	.destroy = vop_plane_destroy,
1135 	.reset = drm_atomic_helper_plane_reset,
1136 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1137 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1138 	.format_mod_supported = rockchip_mod_supported,
1139 };
1140 
1141 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1142 {
1143 	struct vop *vop = to_vop(crtc);
1144 	unsigned long flags;
1145 
1146 	if (WARN_ON(!vop->is_enabled))
1147 		return -EPERM;
1148 
1149 	spin_lock_irqsave(&vop->irq_lock, flags);
1150 
1151 	VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1152 	VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1153 
1154 	spin_unlock_irqrestore(&vop->irq_lock, flags);
1155 
1156 	return 0;
1157 }
1158 
1159 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1160 {
1161 	struct vop *vop = to_vop(crtc);
1162 	unsigned long flags;
1163 
1164 	if (WARN_ON(!vop->is_enabled))
1165 		return;
1166 
1167 	spin_lock_irqsave(&vop->irq_lock, flags);
1168 
1169 	VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1170 
1171 	spin_unlock_irqrestore(&vop->irq_lock, flags);
1172 }
1173 
1174 static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
1175 						const struct drm_display_mode *mode)
1176 {
1177 	struct vop *vop = to_vop(crtc);
1178 
1179 	if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width)
1180 		return MODE_BAD_HVALUE;
1181 
1182 	return MODE_OK;
1183 }
1184 
1185 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1186 				const struct drm_display_mode *mode,
1187 				struct drm_display_mode *adjusted_mode)
1188 {
1189 	struct vop *vop = to_vop(crtc);
1190 	unsigned long rate;
1191 
1192 	/*
1193 	 * Clock craziness.
1194 	 *
1195 	 * Key points:
1196 	 *
1197 	 * - DRM works in kHz.
1198 	 * - Clock framework works in Hz.
1199 	 * - Rockchip's clock driver picks the clock rate that is the
1200 	 *   same _OR LOWER_ than the one requested.
1201 	 *
1202 	 * Action plan:
1203 	 *
1204 	 * 1. Try to set the exact rate first, and confirm the clock framework
1205 	 *    can provide it.
1206 	 *
1207 	 * 2. If the clock framework cannot provide the exact rate, we should
1208 	 *    add 999 Hz to the requested rate.  That way if the clock we need
1209 	 *    is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then
1210 	 *    the clock framework will actually give us the right clock.
1211 	 *
1212 	 * 3. Get the clock framework to round the rate for us to tell us
1213 	 *    what it will actually make.
1214 	 *
1215 	 * 4. Store the rounded up rate so that we don't need to worry about
1216 	 *    this in the actual clk_set_rate().
1217 	 */
1218 	rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);
1219 	if (rate / 1000 != adjusted_mode->clock)
1220 		rate = clk_round_rate(vop->dclk,
1221 				      adjusted_mode->clock * 1000 + 999);
1222 	adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
1223 
1224 	return true;
1225 }
1226 
1227 static bool vop_dsp_lut_is_enabled(struct vop *vop)
1228 {
1229 	return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1230 }
1231 
1232 static u32 vop_lut_buffer_index(struct vop *vop)
1233 {
1234 	return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
1235 }
1236 
1237 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1238 {
1239 	struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1240 	unsigned int i, bpc = ilog2(vop->data->lut_size);
1241 
1242 	for (i = 0; i < crtc->gamma_size; i++) {
1243 		u32 word;
1244 
1245 		word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) |
1246 		       (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
1247 			drm_color_lut_extract(lut[i].blue, bpc);
1248 		writel(word, vop->lut_regs + i * 4);
1249 	}
1250 }
1251 
1252 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1253 			       struct drm_crtc_state *old_state)
1254 {
1255 	struct drm_crtc_state *state = crtc->state;
1256 	unsigned int idle;
1257 	u32 lut_idx, old_idx;
1258 	int ret;
1259 
1260 	if (!vop->lut_regs)
1261 		return;
1262 
1263 	if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {
1264 		/*
1265 		 * To disable gamma (gamma_lut is null) or to write
1266 		 * an update to the LUT, clear dsp_lut_en.
1267 		 */
1268 		spin_lock(&vop->reg_lock);
1269 		VOP_REG_SET(vop, common, dsp_lut_en, 0);
1270 		vop_cfg_done(vop);
1271 		spin_unlock(&vop->reg_lock);
1272 
1273 		/*
1274 		 * In order to write the LUT to the internal memory,
1275 		 * we need to first make sure the dsp_lut_en bit is cleared.
1276 		 */
1277 		ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1278 					 idle, !idle, 5, 30 * 1000);
1279 		if (ret) {
1280 			DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1281 			return;
1282 		}
1283 
1284 		if (!state->gamma_lut)
1285 			return;
1286 	} else {
1287 		/*
1288 		 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en,
1289 		 * by setting update_gamma_lut then waiting for lut_buffer_index change
1290 		 */
1291 		old_idx = vop_lut_buffer_index(vop);
1292 	}
1293 
1294 	spin_lock(&vop->reg_lock);
1295 	vop_crtc_write_gamma_lut(vop, crtc);
1296 	VOP_REG_SET(vop, common, dsp_lut_en, 1);
1297 	VOP_REG_SET(vop, common, update_gamma_lut, 1);
1298 	vop_cfg_done(vop);
1299 	spin_unlock(&vop->reg_lock);
1300 
1301 	if (VOP_HAS_REG(vop, common, update_gamma_lut)) {
1302 		ret = readx_poll_timeout(vop_lut_buffer_index, vop,
1303 					 lut_idx, lut_idx != old_idx, 5, 30 * 1000);
1304 		if (ret) {
1305 			DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");
1306 			return;
1307 		}
1308 
1309 		/*
1310 		 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit
1311 		 * in our backup of the regs.
1312 		 */
1313 		spin_lock(&vop->reg_lock);
1314 		VOP_REG_SET(vop, common, update_gamma_lut, 0);
1315 		spin_unlock(&vop->reg_lock);
1316 	}
1317 }
1318 
1319 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1320 				  struct drm_atomic_state *state)
1321 {
1322 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1323 									  crtc);
1324 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1325 									      crtc);
1326 	struct vop *vop = to_vop(crtc);
1327 
1328 	/*
1329 	 * Only update GAMMA if the 'active' flag is not changed,
1330 	 * otherwise it's updated by .atomic_enable.
1331 	 */
1332 	if (crtc_state->color_mgmt_changed &&
1333 	    !crtc_state->active_changed)
1334 		vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1335 }
1336 
1337 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1338 				   struct drm_atomic_state *state)
1339 {
1340 	struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
1341 									 crtc);
1342 	struct vop *vop = to_vop(crtc);
1343 	const struct vop_data *vop_data = vop->data;
1344 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1345 	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1346 	u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1347 	u16 hdisplay = adjusted_mode->hdisplay;
1348 	u16 htotal = adjusted_mode->htotal;
1349 	u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1350 	u16 hact_end = hact_st + hdisplay;
1351 	u16 vdisplay = adjusted_mode->vdisplay;
1352 	u16 vtotal = adjusted_mode->vtotal;
1353 	u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1354 	u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1355 	u16 vact_end = vact_st + vdisplay;
1356 	uint32_t pin_pol, val;
1357 	int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1358 	int ret;
1359 
1360 	if (old_state && old_state->self_refresh_active) {
1361 		drm_crtc_vblank_on(crtc);
1362 		rockchip_drm_set_win_enabled(crtc, true);
1363 		return;
1364 	}
1365 
1366 	mutex_lock(&vop->vop_lock);
1367 
1368 	WARN_ON(vop->event);
1369 
1370 	ret = vop_enable(crtc, old_state);
1371 	if (ret) {
1372 		mutex_unlock(&vop->vop_lock);
1373 		DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1374 		return;
1375 	}
1376 	pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1377 		   BIT(HSYNC_POSITIVE) : 0;
1378 	pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1379 		   BIT(VSYNC_POSITIVE) : 0;
1380 	VOP_REG_SET(vop, output, pin_pol, pin_pol);
1381 	VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1382 
1383 	switch (s->output_type) {
1384 	case DRM_MODE_CONNECTOR_LVDS:
1385 		VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1386 		VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1387 		VOP_REG_SET(vop, output, rgb_en, 1);
1388 		break;
1389 	case DRM_MODE_CONNECTOR_eDP:
1390 		VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1391 		VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1392 		VOP_REG_SET(vop, output, edp_en, 1);
1393 		break;
1394 	case DRM_MODE_CONNECTOR_HDMIA:
1395 		VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1396 		VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1397 		VOP_REG_SET(vop, output, hdmi_en, 1);
1398 		break;
1399 	case DRM_MODE_CONNECTOR_DSI:
1400 		VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1401 		VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1402 		VOP_REG_SET(vop, output, mipi_en, 1);
1403 		VOP_REG_SET(vop, output, mipi_dual_channel_en,
1404 			    !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1405 		break;
1406 	case DRM_MODE_CONNECTOR_DisplayPort:
1407 		VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1408 		VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1409 		VOP_REG_SET(vop, output, dp_en, 1);
1410 		break;
1411 	default:
1412 		DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1413 			      s->output_type);
1414 	}
1415 
1416 	/*
1417 	 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1418 	 */
1419 	if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1420 	    !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1421 		s->output_mode = ROCKCHIP_OUT_MODE_P888;
1422 
1423 	if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1424 		VOP_REG_SET(vop, common, pre_dither_down, 1);
1425 	else
1426 		VOP_REG_SET(vop, common, pre_dither_down, 0);
1427 
1428 	if (dither_bpc == 6) {
1429 		VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1430 		VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1431 		VOP_REG_SET(vop, common, dither_down_en, 1);
1432 	} else {
1433 		VOP_REG_SET(vop, common, dither_down_en, 0);
1434 	}
1435 
1436 	VOP_REG_SET(vop, common, out_mode, s->output_mode);
1437 
1438 	VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1439 	val = hact_st << 16;
1440 	val |= hact_end;
1441 	VOP_REG_SET(vop, modeset, hact_st_end, val);
1442 	VOP_REG_SET(vop, modeset, hpost_st_end, val);
1443 
1444 	VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1445 	val = vact_st << 16;
1446 	val |= vact_end;
1447 	VOP_REG_SET(vop, modeset, vact_st_end, val);
1448 	VOP_REG_SET(vop, modeset, vpost_st_end, val);
1449 
1450 	VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1451 
1452 	clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1453 
1454 	VOP_REG_SET(vop, common, standby, 0);
1455 	mutex_unlock(&vop->vop_lock);
1456 
1457 	/*
1458 	 * If we have a GAMMA LUT in the state, then let's make sure
1459 	 * it's updated. We might be coming out of suspend,
1460 	 * which means the LUT internal memory needs to be re-written.
1461 	 */
1462 	if (crtc->state->gamma_lut)
1463 		vop_crtc_gamma_set(vop, crtc, old_state);
1464 }
1465 
1466 static bool vop_fs_irq_is_pending(struct vop *vop)
1467 {
1468 	return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1469 }
1470 
1471 static void vop_wait_for_irq_handler(struct vop *vop)
1472 {
1473 	bool pending;
1474 	int ret;
1475 
1476 	/*
1477 	 * Spin until frame start interrupt status bit goes low, which means
1478 	 * that interrupt handler was invoked and cleared it. The timeout of
1479 	 * 10 msecs is really too long, but it is just a safety measure if
1480 	 * something goes really wrong. The wait will only happen in the very
1481 	 * unlikely case of a vblank happening exactly at the same time and
1482 	 * shouldn't exceed microseconds range.
1483 	 */
1484 	ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1485 					!pending, 0, 10 * 1000);
1486 	if (ret)
1487 		DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1488 
1489 	synchronize_irq(vop->irq);
1490 }
1491 
1492 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1493 				 struct drm_atomic_state *state)
1494 {
1495 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1496 									  crtc);
1497 	struct vop *vop = to_vop(crtc);
1498 	struct drm_plane *plane;
1499 	struct drm_plane_state *plane_state;
1500 	struct rockchip_crtc_state *s;
1501 	int afbc_planes = 0;
1502 
1503 	if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1504 	    crtc_state->gamma_lut) {
1505 		unsigned int len;
1506 
1507 		len = drm_color_lut_size(crtc_state->gamma_lut);
1508 		if (len != crtc->gamma_size) {
1509 			DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1510 				      len, crtc->gamma_size);
1511 			return -EINVAL;
1512 		}
1513 	}
1514 
1515 	drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1516 		plane_state =
1517 			drm_atomic_get_plane_state(crtc_state->state, plane);
1518 		if (IS_ERR(plane_state)) {
1519 			DRM_DEBUG_KMS("Cannot get plane state for plane %s\n",
1520 				      plane->name);
1521 			return PTR_ERR(plane_state);
1522 		}
1523 
1524 		if (drm_is_afbc(plane_state->fb->modifier))
1525 			++afbc_planes;
1526 	}
1527 
1528 	if (afbc_planes > 1) {
1529 		DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes);
1530 		return -EINVAL;
1531 	}
1532 
1533 	s = to_rockchip_crtc_state(crtc_state);
1534 	s->enable_afbc = afbc_planes > 0;
1535 
1536 	return 0;
1537 }
1538 
1539 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1540 				  struct drm_atomic_state *state)
1541 {
1542 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1543 									      crtc);
1544 	struct drm_atomic_state *old_state = old_crtc_state->state;
1545 	struct drm_plane_state *old_plane_state, *new_plane_state;
1546 	struct vop *vop = to_vop(crtc);
1547 	struct drm_plane *plane;
1548 	struct rockchip_crtc_state *s;
1549 	int i;
1550 
1551 	if (WARN_ON(!vop->is_enabled))
1552 		return;
1553 
1554 	spin_lock(&vop->reg_lock);
1555 
1556 	/* Enable AFBC if there is some AFBC window, disable otherwise. */
1557 	s = to_rockchip_crtc_state(crtc->state);
1558 	VOP_AFBC_SET(vop, enable, s->enable_afbc);
1559 	vop_cfg_done(vop);
1560 
1561 	spin_unlock(&vop->reg_lock);
1562 
1563 	/*
1564 	 * There is a (rather unlikely) possiblity that a vblank interrupt
1565 	 * fired before we set the cfg_done bit. To avoid spuriously
1566 	 * signalling flip completion we need to wait for it to finish.
1567 	 */
1568 	vop_wait_for_irq_handler(vop);
1569 
1570 	spin_lock_irq(&crtc->dev->event_lock);
1571 	if (crtc->state->event) {
1572 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1573 		WARN_ON(vop->event);
1574 
1575 		vop->event = crtc->state->event;
1576 		crtc->state->event = NULL;
1577 	}
1578 	spin_unlock_irq(&crtc->dev->event_lock);
1579 
1580 	for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1581 				       new_plane_state, i) {
1582 		if (!old_plane_state->fb)
1583 			continue;
1584 
1585 		if (old_plane_state->fb == new_plane_state->fb)
1586 			continue;
1587 
1588 		drm_framebuffer_get(old_plane_state->fb);
1589 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1590 		drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1591 		set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1592 	}
1593 }
1594 
1595 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1596 	.mode_valid = vop_crtc_mode_valid,
1597 	.mode_fixup = vop_crtc_mode_fixup,
1598 	.atomic_check = vop_crtc_atomic_check,
1599 	.atomic_begin = vop_crtc_atomic_begin,
1600 	.atomic_flush = vop_crtc_atomic_flush,
1601 	.atomic_enable = vop_crtc_atomic_enable,
1602 	.atomic_disable = vop_crtc_atomic_disable,
1603 };
1604 
1605 static void vop_crtc_destroy(struct drm_crtc *crtc)
1606 {
1607 	drm_crtc_cleanup(crtc);
1608 }
1609 
1610 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1611 {
1612 	struct rockchip_crtc_state *rockchip_state;
1613 
1614 	if (WARN_ON(!crtc->state))
1615 		return NULL;
1616 
1617 	rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1618 	if (!rockchip_state)
1619 		return NULL;
1620 
1621 	__drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1622 	return &rockchip_state->base;
1623 }
1624 
1625 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1626 				   struct drm_crtc_state *state)
1627 {
1628 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1629 
1630 	__drm_atomic_helper_crtc_destroy_state(&s->base);
1631 	kfree(s);
1632 }
1633 
1634 static void vop_crtc_reset(struct drm_crtc *crtc)
1635 {
1636 	struct rockchip_crtc_state *crtc_state =
1637 		kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1638 
1639 	if (crtc->state)
1640 		vop_crtc_destroy_state(crtc, crtc->state);
1641 
1642 	__drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1643 }
1644 
1645 #ifdef CONFIG_DRM_ANALOGIX_DP
1646 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1647 {
1648 	struct drm_connector *connector;
1649 	struct drm_connector_list_iter conn_iter;
1650 
1651 	drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1652 	drm_for_each_connector_iter(connector, &conn_iter) {
1653 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1654 			drm_connector_list_iter_end(&conn_iter);
1655 			return connector;
1656 		}
1657 	}
1658 	drm_connector_list_iter_end(&conn_iter);
1659 
1660 	return NULL;
1661 }
1662 
1663 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1664 				   const char *source_name)
1665 {
1666 	struct vop *vop = to_vop(crtc);
1667 	struct drm_connector *connector;
1668 	int ret;
1669 
1670 	connector = vop_get_edp_connector(vop);
1671 	if (!connector)
1672 		return -EINVAL;
1673 
1674 	if (source_name && strcmp(source_name, "auto") == 0)
1675 		ret = analogix_dp_start_crc(connector);
1676 	else if (!source_name)
1677 		ret = analogix_dp_stop_crc(connector);
1678 	else
1679 		ret = -EINVAL;
1680 
1681 	return ret;
1682 }
1683 
1684 static int
1685 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1686 			   size_t *values_cnt)
1687 {
1688 	if (source_name && strcmp(source_name, "auto") != 0)
1689 		return -EINVAL;
1690 
1691 	*values_cnt = 3;
1692 	return 0;
1693 }
1694 
1695 #else
1696 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1697 				   const char *source_name)
1698 {
1699 	return -ENODEV;
1700 }
1701 
1702 static int
1703 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1704 			   size_t *values_cnt)
1705 {
1706 	return -ENODEV;
1707 }
1708 #endif
1709 
1710 static const struct drm_crtc_funcs vop_crtc_funcs = {
1711 	.set_config = drm_atomic_helper_set_config,
1712 	.page_flip = drm_atomic_helper_page_flip,
1713 	.destroy = vop_crtc_destroy,
1714 	.reset = vop_crtc_reset,
1715 	.atomic_duplicate_state = vop_crtc_duplicate_state,
1716 	.atomic_destroy_state = vop_crtc_destroy_state,
1717 	.enable_vblank = vop_crtc_enable_vblank,
1718 	.disable_vblank = vop_crtc_disable_vblank,
1719 	.set_crc_source = vop_crtc_set_crc_source,
1720 	.verify_crc_source = vop_crtc_verify_crc_source,
1721 };
1722 
1723 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1724 {
1725 	struct vop *vop = container_of(work, struct vop, fb_unref_work);
1726 	struct drm_framebuffer *fb = val;
1727 
1728 	drm_crtc_vblank_put(&vop->crtc);
1729 	drm_framebuffer_put(fb);
1730 }
1731 
1732 static void vop_handle_vblank(struct vop *vop)
1733 {
1734 	struct drm_device *drm = vop->drm_dev;
1735 	struct drm_crtc *crtc = &vop->crtc;
1736 
1737 	spin_lock(&drm->event_lock);
1738 	if (vop->event) {
1739 		drm_crtc_send_vblank_event(crtc, vop->event);
1740 		drm_crtc_vblank_put(crtc);
1741 		vop->event = NULL;
1742 	}
1743 	spin_unlock(&drm->event_lock);
1744 
1745 	if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1746 		drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1747 }
1748 
1749 static irqreturn_t vop_isr(int irq, void *data)
1750 {
1751 	struct vop *vop = data;
1752 	struct drm_crtc *crtc = &vop->crtc;
1753 	uint32_t active_irqs;
1754 	int ret = IRQ_NONE;
1755 
1756 	/*
1757 	 * The irq is shared with the iommu. If the runtime-pm state of the
1758 	 * vop-device is disabled the irq has to be targeted at the iommu.
1759 	 */
1760 	if (!pm_runtime_get_if_in_use(vop->dev))
1761 		return IRQ_NONE;
1762 
1763 	if (vop_core_clks_enable(vop)) {
1764 		DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1765 		goto out;
1766 	}
1767 
1768 	/*
1769 	 * interrupt register has interrupt status, enable and clear bits, we
1770 	 * must hold irq_lock to avoid a race with enable/disable_vblank().
1771 	*/
1772 	spin_lock(&vop->irq_lock);
1773 
1774 	active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1775 	/* Clear all active interrupt sources */
1776 	if (active_irqs)
1777 		VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1778 
1779 	spin_unlock(&vop->irq_lock);
1780 
1781 	/* This is expected for vop iommu irqs, since the irq is shared */
1782 	if (!active_irqs)
1783 		goto out_disable;
1784 
1785 	if (active_irqs & DSP_HOLD_VALID_INTR) {
1786 		complete(&vop->dsp_hold_completion);
1787 		active_irqs &= ~DSP_HOLD_VALID_INTR;
1788 		ret = IRQ_HANDLED;
1789 	}
1790 
1791 	if (active_irqs & LINE_FLAG_INTR) {
1792 		complete(&vop->line_flag_completion);
1793 		active_irqs &= ~LINE_FLAG_INTR;
1794 		ret = IRQ_HANDLED;
1795 	}
1796 
1797 	if (active_irqs & FS_INTR) {
1798 		drm_crtc_handle_vblank(crtc);
1799 		vop_handle_vblank(vop);
1800 		active_irqs &= ~FS_INTR;
1801 		ret = IRQ_HANDLED;
1802 	}
1803 
1804 	/* Unhandled irqs are spurious. */
1805 	if (active_irqs)
1806 		DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1807 			      active_irqs);
1808 
1809 out_disable:
1810 	vop_core_clks_disable(vop);
1811 out:
1812 	pm_runtime_put(vop->dev);
1813 	return ret;
1814 }
1815 
1816 static void vop_plane_add_properties(struct drm_plane *plane,
1817 				     const struct vop_win_data *win_data)
1818 {
1819 	unsigned int flags = 0;
1820 
1821 	flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1822 	flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1823 	if (flags)
1824 		drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1825 						   DRM_MODE_ROTATE_0 | flags);
1826 }
1827 
1828 static int vop_create_crtc(struct vop *vop)
1829 {
1830 	const struct vop_data *vop_data = vop->data;
1831 	struct device *dev = vop->dev;
1832 	struct drm_device *drm_dev = vop->drm_dev;
1833 	struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1834 	struct drm_crtc *crtc = &vop->crtc;
1835 	struct device_node *port;
1836 	int ret;
1837 	int i;
1838 
1839 	/*
1840 	 * Create drm_plane for primary and cursor planes first, since we need
1841 	 * to pass them to drm_crtc_init_with_planes, which sets the
1842 	 * "possible_crtcs" to the newly initialized crtc.
1843 	 */
1844 	for (i = 0; i < vop_data->win_size; i++) {
1845 		struct vop_win *vop_win = &vop->win[i];
1846 		const struct vop_win_data *win_data = vop_win->data;
1847 
1848 		if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1849 		    win_data->type != DRM_PLANE_TYPE_CURSOR)
1850 			continue;
1851 
1852 		ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1853 					       0, &vop_plane_funcs,
1854 					       win_data->phy->data_formats,
1855 					       win_data->phy->nformats,
1856 					       win_data->phy->format_modifiers,
1857 					       win_data->type, NULL);
1858 		if (ret) {
1859 			DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1860 				      ret);
1861 			goto err_cleanup_planes;
1862 		}
1863 
1864 		plane = &vop_win->base;
1865 		drm_plane_helper_add(plane, &plane_helper_funcs);
1866 		vop_plane_add_properties(plane, win_data);
1867 		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1868 			primary = plane;
1869 		else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1870 			cursor = plane;
1871 	}
1872 
1873 	ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1874 					&vop_crtc_funcs, NULL);
1875 	if (ret)
1876 		goto err_cleanup_planes;
1877 
1878 	drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1879 	if (vop->lut_regs) {
1880 		drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size);
1881 		drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1882 	}
1883 
1884 	/*
1885 	 * Create drm_planes for overlay windows with possible_crtcs restricted
1886 	 * to the newly created crtc.
1887 	 */
1888 	for (i = 0; i < vop_data->win_size; i++) {
1889 		struct vop_win *vop_win = &vop->win[i];
1890 		const struct vop_win_data *win_data = vop_win->data;
1891 		unsigned long possible_crtcs = drm_crtc_mask(crtc);
1892 
1893 		if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1894 			continue;
1895 
1896 		ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1897 					       possible_crtcs,
1898 					       &vop_plane_funcs,
1899 					       win_data->phy->data_formats,
1900 					       win_data->phy->nformats,
1901 					       win_data->phy->format_modifiers,
1902 					       win_data->type, NULL);
1903 		if (ret) {
1904 			DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1905 				      ret);
1906 			goto err_cleanup_crtc;
1907 		}
1908 		drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1909 		vop_plane_add_properties(&vop_win->base, win_data);
1910 	}
1911 
1912 	port = of_get_child_by_name(dev->of_node, "port");
1913 	if (!port) {
1914 		DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1915 			      dev->of_node);
1916 		ret = -ENOENT;
1917 		goto err_cleanup_crtc;
1918 	}
1919 
1920 	drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1921 			   vop_fb_unref_worker);
1922 
1923 	init_completion(&vop->dsp_hold_completion);
1924 	init_completion(&vop->line_flag_completion);
1925 	crtc->port = port;
1926 
1927 	ret = drm_self_refresh_helper_init(crtc);
1928 	if (ret)
1929 		DRM_DEV_DEBUG_KMS(vop->dev,
1930 			"Failed to init %s with SR helpers %d, ignoring\n",
1931 			crtc->name, ret);
1932 
1933 	return 0;
1934 
1935 err_cleanup_crtc:
1936 	drm_crtc_cleanup(crtc);
1937 err_cleanup_planes:
1938 	list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1939 				 head)
1940 		drm_plane_cleanup(plane);
1941 	return ret;
1942 }
1943 
1944 static void vop_destroy_crtc(struct vop *vop)
1945 {
1946 	struct drm_crtc *crtc = &vop->crtc;
1947 	struct drm_device *drm_dev = vop->drm_dev;
1948 	struct drm_plane *plane, *tmp;
1949 
1950 	drm_self_refresh_helper_cleanup(crtc);
1951 
1952 	of_node_put(crtc->port);
1953 
1954 	/*
1955 	 * We need to cleanup the planes now.  Why?
1956 	 *
1957 	 * The planes are "&vop->win[i].base".  That means the memory is
1958 	 * all part of the big "struct vop" chunk of memory.  That memory
1959 	 * was devm allocated and associated with this component.  We need to
1960 	 * free it ourselves before vop_unbind() finishes.
1961 	 */
1962 	list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1963 				 head)
1964 		vop_plane_destroy(plane);
1965 
1966 	/*
1967 	 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1968 	 * references the CRTC.
1969 	 */
1970 	drm_crtc_cleanup(crtc);
1971 	drm_flip_work_cleanup(&vop->fb_unref_work);
1972 }
1973 
1974 static int vop_initial(struct vop *vop)
1975 {
1976 	struct reset_control *ahb_rst;
1977 	int i, ret;
1978 
1979 	vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1980 	if (IS_ERR(vop->hclk)) {
1981 		DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1982 		return PTR_ERR(vop->hclk);
1983 	}
1984 	vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1985 	if (IS_ERR(vop->aclk)) {
1986 		DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1987 		return PTR_ERR(vop->aclk);
1988 	}
1989 	vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1990 	if (IS_ERR(vop->dclk)) {
1991 		DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1992 		return PTR_ERR(vop->dclk);
1993 	}
1994 
1995 	ret = pm_runtime_resume_and_get(vop->dev);
1996 	if (ret < 0) {
1997 		DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1998 		return ret;
1999 	}
2000 
2001 	ret = clk_prepare(vop->dclk);
2002 	if (ret < 0) {
2003 		DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
2004 		goto err_put_pm_runtime;
2005 	}
2006 
2007 	/* Enable both the hclk and aclk to setup the vop */
2008 	ret = clk_prepare_enable(vop->hclk);
2009 	if (ret < 0) {
2010 		DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
2011 		goto err_unprepare_dclk;
2012 	}
2013 
2014 	ret = clk_prepare_enable(vop->aclk);
2015 	if (ret < 0) {
2016 		DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
2017 		goto err_disable_hclk;
2018 	}
2019 
2020 	/*
2021 	 * do hclk_reset, reset all vop registers.
2022 	 */
2023 	ahb_rst = devm_reset_control_get(vop->dev, "ahb");
2024 	if (IS_ERR(ahb_rst)) {
2025 		DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
2026 		ret = PTR_ERR(ahb_rst);
2027 		goto err_disable_aclk;
2028 	}
2029 	reset_control_assert(ahb_rst);
2030 	usleep_range(10, 20);
2031 	reset_control_deassert(ahb_rst);
2032 
2033 	VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
2034 	VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
2035 
2036 	for (i = 0; i < vop->len; i += sizeof(u32))
2037 		vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
2038 
2039 	VOP_REG_SET(vop, misc, global_regdone_en, 1);
2040 	VOP_REG_SET(vop, common, dsp_blank, 0);
2041 
2042 	for (i = 0; i < vop->data->win_size; i++) {
2043 		struct vop_win *vop_win = &vop->win[i];
2044 		const struct vop_win_data *win = vop_win->data;
2045 		int channel = i * 2 + 1;
2046 
2047 		VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
2048 		vop_win_disable(vop, vop_win);
2049 		VOP_WIN_SET(vop, win, gate, 1);
2050 	}
2051 
2052 	vop_cfg_done(vop);
2053 
2054 	/*
2055 	 * do dclk_reset, let all config take affect.
2056 	 */
2057 	vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
2058 	if (IS_ERR(vop->dclk_rst)) {
2059 		DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
2060 		ret = PTR_ERR(vop->dclk_rst);
2061 		goto err_disable_aclk;
2062 	}
2063 	reset_control_assert(vop->dclk_rst);
2064 	usleep_range(10, 20);
2065 	reset_control_deassert(vop->dclk_rst);
2066 
2067 	clk_disable(vop->hclk);
2068 	clk_disable(vop->aclk);
2069 
2070 	vop->is_enabled = false;
2071 
2072 	pm_runtime_put_sync(vop->dev);
2073 
2074 	return 0;
2075 
2076 err_disable_aclk:
2077 	clk_disable_unprepare(vop->aclk);
2078 err_disable_hclk:
2079 	clk_disable_unprepare(vop->hclk);
2080 err_unprepare_dclk:
2081 	clk_unprepare(vop->dclk);
2082 err_put_pm_runtime:
2083 	pm_runtime_put_sync(vop->dev);
2084 	return ret;
2085 }
2086 
2087 /*
2088  * Initialize the vop->win array elements.
2089  */
2090 static void vop_win_init(struct vop *vop)
2091 {
2092 	const struct vop_data *vop_data = vop->data;
2093 	unsigned int i;
2094 
2095 	for (i = 0; i < vop_data->win_size; i++) {
2096 		struct vop_win *vop_win = &vop->win[i];
2097 		const struct vop_win_data *win_data = &vop_data->win[i];
2098 
2099 		vop_win->data = win_data;
2100 		vop_win->vop = vop;
2101 
2102 		if (vop_data->win_yuv2yuv)
2103 			vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2104 	}
2105 }
2106 
2107 /**
2108  * rockchip_drm_wait_vact_end
2109  * @crtc: CRTC to enable line flag
2110  * @mstimeout: millisecond for timeout
2111  *
2112  * Wait for vact_end line flag irq or timeout.
2113  *
2114  * Returns:
2115  * Zero on success, negative errno on failure.
2116  */
2117 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
2118 {
2119 	struct vop *vop = to_vop(crtc);
2120 	unsigned long jiffies_left;
2121 	int ret = 0;
2122 
2123 	if (!crtc || !vop->is_enabled)
2124 		return -ENODEV;
2125 
2126 	mutex_lock(&vop->vop_lock);
2127 	if (mstimeout <= 0) {
2128 		ret = -EINVAL;
2129 		goto out;
2130 	}
2131 
2132 	if (vop_line_flag_irq_is_enabled(vop)) {
2133 		ret = -EBUSY;
2134 		goto out;
2135 	}
2136 
2137 	reinit_completion(&vop->line_flag_completion);
2138 	vop_line_flag_irq_enable(vop);
2139 
2140 	jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2141 						   msecs_to_jiffies(mstimeout));
2142 	vop_line_flag_irq_disable(vop);
2143 
2144 	if (jiffies_left == 0) {
2145 		DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2146 		ret = -ETIMEDOUT;
2147 		goto out;
2148 	}
2149 
2150 out:
2151 	mutex_unlock(&vop->vop_lock);
2152 	return ret;
2153 }
2154 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
2155 
2156 static int vop_bind(struct device *dev, struct device *master, void *data)
2157 {
2158 	struct platform_device *pdev = to_platform_device(dev);
2159 	const struct vop_data *vop_data;
2160 	struct drm_device *drm_dev = data;
2161 	struct vop *vop;
2162 	struct resource *res;
2163 	int ret, irq;
2164 
2165 	vop_data = of_device_get_match_data(dev);
2166 	if (!vop_data)
2167 		return -ENODEV;
2168 
2169 	/* Allocate vop struct and its vop_win array */
2170 	vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2171 			   GFP_KERNEL);
2172 	if (!vop)
2173 		return -ENOMEM;
2174 
2175 	vop->dev = dev;
2176 	vop->data = vop_data;
2177 	vop->drm_dev = drm_dev;
2178 	dev_set_drvdata(dev, vop);
2179 
2180 	vop_win_init(vop);
2181 
2182 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2183 	vop->regs = devm_ioremap_resource(dev, res);
2184 	if (IS_ERR(vop->regs))
2185 		return PTR_ERR(vop->regs);
2186 	vop->len = resource_size(res);
2187 
2188 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2189 	if (res) {
2190 		if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) {
2191 			DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size);
2192 			return -EINVAL;
2193 		}
2194 		vop->lut_regs = devm_ioremap_resource(dev, res);
2195 		if (IS_ERR(vop->lut_regs))
2196 			return PTR_ERR(vop->lut_regs);
2197 	}
2198 
2199 	vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2200 	if (!vop->regsbak)
2201 		return -ENOMEM;
2202 
2203 	irq = platform_get_irq(pdev, 0);
2204 	if (irq < 0) {
2205 		DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2206 		return irq;
2207 	}
2208 	vop->irq = (unsigned int)irq;
2209 
2210 	spin_lock_init(&vop->reg_lock);
2211 	spin_lock_init(&vop->irq_lock);
2212 	mutex_init(&vop->vop_lock);
2213 
2214 	ret = vop_create_crtc(vop);
2215 	if (ret)
2216 		return ret;
2217 
2218 	pm_runtime_enable(&pdev->dev);
2219 
2220 	ret = vop_initial(vop);
2221 	if (ret < 0) {
2222 		DRM_DEV_ERROR(&pdev->dev,
2223 			      "cannot initial vop dev - err %d\n", ret);
2224 		goto err_disable_pm_runtime;
2225 	}
2226 
2227 	ret = devm_request_irq(dev, vop->irq, vop_isr,
2228 			       IRQF_SHARED, dev_name(dev), vop);
2229 	if (ret)
2230 		goto err_disable_pm_runtime;
2231 
2232 	if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2233 		vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0);
2234 		if (IS_ERR(vop->rgb)) {
2235 			ret = PTR_ERR(vop->rgb);
2236 			goto err_disable_pm_runtime;
2237 		}
2238 	}
2239 
2240 	rockchip_drm_dma_init_device(drm_dev, dev);
2241 
2242 	return 0;
2243 
2244 err_disable_pm_runtime:
2245 	pm_runtime_disable(&pdev->dev);
2246 	vop_destroy_crtc(vop);
2247 	return ret;
2248 }
2249 
2250 static void vop_unbind(struct device *dev, struct device *master, void *data)
2251 {
2252 	struct vop *vop = dev_get_drvdata(dev);
2253 
2254 	if (vop->rgb)
2255 		rockchip_rgb_fini(vop->rgb);
2256 
2257 	pm_runtime_disable(dev);
2258 	vop_destroy_crtc(vop);
2259 
2260 	clk_unprepare(vop->aclk);
2261 	clk_unprepare(vop->hclk);
2262 	clk_unprepare(vop->dclk);
2263 }
2264 
2265 const struct component_ops vop_component_ops = {
2266 	.bind = vop_bind,
2267 	.unbind = vop_unbind,
2268 };
2269 EXPORT_SYMBOL_GPL(vop_component_ops);
2270