1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_uapi.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_flip_work.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_gem_framebuffer_helper.h> 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_probe_helper.h> 29 #include <drm/drm_self_refresh_helper.h> 30 #include <drm/drm_vblank.h> 31 32 #ifdef CONFIG_DRM_ANALOGIX_DP 33 #include <drm/bridge/analogix_dp.h> 34 #endif 35 36 #include "rockchip_drm_drv.h" 37 #include "rockchip_drm_gem.h" 38 #include "rockchip_drm_fb.h" 39 #include "rockchip_drm_vop.h" 40 #include "rockchip_rgb.h" 41 42 #define VOP_WIN_SET(vop, win, name, v) \ 43 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 44 #define VOP_SCL_SET(vop, win, name, v) \ 45 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 46 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 47 vop_reg_set(vop, &win->phy->scl->ext->name, \ 48 win->base, ~0, v, #name) 49 50 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 51 do { \ 52 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 53 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 54 } while (0) 55 56 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 57 do { \ 58 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 59 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 60 } while (0) 61 62 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 63 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 64 65 #define VOP_REG_SET(vop, group, name, v) \ 66 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 67 68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 69 do { \ 70 int i, reg = 0, mask = 0; \ 71 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 72 if (vop->data->intr->intrs[i] & type) { \ 73 reg |= (v) << i; \ 74 mask |= 1 << i; \ 75 } \ 76 } \ 77 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 78 } while (0) 79 #define VOP_INTR_GET_TYPE(vop, name, type) \ 80 vop_get_intr_type(vop, &vop->data->intr->name, type) 81 82 #define VOP_WIN_GET(vop, win, name) \ 83 vop_read_reg(vop, win->base, &win->phy->name) 84 85 #define VOP_WIN_HAS_REG(win, name) \ 86 (!!(win->phy->name.mask)) 87 88 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 89 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 90 91 #define VOP_WIN_TO_INDEX(vop_win) \ 92 ((vop_win) - (vop_win)->vop->win) 93 94 #define VOP_AFBC_SET(vop, name, v) \ 95 do { \ 96 if ((vop)->data->afbc) \ 97 vop_reg_set((vop), &(vop)->data->afbc->name, \ 98 0, ~0, v, #name); \ 99 } while (0) 100 101 #define to_vop(x) container_of(x, struct vop, crtc) 102 #define to_vop_win(x) container_of(x, struct vop_win, base) 103 104 #define AFBC_FMT_RGB565 0x0 105 #define AFBC_FMT_U8U8U8U8 0x5 106 #define AFBC_FMT_U8U8U8 0x4 107 108 #define AFBC_TILE_16x16 BIT(4) 109 110 /* 111 * The coefficients of the following matrix are all fixed points. 112 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 113 * They are all represented in two's complement. 114 */ 115 static const uint32_t bt601_yuv2rgb[] = { 116 0x4A8, 0x0, 0x662, 117 0x4A8, 0x1E6F, 0x1CBF, 118 0x4A8, 0x812, 0x0, 119 0x321168, 0x0877CF, 0x2EB127 120 }; 121 122 enum vop_pending { 123 VOP_PENDING_FB_UNREF, 124 }; 125 126 struct vop_win { 127 struct drm_plane base; 128 const struct vop_win_data *data; 129 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 130 struct vop *vop; 131 }; 132 133 struct rockchip_rgb; 134 struct vop { 135 struct drm_crtc crtc; 136 struct device *dev; 137 struct drm_device *drm_dev; 138 bool is_enabled; 139 140 struct completion dsp_hold_completion; 141 unsigned int win_enabled; 142 143 /* protected by dev->event_lock */ 144 struct drm_pending_vblank_event *event; 145 146 struct drm_flip_work fb_unref_work; 147 unsigned long pending; 148 149 struct completion line_flag_completion; 150 151 const struct vop_data *data; 152 153 uint32_t *regsbak; 154 void __iomem *regs; 155 void __iomem *lut_regs; 156 157 /* physical map length of vop register */ 158 uint32_t len; 159 160 /* one time only one process allowed to config the register */ 161 spinlock_t reg_lock; 162 /* lock vop irq reg */ 163 spinlock_t irq_lock; 164 /* protects crtc enable/disable */ 165 struct mutex vop_lock; 166 167 unsigned int irq; 168 169 /* vop AHP clk */ 170 struct clk *hclk; 171 /* vop dclk */ 172 struct clk *dclk; 173 /* vop share memory frequency */ 174 struct clk *aclk; 175 176 /* vop dclk reset */ 177 struct reset_control *dclk_rst; 178 179 /* optional internal rgb encoder */ 180 struct rockchip_rgb *rgb; 181 182 struct vop_win win[]; 183 }; 184 185 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 186 { 187 writel(v, vop->regs + offset); 188 vop->regsbak[offset >> 2] = v; 189 } 190 191 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 192 { 193 return readl(vop->regs + offset); 194 } 195 196 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 197 const struct vop_reg *reg) 198 { 199 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 200 } 201 202 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 203 uint32_t _offset, uint32_t _mask, uint32_t v, 204 const char *reg_name) 205 { 206 int offset, mask, shift; 207 208 if (!reg || !reg->mask) { 209 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 210 return; 211 } 212 213 offset = reg->offset + _offset; 214 mask = reg->mask & _mask; 215 shift = reg->shift; 216 217 if (reg->write_mask) { 218 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 219 } else { 220 uint32_t cached_val = vop->regsbak[offset >> 2]; 221 222 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 223 vop->regsbak[offset >> 2] = v; 224 } 225 226 if (reg->relaxed) 227 writel_relaxed(v, vop->regs + offset); 228 else 229 writel(v, vop->regs + offset); 230 } 231 232 static inline uint32_t vop_get_intr_type(struct vop *vop, 233 const struct vop_reg *reg, int type) 234 { 235 uint32_t i, ret = 0; 236 uint32_t regs = vop_read_reg(vop, 0, reg); 237 238 for (i = 0; i < vop->data->intr->nintrs; i++) { 239 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 240 ret |= vop->data->intr->intrs[i]; 241 } 242 243 return ret; 244 } 245 246 static inline void vop_cfg_done(struct vop *vop) 247 { 248 VOP_REG_SET(vop, common, cfg_done, 1); 249 } 250 251 static bool has_rb_swapped(uint32_t format) 252 { 253 switch (format) { 254 case DRM_FORMAT_XBGR8888: 255 case DRM_FORMAT_ABGR8888: 256 case DRM_FORMAT_BGR888: 257 case DRM_FORMAT_BGR565: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static enum vop_data_format vop_convert_format(uint32_t format) 265 { 266 switch (format) { 267 case DRM_FORMAT_XRGB8888: 268 case DRM_FORMAT_ARGB8888: 269 case DRM_FORMAT_XBGR8888: 270 case DRM_FORMAT_ABGR8888: 271 return VOP_FMT_ARGB8888; 272 case DRM_FORMAT_RGB888: 273 case DRM_FORMAT_BGR888: 274 return VOP_FMT_RGB888; 275 case DRM_FORMAT_RGB565: 276 case DRM_FORMAT_BGR565: 277 return VOP_FMT_RGB565; 278 case DRM_FORMAT_NV12: 279 return VOP_FMT_YUV420SP; 280 case DRM_FORMAT_NV16: 281 return VOP_FMT_YUV422SP; 282 case DRM_FORMAT_NV24: 283 return VOP_FMT_YUV444SP; 284 default: 285 DRM_ERROR("unsupported format[%08x]\n", format); 286 return -EINVAL; 287 } 288 } 289 290 static int vop_convert_afbc_format(uint32_t format) 291 { 292 switch (format) { 293 case DRM_FORMAT_XRGB8888: 294 case DRM_FORMAT_ARGB8888: 295 case DRM_FORMAT_XBGR8888: 296 case DRM_FORMAT_ABGR8888: 297 return AFBC_FMT_U8U8U8U8; 298 case DRM_FORMAT_RGB888: 299 case DRM_FORMAT_BGR888: 300 return AFBC_FMT_U8U8U8; 301 case DRM_FORMAT_RGB565: 302 case DRM_FORMAT_BGR565: 303 return AFBC_FMT_RGB565; 304 /* either of the below should not be reachable */ 305 default: 306 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); 307 return -EINVAL; 308 } 309 310 return -EINVAL; 311 } 312 313 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 314 uint32_t dst, bool is_horizontal, 315 int vsu_mode, int *vskiplines) 316 { 317 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 318 319 if (vskiplines) 320 *vskiplines = 0; 321 322 if (is_horizontal) { 323 if (mode == SCALE_UP) 324 val = GET_SCL_FT_BIC(src, dst); 325 else if (mode == SCALE_DOWN) 326 val = GET_SCL_FT_BILI_DN(src, dst); 327 } else { 328 if (mode == SCALE_UP) { 329 if (vsu_mode == SCALE_UP_BIL) 330 val = GET_SCL_FT_BILI_UP(src, dst); 331 else 332 val = GET_SCL_FT_BIC(src, dst); 333 } else if (mode == SCALE_DOWN) { 334 if (vskiplines) { 335 *vskiplines = scl_get_vskiplines(src, dst); 336 val = scl_get_bili_dn_vskip(src, dst, 337 *vskiplines); 338 } else { 339 val = GET_SCL_FT_BILI_DN(src, dst); 340 } 341 } 342 } 343 344 return val; 345 } 346 347 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 348 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 349 uint32_t dst_h, const struct drm_format_info *info) 350 { 351 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 352 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 353 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 354 bool is_yuv = false; 355 uint16_t cbcr_src_w = src_w / info->hsub; 356 uint16_t cbcr_src_h = src_h / info->vsub; 357 uint16_t vsu_mode; 358 uint16_t lb_mode; 359 uint32_t val; 360 int vskiplines; 361 362 if (info->is_yuv) 363 is_yuv = true; 364 365 if (dst_w > 3840) { 366 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 367 return; 368 } 369 370 if (!win->phy->scl->ext) { 371 VOP_SCL_SET(vop, win, scale_yrgb_x, 372 scl_cal_scale2(src_w, dst_w)); 373 VOP_SCL_SET(vop, win, scale_yrgb_y, 374 scl_cal_scale2(src_h, dst_h)); 375 if (is_yuv) { 376 VOP_SCL_SET(vop, win, scale_cbcr_x, 377 scl_cal_scale2(cbcr_src_w, dst_w)); 378 VOP_SCL_SET(vop, win, scale_cbcr_y, 379 scl_cal_scale2(cbcr_src_h, dst_h)); 380 } 381 return; 382 } 383 384 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 385 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 386 387 if (is_yuv) { 388 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 389 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 390 if (cbcr_hor_scl_mode == SCALE_DOWN) 391 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 392 else 393 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 394 } else { 395 if (yrgb_hor_scl_mode == SCALE_DOWN) 396 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 397 else 398 lb_mode = scl_vop_cal_lb_mode(src_w, false); 399 } 400 401 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 402 if (lb_mode == LB_RGB_3840X2) { 403 if (yrgb_ver_scl_mode != SCALE_NONE) { 404 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 405 return; 406 } 407 if (cbcr_ver_scl_mode != SCALE_NONE) { 408 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 409 return; 410 } 411 vsu_mode = SCALE_UP_BIL; 412 } else if (lb_mode == LB_RGB_2560X4) { 413 vsu_mode = SCALE_UP_BIL; 414 } else { 415 vsu_mode = SCALE_UP_BIC; 416 } 417 418 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 419 true, 0, NULL); 420 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 421 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 422 false, vsu_mode, &vskiplines); 423 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 424 425 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 426 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 427 428 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 429 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 430 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 431 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 432 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 433 if (is_yuv) { 434 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 435 dst_w, true, 0, NULL); 436 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 437 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 438 dst_h, false, vsu_mode, &vskiplines); 439 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 440 441 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 442 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 443 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 444 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 445 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 446 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 447 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 448 } 449 } 450 451 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 452 { 453 unsigned long flags; 454 455 if (WARN_ON(!vop->is_enabled)) 456 return; 457 458 spin_lock_irqsave(&vop->irq_lock, flags); 459 460 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 461 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 462 463 spin_unlock_irqrestore(&vop->irq_lock, flags); 464 } 465 466 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 467 { 468 unsigned long flags; 469 470 if (WARN_ON(!vop->is_enabled)) 471 return; 472 473 spin_lock_irqsave(&vop->irq_lock, flags); 474 475 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 476 477 spin_unlock_irqrestore(&vop->irq_lock, flags); 478 } 479 480 /* 481 * (1) each frame starts at the start of the Vsync pulse which is signaled by 482 * the "FRAME_SYNC" interrupt. 483 * (2) the active data region of each frame ends at dsp_vact_end 484 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 485 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 486 * 487 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 488 * Interrupts 489 * LINE_FLAG -------------------------------+ 490 * FRAME_SYNC ----+ | 491 * | | 492 * v v 493 * | Vsync | Vbp | Vactive | Vfp | 494 * ^ ^ ^ ^ 495 * | | | | 496 * | | | | 497 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 498 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 499 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 500 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 501 */ 502 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 503 { 504 uint32_t line_flag_irq; 505 unsigned long flags; 506 507 spin_lock_irqsave(&vop->irq_lock, flags); 508 509 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 510 511 spin_unlock_irqrestore(&vop->irq_lock, flags); 512 513 return !!line_flag_irq; 514 } 515 516 static void vop_line_flag_irq_enable(struct vop *vop) 517 { 518 unsigned long flags; 519 520 if (WARN_ON(!vop->is_enabled)) 521 return; 522 523 spin_lock_irqsave(&vop->irq_lock, flags); 524 525 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 526 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 527 528 spin_unlock_irqrestore(&vop->irq_lock, flags); 529 } 530 531 static void vop_line_flag_irq_disable(struct vop *vop) 532 { 533 unsigned long flags; 534 535 if (WARN_ON(!vop->is_enabled)) 536 return; 537 538 spin_lock_irqsave(&vop->irq_lock, flags); 539 540 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 541 542 spin_unlock_irqrestore(&vop->irq_lock, flags); 543 } 544 545 static int vop_core_clks_enable(struct vop *vop) 546 { 547 int ret; 548 549 ret = clk_enable(vop->hclk); 550 if (ret < 0) 551 return ret; 552 553 ret = clk_enable(vop->aclk); 554 if (ret < 0) 555 goto err_disable_hclk; 556 557 return 0; 558 559 err_disable_hclk: 560 clk_disable(vop->hclk); 561 return ret; 562 } 563 564 static void vop_core_clks_disable(struct vop *vop) 565 { 566 clk_disable(vop->aclk); 567 clk_disable(vop->hclk); 568 } 569 570 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 571 { 572 const struct vop_win_data *win = vop_win->data; 573 574 if (win->phy->scl && win->phy->scl->ext) { 575 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 576 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 577 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 578 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 579 } 580 581 VOP_WIN_SET(vop, win, enable, 0); 582 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 583 } 584 585 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 586 { 587 struct vop *vop = to_vop(crtc); 588 int ret, i; 589 590 ret = pm_runtime_get_sync(vop->dev); 591 if (ret < 0) { 592 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 593 return ret; 594 } 595 596 ret = vop_core_clks_enable(vop); 597 if (WARN_ON(ret < 0)) 598 goto err_put_pm_runtime; 599 600 ret = clk_enable(vop->dclk); 601 if (WARN_ON(ret < 0)) 602 goto err_disable_core; 603 604 /* 605 * Slave iommu shares power, irq and clock with vop. It was associated 606 * automatically with this master device via common driver code. 607 * Now that we have enabled the clock we attach it to the shared drm 608 * mapping. 609 */ 610 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 611 if (ret) { 612 DRM_DEV_ERROR(vop->dev, 613 "failed to attach dma mapping, %d\n", ret); 614 goto err_disable_dclk; 615 } 616 617 spin_lock(&vop->reg_lock); 618 for (i = 0; i < vop->len; i += 4) 619 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 620 621 /* 622 * We need to make sure that all windows are disabled before we 623 * enable the crtc. Otherwise we might try to scan from a destroyed 624 * buffer later. 625 * 626 * In the case of enable-after-PSR, we don't need to worry about this 627 * case since the buffer is guaranteed to be valid and disabling the 628 * window will result in screen glitches on PSR exit. 629 */ 630 if (!old_state || !old_state->self_refresh_active) { 631 for (i = 0; i < vop->data->win_size; i++) { 632 struct vop_win *vop_win = &vop->win[i]; 633 634 vop_win_disable(vop, vop_win); 635 } 636 } 637 638 if (vop->data->afbc) { 639 struct rockchip_crtc_state *s; 640 /* 641 * Disable AFBC and forget there was a vop window with AFBC 642 */ 643 VOP_AFBC_SET(vop, enable, 0); 644 s = to_rockchip_crtc_state(crtc->state); 645 s->enable_afbc = false; 646 } 647 648 vop_cfg_done(vop); 649 650 spin_unlock(&vop->reg_lock); 651 652 /* 653 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 654 */ 655 vop->is_enabled = true; 656 657 spin_lock(&vop->reg_lock); 658 659 VOP_REG_SET(vop, common, standby, 1); 660 661 spin_unlock(&vop->reg_lock); 662 663 drm_crtc_vblank_on(crtc); 664 665 return 0; 666 667 err_disable_dclk: 668 clk_disable(vop->dclk); 669 err_disable_core: 670 vop_core_clks_disable(vop); 671 err_put_pm_runtime: 672 pm_runtime_put_sync(vop->dev); 673 return ret; 674 } 675 676 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 677 { 678 struct vop *vop = to_vop(crtc); 679 int i; 680 681 spin_lock(&vop->reg_lock); 682 683 for (i = 0; i < vop->data->win_size; i++) { 684 struct vop_win *vop_win = &vop->win[i]; 685 const struct vop_win_data *win = vop_win->data; 686 687 VOP_WIN_SET(vop, win, enable, 688 enabled && (vop->win_enabled & BIT(i))); 689 } 690 vop_cfg_done(vop); 691 692 spin_unlock(&vop->reg_lock); 693 } 694 695 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 696 struct drm_atomic_state *state) 697 { 698 struct vop *vop = to_vop(crtc); 699 700 WARN_ON(vop->event); 701 702 if (crtc->state->self_refresh_active) 703 rockchip_drm_set_win_enabled(crtc, false); 704 705 mutex_lock(&vop->vop_lock); 706 707 drm_crtc_vblank_off(crtc); 708 709 if (crtc->state->self_refresh_active) 710 goto out; 711 712 /* 713 * Vop standby will take effect at end of current frame, 714 * if dsp hold valid irq happen, it means standby complete. 715 * 716 * we must wait standby complete when we want to disable aclk, 717 * if not, memory bus maybe dead. 718 */ 719 reinit_completion(&vop->dsp_hold_completion); 720 vop_dsp_hold_valid_irq_enable(vop); 721 722 spin_lock(&vop->reg_lock); 723 724 VOP_REG_SET(vop, common, standby, 1); 725 726 spin_unlock(&vop->reg_lock); 727 728 wait_for_completion(&vop->dsp_hold_completion); 729 730 vop_dsp_hold_valid_irq_disable(vop); 731 732 vop->is_enabled = false; 733 734 /* 735 * vop standby complete, so iommu detach is safe. 736 */ 737 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 738 739 clk_disable(vop->dclk); 740 vop_core_clks_disable(vop); 741 pm_runtime_put(vop->dev); 742 743 out: 744 mutex_unlock(&vop->vop_lock); 745 746 if (crtc->state->event && !crtc->state->active) { 747 spin_lock_irq(&crtc->dev->event_lock); 748 drm_crtc_send_vblank_event(crtc, crtc->state->event); 749 spin_unlock_irq(&crtc->dev->event_lock); 750 751 crtc->state->event = NULL; 752 } 753 } 754 755 static void vop_plane_destroy(struct drm_plane *plane) 756 { 757 drm_plane_cleanup(plane); 758 } 759 760 static inline bool rockchip_afbc(u64 modifier) 761 { 762 return modifier == ROCKCHIP_AFBC_MOD; 763 } 764 765 static bool rockchip_mod_supported(struct drm_plane *plane, 766 u32 format, u64 modifier) 767 { 768 if (modifier == DRM_FORMAT_MOD_LINEAR) 769 return true; 770 771 if (!rockchip_afbc(modifier)) { 772 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 773 774 return false; 775 } 776 777 return vop_convert_afbc_format(format) >= 0; 778 } 779 780 static int vop_plane_atomic_check(struct drm_plane *plane, 781 struct drm_plane_state *state) 782 { 783 struct drm_crtc *crtc = state->crtc; 784 struct drm_crtc_state *crtc_state; 785 struct drm_framebuffer *fb = state->fb; 786 struct vop_win *vop_win = to_vop_win(plane); 787 const struct vop_win_data *win = vop_win->data; 788 int ret; 789 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 790 DRM_PLANE_HELPER_NO_SCALING; 791 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 792 DRM_PLANE_HELPER_NO_SCALING; 793 794 if (!crtc || WARN_ON(!fb)) 795 return 0; 796 797 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 798 if (WARN_ON(!crtc_state)) 799 return -EINVAL; 800 801 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 802 min_scale, max_scale, 803 true, true); 804 if (ret) 805 return ret; 806 807 if (!state->visible) 808 return 0; 809 810 ret = vop_convert_format(fb->format->format); 811 if (ret < 0) 812 return ret; 813 814 /* 815 * Src.x1 can be odd when do clip, but yuv plane start point 816 * need align with 2 pixel. 817 */ 818 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 819 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 820 return -EINVAL; 821 } 822 823 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 824 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 825 return -EINVAL; 826 } 827 828 if (rockchip_afbc(fb->modifier)) { 829 struct vop *vop = to_vop(crtc); 830 831 if (!vop->data->afbc) { 832 DRM_ERROR("vop does not support AFBC\n"); 833 return -EINVAL; 834 } 835 836 ret = vop_convert_afbc_format(fb->format->format); 837 if (ret < 0) 838 return ret; 839 840 if (state->src.x1 || state->src.y1) { 841 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", state->src.x1, state->src.y1, fb->offsets[0]); 842 return -EINVAL; 843 } 844 845 if (state->rotation && state->rotation != DRM_MODE_ROTATE_0) { 846 DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 847 state->rotation); 848 return -EINVAL; 849 } 850 } 851 852 return 0; 853 } 854 855 static void vop_plane_atomic_disable(struct drm_plane *plane, 856 struct drm_plane_state *old_state) 857 { 858 struct vop_win *vop_win = to_vop_win(plane); 859 struct vop *vop = to_vop(old_state->crtc); 860 861 if (!old_state->crtc) 862 return; 863 864 spin_lock(&vop->reg_lock); 865 866 vop_win_disable(vop, vop_win); 867 868 spin_unlock(&vop->reg_lock); 869 } 870 871 static void vop_plane_atomic_update(struct drm_plane *plane, 872 struct drm_plane_state *old_state) 873 { 874 struct drm_plane_state *state = plane->state; 875 struct drm_crtc *crtc = state->crtc; 876 struct vop_win *vop_win = to_vop_win(plane); 877 const struct vop_win_data *win = vop_win->data; 878 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 879 struct vop *vop = to_vop(state->crtc); 880 struct drm_framebuffer *fb = state->fb; 881 unsigned int actual_w, actual_h; 882 unsigned int dsp_stx, dsp_sty; 883 uint32_t act_info, dsp_info, dsp_st; 884 struct drm_rect *src = &state->src; 885 struct drm_rect *dest = &state->dst; 886 struct drm_gem_object *obj, *uv_obj; 887 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 888 unsigned long offset; 889 dma_addr_t dma_addr; 890 uint32_t val; 891 bool rb_swap; 892 int win_index = VOP_WIN_TO_INDEX(vop_win); 893 int format; 894 int is_yuv = fb->format->is_yuv; 895 int i; 896 897 /* 898 * can't update plane when vop is disabled. 899 */ 900 if (WARN_ON(!crtc)) 901 return; 902 903 if (WARN_ON(!vop->is_enabled)) 904 return; 905 906 if (!state->visible) { 907 vop_plane_atomic_disable(plane, old_state); 908 return; 909 } 910 911 obj = fb->obj[0]; 912 rk_obj = to_rockchip_obj(obj); 913 914 actual_w = drm_rect_width(src) >> 16; 915 actual_h = drm_rect_height(src) >> 16; 916 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 917 918 dsp_info = (drm_rect_height(dest) - 1) << 16; 919 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 920 921 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 922 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 923 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 924 925 offset = (src->x1 >> 16) * fb->format->cpp[0]; 926 offset += (src->y1 >> 16) * fb->pitches[0]; 927 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 928 929 /* 930 * For y-mirroring we need to move address 931 * to the beginning of the last line. 932 */ 933 if (state->rotation & DRM_MODE_REFLECT_Y) 934 dma_addr += (actual_h - 1) * fb->pitches[0]; 935 936 format = vop_convert_format(fb->format->format); 937 938 spin_lock(&vop->reg_lock); 939 940 if (rockchip_afbc(fb->modifier)) { 941 int afbc_format = vop_convert_afbc_format(fb->format->format); 942 943 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 944 VOP_AFBC_SET(vop, hreg_block_split, 0); 945 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 946 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 947 VOP_AFBC_SET(vop, pic_size, act_info); 948 } 949 950 VOP_WIN_SET(vop, win, format, format); 951 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 952 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 953 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 954 VOP_WIN_SET(vop, win, y_mir_en, 955 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 956 VOP_WIN_SET(vop, win, x_mir_en, 957 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 958 959 if (is_yuv) { 960 int hsub = fb->format->hsub; 961 int vsub = fb->format->vsub; 962 int bpp = fb->format->cpp[1]; 963 964 uv_obj = fb->obj[1]; 965 rk_uv_obj = to_rockchip_obj(uv_obj); 966 967 offset = (src->x1 >> 16) * bpp / hsub; 968 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 969 970 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 971 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 972 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 973 974 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 975 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 976 win_yuv2yuv, 977 y2r_coefficients[i], 978 bt601_yuv2rgb[i]); 979 } 980 } 981 982 if (win->phy->scl) 983 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 984 drm_rect_width(dest), drm_rect_height(dest), 985 fb->format); 986 987 VOP_WIN_SET(vop, win, act_info, act_info); 988 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 989 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 990 991 rb_swap = has_rb_swapped(fb->format->format); 992 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 993 994 /* 995 * Blending win0 with the background color doesn't seem to work 996 * correctly. We only get the background color, no matter the contents 997 * of the win0 framebuffer. However, blending pre-multiplied color 998 * with the default opaque black default background color is a no-op, 999 * so we can just disable blending to get the correct result. 1000 */ 1001 if (fb->format->has_alpha && win_index > 0) { 1002 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1003 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1004 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1005 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1006 SRC_BLEND_M0(ALPHA_PER_PIX) | 1007 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1008 SRC_FACTOR_M0(ALPHA_ONE); 1009 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1010 1011 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1012 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1013 VOP_WIN_SET(vop, win, alpha_en, 1); 1014 } else { 1015 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1016 } 1017 1018 VOP_WIN_SET(vop, win, enable, 1); 1019 vop->win_enabled |= BIT(win_index); 1020 spin_unlock(&vop->reg_lock); 1021 } 1022 1023 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1024 struct drm_plane_state *state) 1025 { 1026 struct vop_win *vop_win = to_vop_win(plane); 1027 const struct vop_win_data *win = vop_win->data; 1028 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1029 DRM_PLANE_HELPER_NO_SCALING; 1030 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1031 DRM_PLANE_HELPER_NO_SCALING; 1032 struct drm_crtc_state *crtc_state; 1033 1034 if (plane != state->crtc->cursor) 1035 return -EINVAL; 1036 1037 if (!plane->state) 1038 return -EINVAL; 1039 1040 if (!plane->state->fb) 1041 return -EINVAL; 1042 1043 if (state->state) 1044 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 1045 state->crtc); 1046 else /* Special case for asynchronous cursor updates. */ 1047 crtc_state = plane->crtc->state; 1048 1049 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1050 min_scale, max_scale, 1051 true, true); 1052 } 1053 1054 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1055 struct drm_plane_state *new_state) 1056 { 1057 struct vop *vop = to_vop(plane->state->crtc); 1058 struct drm_framebuffer *old_fb = plane->state->fb; 1059 1060 plane->state->crtc_x = new_state->crtc_x; 1061 plane->state->crtc_y = new_state->crtc_y; 1062 plane->state->crtc_h = new_state->crtc_h; 1063 plane->state->crtc_w = new_state->crtc_w; 1064 plane->state->src_x = new_state->src_x; 1065 plane->state->src_y = new_state->src_y; 1066 plane->state->src_h = new_state->src_h; 1067 plane->state->src_w = new_state->src_w; 1068 swap(plane->state->fb, new_state->fb); 1069 1070 if (vop->is_enabled) { 1071 vop_plane_atomic_update(plane, plane->state); 1072 spin_lock(&vop->reg_lock); 1073 vop_cfg_done(vop); 1074 spin_unlock(&vop->reg_lock); 1075 1076 /* 1077 * A scanout can still be occurring, so we can't drop the 1078 * reference to the old framebuffer. To solve this we get a 1079 * reference to old_fb and set a worker to release it later. 1080 * FIXME: if we perform 500 async_update calls before the 1081 * vblank, then we can have 500 different framebuffers waiting 1082 * to be released. 1083 */ 1084 if (old_fb && plane->state->fb != old_fb) { 1085 drm_framebuffer_get(old_fb); 1086 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1087 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1088 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1089 } 1090 } 1091 } 1092 1093 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1094 .atomic_check = vop_plane_atomic_check, 1095 .atomic_update = vop_plane_atomic_update, 1096 .atomic_disable = vop_plane_atomic_disable, 1097 .atomic_async_check = vop_plane_atomic_async_check, 1098 .atomic_async_update = vop_plane_atomic_async_update, 1099 .prepare_fb = drm_gem_fb_prepare_fb, 1100 }; 1101 1102 static const struct drm_plane_funcs vop_plane_funcs = { 1103 .update_plane = drm_atomic_helper_update_plane, 1104 .disable_plane = drm_atomic_helper_disable_plane, 1105 .destroy = vop_plane_destroy, 1106 .reset = drm_atomic_helper_plane_reset, 1107 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1108 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1109 .format_mod_supported = rockchip_mod_supported, 1110 }; 1111 1112 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1113 { 1114 struct vop *vop = to_vop(crtc); 1115 unsigned long flags; 1116 1117 if (WARN_ON(!vop->is_enabled)) 1118 return -EPERM; 1119 1120 spin_lock_irqsave(&vop->irq_lock, flags); 1121 1122 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1123 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1124 1125 spin_unlock_irqrestore(&vop->irq_lock, flags); 1126 1127 return 0; 1128 } 1129 1130 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1131 { 1132 struct vop *vop = to_vop(crtc); 1133 unsigned long flags; 1134 1135 if (WARN_ON(!vop->is_enabled)) 1136 return; 1137 1138 spin_lock_irqsave(&vop->irq_lock, flags); 1139 1140 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1141 1142 spin_unlock_irqrestore(&vop->irq_lock, flags); 1143 } 1144 1145 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1146 const struct drm_display_mode *mode, 1147 struct drm_display_mode *adjusted_mode) 1148 { 1149 struct vop *vop = to_vop(crtc); 1150 unsigned long rate; 1151 1152 /* 1153 * Clock craziness. 1154 * 1155 * Key points: 1156 * 1157 * - DRM works in in kHz. 1158 * - Clock framework works in Hz. 1159 * - Rockchip's clock driver picks the clock rate that is the 1160 * same _OR LOWER_ than the one requested. 1161 * 1162 * Action plan: 1163 * 1164 * 1. When DRM gives us a mode, we should add 999 Hz to it. That way 1165 * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to 1166 * make 60000 kHz then the clock framework will actually give us 1167 * the right clock. 1168 * 1169 * NOTE: if the PLL (maybe through a divider) could actually make 1170 * a clock rate 999 Hz higher instead of the one we want then this 1171 * could be a problem. Unfortunately there's not much we can do 1172 * since it's baked into DRM to use kHz. It shouldn't matter in 1173 * practice since Rockchip PLLs are controlled by tables and 1174 * even if there is a divider in the middle I wouldn't expect PLL 1175 * rates in the table that are just a few kHz different. 1176 * 1177 * 2. Get the clock framework to round the rate for us to tell us 1178 * what it will actually make. 1179 * 1180 * 3. Store the rounded up rate so that we don't need to worry about 1181 * this in the actual clk_set_rate(). 1182 */ 1183 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); 1184 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1185 1186 return true; 1187 } 1188 1189 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1190 { 1191 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1192 } 1193 1194 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1195 { 1196 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1197 unsigned int i; 1198 1199 for (i = 0; i < crtc->gamma_size; i++) { 1200 u32 word; 1201 1202 word = (drm_color_lut_extract(lut[i].red, 10) << 20) | 1203 (drm_color_lut_extract(lut[i].green, 10) << 10) | 1204 drm_color_lut_extract(lut[i].blue, 10); 1205 writel(word, vop->lut_regs + i * 4); 1206 } 1207 } 1208 1209 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1210 struct drm_crtc_state *old_state) 1211 { 1212 struct drm_crtc_state *state = crtc->state; 1213 unsigned int idle; 1214 int ret; 1215 1216 if (!vop->lut_regs) 1217 return; 1218 /* 1219 * To disable gamma (gamma_lut is null) or to write 1220 * an update to the LUT, clear dsp_lut_en. 1221 */ 1222 spin_lock(&vop->reg_lock); 1223 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1224 vop_cfg_done(vop); 1225 spin_unlock(&vop->reg_lock); 1226 1227 /* 1228 * In order to write the LUT to the internal memory, 1229 * we need to first make sure the dsp_lut_en bit is cleared. 1230 */ 1231 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1232 idle, !idle, 5, 30 * 1000); 1233 if (ret) { 1234 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1235 return; 1236 } 1237 1238 if (!state->gamma_lut) 1239 return; 1240 1241 spin_lock(&vop->reg_lock); 1242 vop_crtc_write_gamma_lut(vop, crtc); 1243 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1244 vop_cfg_done(vop); 1245 spin_unlock(&vop->reg_lock); 1246 } 1247 1248 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1249 struct drm_atomic_state *state) 1250 { 1251 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1252 crtc); 1253 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1254 crtc); 1255 struct vop *vop = to_vop(crtc); 1256 1257 /* 1258 * Only update GAMMA if the 'active' flag is not changed, 1259 * otherwise it's updated by .atomic_enable. 1260 */ 1261 if (crtc_state->color_mgmt_changed && 1262 !crtc_state->active_changed) 1263 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1264 } 1265 1266 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1267 struct drm_atomic_state *state) 1268 { 1269 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1270 crtc); 1271 struct vop *vop = to_vop(crtc); 1272 const struct vop_data *vop_data = vop->data; 1273 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1274 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1275 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1276 u16 hdisplay = adjusted_mode->hdisplay; 1277 u16 htotal = adjusted_mode->htotal; 1278 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1279 u16 hact_end = hact_st + hdisplay; 1280 u16 vdisplay = adjusted_mode->vdisplay; 1281 u16 vtotal = adjusted_mode->vtotal; 1282 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1283 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1284 u16 vact_end = vact_st + vdisplay; 1285 uint32_t pin_pol, val; 1286 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1287 int ret; 1288 1289 if (old_state && old_state->self_refresh_active) { 1290 drm_crtc_vblank_on(crtc); 1291 rockchip_drm_set_win_enabled(crtc, true); 1292 return; 1293 } 1294 1295 /* 1296 * If we have a GAMMA LUT in the state, then let's make sure 1297 * it's updated. We might be coming out of suspend, 1298 * which means the LUT internal memory needs to be re-written. 1299 */ 1300 if (crtc->state->gamma_lut) 1301 vop_crtc_gamma_set(vop, crtc, old_state); 1302 1303 mutex_lock(&vop->vop_lock); 1304 1305 WARN_ON(vop->event); 1306 1307 ret = vop_enable(crtc, old_state); 1308 if (ret) { 1309 mutex_unlock(&vop->vop_lock); 1310 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1311 return; 1312 } 1313 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1314 BIT(HSYNC_POSITIVE) : 0; 1315 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1316 BIT(VSYNC_POSITIVE) : 0; 1317 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1318 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1319 1320 switch (s->output_type) { 1321 case DRM_MODE_CONNECTOR_LVDS: 1322 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1323 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1324 VOP_REG_SET(vop, output, rgb_en, 1); 1325 break; 1326 case DRM_MODE_CONNECTOR_eDP: 1327 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1328 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1329 VOP_REG_SET(vop, output, edp_en, 1); 1330 break; 1331 case DRM_MODE_CONNECTOR_HDMIA: 1332 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1333 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1334 VOP_REG_SET(vop, output, hdmi_en, 1); 1335 break; 1336 case DRM_MODE_CONNECTOR_DSI: 1337 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1338 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1339 VOP_REG_SET(vop, output, mipi_en, 1); 1340 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1341 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1342 break; 1343 case DRM_MODE_CONNECTOR_DisplayPort: 1344 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1345 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1346 VOP_REG_SET(vop, output, dp_en, 1); 1347 break; 1348 default: 1349 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1350 s->output_type); 1351 } 1352 1353 /* 1354 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1355 */ 1356 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1357 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1358 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1359 1360 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1361 VOP_REG_SET(vop, common, pre_dither_down, 1); 1362 else 1363 VOP_REG_SET(vop, common, pre_dither_down, 0); 1364 1365 if (dither_bpc == 6) { 1366 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1367 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1368 VOP_REG_SET(vop, common, dither_down_en, 1); 1369 } else { 1370 VOP_REG_SET(vop, common, dither_down_en, 0); 1371 } 1372 1373 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1374 1375 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1376 val = hact_st << 16; 1377 val |= hact_end; 1378 VOP_REG_SET(vop, modeset, hact_st_end, val); 1379 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1380 1381 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1382 val = vact_st << 16; 1383 val |= vact_end; 1384 VOP_REG_SET(vop, modeset, vact_st_end, val); 1385 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1386 1387 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1388 1389 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1390 1391 VOP_REG_SET(vop, common, standby, 0); 1392 mutex_unlock(&vop->vop_lock); 1393 } 1394 1395 static bool vop_fs_irq_is_pending(struct vop *vop) 1396 { 1397 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1398 } 1399 1400 static void vop_wait_for_irq_handler(struct vop *vop) 1401 { 1402 bool pending; 1403 int ret; 1404 1405 /* 1406 * Spin until frame start interrupt status bit goes low, which means 1407 * that interrupt handler was invoked and cleared it. The timeout of 1408 * 10 msecs is really too long, but it is just a safety measure if 1409 * something goes really wrong. The wait will only happen in the very 1410 * unlikely case of a vblank happening exactly at the same time and 1411 * shouldn't exceed microseconds range. 1412 */ 1413 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1414 !pending, 0, 10 * 1000); 1415 if (ret) 1416 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1417 1418 synchronize_irq(vop->irq); 1419 } 1420 1421 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1422 struct drm_atomic_state *state) 1423 { 1424 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1425 crtc); 1426 struct vop *vop = to_vop(crtc); 1427 struct drm_plane *plane; 1428 struct drm_plane_state *plane_state; 1429 struct rockchip_crtc_state *s; 1430 int afbc_planes = 0; 1431 1432 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1433 crtc_state->gamma_lut) { 1434 unsigned int len; 1435 1436 len = drm_color_lut_size(crtc_state->gamma_lut); 1437 if (len != crtc->gamma_size) { 1438 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1439 len, crtc->gamma_size); 1440 return -EINVAL; 1441 } 1442 } 1443 1444 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1445 plane_state = 1446 drm_atomic_get_plane_state(crtc_state->state, plane); 1447 if (IS_ERR(plane_state)) { 1448 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1449 plane->name); 1450 return PTR_ERR(plane_state); 1451 } 1452 1453 if (drm_is_afbc(plane_state->fb->modifier)) 1454 ++afbc_planes; 1455 } 1456 1457 if (afbc_planes > 1) { 1458 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1459 return -EINVAL; 1460 } 1461 1462 s = to_rockchip_crtc_state(crtc_state); 1463 s->enable_afbc = afbc_planes > 0; 1464 1465 return 0; 1466 } 1467 1468 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1469 struct drm_atomic_state *state) 1470 { 1471 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1472 crtc); 1473 struct drm_atomic_state *old_state = old_crtc_state->state; 1474 struct drm_plane_state *old_plane_state, *new_plane_state; 1475 struct vop *vop = to_vop(crtc); 1476 struct drm_plane *plane; 1477 struct rockchip_crtc_state *s; 1478 int i; 1479 1480 if (WARN_ON(!vop->is_enabled)) 1481 return; 1482 1483 spin_lock(&vop->reg_lock); 1484 1485 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1486 s = to_rockchip_crtc_state(crtc->state); 1487 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1488 vop_cfg_done(vop); 1489 1490 spin_unlock(&vop->reg_lock); 1491 1492 /* 1493 * There is a (rather unlikely) possiblity that a vblank interrupt 1494 * fired before we set the cfg_done bit. To avoid spuriously 1495 * signalling flip completion we need to wait for it to finish. 1496 */ 1497 vop_wait_for_irq_handler(vop); 1498 1499 spin_lock_irq(&crtc->dev->event_lock); 1500 if (crtc->state->event) { 1501 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1502 WARN_ON(vop->event); 1503 1504 vop->event = crtc->state->event; 1505 crtc->state->event = NULL; 1506 } 1507 spin_unlock_irq(&crtc->dev->event_lock); 1508 1509 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1510 new_plane_state, i) { 1511 if (!old_plane_state->fb) 1512 continue; 1513 1514 if (old_plane_state->fb == new_plane_state->fb) 1515 continue; 1516 1517 drm_framebuffer_get(old_plane_state->fb); 1518 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1519 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1520 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1521 } 1522 } 1523 1524 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1525 .mode_fixup = vop_crtc_mode_fixup, 1526 .atomic_check = vop_crtc_atomic_check, 1527 .atomic_begin = vop_crtc_atomic_begin, 1528 .atomic_flush = vop_crtc_atomic_flush, 1529 .atomic_enable = vop_crtc_atomic_enable, 1530 .atomic_disable = vop_crtc_atomic_disable, 1531 }; 1532 1533 static void vop_crtc_destroy(struct drm_crtc *crtc) 1534 { 1535 drm_crtc_cleanup(crtc); 1536 } 1537 1538 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1539 { 1540 struct rockchip_crtc_state *rockchip_state; 1541 1542 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1543 if (!rockchip_state) 1544 return NULL; 1545 1546 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1547 return &rockchip_state->base; 1548 } 1549 1550 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1551 struct drm_crtc_state *state) 1552 { 1553 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1554 1555 __drm_atomic_helper_crtc_destroy_state(&s->base); 1556 kfree(s); 1557 } 1558 1559 static void vop_crtc_reset(struct drm_crtc *crtc) 1560 { 1561 struct rockchip_crtc_state *crtc_state = 1562 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1563 1564 if (crtc->state) 1565 vop_crtc_destroy_state(crtc, crtc->state); 1566 1567 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1568 } 1569 1570 #ifdef CONFIG_DRM_ANALOGIX_DP 1571 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1572 { 1573 struct drm_connector *connector; 1574 struct drm_connector_list_iter conn_iter; 1575 1576 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1577 drm_for_each_connector_iter(connector, &conn_iter) { 1578 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1579 drm_connector_list_iter_end(&conn_iter); 1580 return connector; 1581 } 1582 } 1583 drm_connector_list_iter_end(&conn_iter); 1584 1585 return NULL; 1586 } 1587 1588 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1589 const char *source_name) 1590 { 1591 struct vop *vop = to_vop(crtc); 1592 struct drm_connector *connector; 1593 int ret; 1594 1595 connector = vop_get_edp_connector(vop); 1596 if (!connector) 1597 return -EINVAL; 1598 1599 if (source_name && strcmp(source_name, "auto") == 0) 1600 ret = analogix_dp_start_crc(connector); 1601 else if (!source_name) 1602 ret = analogix_dp_stop_crc(connector); 1603 else 1604 ret = -EINVAL; 1605 1606 return ret; 1607 } 1608 1609 static int 1610 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1611 size_t *values_cnt) 1612 { 1613 if (source_name && strcmp(source_name, "auto") != 0) 1614 return -EINVAL; 1615 1616 *values_cnt = 3; 1617 return 0; 1618 } 1619 1620 #else 1621 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1622 const char *source_name) 1623 { 1624 return -ENODEV; 1625 } 1626 1627 static int 1628 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1629 size_t *values_cnt) 1630 { 1631 return -ENODEV; 1632 } 1633 #endif 1634 1635 static const struct drm_crtc_funcs vop_crtc_funcs = { 1636 .set_config = drm_atomic_helper_set_config, 1637 .page_flip = drm_atomic_helper_page_flip, 1638 .destroy = vop_crtc_destroy, 1639 .reset = vop_crtc_reset, 1640 .atomic_duplicate_state = vop_crtc_duplicate_state, 1641 .atomic_destroy_state = vop_crtc_destroy_state, 1642 .enable_vblank = vop_crtc_enable_vblank, 1643 .disable_vblank = vop_crtc_disable_vblank, 1644 .set_crc_source = vop_crtc_set_crc_source, 1645 .verify_crc_source = vop_crtc_verify_crc_source, 1646 }; 1647 1648 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1649 { 1650 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1651 struct drm_framebuffer *fb = val; 1652 1653 drm_crtc_vblank_put(&vop->crtc); 1654 drm_framebuffer_put(fb); 1655 } 1656 1657 static void vop_handle_vblank(struct vop *vop) 1658 { 1659 struct drm_device *drm = vop->drm_dev; 1660 struct drm_crtc *crtc = &vop->crtc; 1661 1662 spin_lock(&drm->event_lock); 1663 if (vop->event) { 1664 drm_crtc_send_vblank_event(crtc, vop->event); 1665 drm_crtc_vblank_put(crtc); 1666 vop->event = NULL; 1667 } 1668 spin_unlock(&drm->event_lock); 1669 1670 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1671 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1672 } 1673 1674 static irqreturn_t vop_isr(int irq, void *data) 1675 { 1676 struct vop *vop = data; 1677 struct drm_crtc *crtc = &vop->crtc; 1678 uint32_t active_irqs; 1679 int ret = IRQ_NONE; 1680 1681 /* 1682 * The irq is shared with the iommu. If the runtime-pm state of the 1683 * vop-device is disabled the irq has to be targeted at the iommu. 1684 */ 1685 if (!pm_runtime_get_if_in_use(vop->dev)) 1686 return IRQ_NONE; 1687 1688 if (vop_core_clks_enable(vop)) { 1689 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1690 goto out; 1691 } 1692 1693 /* 1694 * interrupt register has interrupt status, enable and clear bits, we 1695 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1696 */ 1697 spin_lock(&vop->irq_lock); 1698 1699 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1700 /* Clear all active interrupt sources */ 1701 if (active_irqs) 1702 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1703 1704 spin_unlock(&vop->irq_lock); 1705 1706 /* This is expected for vop iommu irqs, since the irq is shared */ 1707 if (!active_irqs) 1708 goto out_disable; 1709 1710 if (active_irqs & DSP_HOLD_VALID_INTR) { 1711 complete(&vop->dsp_hold_completion); 1712 active_irqs &= ~DSP_HOLD_VALID_INTR; 1713 ret = IRQ_HANDLED; 1714 } 1715 1716 if (active_irqs & LINE_FLAG_INTR) { 1717 complete(&vop->line_flag_completion); 1718 active_irqs &= ~LINE_FLAG_INTR; 1719 ret = IRQ_HANDLED; 1720 } 1721 1722 if (active_irqs & FS_INTR) { 1723 drm_crtc_handle_vblank(crtc); 1724 vop_handle_vblank(vop); 1725 active_irqs &= ~FS_INTR; 1726 ret = IRQ_HANDLED; 1727 } 1728 1729 /* Unhandled irqs are spurious. */ 1730 if (active_irqs) 1731 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1732 active_irqs); 1733 1734 out_disable: 1735 vop_core_clks_disable(vop); 1736 out: 1737 pm_runtime_put(vop->dev); 1738 return ret; 1739 } 1740 1741 static void vop_plane_add_properties(struct drm_plane *plane, 1742 const struct vop_win_data *win_data) 1743 { 1744 unsigned int flags = 0; 1745 1746 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1747 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1748 if (flags) 1749 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1750 DRM_MODE_ROTATE_0 | flags); 1751 } 1752 1753 static int vop_create_crtc(struct vop *vop) 1754 { 1755 const struct vop_data *vop_data = vop->data; 1756 struct device *dev = vop->dev; 1757 struct drm_device *drm_dev = vop->drm_dev; 1758 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1759 struct drm_crtc *crtc = &vop->crtc; 1760 struct device_node *port; 1761 int ret; 1762 int i; 1763 1764 /* 1765 * Create drm_plane for primary and cursor planes first, since we need 1766 * to pass them to drm_crtc_init_with_planes, which sets the 1767 * "possible_crtcs" to the newly initialized crtc. 1768 */ 1769 for (i = 0; i < vop_data->win_size; i++) { 1770 struct vop_win *vop_win = &vop->win[i]; 1771 const struct vop_win_data *win_data = vop_win->data; 1772 1773 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1774 win_data->type != DRM_PLANE_TYPE_CURSOR) 1775 continue; 1776 1777 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1778 0, &vop_plane_funcs, 1779 win_data->phy->data_formats, 1780 win_data->phy->nformats, 1781 win_data->phy->format_modifiers, 1782 win_data->type, NULL); 1783 if (ret) { 1784 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1785 ret); 1786 goto err_cleanup_planes; 1787 } 1788 1789 plane = &vop_win->base; 1790 drm_plane_helper_add(plane, &plane_helper_funcs); 1791 vop_plane_add_properties(plane, win_data); 1792 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1793 primary = plane; 1794 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1795 cursor = plane; 1796 } 1797 1798 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1799 &vop_crtc_funcs, NULL); 1800 if (ret) 1801 goto err_cleanup_planes; 1802 1803 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1804 if (vop->lut_regs) { 1805 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1806 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1807 } 1808 1809 /* 1810 * Create drm_planes for overlay windows with possible_crtcs restricted 1811 * to the newly created crtc. 1812 */ 1813 for (i = 0; i < vop_data->win_size; i++) { 1814 struct vop_win *vop_win = &vop->win[i]; 1815 const struct vop_win_data *win_data = vop_win->data; 1816 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1817 1818 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1819 continue; 1820 1821 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1822 possible_crtcs, 1823 &vop_plane_funcs, 1824 win_data->phy->data_formats, 1825 win_data->phy->nformats, 1826 win_data->phy->format_modifiers, 1827 win_data->type, NULL); 1828 if (ret) { 1829 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1830 ret); 1831 goto err_cleanup_crtc; 1832 } 1833 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1834 vop_plane_add_properties(&vop_win->base, win_data); 1835 } 1836 1837 port = of_get_child_by_name(dev->of_node, "port"); 1838 if (!port) { 1839 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1840 dev->of_node); 1841 ret = -ENOENT; 1842 goto err_cleanup_crtc; 1843 } 1844 1845 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1846 vop_fb_unref_worker); 1847 1848 init_completion(&vop->dsp_hold_completion); 1849 init_completion(&vop->line_flag_completion); 1850 crtc->port = port; 1851 1852 ret = drm_self_refresh_helper_init(crtc); 1853 if (ret) 1854 DRM_DEV_DEBUG_KMS(vop->dev, 1855 "Failed to init %s with SR helpers %d, ignoring\n", 1856 crtc->name, ret); 1857 1858 return 0; 1859 1860 err_cleanup_crtc: 1861 drm_crtc_cleanup(crtc); 1862 err_cleanup_planes: 1863 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1864 head) 1865 drm_plane_cleanup(plane); 1866 return ret; 1867 } 1868 1869 static void vop_destroy_crtc(struct vop *vop) 1870 { 1871 struct drm_crtc *crtc = &vop->crtc; 1872 struct drm_device *drm_dev = vop->drm_dev; 1873 struct drm_plane *plane, *tmp; 1874 1875 drm_self_refresh_helper_cleanup(crtc); 1876 1877 of_node_put(crtc->port); 1878 1879 /* 1880 * We need to cleanup the planes now. Why? 1881 * 1882 * The planes are "&vop->win[i].base". That means the memory is 1883 * all part of the big "struct vop" chunk of memory. That memory 1884 * was devm allocated and associated with this component. We need to 1885 * free it ourselves before vop_unbind() finishes. 1886 */ 1887 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1888 head) 1889 vop_plane_destroy(plane); 1890 1891 /* 1892 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1893 * references the CRTC. 1894 */ 1895 drm_crtc_cleanup(crtc); 1896 drm_flip_work_cleanup(&vop->fb_unref_work); 1897 } 1898 1899 static int vop_initial(struct vop *vop) 1900 { 1901 struct reset_control *ahb_rst; 1902 int i, ret; 1903 1904 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1905 if (IS_ERR(vop->hclk)) { 1906 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1907 return PTR_ERR(vop->hclk); 1908 } 1909 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1910 if (IS_ERR(vop->aclk)) { 1911 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1912 return PTR_ERR(vop->aclk); 1913 } 1914 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1915 if (IS_ERR(vop->dclk)) { 1916 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1917 return PTR_ERR(vop->dclk); 1918 } 1919 1920 ret = pm_runtime_get_sync(vop->dev); 1921 if (ret < 0) { 1922 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1923 return ret; 1924 } 1925 1926 ret = clk_prepare(vop->dclk); 1927 if (ret < 0) { 1928 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1929 goto err_put_pm_runtime; 1930 } 1931 1932 /* Enable both the hclk and aclk to setup the vop */ 1933 ret = clk_prepare_enable(vop->hclk); 1934 if (ret < 0) { 1935 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1936 goto err_unprepare_dclk; 1937 } 1938 1939 ret = clk_prepare_enable(vop->aclk); 1940 if (ret < 0) { 1941 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1942 goto err_disable_hclk; 1943 } 1944 1945 /* 1946 * do hclk_reset, reset all vop registers. 1947 */ 1948 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1949 if (IS_ERR(ahb_rst)) { 1950 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1951 ret = PTR_ERR(ahb_rst); 1952 goto err_disable_aclk; 1953 } 1954 reset_control_assert(ahb_rst); 1955 usleep_range(10, 20); 1956 reset_control_deassert(ahb_rst); 1957 1958 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1959 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1960 1961 for (i = 0; i < vop->len; i += sizeof(u32)) 1962 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1963 1964 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1965 VOP_REG_SET(vop, common, dsp_blank, 0); 1966 1967 for (i = 0; i < vop->data->win_size; i++) { 1968 struct vop_win *vop_win = &vop->win[i]; 1969 const struct vop_win_data *win = vop_win->data; 1970 int channel = i * 2 + 1; 1971 1972 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1973 vop_win_disable(vop, vop_win); 1974 VOP_WIN_SET(vop, win, gate, 1); 1975 } 1976 1977 vop_cfg_done(vop); 1978 1979 /* 1980 * do dclk_reset, let all config take affect. 1981 */ 1982 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1983 if (IS_ERR(vop->dclk_rst)) { 1984 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1985 ret = PTR_ERR(vop->dclk_rst); 1986 goto err_disable_aclk; 1987 } 1988 reset_control_assert(vop->dclk_rst); 1989 usleep_range(10, 20); 1990 reset_control_deassert(vop->dclk_rst); 1991 1992 clk_disable(vop->hclk); 1993 clk_disable(vop->aclk); 1994 1995 vop->is_enabled = false; 1996 1997 pm_runtime_put_sync(vop->dev); 1998 1999 return 0; 2000 2001 err_disable_aclk: 2002 clk_disable_unprepare(vop->aclk); 2003 err_disable_hclk: 2004 clk_disable_unprepare(vop->hclk); 2005 err_unprepare_dclk: 2006 clk_unprepare(vop->dclk); 2007 err_put_pm_runtime: 2008 pm_runtime_put_sync(vop->dev); 2009 return ret; 2010 } 2011 2012 /* 2013 * Initialize the vop->win array elements. 2014 */ 2015 static void vop_win_init(struct vop *vop) 2016 { 2017 const struct vop_data *vop_data = vop->data; 2018 unsigned int i; 2019 2020 for (i = 0; i < vop_data->win_size; i++) { 2021 struct vop_win *vop_win = &vop->win[i]; 2022 const struct vop_win_data *win_data = &vop_data->win[i]; 2023 2024 vop_win->data = win_data; 2025 vop_win->vop = vop; 2026 2027 if (vop_data->win_yuv2yuv) 2028 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2029 } 2030 } 2031 2032 /** 2033 * rockchip_drm_wait_vact_end 2034 * @crtc: CRTC to enable line flag 2035 * @mstimeout: millisecond for timeout 2036 * 2037 * Wait for vact_end line flag irq or timeout. 2038 * 2039 * Returns: 2040 * Zero on success, negative errno on failure. 2041 */ 2042 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2043 { 2044 struct vop *vop = to_vop(crtc); 2045 unsigned long jiffies_left; 2046 int ret = 0; 2047 2048 if (!crtc || !vop->is_enabled) 2049 return -ENODEV; 2050 2051 mutex_lock(&vop->vop_lock); 2052 if (mstimeout <= 0) { 2053 ret = -EINVAL; 2054 goto out; 2055 } 2056 2057 if (vop_line_flag_irq_is_enabled(vop)) { 2058 ret = -EBUSY; 2059 goto out; 2060 } 2061 2062 reinit_completion(&vop->line_flag_completion); 2063 vop_line_flag_irq_enable(vop); 2064 2065 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2066 msecs_to_jiffies(mstimeout)); 2067 vop_line_flag_irq_disable(vop); 2068 2069 if (jiffies_left == 0) { 2070 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2071 ret = -ETIMEDOUT; 2072 goto out; 2073 } 2074 2075 out: 2076 mutex_unlock(&vop->vop_lock); 2077 return ret; 2078 } 2079 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2080 2081 static int vop_bind(struct device *dev, struct device *master, void *data) 2082 { 2083 struct platform_device *pdev = to_platform_device(dev); 2084 const struct vop_data *vop_data; 2085 struct drm_device *drm_dev = data; 2086 struct vop *vop; 2087 struct resource *res; 2088 int ret, irq; 2089 2090 vop_data = of_device_get_match_data(dev); 2091 if (!vop_data) 2092 return -ENODEV; 2093 2094 /* Allocate vop struct and its vop_win array */ 2095 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2096 GFP_KERNEL); 2097 if (!vop) 2098 return -ENOMEM; 2099 2100 vop->dev = dev; 2101 vop->data = vop_data; 2102 vop->drm_dev = drm_dev; 2103 dev_set_drvdata(dev, vop); 2104 2105 vop_win_init(vop); 2106 2107 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2108 vop->len = resource_size(res); 2109 vop->regs = devm_ioremap_resource(dev, res); 2110 if (IS_ERR(vop->regs)) 2111 return PTR_ERR(vop->regs); 2112 2113 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2114 if (res) { 2115 if (!vop_data->lut_size) { 2116 DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); 2117 return -EINVAL; 2118 } 2119 vop->lut_regs = devm_ioremap_resource(dev, res); 2120 if (IS_ERR(vop->lut_regs)) 2121 return PTR_ERR(vop->lut_regs); 2122 } 2123 2124 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2125 if (!vop->regsbak) 2126 return -ENOMEM; 2127 2128 irq = platform_get_irq(pdev, 0); 2129 if (irq < 0) { 2130 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2131 return irq; 2132 } 2133 vop->irq = (unsigned int)irq; 2134 2135 spin_lock_init(&vop->reg_lock); 2136 spin_lock_init(&vop->irq_lock); 2137 mutex_init(&vop->vop_lock); 2138 2139 ret = vop_create_crtc(vop); 2140 if (ret) 2141 return ret; 2142 2143 pm_runtime_enable(&pdev->dev); 2144 2145 ret = vop_initial(vop); 2146 if (ret < 0) { 2147 DRM_DEV_ERROR(&pdev->dev, 2148 "cannot initial vop dev - err %d\n", ret); 2149 goto err_disable_pm_runtime; 2150 } 2151 2152 ret = devm_request_irq(dev, vop->irq, vop_isr, 2153 IRQF_SHARED, dev_name(dev), vop); 2154 if (ret) 2155 goto err_disable_pm_runtime; 2156 2157 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2158 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 2159 if (IS_ERR(vop->rgb)) { 2160 ret = PTR_ERR(vop->rgb); 2161 goto err_disable_pm_runtime; 2162 } 2163 } 2164 2165 return 0; 2166 2167 err_disable_pm_runtime: 2168 pm_runtime_disable(&pdev->dev); 2169 vop_destroy_crtc(vop); 2170 return ret; 2171 } 2172 2173 static void vop_unbind(struct device *dev, struct device *master, void *data) 2174 { 2175 struct vop *vop = dev_get_drvdata(dev); 2176 2177 if (vop->rgb) 2178 rockchip_rgb_fini(vop->rgb); 2179 2180 pm_runtime_disable(dev); 2181 vop_destroy_crtc(vop); 2182 2183 clk_unprepare(vop->aclk); 2184 clk_unprepare(vop->hclk); 2185 clk_unprepare(vop->dclk); 2186 } 2187 2188 const struct component_ops vop_component_ops = { 2189 .bind = vop_bind, 2190 .unbind = vop_unbind, 2191 }; 2192 EXPORT_SYMBOL_GPL(vop_component_ops); 2193