1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/log2.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/overflow.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 21 #include <drm/drm.h> 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_uapi.h> 24 #include <drm/drm_blend.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_flip_work.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_framebuffer.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_self_refresh_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #ifdef CONFIG_DRM_ANALOGIX_DP 36 #include <drm/bridge/analogix_dp.h> 37 #endif 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_vop.h" 43 #include "rockchip_rgb.h" 44 45 #define VOP_WIN_SET(vop, win, name, v) \ 46 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET(vop, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 49 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 50 vop_reg_set(vop, &win->phy->scl->ext->name, \ 51 win->base, ~0, v, #name) 52 53 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 54 do { \ 55 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 56 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 57 } while (0) 58 59 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 60 do { \ 61 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 62 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 63 } while (0) 64 65 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 66 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 67 68 #define VOP_REG_SET(vop, group, name, v) \ 69 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 70 71 #define VOP_HAS_REG(vop, group, name) \ 72 (!!(vop->data->group->name.mask)) 73 74 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 75 do { \ 76 int i, reg = 0, mask = 0; \ 77 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 78 if (vop->data->intr->intrs[i] & type) { \ 79 reg |= (v) << i; \ 80 mask |= 1 << i; \ 81 } \ 82 } \ 83 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 84 } while (0) 85 #define VOP_INTR_GET_TYPE(vop, name, type) \ 86 vop_get_intr_type(vop, &vop->data->intr->name, type) 87 88 #define VOP_WIN_GET(vop, win, name) \ 89 vop_read_reg(vop, win->base, &win->phy->name) 90 91 #define VOP_WIN_HAS_REG(win, name) \ 92 (!!(win->phy->name.mask)) 93 94 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 95 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 96 97 #define VOP_WIN_TO_INDEX(vop_win) \ 98 ((vop_win) - (vop_win)->vop->win) 99 100 #define VOP_AFBC_SET(vop, name, v) \ 101 do { \ 102 if ((vop)->data->afbc) \ 103 vop_reg_set((vop), &(vop)->data->afbc->name, \ 104 0, ~0, v, #name); \ 105 } while (0) 106 107 #define to_vop(x) container_of(x, struct vop, crtc) 108 #define to_vop_win(x) container_of(x, struct vop_win, base) 109 110 #define AFBC_FMT_RGB565 0x0 111 #define AFBC_FMT_U8U8U8U8 0x5 112 #define AFBC_FMT_U8U8U8 0x4 113 114 #define AFBC_TILE_16x16 BIT(4) 115 116 /* 117 * The coefficients of the following matrix are all fixed points. 118 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 119 * They are all represented in two's complement. 120 */ 121 static const uint32_t bt601_yuv2rgb[] = { 122 0x4A8, 0x0, 0x662, 123 0x4A8, 0x1E6F, 0x1CBF, 124 0x4A8, 0x812, 0x0, 125 0x321168, 0x0877CF, 0x2EB127 126 }; 127 128 enum vop_pending { 129 VOP_PENDING_FB_UNREF, 130 }; 131 132 struct vop_win { 133 struct drm_plane base; 134 const struct vop_win_data *data; 135 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 136 struct vop *vop; 137 }; 138 139 struct rockchip_rgb; 140 struct vop { 141 struct drm_crtc crtc; 142 struct device *dev; 143 struct drm_device *drm_dev; 144 bool is_enabled; 145 146 struct completion dsp_hold_completion; 147 unsigned int win_enabled; 148 149 /* protected by dev->event_lock */ 150 struct drm_pending_vblank_event *event; 151 152 struct drm_flip_work fb_unref_work; 153 unsigned long pending; 154 155 struct completion line_flag_completion; 156 157 const struct vop_data *data; 158 159 uint32_t *regsbak; 160 void __iomem *regs; 161 void __iomem *lut_regs; 162 163 /* physical map length of vop register */ 164 uint32_t len; 165 166 /* one time only one process allowed to config the register */ 167 spinlock_t reg_lock; 168 /* lock vop irq reg */ 169 spinlock_t irq_lock; 170 /* protects crtc enable/disable */ 171 struct mutex vop_lock; 172 173 unsigned int irq; 174 175 /* vop AHP clk */ 176 struct clk *hclk; 177 /* vop dclk */ 178 struct clk *dclk; 179 /* vop share memory frequency */ 180 struct clk *aclk; 181 182 /* vop dclk reset */ 183 struct reset_control *dclk_rst; 184 185 /* optional internal rgb encoder */ 186 struct rockchip_rgb *rgb; 187 188 struct vop_win win[]; 189 }; 190 191 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 192 { 193 return readl(vop->regs + offset); 194 } 195 196 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 197 const struct vop_reg *reg) 198 { 199 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 200 } 201 202 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 203 uint32_t _offset, uint32_t _mask, uint32_t v, 204 const char *reg_name) 205 { 206 int offset, mask, shift; 207 208 if (!reg || !reg->mask) { 209 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 210 return; 211 } 212 213 offset = reg->offset + _offset; 214 mask = reg->mask & _mask; 215 shift = reg->shift; 216 217 if (reg->write_mask) { 218 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 219 } else { 220 uint32_t cached_val = vop->regsbak[offset >> 2]; 221 222 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 223 vop->regsbak[offset >> 2] = v; 224 } 225 226 if (reg->relaxed) 227 writel_relaxed(v, vop->regs + offset); 228 else 229 writel(v, vop->regs + offset); 230 } 231 232 static inline uint32_t vop_get_intr_type(struct vop *vop, 233 const struct vop_reg *reg, int type) 234 { 235 uint32_t i, ret = 0; 236 uint32_t regs = vop_read_reg(vop, 0, reg); 237 238 for (i = 0; i < vop->data->intr->nintrs; i++) { 239 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 240 ret |= vop->data->intr->intrs[i]; 241 } 242 243 return ret; 244 } 245 246 static inline void vop_cfg_done(struct vop *vop) 247 { 248 VOP_REG_SET(vop, common, cfg_done, 1); 249 } 250 251 static bool has_rb_swapped(uint32_t format) 252 { 253 switch (format) { 254 case DRM_FORMAT_XBGR8888: 255 case DRM_FORMAT_ABGR8888: 256 case DRM_FORMAT_BGR888: 257 case DRM_FORMAT_BGR565: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static bool has_uv_swapped(uint32_t format) 265 { 266 switch (format) { 267 case DRM_FORMAT_NV21: 268 case DRM_FORMAT_NV61: 269 case DRM_FORMAT_NV42: 270 return true; 271 default: 272 return false; 273 } 274 } 275 276 static enum vop_data_format vop_convert_format(uint32_t format) 277 { 278 switch (format) { 279 case DRM_FORMAT_XRGB8888: 280 case DRM_FORMAT_ARGB8888: 281 case DRM_FORMAT_XBGR8888: 282 case DRM_FORMAT_ABGR8888: 283 return VOP_FMT_ARGB8888; 284 case DRM_FORMAT_RGB888: 285 case DRM_FORMAT_BGR888: 286 return VOP_FMT_RGB888; 287 case DRM_FORMAT_RGB565: 288 case DRM_FORMAT_BGR565: 289 return VOP_FMT_RGB565; 290 case DRM_FORMAT_NV12: 291 case DRM_FORMAT_NV21: 292 return VOP_FMT_YUV420SP; 293 case DRM_FORMAT_NV16: 294 case DRM_FORMAT_NV61: 295 return VOP_FMT_YUV422SP; 296 case DRM_FORMAT_NV24: 297 case DRM_FORMAT_NV42: 298 return VOP_FMT_YUV444SP; 299 default: 300 DRM_ERROR("unsupported format[%08x]\n", format); 301 return -EINVAL; 302 } 303 } 304 305 static int vop_convert_afbc_format(uint32_t format) 306 { 307 switch (format) { 308 case DRM_FORMAT_XRGB8888: 309 case DRM_FORMAT_ARGB8888: 310 case DRM_FORMAT_XBGR8888: 311 case DRM_FORMAT_ABGR8888: 312 return AFBC_FMT_U8U8U8U8; 313 case DRM_FORMAT_RGB888: 314 case DRM_FORMAT_BGR888: 315 return AFBC_FMT_U8U8U8; 316 case DRM_FORMAT_RGB565: 317 case DRM_FORMAT_BGR565: 318 return AFBC_FMT_RGB565; 319 default: 320 DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format); 321 return -EINVAL; 322 } 323 } 324 325 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 326 uint32_t dst, bool is_horizontal, 327 int vsu_mode, int *vskiplines) 328 { 329 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 330 331 if (vskiplines) 332 *vskiplines = 0; 333 334 if (is_horizontal) { 335 if (mode == SCALE_UP) 336 val = GET_SCL_FT_BIC(src, dst); 337 else if (mode == SCALE_DOWN) 338 val = GET_SCL_FT_BILI_DN(src, dst); 339 } else { 340 if (mode == SCALE_UP) { 341 if (vsu_mode == SCALE_UP_BIL) 342 val = GET_SCL_FT_BILI_UP(src, dst); 343 else 344 val = GET_SCL_FT_BIC(src, dst); 345 } else if (mode == SCALE_DOWN) { 346 if (vskiplines) { 347 *vskiplines = scl_get_vskiplines(src, dst); 348 val = scl_get_bili_dn_vskip(src, dst, 349 *vskiplines); 350 } else { 351 val = GET_SCL_FT_BILI_DN(src, dst); 352 } 353 } 354 } 355 356 return val; 357 } 358 359 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 360 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 361 uint32_t dst_h, const struct drm_format_info *info) 362 { 363 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 364 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 365 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 366 bool is_yuv = false; 367 uint16_t cbcr_src_w = src_w / info->hsub; 368 uint16_t cbcr_src_h = src_h / info->vsub; 369 uint16_t vsu_mode; 370 uint16_t lb_mode; 371 uint32_t val; 372 int vskiplines; 373 374 if (info->is_yuv) 375 is_yuv = true; 376 377 if (dst_w > 3840) { 378 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 379 return; 380 } 381 382 if (!win->phy->scl->ext) { 383 VOP_SCL_SET(vop, win, scale_yrgb_x, 384 scl_cal_scale2(src_w, dst_w)); 385 VOP_SCL_SET(vop, win, scale_yrgb_y, 386 scl_cal_scale2(src_h, dst_h)); 387 if (is_yuv) { 388 VOP_SCL_SET(vop, win, scale_cbcr_x, 389 scl_cal_scale2(cbcr_src_w, dst_w)); 390 VOP_SCL_SET(vop, win, scale_cbcr_y, 391 scl_cal_scale2(cbcr_src_h, dst_h)); 392 } 393 return; 394 } 395 396 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 397 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 398 399 if (is_yuv) { 400 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 401 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 402 if (cbcr_hor_scl_mode == SCALE_DOWN) 403 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 404 else 405 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 406 } else { 407 if (yrgb_hor_scl_mode == SCALE_DOWN) 408 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 409 else 410 lb_mode = scl_vop_cal_lb_mode(src_w, false); 411 } 412 413 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 414 if (lb_mode == LB_RGB_3840X2) { 415 if (yrgb_ver_scl_mode != SCALE_NONE) { 416 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 417 return; 418 } 419 if (cbcr_ver_scl_mode != SCALE_NONE) { 420 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 421 return; 422 } 423 vsu_mode = SCALE_UP_BIL; 424 } else if (lb_mode == LB_RGB_2560X4) { 425 vsu_mode = SCALE_UP_BIL; 426 } else { 427 vsu_mode = SCALE_UP_BIC; 428 } 429 430 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 431 true, 0, NULL); 432 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 433 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 434 false, vsu_mode, &vskiplines); 435 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 436 437 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 438 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 439 440 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 441 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 442 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 443 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 444 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 445 if (is_yuv) { 446 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 447 dst_w, true, 0, NULL); 448 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 449 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 450 dst_h, false, vsu_mode, &vskiplines); 451 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 452 453 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 454 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 455 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 456 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 457 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 458 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 459 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 460 } 461 } 462 463 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 464 { 465 unsigned long flags; 466 467 if (WARN_ON(!vop->is_enabled)) 468 return; 469 470 spin_lock_irqsave(&vop->irq_lock, flags); 471 472 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 473 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 474 475 spin_unlock_irqrestore(&vop->irq_lock, flags); 476 } 477 478 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 479 { 480 unsigned long flags; 481 482 if (WARN_ON(!vop->is_enabled)) 483 return; 484 485 spin_lock_irqsave(&vop->irq_lock, flags); 486 487 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 488 489 spin_unlock_irqrestore(&vop->irq_lock, flags); 490 } 491 492 /* 493 * (1) each frame starts at the start of the Vsync pulse which is signaled by 494 * the "FRAME_SYNC" interrupt. 495 * (2) the active data region of each frame ends at dsp_vact_end 496 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 497 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 498 * 499 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 500 * Interrupts 501 * LINE_FLAG -------------------------------+ 502 * FRAME_SYNC ----+ | 503 * | | 504 * v v 505 * | Vsync | Vbp | Vactive | Vfp | 506 * ^ ^ ^ ^ 507 * | | | | 508 * | | | | 509 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 510 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 511 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 512 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 513 */ 514 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 515 { 516 uint32_t line_flag_irq; 517 unsigned long flags; 518 519 spin_lock_irqsave(&vop->irq_lock, flags); 520 521 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 522 523 spin_unlock_irqrestore(&vop->irq_lock, flags); 524 525 return !!line_flag_irq; 526 } 527 528 static void vop_line_flag_irq_enable(struct vop *vop) 529 { 530 unsigned long flags; 531 532 if (WARN_ON(!vop->is_enabled)) 533 return; 534 535 spin_lock_irqsave(&vop->irq_lock, flags); 536 537 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 538 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 539 540 spin_unlock_irqrestore(&vop->irq_lock, flags); 541 } 542 543 static void vop_line_flag_irq_disable(struct vop *vop) 544 { 545 unsigned long flags; 546 547 if (WARN_ON(!vop->is_enabled)) 548 return; 549 550 spin_lock_irqsave(&vop->irq_lock, flags); 551 552 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 553 554 spin_unlock_irqrestore(&vop->irq_lock, flags); 555 } 556 557 static int vop_core_clks_enable(struct vop *vop) 558 { 559 int ret; 560 561 ret = clk_enable(vop->hclk); 562 if (ret < 0) 563 return ret; 564 565 ret = clk_enable(vop->aclk); 566 if (ret < 0) 567 goto err_disable_hclk; 568 569 return 0; 570 571 err_disable_hclk: 572 clk_disable(vop->hclk); 573 return ret; 574 } 575 576 static void vop_core_clks_disable(struct vop *vop) 577 { 578 clk_disable(vop->aclk); 579 clk_disable(vop->hclk); 580 } 581 582 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 583 { 584 const struct vop_win_data *win = vop_win->data; 585 586 if (win->phy->scl && win->phy->scl->ext) { 587 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 588 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 589 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 590 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 591 } 592 593 VOP_WIN_SET(vop, win, enable, 0); 594 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 595 } 596 597 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 598 { 599 struct vop *vop = to_vop(crtc); 600 int ret, i; 601 602 ret = pm_runtime_resume_and_get(vop->dev); 603 if (ret < 0) { 604 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 605 return ret; 606 } 607 608 ret = vop_core_clks_enable(vop); 609 if (WARN_ON(ret < 0)) 610 goto err_put_pm_runtime; 611 612 ret = clk_enable(vop->dclk); 613 if (WARN_ON(ret < 0)) 614 goto err_disable_core; 615 616 /* 617 * Slave iommu shares power, irq and clock with vop. It was associated 618 * automatically with this master device via common driver code. 619 * Now that we have enabled the clock we attach it to the shared drm 620 * mapping. 621 */ 622 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 623 if (ret) { 624 DRM_DEV_ERROR(vop->dev, 625 "failed to attach dma mapping, %d\n", ret); 626 goto err_disable_dclk; 627 } 628 629 spin_lock(&vop->reg_lock); 630 for (i = 0; i < vop->len; i += 4) 631 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 632 633 /* 634 * We need to make sure that all windows are disabled before we 635 * enable the crtc. Otherwise we might try to scan from a destroyed 636 * buffer later. 637 * 638 * In the case of enable-after-PSR, we don't need to worry about this 639 * case since the buffer is guaranteed to be valid and disabling the 640 * window will result in screen glitches on PSR exit. 641 */ 642 if (!old_state || !old_state->self_refresh_active) { 643 for (i = 0; i < vop->data->win_size; i++) { 644 struct vop_win *vop_win = &vop->win[i]; 645 646 vop_win_disable(vop, vop_win); 647 } 648 } 649 650 if (vop->data->afbc) { 651 struct rockchip_crtc_state *s; 652 /* 653 * Disable AFBC and forget there was a vop window with AFBC 654 */ 655 VOP_AFBC_SET(vop, enable, 0); 656 s = to_rockchip_crtc_state(crtc->state); 657 s->enable_afbc = false; 658 } 659 660 vop_cfg_done(vop); 661 662 spin_unlock(&vop->reg_lock); 663 664 /* 665 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 666 */ 667 vop->is_enabled = true; 668 669 spin_lock(&vop->reg_lock); 670 671 VOP_REG_SET(vop, common, standby, 1); 672 673 spin_unlock(&vop->reg_lock); 674 675 drm_crtc_vblank_on(crtc); 676 677 return 0; 678 679 err_disable_dclk: 680 clk_disable(vop->dclk); 681 err_disable_core: 682 vop_core_clks_disable(vop); 683 err_put_pm_runtime: 684 pm_runtime_put_sync(vop->dev); 685 return ret; 686 } 687 688 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 689 { 690 struct vop *vop = to_vop(crtc); 691 int i; 692 693 spin_lock(&vop->reg_lock); 694 695 for (i = 0; i < vop->data->win_size; i++) { 696 struct vop_win *vop_win = &vop->win[i]; 697 const struct vop_win_data *win = vop_win->data; 698 699 VOP_WIN_SET(vop, win, enable, 700 enabled && (vop->win_enabled & BIT(i))); 701 } 702 vop_cfg_done(vop); 703 704 spin_unlock(&vop->reg_lock); 705 } 706 707 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 708 struct drm_atomic_state *state) 709 { 710 struct vop *vop = to_vop(crtc); 711 712 WARN_ON(vop->event); 713 714 if (crtc->state->self_refresh_active) 715 rockchip_drm_set_win_enabled(crtc, false); 716 717 mutex_lock(&vop->vop_lock); 718 719 drm_crtc_vblank_off(crtc); 720 721 if (crtc->state->self_refresh_active) 722 goto out; 723 724 /* 725 * Vop standby will take effect at end of current frame, 726 * if dsp hold valid irq happen, it means standby complete. 727 * 728 * we must wait standby complete when we want to disable aclk, 729 * if not, memory bus maybe dead. 730 */ 731 reinit_completion(&vop->dsp_hold_completion); 732 vop_dsp_hold_valid_irq_enable(vop); 733 734 spin_lock(&vop->reg_lock); 735 736 VOP_REG_SET(vop, common, standby, 1); 737 738 spin_unlock(&vop->reg_lock); 739 740 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 741 msecs_to_jiffies(200))) 742 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 743 744 vop_dsp_hold_valid_irq_disable(vop); 745 746 vop->is_enabled = false; 747 748 /* 749 * vop standby complete, so iommu detach is safe. 750 */ 751 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 752 753 clk_disable(vop->dclk); 754 vop_core_clks_disable(vop); 755 pm_runtime_put(vop->dev); 756 757 out: 758 mutex_unlock(&vop->vop_lock); 759 760 if (crtc->state->event && !crtc->state->active) { 761 spin_lock_irq(&crtc->dev->event_lock); 762 drm_crtc_send_vblank_event(crtc, crtc->state->event); 763 spin_unlock_irq(&crtc->dev->event_lock); 764 765 crtc->state->event = NULL; 766 } 767 } 768 769 static void vop_plane_destroy(struct drm_plane *plane) 770 { 771 drm_plane_cleanup(plane); 772 } 773 774 static inline bool rockchip_afbc(u64 modifier) 775 { 776 return modifier == ROCKCHIP_AFBC_MOD; 777 } 778 779 static bool rockchip_mod_supported(struct drm_plane *plane, 780 u32 format, u64 modifier) 781 { 782 if (modifier == DRM_FORMAT_MOD_LINEAR) 783 return true; 784 785 if (!rockchip_afbc(modifier)) { 786 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 787 788 return false; 789 } 790 791 return vop_convert_afbc_format(format) >= 0; 792 } 793 794 static int vop_plane_atomic_check(struct drm_plane *plane, 795 struct drm_atomic_state *state) 796 { 797 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 798 plane); 799 struct drm_crtc *crtc = new_plane_state->crtc; 800 struct drm_crtc_state *crtc_state; 801 struct drm_framebuffer *fb = new_plane_state->fb; 802 struct vop_win *vop_win = to_vop_win(plane); 803 const struct vop_win_data *win = vop_win->data; 804 int ret; 805 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 806 DRM_PLANE_NO_SCALING; 807 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 808 DRM_PLANE_NO_SCALING; 809 810 if (!crtc || WARN_ON(!fb)) 811 return 0; 812 813 crtc_state = drm_atomic_get_existing_crtc_state(state, 814 crtc); 815 if (WARN_ON(!crtc_state)) 816 return -EINVAL; 817 818 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 819 min_scale, max_scale, 820 true, true); 821 if (ret) 822 return ret; 823 824 if (!new_plane_state->visible) 825 return 0; 826 827 ret = vop_convert_format(fb->format->format); 828 if (ret < 0) 829 return ret; 830 831 /* 832 * Src.x1 can be odd when do clip, but yuv plane start point 833 * need align with 2 pixel. 834 */ 835 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 836 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 837 return -EINVAL; 838 } 839 840 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 841 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 842 return -EINVAL; 843 } 844 845 if (rockchip_afbc(fb->modifier)) { 846 struct vop *vop = to_vop(crtc); 847 848 if (!vop->data->afbc) { 849 DRM_ERROR("vop does not support AFBC\n"); 850 return -EINVAL; 851 } 852 853 ret = vop_convert_afbc_format(fb->format->format); 854 if (ret < 0) 855 return ret; 856 857 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 858 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", 859 new_plane_state->src.x1, 860 new_plane_state->src.y1, fb->offsets[0]); 861 return -EINVAL; 862 } 863 864 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 865 DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 866 new_plane_state->rotation); 867 return -EINVAL; 868 } 869 } 870 871 return 0; 872 } 873 874 static void vop_plane_atomic_disable(struct drm_plane *plane, 875 struct drm_atomic_state *state) 876 { 877 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 878 plane); 879 struct vop_win *vop_win = to_vop_win(plane); 880 struct vop *vop = to_vop(old_state->crtc); 881 882 if (!old_state->crtc) 883 return; 884 885 spin_lock(&vop->reg_lock); 886 887 vop_win_disable(vop, vop_win); 888 889 spin_unlock(&vop->reg_lock); 890 } 891 892 static void vop_plane_atomic_update(struct drm_plane *plane, 893 struct drm_atomic_state *state) 894 { 895 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 896 plane); 897 struct drm_crtc *crtc = new_state->crtc; 898 struct vop_win *vop_win = to_vop_win(plane); 899 const struct vop_win_data *win = vop_win->data; 900 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 901 struct vop *vop = to_vop(new_state->crtc); 902 struct drm_framebuffer *fb = new_state->fb; 903 unsigned int actual_w, actual_h; 904 unsigned int dsp_stx, dsp_sty; 905 uint32_t act_info, dsp_info, dsp_st; 906 struct drm_rect *src = &new_state->src; 907 struct drm_rect *dest = &new_state->dst; 908 struct drm_gem_object *obj, *uv_obj; 909 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 910 unsigned long offset; 911 dma_addr_t dma_addr; 912 uint32_t val; 913 bool rb_swap, uv_swap; 914 int win_index = VOP_WIN_TO_INDEX(vop_win); 915 int format; 916 int is_yuv = fb->format->is_yuv; 917 int i; 918 919 /* 920 * can't update plane when vop is disabled. 921 */ 922 if (WARN_ON(!crtc)) 923 return; 924 925 if (WARN_ON(!vop->is_enabled)) 926 return; 927 928 if (!new_state->visible) { 929 vop_plane_atomic_disable(plane, state); 930 return; 931 } 932 933 obj = fb->obj[0]; 934 rk_obj = to_rockchip_obj(obj); 935 936 actual_w = drm_rect_width(src) >> 16; 937 actual_h = drm_rect_height(src) >> 16; 938 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 939 940 dsp_info = (drm_rect_height(dest) - 1) << 16; 941 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 942 943 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 944 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 945 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 946 947 offset = (src->x1 >> 16) * fb->format->cpp[0]; 948 offset += (src->y1 >> 16) * fb->pitches[0]; 949 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 950 951 /* 952 * For y-mirroring we need to move address 953 * to the beginning of the last line. 954 */ 955 if (new_state->rotation & DRM_MODE_REFLECT_Y) 956 dma_addr += (actual_h - 1) * fb->pitches[0]; 957 958 format = vop_convert_format(fb->format->format); 959 960 spin_lock(&vop->reg_lock); 961 962 if (rockchip_afbc(fb->modifier)) { 963 int afbc_format = vop_convert_afbc_format(fb->format->format); 964 965 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 966 VOP_AFBC_SET(vop, hreg_block_split, 0); 967 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 968 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 969 VOP_AFBC_SET(vop, pic_size, act_info); 970 } 971 972 VOP_WIN_SET(vop, win, format, format); 973 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 974 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 975 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 976 VOP_WIN_SET(vop, win, y_mir_en, 977 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 978 VOP_WIN_SET(vop, win, x_mir_en, 979 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 980 981 if (is_yuv) { 982 int hsub = fb->format->hsub; 983 int vsub = fb->format->vsub; 984 int bpp = fb->format->cpp[1]; 985 986 uv_obj = fb->obj[1]; 987 rk_uv_obj = to_rockchip_obj(uv_obj); 988 989 offset = (src->x1 >> 16) * bpp / hsub; 990 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 991 992 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 993 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 994 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 995 996 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 997 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 998 win_yuv2yuv, 999 y2r_coefficients[i], 1000 bt601_yuv2rgb[i]); 1001 } 1002 1003 uv_swap = has_uv_swapped(fb->format->format); 1004 VOP_WIN_SET(vop, win, uv_swap, uv_swap); 1005 } 1006 1007 if (win->phy->scl) 1008 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 1009 drm_rect_width(dest), drm_rect_height(dest), 1010 fb->format); 1011 1012 VOP_WIN_SET(vop, win, act_info, act_info); 1013 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1014 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1015 1016 rb_swap = has_rb_swapped(fb->format->format); 1017 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1018 1019 /* 1020 * Blending win0 with the background color doesn't seem to work 1021 * correctly. We only get the background color, no matter the contents 1022 * of the win0 framebuffer. However, blending pre-multiplied color 1023 * with the default opaque black default background color is a no-op, 1024 * so we can just disable blending to get the correct result. 1025 */ 1026 if (fb->format->has_alpha && win_index > 0) { 1027 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1028 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1029 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1030 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1031 SRC_BLEND_M0(ALPHA_PER_PIX) | 1032 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1033 SRC_FACTOR_M0(ALPHA_ONE); 1034 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1035 1036 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1037 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1038 VOP_WIN_SET(vop, win, alpha_en, 1); 1039 } else { 1040 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1041 VOP_WIN_SET(vop, win, alpha_en, 0); 1042 } 1043 1044 VOP_WIN_SET(vop, win, enable, 1); 1045 vop->win_enabled |= BIT(win_index); 1046 spin_unlock(&vop->reg_lock); 1047 } 1048 1049 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1050 struct drm_atomic_state *state) 1051 { 1052 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1053 plane); 1054 struct vop_win *vop_win = to_vop_win(plane); 1055 const struct vop_win_data *win = vop_win->data; 1056 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1057 DRM_PLANE_NO_SCALING; 1058 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1059 DRM_PLANE_NO_SCALING; 1060 struct drm_crtc_state *crtc_state; 1061 1062 if (plane != new_plane_state->crtc->cursor) 1063 return -EINVAL; 1064 1065 if (!plane->state) 1066 return -EINVAL; 1067 1068 if (!plane->state->fb) 1069 return -EINVAL; 1070 1071 if (state) 1072 crtc_state = drm_atomic_get_existing_crtc_state(state, 1073 new_plane_state->crtc); 1074 else /* Special case for asynchronous cursor updates. */ 1075 crtc_state = plane->crtc->state; 1076 1077 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1078 min_scale, max_scale, 1079 true, true); 1080 } 1081 1082 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1083 struct drm_atomic_state *state) 1084 { 1085 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1086 plane); 1087 struct vop *vop = to_vop(plane->state->crtc); 1088 struct drm_framebuffer *old_fb = plane->state->fb; 1089 1090 plane->state->crtc_x = new_state->crtc_x; 1091 plane->state->crtc_y = new_state->crtc_y; 1092 plane->state->crtc_h = new_state->crtc_h; 1093 plane->state->crtc_w = new_state->crtc_w; 1094 plane->state->src_x = new_state->src_x; 1095 plane->state->src_y = new_state->src_y; 1096 plane->state->src_h = new_state->src_h; 1097 plane->state->src_w = new_state->src_w; 1098 swap(plane->state->fb, new_state->fb); 1099 1100 if (vop->is_enabled) { 1101 vop_plane_atomic_update(plane, state); 1102 spin_lock(&vop->reg_lock); 1103 vop_cfg_done(vop); 1104 spin_unlock(&vop->reg_lock); 1105 1106 /* 1107 * A scanout can still be occurring, so we can't drop the 1108 * reference to the old framebuffer. To solve this we get a 1109 * reference to old_fb and set a worker to release it later. 1110 * FIXME: if we perform 500 async_update calls before the 1111 * vblank, then we can have 500 different framebuffers waiting 1112 * to be released. 1113 */ 1114 if (old_fb && plane->state->fb != old_fb) { 1115 drm_framebuffer_get(old_fb); 1116 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1117 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1118 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1119 } 1120 } 1121 } 1122 1123 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1124 .atomic_check = vop_plane_atomic_check, 1125 .atomic_update = vop_plane_atomic_update, 1126 .atomic_disable = vop_plane_atomic_disable, 1127 .atomic_async_check = vop_plane_atomic_async_check, 1128 .atomic_async_update = vop_plane_atomic_async_update, 1129 }; 1130 1131 static const struct drm_plane_funcs vop_plane_funcs = { 1132 .update_plane = drm_atomic_helper_update_plane, 1133 .disable_plane = drm_atomic_helper_disable_plane, 1134 .destroy = vop_plane_destroy, 1135 .reset = drm_atomic_helper_plane_reset, 1136 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1137 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1138 .format_mod_supported = rockchip_mod_supported, 1139 }; 1140 1141 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1142 { 1143 struct vop *vop = to_vop(crtc); 1144 unsigned long flags; 1145 1146 if (WARN_ON(!vop->is_enabled)) 1147 return -EPERM; 1148 1149 spin_lock_irqsave(&vop->irq_lock, flags); 1150 1151 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1152 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1153 1154 spin_unlock_irqrestore(&vop->irq_lock, flags); 1155 1156 return 0; 1157 } 1158 1159 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1160 { 1161 struct vop *vop = to_vop(crtc); 1162 unsigned long flags; 1163 1164 if (WARN_ON(!vop->is_enabled)) 1165 return; 1166 1167 spin_lock_irqsave(&vop->irq_lock, flags); 1168 1169 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1170 1171 spin_unlock_irqrestore(&vop->irq_lock, flags); 1172 } 1173 1174 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1175 const struct drm_display_mode *mode, 1176 struct drm_display_mode *adjusted_mode) 1177 { 1178 struct vop *vop = to_vop(crtc); 1179 unsigned long rate; 1180 1181 /* 1182 * Clock craziness. 1183 * 1184 * Key points: 1185 * 1186 * - DRM works in kHz. 1187 * - Clock framework works in Hz. 1188 * - Rockchip's clock driver picks the clock rate that is the 1189 * same _OR LOWER_ than the one requested. 1190 * 1191 * Action plan: 1192 * 1193 * 1. Try to set the exact rate first, and confirm the clock framework 1194 * can provide it. 1195 * 1196 * 2. If the clock framework cannot provide the exact rate, we should 1197 * add 999 Hz to the requested rate. That way if the clock we need 1198 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 1199 * the clock framework will actually give us the right clock. 1200 * 1201 * 3. Get the clock framework to round the rate for us to tell us 1202 * what it will actually make. 1203 * 1204 * 4. Store the rounded up rate so that we don't need to worry about 1205 * this in the actual clk_set_rate(). 1206 */ 1207 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 1208 if (rate / 1000 != adjusted_mode->clock) 1209 rate = clk_round_rate(vop->dclk, 1210 adjusted_mode->clock * 1000 + 999); 1211 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1212 1213 return true; 1214 } 1215 1216 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1217 { 1218 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1219 } 1220 1221 static u32 vop_lut_buffer_index(struct vop *vop) 1222 { 1223 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); 1224 } 1225 1226 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1227 { 1228 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1229 unsigned int i, bpc = ilog2(vop->data->lut_size); 1230 1231 for (i = 0; i < crtc->gamma_size; i++) { 1232 u32 word; 1233 1234 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | 1235 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1236 drm_color_lut_extract(lut[i].blue, bpc); 1237 writel(word, vop->lut_regs + i * 4); 1238 } 1239 } 1240 1241 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1242 struct drm_crtc_state *old_state) 1243 { 1244 struct drm_crtc_state *state = crtc->state; 1245 unsigned int idle; 1246 u32 lut_idx, old_idx; 1247 int ret; 1248 1249 if (!vop->lut_regs) 1250 return; 1251 1252 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { 1253 /* 1254 * To disable gamma (gamma_lut is null) or to write 1255 * an update to the LUT, clear dsp_lut_en. 1256 */ 1257 spin_lock(&vop->reg_lock); 1258 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1259 vop_cfg_done(vop); 1260 spin_unlock(&vop->reg_lock); 1261 1262 /* 1263 * In order to write the LUT to the internal memory, 1264 * we need to first make sure the dsp_lut_en bit is cleared. 1265 */ 1266 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1267 idle, !idle, 5, 30 * 1000); 1268 if (ret) { 1269 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1270 return; 1271 } 1272 1273 if (!state->gamma_lut) 1274 return; 1275 } else { 1276 /* 1277 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, 1278 * by setting update_gamma_lut then waiting for lut_buffer_index change 1279 */ 1280 old_idx = vop_lut_buffer_index(vop); 1281 } 1282 1283 spin_lock(&vop->reg_lock); 1284 vop_crtc_write_gamma_lut(vop, crtc); 1285 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1286 VOP_REG_SET(vop, common, update_gamma_lut, 1); 1287 vop_cfg_done(vop); 1288 spin_unlock(&vop->reg_lock); 1289 1290 if (VOP_HAS_REG(vop, common, update_gamma_lut)) { 1291 ret = readx_poll_timeout(vop_lut_buffer_index, vop, 1292 lut_idx, lut_idx != old_idx, 5, 30 * 1000); 1293 if (ret) { 1294 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); 1295 return; 1296 } 1297 1298 /* 1299 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit 1300 * in our backup of the regs. 1301 */ 1302 spin_lock(&vop->reg_lock); 1303 VOP_REG_SET(vop, common, update_gamma_lut, 0); 1304 spin_unlock(&vop->reg_lock); 1305 } 1306 } 1307 1308 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1309 struct drm_atomic_state *state) 1310 { 1311 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1312 crtc); 1313 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1314 crtc); 1315 struct vop *vop = to_vop(crtc); 1316 1317 /* 1318 * Only update GAMMA if the 'active' flag is not changed, 1319 * otherwise it's updated by .atomic_enable. 1320 */ 1321 if (crtc_state->color_mgmt_changed && 1322 !crtc_state->active_changed) 1323 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1324 } 1325 1326 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1327 struct drm_atomic_state *state) 1328 { 1329 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1330 crtc); 1331 struct vop *vop = to_vop(crtc); 1332 const struct vop_data *vop_data = vop->data; 1333 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1334 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1335 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1336 u16 hdisplay = adjusted_mode->hdisplay; 1337 u16 htotal = adjusted_mode->htotal; 1338 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1339 u16 hact_end = hact_st + hdisplay; 1340 u16 vdisplay = adjusted_mode->vdisplay; 1341 u16 vtotal = adjusted_mode->vtotal; 1342 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1343 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1344 u16 vact_end = vact_st + vdisplay; 1345 uint32_t pin_pol, val; 1346 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1347 int ret; 1348 1349 if (old_state && old_state->self_refresh_active) { 1350 drm_crtc_vblank_on(crtc); 1351 rockchip_drm_set_win_enabled(crtc, true); 1352 return; 1353 } 1354 1355 mutex_lock(&vop->vop_lock); 1356 1357 WARN_ON(vop->event); 1358 1359 ret = vop_enable(crtc, old_state); 1360 if (ret) { 1361 mutex_unlock(&vop->vop_lock); 1362 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1363 return; 1364 } 1365 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1366 BIT(HSYNC_POSITIVE) : 0; 1367 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1368 BIT(VSYNC_POSITIVE) : 0; 1369 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1370 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1371 1372 switch (s->output_type) { 1373 case DRM_MODE_CONNECTOR_LVDS: 1374 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1375 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1376 VOP_REG_SET(vop, output, rgb_en, 1); 1377 break; 1378 case DRM_MODE_CONNECTOR_eDP: 1379 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1380 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1381 VOP_REG_SET(vop, output, edp_en, 1); 1382 break; 1383 case DRM_MODE_CONNECTOR_HDMIA: 1384 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1385 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1386 VOP_REG_SET(vop, output, hdmi_en, 1); 1387 break; 1388 case DRM_MODE_CONNECTOR_DSI: 1389 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1390 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1391 VOP_REG_SET(vop, output, mipi_en, 1); 1392 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1393 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1394 break; 1395 case DRM_MODE_CONNECTOR_DisplayPort: 1396 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1397 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1398 VOP_REG_SET(vop, output, dp_en, 1); 1399 break; 1400 default: 1401 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1402 s->output_type); 1403 } 1404 1405 /* 1406 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1407 */ 1408 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1409 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1410 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1411 1412 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1413 VOP_REG_SET(vop, common, pre_dither_down, 1); 1414 else 1415 VOP_REG_SET(vop, common, pre_dither_down, 0); 1416 1417 if (dither_bpc == 6) { 1418 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1419 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1420 VOP_REG_SET(vop, common, dither_down_en, 1); 1421 } else { 1422 VOP_REG_SET(vop, common, dither_down_en, 0); 1423 } 1424 1425 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1426 1427 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1428 val = hact_st << 16; 1429 val |= hact_end; 1430 VOP_REG_SET(vop, modeset, hact_st_end, val); 1431 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1432 1433 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1434 val = vact_st << 16; 1435 val |= vact_end; 1436 VOP_REG_SET(vop, modeset, vact_st_end, val); 1437 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1438 1439 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1440 1441 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1442 1443 VOP_REG_SET(vop, common, standby, 0); 1444 mutex_unlock(&vop->vop_lock); 1445 1446 /* 1447 * If we have a GAMMA LUT in the state, then let's make sure 1448 * it's updated. We might be coming out of suspend, 1449 * which means the LUT internal memory needs to be re-written. 1450 */ 1451 if (crtc->state->gamma_lut) 1452 vop_crtc_gamma_set(vop, crtc, old_state); 1453 } 1454 1455 static bool vop_fs_irq_is_pending(struct vop *vop) 1456 { 1457 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1458 } 1459 1460 static void vop_wait_for_irq_handler(struct vop *vop) 1461 { 1462 bool pending; 1463 int ret; 1464 1465 /* 1466 * Spin until frame start interrupt status bit goes low, which means 1467 * that interrupt handler was invoked and cleared it. The timeout of 1468 * 10 msecs is really too long, but it is just a safety measure if 1469 * something goes really wrong. The wait will only happen in the very 1470 * unlikely case of a vblank happening exactly at the same time and 1471 * shouldn't exceed microseconds range. 1472 */ 1473 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1474 !pending, 0, 10 * 1000); 1475 if (ret) 1476 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1477 1478 synchronize_irq(vop->irq); 1479 } 1480 1481 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1482 struct drm_atomic_state *state) 1483 { 1484 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1485 crtc); 1486 struct vop *vop = to_vop(crtc); 1487 struct drm_plane *plane; 1488 struct drm_plane_state *plane_state; 1489 struct rockchip_crtc_state *s; 1490 int afbc_planes = 0; 1491 1492 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1493 crtc_state->gamma_lut) { 1494 unsigned int len; 1495 1496 len = drm_color_lut_size(crtc_state->gamma_lut); 1497 if (len != crtc->gamma_size) { 1498 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1499 len, crtc->gamma_size); 1500 return -EINVAL; 1501 } 1502 } 1503 1504 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1505 plane_state = 1506 drm_atomic_get_plane_state(crtc_state->state, plane); 1507 if (IS_ERR(plane_state)) { 1508 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1509 plane->name); 1510 return PTR_ERR(plane_state); 1511 } 1512 1513 if (drm_is_afbc(plane_state->fb->modifier)) 1514 ++afbc_planes; 1515 } 1516 1517 if (afbc_planes > 1) { 1518 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1519 return -EINVAL; 1520 } 1521 1522 s = to_rockchip_crtc_state(crtc_state); 1523 s->enable_afbc = afbc_planes > 0; 1524 1525 return 0; 1526 } 1527 1528 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1529 struct drm_atomic_state *state) 1530 { 1531 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1532 crtc); 1533 struct drm_atomic_state *old_state = old_crtc_state->state; 1534 struct drm_plane_state *old_plane_state, *new_plane_state; 1535 struct vop *vop = to_vop(crtc); 1536 struct drm_plane *plane; 1537 struct rockchip_crtc_state *s; 1538 int i; 1539 1540 if (WARN_ON(!vop->is_enabled)) 1541 return; 1542 1543 spin_lock(&vop->reg_lock); 1544 1545 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1546 s = to_rockchip_crtc_state(crtc->state); 1547 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1548 vop_cfg_done(vop); 1549 1550 spin_unlock(&vop->reg_lock); 1551 1552 /* 1553 * There is a (rather unlikely) possiblity that a vblank interrupt 1554 * fired before we set the cfg_done bit. To avoid spuriously 1555 * signalling flip completion we need to wait for it to finish. 1556 */ 1557 vop_wait_for_irq_handler(vop); 1558 1559 spin_lock_irq(&crtc->dev->event_lock); 1560 if (crtc->state->event) { 1561 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1562 WARN_ON(vop->event); 1563 1564 vop->event = crtc->state->event; 1565 crtc->state->event = NULL; 1566 } 1567 spin_unlock_irq(&crtc->dev->event_lock); 1568 1569 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1570 new_plane_state, i) { 1571 if (!old_plane_state->fb) 1572 continue; 1573 1574 if (old_plane_state->fb == new_plane_state->fb) 1575 continue; 1576 1577 drm_framebuffer_get(old_plane_state->fb); 1578 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1579 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1580 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1581 } 1582 } 1583 1584 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1585 .mode_fixup = vop_crtc_mode_fixup, 1586 .atomic_check = vop_crtc_atomic_check, 1587 .atomic_begin = vop_crtc_atomic_begin, 1588 .atomic_flush = vop_crtc_atomic_flush, 1589 .atomic_enable = vop_crtc_atomic_enable, 1590 .atomic_disable = vop_crtc_atomic_disable, 1591 }; 1592 1593 static void vop_crtc_destroy(struct drm_crtc *crtc) 1594 { 1595 drm_crtc_cleanup(crtc); 1596 } 1597 1598 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1599 { 1600 struct rockchip_crtc_state *rockchip_state; 1601 1602 if (WARN_ON(!crtc->state)) 1603 return NULL; 1604 1605 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1606 if (!rockchip_state) 1607 return NULL; 1608 1609 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1610 return &rockchip_state->base; 1611 } 1612 1613 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1614 struct drm_crtc_state *state) 1615 { 1616 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1617 1618 __drm_atomic_helper_crtc_destroy_state(&s->base); 1619 kfree(s); 1620 } 1621 1622 static void vop_crtc_reset(struct drm_crtc *crtc) 1623 { 1624 struct rockchip_crtc_state *crtc_state = 1625 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1626 1627 if (crtc->state) 1628 vop_crtc_destroy_state(crtc, crtc->state); 1629 1630 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1631 } 1632 1633 #ifdef CONFIG_DRM_ANALOGIX_DP 1634 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1635 { 1636 struct drm_connector *connector; 1637 struct drm_connector_list_iter conn_iter; 1638 1639 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1640 drm_for_each_connector_iter(connector, &conn_iter) { 1641 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1642 drm_connector_list_iter_end(&conn_iter); 1643 return connector; 1644 } 1645 } 1646 drm_connector_list_iter_end(&conn_iter); 1647 1648 return NULL; 1649 } 1650 1651 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1652 const char *source_name) 1653 { 1654 struct vop *vop = to_vop(crtc); 1655 struct drm_connector *connector; 1656 int ret; 1657 1658 connector = vop_get_edp_connector(vop); 1659 if (!connector) 1660 return -EINVAL; 1661 1662 if (source_name && strcmp(source_name, "auto") == 0) 1663 ret = analogix_dp_start_crc(connector); 1664 else if (!source_name) 1665 ret = analogix_dp_stop_crc(connector); 1666 else 1667 ret = -EINVAL; 1668 1669 return ret; 1670 } 1671 1672 static int 1673 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1674 size_t *values_cnt) 1675 { 1676 if (source_name && strcmp(source_name, "auto") != 0) 1677 return -EINVAL; 1678 1679 *values_cnt = 3; 1680 return 0; 1681 } 1682 1683 #else 1684 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1685 const char *source_name) 1686 { 1687 return -ENODEV; 1688 } 1689 1690 static int 1691 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1692 size_t *values_cnt) 1693 { 1694 return -ENODEV; 1695 } 1696 #endif 1697 1698 static const struct drm_crtc_funcs vop_crtc_funcs = { 1699 .set_config = drm_atomic_helper_set_config, 1700 .page_flip = drm_atomic_helper_page_flip, 1701 .destroy = vop_crtc_destroy, 1702 .reset = vop_crtc_reset, 1703 .atomic_duplicate_state = vop_crtc_duplicate_state, 1704 .atomic_destroy_state = vop_crtc_destroy_state, 1705 .enable_vblank = vop_crtc_enable_vblank, 1706 .disable_vblank = vop_crtc_disable_vblank, 1707 .set_crc_source = vop_crtc_set_crc_source, 1708 .verify_crc_source = vop_crtc_verify_crc_source, 1709 }; 1710 1711 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1712 { 1713 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1714 struct drm_framebuffer *fb = val; 1715 1716 drm_crtc_vblank_put(&vop->crtc); 1717 drm_framebuffer_put(fb); 1718 } 1719 1720 static void vop_handle_vblank(struct vop *vop) 1721 { 1722 struct drm_device *drm = vop->drm_dev; 1723 struct drm_crtc *crtc = &vop->crtc; 1724 1725 spin_lock(&drm->event_lock); 1726 if (vop->event) { 1727 drm_crtc_send_vblank_event(crtc, vop->event); 1728 drm_crtc_vblank_put(crtc); 1729 vop->event = NULL; 1730 } 1731 spin_unlock(&drm->event_lock); 1732 1733 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1734 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1735 } 1736 1737 static irqreturn_t vop_isr(int irq, void *data) 1738 { 1739 struct vop *vop = data; 1740 struct drm_crtc *crtc = &vop->crtc; 1741 uint32_t active_irqs; 1742 int ret = IRQ_NONE; 1743 1744 /* 1745 * The irq is shared with the iommu. If the runtime-pm state of the 1746 * vop-device is disabled the irq has to be targeted at the iommu. 1747 */ 1748 if (!pm_runtime_get_if_in_use(vop->dev)) 1749 return IRQ_NONE; 1750 1751 if (vop_core_clks_enable(vop)) { 1752 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1753 goto out; 1754 } 1755 1756 /* 1757 * interrupt register has interrupt status, enable and clear bits, we 1758 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1759 */ 1760 spin_lock(&vop->irq_lock); 1761 1762 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1763 /* Clear all active interrupt sources */ 1764 if (active_irqs) 1765 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1766 1767 spin_unlock(&vop->irq_lock); 1768 1769 /* This is expected for vop iommu irqs, since the irq is shared */ 1770 if (!active_irqs) 1771 goto out_disable; 1772 1773 if (active_irqs & DSP_HOLD_VALID_INTR) { 1774 complete(&vop->dsp_hold_completion); 1775 active_irqs &= ~DSP_HOLD_VALID_INTR; 1776 ret = IRQ_HANDLED; 1777 } 1778 1779 if (active_irqs & LINE_FLAG_INTR) { 1780 complete(&vop->line_flag_completion); 1781 active_irqs &= ~LINE_FLAG_INTR; 1782 ret = IRQ_HANDLED; 1783 } 1784 1785 if (active_irqs & FS_INTR) { 1786 drm_crtc_handle_vblank(crtc); 1787 vop_handle_vblank(vop); 1788 active_irqs &= ~FS_INTR; 1789 ret = IRQ_HANDLED; 1790 } 1791 1792 /* Unhandled irqs are spurious. */ 1793 if (active_irqs) 1794 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1795 active_irqs); 1796 1797 out_disable: 1798 vop_core_clks_disable(vop); 1799 out: 1800 pm_runtime_put(vop->dev); 1801 return ret; 1802 } 1803 1804 static void vop_plane_add_properties(struct drm_plane *plane, 1805 const struct vop_win_data *win_data) 1806 { 1807 unsigned int flags = 0; 1808 1809 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1810 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1811 if (flags) 1812 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1813 DRM_MODE_ROTATE_0 | flags); 1814 } 1815 1816 static int vop_create_crtc(struct vop *vop) 1817 { 1818 const struct vop_data *vop_data = vop->data; 1819 struct device *dev = vop->dev; 1820 struct drm_device *drm_dev = vop->drm_dev; 1821 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1822 struct drm_crtc *crtc = &vop->crtc; 1823 struct device_node *port; 1824 int ret; 1825 int i; 1826 1827 /* 1828 * Create drm_plane for primary and cursor planes first, since we need 1829 * to pass them to drm_crtc_init_with_planes, which sets the 1830 * "possible_crtcs" to the newly initialized crtc. 1831 */ 1832 for (i = 0; i < vop_data->win_size; i++) { 1833 struct vop_win *vop_win = &vop->win[i]; 1834 const struct vop_win_data *win_data = vop_win->data; 1835 1836 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1837 win_data->type != DRM_PLANE_TYPE_CURSOR) 1838 continue; 1839 1840 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1841 0, &vop_plane_funcs, 1842 win_data->phy->data_formats, 1843 win_data->phy->nformats, 1844 win_data->phy->format_modifiers, 1845 win_data->type, NULL); 1846 if (ret) { 1847 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1848 ret); 1849 goto err_cleanup_planes; 1850 } 1851 1852 plane = &vop_win->base; 1853 drm_plane_helper_add(plane, &plane_helper_funcs); 1854 vop_plane_add_properties(plane, win_data); 1855 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1856 primary = plane; 1857 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1858 cursor = plane; 1859 } 1860 1861 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1862 &vop_crtc_funcs, NULL); 1863 if (ret) 1864 goto err_cleanup_planes; 1865 1866 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1867 if (vop->lut_regs) { 1868 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1869 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1870 } 1871 1872 /* 1873 * Create drm_planes for overlay windows with possible_crtcs restricted 1874 * to the newly created crtc. 1875 */ 1876 for (i = 0; i < vop_data->win_size; i++) { 1877 struct vop_win *vop_win = &vop->win[i]; 1878 const struct vop_win_data *win_data = vop_win->data; 1879 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1880 1881 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1882 continue; 1883 1884 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1885 possible_crtcs, 1886 &vop_plane_funcs, 1887 win_data->phy->data_formats, 1888 win_data->phy->nformats, 1889 win_data->phy->format_modifiers, 1890 win_data->type, NULL); 1891 if (ret) { 1892 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1893 ret); 1894 goto err_cleanup_crtc; 1895 } 1896 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1897 vop_plane_add_properties(&vop_win->base, win_data); 1898 } 1899 1900 port = of_get_child_by_name(dev->of_node, "port"); 1901 if (!port) { 1902 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1903 dev->of_node); 1904 ret = -ENOENT; 1905 goto err_cleanup_crtc; 1906 } 1907 1908 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1909 vop_fb_unref_worker); 1910 1911 init_completion(&vop->dsp_hold_completion); 1912 init_completion(&vop->line_flag_completion); 1913 crtc->port = port; 1914 1915 ret = drm_self_refresh_helper_init(crtc); 1916 if (ret) 1917 DRM_DEV_DEBUG_KMS(vop->dev, 1918 "Failed to init %s with SR helpers %d, ignoring\n", 1919 crtc->name, ret); 1920 1921 return 0; 1922 1923 err_cleanup_crtc: 1924 drm_crtc_cleanup(crtc); 1925 err_cleanup_planes: 1926 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1927 head) 1928 drm_plane_cleanup(plane); 1929 return ret; 1930 } 1931 1932 static void vop_destroy_crtc(struct vop *vop) 1933 { 1934 struct drm_crtc *crtc = &vop->crtc; 1935 struct drm_device *drm_dev = vop->drm_dev; 1936 struct drm_plane *plane, *tmp; 1937 1938 drm_self_refresh_helper_cleanup(crtc); 1939 1940 of_node_put(crtc->port); 1941 1942 /* 1943 * We need to cleanup the planes now. Why? 1944 * 1945 * The planes are "&vop->win[i].base". That means the memory is 1946 * all part of the big "struct vop" chunk of memory. That memory 1947 * was devm allocated and associated with this component. We need to 1948 * free it ourselves before vop_unbind() finishes. 1949 */ 1950 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1951 head) 1952 vop_plane_destroy(plane); 1953 1954 /* 1955 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1956 * references the CRTC. 1957 */ 1958 drm_crtc_cleanup(crtc); 1959 drm_flip_work_cleanup(&vop->fb_unref_work); 1960 } 1961 1962 static int vop_initial(struct vop *vop) 1963 { 1964 struct reset_control *ahb_rst; 1965 int i, ret; 1966 1967 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1968 if (IS_ERR(vop->hclk)) { 1969 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1970 return PTR_ERR(vop->hclk); 1971 } 1972 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1973 if (IS_ERR(vop->aclk)) { 1974 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1975 return PTR_ERR(vop->aclk); 1976 } 1977 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1978 if (IS_ERR(vop->dclk)) { 1979 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1980 return PTR_ERR(vop->dclk); 1981 } 1982 1983 ret = pm_runtime_resume_and_get(vop->dev); 1984 if (ret < 0) { 1985 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1986 return ret; 1987 } 1988 1989 ret = clk_prepare(vop->dclk); 1990 if (ret < 0) { 1991 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1992 goto err_put_pm_runtime; 1993 } 1994 1995 /* Enable both the hclk and aclk to setup the vop */ 1996 ret = clk_prepare_enable(vop->hclk); 1997 if (ret < 0) { 1998 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1999 goto err_unprepare_dclk; 2000 } 2001 2002 ret = clk_prepare_enable(vop->aclk); 2003 if (ret < 0) { 2004 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 2005 goto err_disable_hclk; 2006 } 2007 2008 /* 2009 * do hclk_reset, reset all vop registers. 2010 */ 2011 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 2012 if (IS_ERR(ahb_rst)) { 2013 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 2014 ret = PTR_ERR(ahb_rst); 2015 goto err_disable_aclk; 2016 } 2017 reset_control_assert(ahb_rst); 2018 usleep_range(10, 20); 2019 reset_control_deassert(ahb_rst); 2020 2021 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 2022 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 2023 2024 for (i = 0; i < vop->len; i += sizeof(u32)) 2025 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 2026 2027 VOP_REG_SET(vop, misc, global_regdone_en, 1); 2028 VOP_REG_SET(vop, common, dsp_blank, 0); 2029 2030 for (i = 0; i < vop->data->win_size; i++) { 2031 struct vop_win *vop_win = &vop->win[i]; 2032 const struct vop_win_data *win = vop_win->data; 2033 int channel = i * 2 + 1; 2034 2035 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 2036 vop_win_disable(vop, vop_win); 2037 VOP_WIN_SET(vop, win, gate, 1); 2038 } 2039 2040 vop_cfg_done(vop); 2041 2042 /* 2043 * do dclk_reset, let all config take affect. 2044 */ 2045 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 2046 if (IS_ERR(vop->dclk_rst)) { 2047 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2048 ret = PTR_ERR(vop->dclk_rst); 2049 goto err_disable_aclk; 2050 } 2051 reset_control_assert(vop->dclk_rst); 2052 usleep_range(10, 20); 2053 reset_control_deassert(vop->dclk_rst); 2054 2055 clk_disable(vop->hclk); 2056 clk_disable(vop->aclk); 2057 2058 vop->is_enabled = false; 2059 2060 pm_runtime_put_sync(vop->dev); 2061 2062 return 0; 2063 2064 err_disable_aclk: 2065 clk_disable_unprepare(vop->aclk); 2066 err_disable_hclk: 2067 clk_disable_unprepare(vop->hclk); 2068 err_unprepare_dclk: 2069 clk_unprepare(vop->dclk); 2070 err_put_pm_runtime: 2071 pm_runtime_put_sync(vop->dev); 2072 return ret; 2073 } 2074 2075 /* 2076 * Initialize the vop->win array elements. 2077 */ 2078 static void vop_win_init(struct vop *vop) 2079 { 2080 const struct vop_data *vop_data = vop->data; 2081 unsigned int i; 2082 2083 for (i = 0; i < vop_data->win_size; i++) { 2084 struct vop_win *vop_win = &vop->win[i]; 2085 const struct vop_win_data *win_data = &vop_data->win[i]; 2086 2087 vop_win->data = win_data; 2088 vop_win->vop = vop; 2089 2090 if (vop_data->win_yuv2yuv) 2091 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2092 } 2093 } 2094 2095 /** 2096 * rockchip_drm_wait_vact_end 2097 * @crtc: CRTC to enable line flag 2098 * @mstimeout: millisecond for timeout 2099 * 2100 * Wait for vact_end line flag irq or timeout. 2101 * 2102 * Returns: 2103 * Zero on success, negative errno on failure. 2104 */ 2105 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2106 { 2107 struct vop *vop = to_vop(crtc); 2108 unsigned long jiffies_left; 2109 int ret = 0; 2110 2111 if (!crtc || !vop->is_enabled) 2112 return -ENODEV; 2113 2114 mutex_lock(&vop->vop_lock); 2115 if (mstimeout <= 0) { 2116 ret = -EINVAL; 2117 goto out; 2118 } 2119 2120 if (vop_line_flag_irq_is_enabled(vop)) { 2121 ret = -EBUSY; 2122 goto out; 2123 } 2124 2125 reinit_completion(&vop->line_flag_completion); 2126 vop_line_flag_irq_enable(vop); 2127 2128 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2129 msecs_to_jiffies(mstimeout)); 2130 vop_line_flag_irq_disable(vop); 2131 2132 if (jiffies_left == 0) { 2133 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2134 ret = -ETIMEDOUT; 2135 goto out; 2136 } 2137 2138 out: 2139 mutex_unlock(&vop->vop_lock); 2140 return ret; 2141 } 2142 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2143 2144 static int vop_bind(struct device *dev, struct device *master, void *data) 2145 { 2146 struct platform_device *pdev = to_platform_device(dev); 2147 const struct vop_data *vop_data; 2148 struct drm_device *drm_dev = data; 2149 struct vop *vop; 2150 struct resource *res; 2151 int ret, irq; 2152 2153 vop_data = of_device_get_match_data(dev); 2154 if (!vop_data) 2155 return -ENODEV; 2156 2157 /* Allocate vop struct and its vop_win array */ 2158 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2159 GFP_KERNEL); 2160 if (!vop) 2161 return -ENOMEM; 2162 2163 vop->dev = dev; 2164 vop->data = vop_data; 2165 vop->drm_dev = drm_dev; 2166 dev_set_drvdata(dev, vop); 2167 2168 vop_win_init(vop); 2169 2170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2171 vop->regs = devm_ioremap_resource(dev, res); 2172 if (IS_ERR(vop->regs)) 2173 return PTR_ERR(vop->regs); 2174 vop->len = resource_size(res); 2175 2176 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2177 if (res) { 2178 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { 2179 DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); 2180 return -EINVAL; 2181 } 2182 vop->lut_regs = devm_ioremap_resource(dev, res); 2183 if (IS_ERR(vop->lut_regs)) 2184 return PTR_ERR(vop->lut_regs); 2185 } 2186 2187 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2188 if (!vop->regsbak) 2189 return -ENOMEM; 2190 2191 irq = platform_get_irq(pdev, 0); 2192 if (irq < 0) { 2193 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2194 return irq; 2195 } 2196 vop->irq = (unsigned int)irq; 2197 2198 spin_lock_init(&vop->reg_lock); 2199 spin_lock_init(&vop->irq_lock); 2200 mutex_init(&vop->vop_lock); 2201 2202 ret = vop_create_crtc(vop); 2203 if (ret) 2204 return ret; 2205 2206 pm_runtime_enable(&pdev->dev); 2207 2208 ret = vop_initial(vop); 2209 if (ret < 0) { 2210 DRM_DEV_ERROR(&pdev->dev, 2211 "cannot initial vop dev - err %d\n", ret); 2212 goto err_disable_pm_runtime; 2213 } 2214 2215 ret = devm_request_irq(dev, vop->irq, vop_isr, 2216 IRQF_SHARED, dev_name(dev), vop); 2217 if (ret) 2218 goto err_disable_pm_runtime; 2219 2220 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2221 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0); 2222 if (IS_ERR(vop->rgb)) { 2223 ret = PTR_ERR(vop->rgb); 2224 goto err_disable_pm_runtime; 2225 } 2226 } 2227 2228 rockchip_drm_dma_init_device(drm_dev, dev); 2229 2230 return 0; 2231 2232 err_disable_pm_runtime: 2233 pm_runtime_disable(&pdev->dev); 2234 vop_destroy_crtc(vop); 2235 return ret; 2236 } 2237 2238 static void vop_unbind(struct device *dev, struct device *master, void *data) 2239 { 2240 struct vop *vop = dev_get_drvdata(dev); 2241 2242 if (vop->rgb) 2243 rockchip_rgb_fini(vop->rgb); 2244 2245 pm_runtime_disable(dev); 2246 vop_destroy_crtc(vop); 2247 2248 clk_unprepare(vop->aclk); 2249 clk_unprepare(vop->hclk); 2250 clk_unprepare(vop->dclk); 2251 } 2252 2253 const struct component_ops vop_component_ops = { 2254 .bind = vop_bind, 2255 .unbind = vop_unbind, 2256 }; 2257 EXPORT_SYMBOL_GPL(vop_component_ops); 2258