1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_plane_helper.h> 22 #ifdef CONFIG_DRM_ANALOGIX_DP 23 #include <drm/bridge/analogix_dp.h> 24 #endif 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/iopoll.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/component.h> 35 36 #include <linux/reset.h> 37 #include <linux/delay.h> 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_psr.h" 43 #include "rockchip_drm_vop.h" 44 45 #define VOP_WIN_SET(x, win, name, v) \ 46 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET(x, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 49 #define VOP_SCL_SET_EXT(x, win, name, v) \ 50 vop_reg_set(vop, &win->phy->scl->ext->name, \ 51 win->base, ~0, v, #name) 52 53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 54 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 55 56 #define VOP_REG_SET(vop, group, name, v) \ 57 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58 59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60 do { \ 61 int i, reg = 0, mask = 0; \ 62 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63 if (vop->data->intr->intrs[i] & type) { \ 64 reg |= (v) << i; \ 65 mask |= 1 << i; \ 66 } \ 67 } \ 68 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69 } while (0) 70 #define VOP_INTR_GET_TYPE(vop, name, type) \ 71 vop_get_intr_type(vop, &vop->data->intr->name, type) 72 73 #define VOP_WIN_GET(x, win, name) \ 74 vop_read_reg(x, win->offset, win->phy->name) 75 76 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 77 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 78 79 #define VOP_WIN_TO_INDEX(vop_win) \ 80 ((vop_win) - (vop_win)->vop->win) 81 82 #define to_vop(x) container_of(x, struct vop, crtc) 83 #define to_vop_win(x) container_of(x, struct vop_win, base) 84 85 enum vop_pending { 86 VOP_PENDING_FB_UNREF, 87 }; 88 89 struct vop_win { 90 struct drm_plane base; 91 const struct vop_win_data *data; 92 struct vop *vop; 93 }; 94 95 struct vop { 96 struct drm_crtc crtc; 97 struct device *dev; 98 struct drm_device *drm_dev; 99 bool is_enabled; 100 101 struct completion dsp_hold_completion; 102 103 /* protected by dev->event_lock */ 104 struct drm_pending_vblank_event *event; 105 106 struct drm_flip_work fb_unref_work; 107 unsigned long pending; 108 109 struct completion line_flag_completion; 110 111 const struct vop_data *data; 112 113 uint32_t *regsbak; 114 void __iomem *regs; 115 116 /* physical map length of vop register */ 117 uint32_t len; 118 119 /* one time only one process allowed to config the register */ 120 spinlock_t reg_lock; 121 /* lock vop irq reg */ 122 spinlock_t irq_lock; 123 /* protects crtc enable/disable */ 124 struct mutex vop_lock; 125 126 unsigned int irq; 127 128 /* vop AHP clk */ 129 struct clk *hclk; 130 /* vop dclk */ 131 struct clk *dclk; 132 /* vop share memory frequency */ 133 struct clk *aclk; 134 135 /* vop dclk reset */ 136 struct reset_control *dclk_rst; 137 138 struct vop_win win[]; 139 }; 140 141 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 142 { 143 writel(v, vop->regs + offset); 144 vop->regsbak[offset >> 2] = v; 145 } 146 147 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 148 { 149 return readl(vop->regs + offset); 150 } 151 152 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 153 const struct vop_reg *reg) 154 { 155 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 156 } 157 158 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 159 uint32_t _offset, uint32_t _mask, uint32_t v, 160 const char *reg_name) 161 { 162 int offset, mask, shift; 163 164 if (!reg || !reg->mask) { 165 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 166 return; 167 } 168 169 offset = reg->offset + _offset; 170 mask = reg->mask & _mask; 171 shift = reg->shift; 172 173 if (reg->write_mask) { 174 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 175 } else { 176 uint32_t cached_val = vop->regsbak[offset >> 2]; 177 178 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 179 vop->regsbak[offset >> 2] = v; 180 } 181 182 if (reg->relaxed) 183 writel_relaxed(v, vop->regs + offset); 184 else 185 writel(v, vop->regs + offset); 186 } 187 188 static inline uint32_t vop_get_intr_type(struct vop *vop, 189 const struct vop_reg *reg, int type) 190 { 191 uint32_t i, ret = 0; 192 uint32_t regs = vop_read_reg(vop, 0, reg); 193 194 for (i = 0; i < vop->data->intr->nintrs; i++) { 195 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 196 ret |= vop->data->intr->intrs[i]; 197 } 198 199 return ret; 200 } 201 202 static inline void vop_cfg_done(struct vop *vop) 203 { 204 VOP_REG_SET(vop, common, cfg_done, 1); 205 } 206 207 static bool has_rb_swapped(uint32_t format) 208 { 209 switch (format) { 210 case DRM_FORMAT_XBGR8888: 211 case DRM_FORMAT_ABGR8888: 212 case DRM_FORMAT_BGR888: 213 case DRM_FORMAT_BGR565: 214 return true; 215 default: 216 return false; 217 } 218 } 219 220 static enum vop_data_format vop_convert_format(uint32_t format) 221 { 222 switch (format) { 223 case DRM_FORMAT_XRGB8888: 224 case DRM_FORMAT_ARGB8888: 225 case DRM_FORMAT_XBGR8888: 226 case DRM_FORMAT_ABGR8888: 227 return VOP_FMT_ARGB8888; 228 case DRM_FORMAT_RGB888: 229 case DRM_FORMAT_BGR888: 230 return VOP_FMT_RGB888; 231 case DRM_FORMAT_RGB565: 232 case DRM_FORMAT_BGR565: 233 return VOP_FMT_RGB565; 234 case DRM_FORMAT_NV12: 235 return VOP_FMT_YUV420SP; 236 case DRM_FORMAT_NV16: 237 return VOP_FMT_YUV422SP; 238 case DRM_FORMAT_NV24: 239 return VOP_FMT_YUV444SP; 240 default: 241 DRM_ERROR("unsupported format[%08x]\n", format); 242 return -EINVAL; 243 } 244 } 245 246 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 247 uint32_t dst, bool is_horizontal, 248 int vsu_mode, int *vskiplines) 249 { 250 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 251 252 if (vskiplines) 253 *vskiplines = 0; 254 255 if (is_horizontal) { 256 if (mode == SCALE_UP) 257 val = GET_SCL_FT_BIC(src, dst); 258 else if (mode == SCALE_DOWN) 259 val = GET_SCL_FT_BILI_DN(src, dst); 260 } else { 261 if (mode == SCALE_UP) { 262 if (vsu_mode == SCALE_UP_BIL) 263 val = GET_SCL_FT_BILI_UP(src, dst); 264 else 265 val = GET_SCL_FT_BIC(src, dst); 266 } else if (mode == SCALE_DOWN) { 267 if (vskiplines) { 268 *vskiplines = scl_get_vskiplines(src, dst); 269 val = scl_get_bili_dn_vskip(src, dst, 270 *vskiplines); 271 } else { 272 val = GET_SCL_FT_BILI_DN(src, dst); 273 } 274 } 275 } 276 277 return val; 278 } 279 280 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 281 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 282 uint32_t dst_h, uint32_t pixel_format) 283 { 284 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 285 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 286 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 287 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 288 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 289 const struct drm_format_info *info; 290 bool is_yuv = false; 291 uint16_t cbcr_src_w = src_w / hsub; 292 uint16_t cbcr_src_h = src_h / vsub; 293 uint16_t vsu_mode; 294 uint16_t lb_mode; 295 uint32_t val; 296 int vskiplines; 297 298 info = drm_format_info(pixel_format); 299 300 if (info->is_yuv) 301 is_yuv = true; 302 303 if (dst_w > 3840) { 304 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 305 return; 306 } 307 308 if (!win->phy->scl->ext) { 309 VOP_SCL_SET(vop, win, scale_yrgb_x, 310 scl_cal_scale2(src_w, dst_w)); 311 VOP_SCL_SET(vop, win, scale_yrgb_y, 312 scl_cal_scale2(src_h, dst_h)); 313 if (is_yuv) { 314 VOP_SCL_SET(vop, win, scale_cbcr_x, 315 scl_cal_scale2(cbcr_src_w, dst_w)); 316 VOP_SCL_SET(vop, win, scale_cbcr_y, 317 scl_cal_scale2(cbcr_src_h, dst_h)); 318 } 319 return; 320 } 321 322 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 323 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 324 325 if (is_yuv) { 326 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 327 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 328 if (cbcr_hor_scl_mode == SCALE_DOWN) 329 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 330 else 331 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 332 } else { 333 if (yrgb_hor_scl_mode == SCALE_DOWN) 334 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 335 else 336 lb_mode = scl_vop_cal_lb_mode(src_w, false); 337 } 338 339 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 340 if (lb_mode == LB_RGB_3840X2) { 341 if (yrgb_ver_scl_mode != SCALE_NONE) { 342 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 343 return; 344 } 345 if (cbcr_ver_scl_mode != SCALE_NONE) { 346 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 347 return; 348 } 349 vsu_mode = SCALE_UP_BIL; 350 } else if (lb_mode == LB_RGB_2560X4) { 351 vsu_mode = SCALE_UP_BIL; 352 } else { 353 vsu_mode = SCALE_UP_BIC; 354 } 355 356 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 357 true, 0, NULL); 358 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 359 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 360 false, vsu_mode, &vskiplines); 361 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 362 363 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 364 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 365 366 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 367 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 368 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 369 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 370 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 371 if (is_yuv) { 372 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 373 dst_w, true, 0, NULL); 374 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 375 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 376 dst_h, false, vsu_mode, &vskiplines); 377 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 378 379 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 380 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 381 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 382 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 383 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 384 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 385 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 386 } 387 } 388 389 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 390 { 391 unsigned long flags; 392 393 if (WARN_ON(!vop->is_enabled)) 394 return; 395 396 spin_lock_irqsave(&vop->irq_lock, flags); 397 398 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 399 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 400 401 spin_unlock_irqrestore(&vop->irq_lock, flags); 402 } 403 404 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 405 { 406 unsigned long flags; 407 408 if (WARN_ON(!vop->is_enabled)) 409 return; 410 411 spin_lock_irqsave(&vop->irq_lock, flags); 412 413 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 414 415 spin_unlock_irqrestore(&vop->irq_lock, flags); 416 } 417 418 /* 419 * (1) each frame starts at the start of the Vsync pulse which is signaled by 420 * the "FRAME_SYNC" interrupt. 421 * (2) the active data region of each frame ends at dsp_vact_end 422 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 423 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 424 * 425 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 426 * Interrupts 427 * LINE_FLAG -------------------------------+ 428 * FRAME_SYNC ----+ | 429 * | | 430 * v v 431 * | Vsync | Vbp | Vactive | Vfp | 432 * ^ ^ ^ ^ 433 * | | | | 434 * | | | | 435 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 436 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 437 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 438 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 439 */ 440 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 441 { 442 uint32_t line_flag_irq; 443 unsigned long flags; 444 445 spin_lock_irqsave(&vop->irq_lock, flags); 446 447 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 448 449 spin_unlock_irqrestore(&vop->irq_lock, flags); 450 451 return !!line_flag_irq; 452 } 453 454 static void vop_line_flag_irq_enable(struct vop *vop) 455 { 456 unsigned long flags; 457 458 if (WARN_ON(!vop->is_enabled)) 459 return; 460 461 spin_lock_irqsave(&vop->irq_lock, flags); 462 463 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 464 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 465 466 spin_unlock_irqrestore(&vop->irq_lock, flags); 467 } 468 469 static void vop_line_flag_irq_disable(struct vop *vop) 470 { 471 unsigned long flags; 472 473 if (WARN_ON(!vop->is_enabled)) 474 return; 475 476 spin_lock_irqsave(&vop->irq_lock, flags); 477 478 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 479 480 spin_unlock_irqrestore(&vop->irq_lock, flags); 481 } 482 483 static int vop_core_clks_enable(struct vop *vop) 484 { 485 int ret; 486 487 ret = clk_enable(vop->hclk); 488 if (ret < 0) 489 return ret; 490 491 ret = clk_enable(vop->aclk); 492 if (ret < 0) 493 goto err_disable_hclk; 494 495 return 0; 496 497 err_disable_hclk: 498 clk_disable(vop->hclk); 499 return ret; 500 } 501 502 static void vop_core_clks_disable(struct vop *vop) 503 { 504 clk_disable(vop->aclk); 505 clk_disable(vop->hclk); 506 } 507 508 static int vop_enable(struct drm_crtc *crtc) 509 { 510 struct vop *vop = to_vop(crtc); 511 int ret, i; 512 513 ret = pm_runtime_get_sync(vop->dev); 514 if (ret < 0) { 515 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 516 return ret; 517 } 518 519 ret = vop_core_clks_enable(vop); 520 if (WARN_ON(ret < 0)) 521 goto err_put_pm_runtime; 522 523 ret = clk_enable(vop->dclk); 524 if (WARN_ON(ret < 0)) 525 goto err_disable_core; 526 527 /* 528 * Slave iommu shares power, irq and clock with vop. It was associated 529 * automatically with this master device via common driver code. 530 * Now that we have enabled the clock we attach it to the shared drm 531 * mapping. 532 */ 533 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 534 if (ret) { 535 DRM_DEV_ERROR(vop->dev, 536 "failed to attach dma mapping, %d\n", ret); 537 goto err_disable_dclk; 538 } 539 540 spin_lock(&vop->reg_lock); 541 for (i = 0; i < vop->len; i += 4) 542 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 543 544 /* 545 * We need to make sure that all windows are disabled before we 546 * enable the crtc. Otherwise we might try to scan from a destroyed 547 * buffer later. 548 */ 549 for (i = 0; i < vop->data->win_size; i++) { 550 struct vop_win *vop_win = &vop->win[i]; 551 const struct vop_win_data *win = vop_win->data; 552 553 VOP_WIN_SET(vop, win, enable, 0); 554 } 555 spin_unlock(&vop->reg_lock); 556 557 vop_cfg_done(vop); 558 559 /* 560 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 561 */ 562 vop->is_enabled = true; 563 564 spin_lock(&vop->reg_lock); 565 566 VOP_REG_SET(vop, common, standby, 1); 567 568 spin_unlock(&vop->reg_lock); 569 570 drm_crtc_vblank_on(crtc); 571 572 return 0; 573 574 err_disable_dclk: 575 clk_disable(vop->dclk); 576 err_disable_core: 577 vop_core_clks_disable(vop); 578 err_put_pm_runtime: 579 pm_runtime_put_sync(vop->dev); 580 return ret; 581 } 582 583 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 584 struct drm_crtc_state *old_state) 585 { 586 struct vop *vop = to_vop(crtc); 587 588 WARN_ON(vop->event); 589 590 mutex_lock(&vop->vop_lock); 591 drm_crtc_vblank_off(crtc); 592 593 /* 594 * Vop standby will take effect at end of current frame, 595 * if dsp hold valid irq happen, it means standby complete. 596 * 597 * we must wait standby complete when we want to disable aclk, 598 * if not, memory bus maybe dead. 599 */ 600 reinit_completion(&vop->dsp_hold_completion); 601 vop_dsp_hold_valid_irq_enable(vop); 602 603 spin_lock(&vop->reg_lock); 604 605 VOP_REG_SET(vop, common, standby, 1); 606 607 spin_unlock(&vop->reg_lock); 608 609 wait_for_completion(&vop->dsp_hold_completion); 610 611 vop_dsp_hold_valid_irq_disable(vop); 612 613 vop->is_enabled = false; 614 615 /* 616 * vop standby complete, so iommu detach is safe. 617 */ 618 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 619 620 clk_disable(vop->dclk); 621 vop_core_clks_disable(vop); 622 pm_runtime_put(vop->dev); 623 mutex_unlock(&vop->vop_lock); 624 625 if (crtc->state->event && !crtc->state->active) { 626 spin_lock_irq(&crtc->dev->event_lock); 627 drm_crtc_send_vblank_event(crtc, crtc->state->event); 628 spin_unlock_irq(&crtc->dev->event_lock); 629 630 crtc->state->event = NULL; 631 } 632 } 633 634 static void vop_plane_destroy(struct drm_plane *plane) 635 { 636 drm_plane_cleanup(plane); 637 } 638 639 static int vop_plane_atomic_check(struct drm_plane *plane, 640 struct drm_plane_state *state) 641 { 642 struct drm_crtc *crtc = state->crtc; 643 struct drm_crtc_state *crtc_state; 644 struct drm_framebuffer *fb = state->fb; 645 struct vop_win *vop_win = to_vop_win(plane); 646 const struct vop_win_data *win = vop_win->data; 647 int ret; 648 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 649 DRM_PLANE_HELPER_NO_SCALING; 650 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 651 DRM_PLANE_HELPER_NO_SCALING; 652 653 if (!crtc || !fb) 654 return 0; 655 656 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 657 if (WARN_ON(!crtc_state)) 658 return -EINVAL; 659 660 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 661 min_scale, max_scale, 662 true, true); 663 if (ret) 664 return ret; 665 666 if (!state->visible) 667 return 0; 668 669 ret = vop_convert_format(fb->format->format); 670 if (ret < 0) 671 return ret; 672 673 /* 674 * Src.x1 can be odd when do clip, but yuv plane start point 675 * need align with 2 pixel. 676 */ 677 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 678 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 679 return -EINVAL; 680 } 681 682 return 0; 683 } 684 685 static void vop_plane_atomic_disable(struct drm_plane *plane, 686 struct drm_plane_state *old_state) 687 { 688 struct vop_win *vop_win = to_vop_win(plane); 689 const struct vop_win_data *win = vop_win->data; 690 struct vop *vop = to_vop(old_state->crtc); 691 692 if (!old_state->crtc) 693 return; 694 695 spin_lock(&vop->reg_lock); 696 697 VOP_WIN_SET(vop, win, enable, 0); 698 699 spin_unlock(&vop->reg_lock); 700 } 701 702 static void vop_plane_atomic_update(struct drm_plane *plane, 703 struct drm_plane_state *old_state) 704 { 705 struct drm_plane_state *state = plane->state; 706 struct drm_crtc *crtc = state->crtc; 707 struct vop_win *vop_win = to_vop_win(plane); 708 const struct vop_win_data *win = vop_win->data; 709 struct vop *vop = to_vop(state->crtc); 710 struct drm_framebuffer *fb = state->fb; 711 unsigned int actual_w, actual_h; 712 unsigned int dsp_stx, dsp_sty; 713 uint32_t act_info, dsp_info, dsp_st; 714 struct drm_rect *src = &state->src; 715 struct drm_rect *dest = &state->dst; 716 struct drm_gem_object *obj, *uv_obj; 717 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 718 unsigned long offset; 719 dma_addr_t dma_addr; 720 uint32_t val; 721 bool rb_swap; 722 int win_index = VOP_WIN_TO_INDEX(vop_win); 723 int format; 724 725 /* 726 * can't update plane when vop is disabled. 727 */ 728 if (WARN_ON(!crtc)) 729 return; 730 731 if (WARN_ON(!vop->is_enabled)) 732 return; 733 734 if (!state->visible) { 735 vop_plane_atomic_disable(plane, old_state); 736 return; 737 } 738 739 obj = fb->obj[0]; 740 rk_obj = to_rockchip_obj(obj); 741 742 actual_w = drm_rect_width(src) >> 16; 743 actual_h = drm_rect_height(src) >> 16; 744 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 745 746 dsp_info = (drm_rect_height(dest) - 1) << 16; 747 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 748 749 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 750 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 751 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 752 753 offset = (src->x1 >> 16) * fb->format->cpp[0]; 754 offset += (src->y1 >> 16) * fb->pitches[0]; 755 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 756 757 format = vop_convert_format(fb->format->format); 758 759 spin_lock(&vop->reg_lock); 760 761 VOP_WIN_SET(vop, win, format, format); 762 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 763 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 764 if (fb->format->is_yuv) { 765 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 766 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 767 int bpp = fb->format->cpp[1]; 768 769 uv_obj = fb->obj[1]; 770 rk_uv_obj = to_rockchip_obj(uv_obj); 771 772 offset = (src->x1 >> 16) * bpp / hsub; 773 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 774 775 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 776 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 777 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 778 } 779 780 if (win->phy->scl) 781 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 782 drm_rect_width(dest), drm_rect_height(dest), 783 fb->format->format); 784 785 VOP_WIN_SET(vop, win, act_info, act_info); 786 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 787 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 788 789 rb_swap = has_rb_swapped(fb->format->format); 790 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 791 792 /* 793 * Blending win0 with the background color doesn't seem to work 794 * correctly. We only get the background color, no matter the contents 795 * of the win0 framebuffer. However, blending pre-multiplied color 796 * with the default opaque black default background color is a no-op, 797 * so we can just disable blending to get the correct result. 798 */ 799 if (fb->format->has_alpha && win_index > 0) { 800 VOP_WIN_SET(vop, win, dst_alpha_ctl, 801 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 802 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 803 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 804 SRC_BLEND_M0(ALPHA_PER_PIX) | 805 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 806 SRC_FACTOR_M0(ALPHA_ONE); 807 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 808 } else { 809 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 810 } 811 812 VOP_WIN_SET(vop, win, enable, 1); 813 spin_unlock(&vop->reg_lock); 814 } 815 816 static const struct drm_plane_helper_funcs plane_helper_funcs = { 817 .atomic_check = vop_plane_atomic_check, 818 .atomic_update = vop_plane_atomic_update, 819 .atomic_disable = vop_plane_atomic_disable, 820 }; 821 822 static const struct drm_plane_funcs vop_plane_funcs = { 823 .update_plane = drm_atomic_helper_update_plane, 824 .disable_plane = drm_atomic_helper_disable_plane, 825 .destroy = vop_plane_destroy, 826 .reset = drm_atomic_helper_plane_reset, 827 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 828 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 829 }; 830 831 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 832 { 833 struct vop *vop = to_vop(crtc); 834 unsigned long flags; 835 836 if (WARN_ON(!vop->is_enabled)) 837 return -EPERM; 838 839 spin_lock_irqsave(&vop->irq_lock, flags); 840 841 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 842 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 843 844 spin_unlock_irqrestore(&vop->irq_lock, flags); 845 846 return 0; 847 } 848 849 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 850 { 851 struct vop *vop = to_vop(crtc); 852 unsigned long flags; 853 854 if (WARN_ON(!vop->is_enabled)) 855 return; 856 857 spin_lock_irqsave(&vop->irq_lock, flags); 858 859 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 860 861 spin_unlock_irqrestore(&vop->irq_lock, flags); 862 } 863 864 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 865 const struct drm_display_mode *mode, 866 struct drm_display_mode *adjusted_mode) 867 { 868 struct vop *vop = to_vop(crtc); 869 870 adjusted_mode->clock = 871 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 872 873 return true; 874 } 875 876 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 877 struct drm_crtc_state *old_state) 878 { 879 struct vop *vop = to_vop(crtc); 880 const struct vop_data *vop_data = vop->data; 881 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 882 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 883 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 884 u16 hdisplay = adjusted_mode->hdisplay; 885 u16 htotal = adjusted_mode->htotal; 886 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 887 u16 hact_end = hact_st + hdisplay; 888 u16 vdisplay = adjusted_mode->vdisplay; 889 u16 vtotal = adjusted_mode->vtotal; 890 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 891 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 892 u16 vact_end = vact_st + vdisplay; 893 uint32_t pin_pol, val; 894 int ret; 895 896 mutex_lock(&vop->vop_lock); 897 898 WARN_ON(vop->event); 899 900 ret = vop_enable(crtc); 901 if (ret) { 902 mutex_unlock(&vop->vop_lock); 903 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 904 return; 905 } 906 907 pin_pol = BIT(DCLK_INVERT); 908 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 909 BIT(HSYNC_POSITIVE) : 0; 910 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 911 BIT(VSYNC_POSITIVE) : 0; 912 VOP_REG_SET(vop, output, pin_pol, pin_pol); 913 914 switch (s->output_type) { 915 case DRM_MODE_CONNECTOR_LVDS: 916 VOP_REG_SET(vop, output, rgb_en, 1); 917 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 918 break; 919 case DRM_MODE_CONNECTOR_eDP: 920 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 921 VOP_REG_SET(vop, output, edp_en, 1); 922 break; 923 case DRM_MODE_CONNECTOR_HDMIA: 924 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 925 VOP_REG_SET(vop, output, hdmi_en, 1); 926 break; 927 case DRM_MODE_CONNECTOR_DSI: 928 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 929 VOP_REG_SET(vop, output, mipi_en, 1); 930 break; 931 case DRM_MODE_CONNECTOR_DisplayPort: 932 pin_pol &= ~BIT(DCLK_INVERT); 933 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 934 VOP_REG_SET(vop, output, dp_en, 1); 935 break; 936 default: 937 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 938 s->output_type); 939 } 940 941 /* 942 * if vop is not support RGB10 output, need force RGB10 to RGB888. 943 */ 944 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 945 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 946 s->output_mode = ROCKCHIP_OUT_MODE_P888; 947 948 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8) 949 VOP_REG_SET(vop, common, pre_dither_down, 1); 950 else 951 VOP_REG_SET(vop, common, pre_dither_down, 0); 952 953 VOP_REG_SET(vop, common, out_mode, s->output_mode); 954 955 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 956 val = hact_st << 16; 957 val |= hact_end; 958 VOP_REG_SET(vop, modeset, hact_st_end, val); 959 VOP_REG_SET(vop, modeset, hpost_st_end, val); 960 961 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 962 val = vact_st << 16; 963 val |= vact_end; 964 VOP_REG_SET(vop, modeset, vact_st_end, val); 965 VOP_REG_SET(vop, modeset, vpost_st_end, val); 966 967 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 968 969 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 970 971 VOP_REG_SET(vop, common, standby, 0); 972 mutex_unlock(&vop->vop_lock); 973 } 974 975 static bool vop_fs_irq_is_pending(struct vop *vop) 976 { 977 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 978 } 979 980 static void vop_wait_for_irq_handler(struct vop *vop) 981 { 982 bool pending; 983 int ret; 984 985 /* 986 * Spin until frame start interrupt status bit goes low, which means 987 * that interrupt handler was invoked and cleared it. The timeout of 988 * 10 msecs is really too long, but it is just a safety measure if 989 * something goes really wrong. The wait will only happen in the very 990 * unlikely case of a vblank happening exactly at the same time and 991 * shouldn't exceed microseconds range. 992 */ 993 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 994 !pending, 0, 10 * 1000); 995 if (ret) 996 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 997 998 synchronize_irq(vop->irq); 999 } 1000 1001 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1002 struct drm_crtc_state *old_crtc_state) 1003 { 1004 struct drm_atomic_state *old_state = old_crtc_state->state; 1005 struct drm_plane_state *old_plane_state, *new_plane_state; 1006 struct vop *vop = to_vop(crtc); 1007 struct drm_plane *plane; 1008 int i; 1009 1010 if (WARN_ON(!vop->is_enabled)) 1011 return; 1012 1013 spin_lock(&vop->reg_lock); 1014 1015 vop_cfg_done(vop); 1016 1017 spin_unlock(&vop->reg_lock); 1018 1019 /* 1020 * There is a (rather unlikely) possiblity that a vblank interrupt 1021 * fired before we set the cfg_done bit. To avoid spuriously 1022 * signalling flip completion we need to wait for it to finish. 1023 */ 1024 vop_wait_for_irq_handler(vop); 1025 1026 spin_lock_irq(&crtc->dev->event_lock); 1027 if (crtc->state->event) { 1028 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1029 WARN_ON(vop->event); 1030 1031 vop->event = crtc->state->event; 1032 crtc->state->event = NULL; 1033 } 1034 spin_unlock_irq(&crtc->dev->event_lock); 1035 1036 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1037 new_plane_state, i) { 1038 if (!old_plane_state->fb) 1039 continue; 1040 1041 if (old_plane_state->fb == new_plane_state->fb) 1042 continue; 1043 1044 drm_framebuffer_get(old_plane_state->fb); 1045 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1046 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1047 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1048 } 1049 } 1050 1051 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1052 .mode_fixup = vop_crtc_mode_fixup, 1053 .atomic_flush = vop_crtc_atomic_flush, 1054 .atomic_enable = vop_crtc_atomic_enable, 1055 .atomic_disable = vop_crtc_atomic_disable, 1056 }; 1057 1058 static void vop_crtc_destroy(struct drm_crtc *crtc) 1059 { 1060 drm_crtc_cleanup(crtc); 1061 } 1062 1063 static void vop_crtc_reset(struct drm_crtc *crtc) 1064 { 1065 if (crtc->state) 1066 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1067 kfree(crtc->state); 1068 1069 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1070 if (crtc->state) 1071 crtc->state->crtc = crtc; 1072 } 1073 1074 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1075 { 1076 struct rockchip_crtc_state *rockchip_state; 1077 1078 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1079 if (!rockchip_state) 1080 return NULL; 1081 1082 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1083 return &rockchip_state->base; 1084 } 1085 1086 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1087 struct drm_crtc_state *state) 1088 { 1089 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1090 1091 __drm_atomic_helper_crtc_destroy_state(&s->base); 1092 kfree(s); 1093 } 1094 1095 #ifdef CONFIG_DRM_ANALOGIX_DP 1096 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1097 { 1098 struct drm_connector *connector; 1099 struct drm_connector_list_iter conn_iter; 1100 1101 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1102 drm_for_each_connector_iter(connector, &conn_iter) { 1103 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1104 drm_connector_list_iter_end(&conn_iter); 1105 return connector; 1106 } 1107 } 1108 drm_connector_list_iter_end(&conn_iter); 1109 1110 return NULL; 1111 } 1112 1113 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1114 const char *source_name, size_t *values_cnt) 1115 { 1116 struct vop *vop = to_vop(crtc); 1117 struct drm_connector *connector; 1118 int ret; 1119 1120 connector = vop_get_edp_connector(vop); 1121 if (!connector) 1122 return -EINVAL; 1123 1124 *values_cnt = 3; 1125 1126 if (source_name && strcmp(source_name, "auto") == 0) 1127 ret = analogix_dp_start_crc(connector); 1128 else if (!source_name) 1129 ret = analogix_dp_stop_crc(connector); 1130 else 1131 ret = -EINVAL; 1132 1133 return ret; 1134 } 1135 #else 1136 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1137 const char *source_name, size_t *values_cnt) 1138 { 1139 return -ENODEV; 1140 } 1141 #endif 1142 1143 static const struct drm_crtc_funcs vop_crtc_funcs = { 1144 .set_config = drm_atomic_helper_set_config, 1145 .page_flip = drm_atomic_helper_page_flip, 1146 .destroy = vop_crtc_destroy, 1147 .reset = vop_crtc_reset, 1148 .atomic_duplicate_state = vop_crtc_duplicate_state, 1149 .atomic_destroy_state = vop_crtc_destroy_state, 1150 .enable_vblank = vop_crtc_enable_vblank, 1151 .disable_vblank = vop_crtc_disable_vblank, 1152 .set_crc_source = vop_crtc_set_crc_source, 1153 }; 1154 1155 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1156 { 1157 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1158 struct drm_framebuffer *fb = val; 1159 1160 drm_crtc_vblank_put(&vop->crtc); 1161 drm_framebuffer_put(fb); 1162 } 1163 1164 static void vop_handle_vblank(struct vop *vop) 1165 { 1166 struct drm_device *drm = vop->drm_dev; 1167 struct drm_crtc *crtc = &vop->crtc; 1168 1169 spin_lock(&drm->event_lock); 1170 if (vop->event) { 1171 drm_crtc_send_vblank_event(crtc, vop->event); 1172 drm_crtc_vblank_put(crtc); 1173 vop->event = NULL; 1174 } 1175 spin_unlock(&drm->event_lock); 1176 1177 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1178 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1179 } 1180 1181 static irqreturn_t vop_isr(int irq, void *data) 1182 { 1183 struct vop *vop = data; 1184 struct drm_crtc *crtc = &vop->crtc; 1185 uint32_t active_irqs; 1186 int ret = IRQ_NONE; 1187 1188 /* 1189 * The irq is shared with the iommu. If the runtime-pm state of the 1190 * vop-device is disabled the irq has to be targeted at the iommu. 1191 */ 1192 if (!pm_runtime_get_if_in_use(vop->dev)) 1193 return IRQ_NONE; 1194 1195 if (vop_core_clks_enable(vop)) { 1196 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1197 goto out; 1198 } 1199 1200 /* 1201 * interrupt register has interrupt status, enable and clear bits, we 1202 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1203 */ 1204 spin_lock(&vop->irq_lock); 1205 1206 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1207 /* Clear all active interrupt sources */ 1208 if (active_irqs) 1209 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1210 1211 spin_unlock(&vop->irq_lock); 1212 1213 /* This is expected for vop iommu irqs, since the irq is shared */ 1214 if (!active_irqs) 1215 goto out_disable; 1216 1217 if (active_irqs & DSP_HOLD_VALID_INTR) { 1218 complete(&vop->dsp_hold_completion); 1219 active_irqs &= ~DSP_HOLD_VALID_INTR; 1220 ret = IRQ_HANDLED; 1221 } 1222 1223 if (active_irqs & LINE_FLAG_INTR) { 1224 complete(&vop->line_flag_completion); 1225 active_irqs &= ~LINE_FLAG_INTR; 1226 ret = IRQ_HANDLED; 1227 } 1228 1229 if (active_irqs & FS_INTR) { 1230 drm_crtc_handle_vblank(crtc); 1231 vop_handle_vblank(vop); 1232 active_irqs &= ~FS_INTR; 1233 ret = IRQ_HANDLED; 1234 } 1235 1236 /* Unhandled irqs are spurious. */ 1237 if (active_irqs) 1238 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1239 active_irqs); 1240 1241 out_disable: 1242 vop_core_clks_disable(vop); 1243 out: 1244 pm_runtime_put(vop->dev); 1245 return ret; 1246 } 1247 1248 static int vop_create_crtc(struct vop *vop) 1249 { 1250 const struct vop_data *vop_data = vop->data; 1251 struct device *dev = vop->dev; 1252 struct drm_device *drm_dev = vop->drm_dev; 1253 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1254 struct drm_crtc *crtc = &vop->crtc; 1255 struct device_node *port; 1256 int ret; 1257 int i; 1258 1259 /* 1260 * Create drm_plane for primary and cursor planes first, since we need 1261 * to pass them to drm_crtc_init_with_planes, which sets the 1262 * "possible_crtcs" to the newly initialized crtc. 1263 */ 1264 for (i = 0; i < vop_data->win_size; i++) { 1265 struct vop_win *vop_win = &vop->win[i]; 1266 const struct vop_win_data *win_data = vop_win->data; 1267 1268 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1269 win_data->type != DRM_PLANE_TYPE_CURSOR) 1270 continue; 1271 1272 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1273 0, &vop_plane_funcs, 1274 win_data->phy->data_formats, 1275 win_data->phy->nformats, 1276 NULL, win_data->type, NULL); 1277 if (ret) { 1278 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1279 ret); 1280 goto err_cleanup_planes; 1281 } 1282 1283 plane = &vop_win->base; 1284 drm_plane_helper_add(plane, &plane_helper_funcs); 1285 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1286 primary = plane; 1287 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1288 cursor = plane; 1289 } 1290 1291 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1292 &vop_crtc_funcs, NULL); 1293 if (ret) 1294 goto err_cleanup_planes; 1295 1296 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1297 1298 /* 1299 * Create drm_planes for overlay windows with possible_crtcs restricted 1300 * to the newly created crtc. 1301 */ 1302 for (i = 0; i < vop_data->win_size; i++) { 1303 struct vop_win *vop_win = &vop->win[i]; 1304 const struct vop_win_data *win_data = vop_win->data; 1305 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1306 1307 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1308 continue; 1309 1310 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1311 possible_crtcs, 1312 &vop_plane_funcs, 1313 win_data->phy->data_formats, 1314 win_data->phy->nformats, 1315 NULL, win_data->type, NULL); 1316 if (ret) { 1317 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1318 ret); 1319 goto err_cleanup_crtc; 1320 } 1321 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1322 } 1323 1324 port = of_get_child_by_name(dev->of_node, "port"); 1325 if (!port) { 1326 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1327 dev->of_node); 1328 ret = -ENOENT; 1329 goto err_cleanup_crtc; 1330 } 1331 1332 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1333 vop_fb_unref_worker); 1334 1335 init_completion(&vop->dsp_hold_completion); 1336 init_completion(&vop->line_flag_completion); 1337 crtc->port = port; 1338 1339 return 0; 1340 1341 err_cleanup_crtc: 1342 drm_crtc_cleanup(crtc); 1343 err_cleanup_planes: 1344 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1345 head) 1346 drm_plane_cleanup(plane); 1347 return ret; 1348 } 1349 1350 static void vop_destroy_crtc(struct vop *vop) 1351 { 1352 struct drm_crtc *crtc = &vop->crtc; 1353 struct drm_device *drm_dev = vop->drm_dev; 1354 struct drm_plane *plane, *tmp; 1355 1356 of_node_put(crtc->port); 1357 1358 /* 1359 * We need to cleanup the planes now. Why? 1360 * 1361 * The planes are "&vop->win[i].base". That means the memory is 1362 * all part of the big "struct vop" chunk of memory. That memory 1363 * was devm allocated and associated with this component. We need to 1364 * free it ourselves before vop_unbind() finishes. 1365 */ 1366 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1367 head) 1368 vop_plane_destroy(plane); 1369 1370 /* 1371 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1372 * references the CRTC. 1373 */ 1374 drm_crtc_cleanup(crtc); 1375 drm_flip_work_cleanup(&vop->fb_unref_work); 1376 } 1377 1378 static int vop_initial(struct vop *vop) 1379 { 1380 const struct vop_data *vop_data = vop->data; 1381 struct reset_control *ahb_rst; 1382 int i, ret; 1383 1384 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1385 if (IS_ERR(vop->hclk)) { 1386 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1387 return PTR_ERR(vop->hclk); 1388 } 1389 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1390 if (IS_ERR(vop->aclk)) { 1391 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1392 return PTR_ERR(vop->aclk); 1393 } 1394 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1395 if (IS_ERR(vop->dclk)) { 1396 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1397 return PTR_ERR(vop->dclk); 1398 } 1399 1400 ret = pm_runtime_get_sync(vop->dev); 1401 if (ret < 0) { 1402 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1403 return ret; 1404 } 1405 1406 ret = clk_prepare(vop->dclk); 1407 if (ret < 0) { 1408 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1409 goto err_put_pm_runtime; 1410 } 1411 1412 /* Enable both the hclk and aclk to setup the vop */ 1413 ret = clk_prepare_enable(vop->hclk); 1414 if (ret < 0) { 1415 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1416 goto err_unprepare_dclk; 1417 } 1418 1419 ret = clk_prepare_enable(vop->aclk); 1420 if (ret < 0) { 1421 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1422 goto err_disable_hclk; 1423 } 1424 1425 /* 1426 * do hclk_reset, reset all vop registers. 1427 */ 1428 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1429 if (IS_ERR(ahb_rst)) { 1430 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1431 ret = PTR_ERR(ahb_rst); 1432 goto err_disable_aclk; 1433 } 1434 reset_control_assert(ahb_rst); 1435 usleep_range(10, 20); 1436 reset_control_deassert(ahb_rst); 1437 1438 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1439 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1440 1441 for (i = 0; i < vop->len; i += sizeof(u32)) 1442 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1443 1444 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1445 VOP_REG_SET(vop, common, dsp_blank, 0); 1446 1447 for (i = 0; i < vop_data->win_size; i++) { 1448 const struct vop_win_data *win = &vop_data->win[i]; 1449 int channel = i * 2 + 1; 1450 1451 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1452 VOP_WIN_SET(vop, win, enable, 0); 1453 VOP_WIN_SET(vop, win, gate, 1); 1454 } 1455 1456 vop_cfg_done(vop); 1457 1458 /* 1459 * do dclk_reset, let all config take affect. 1460 */ 1461 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1462 if (IS_ERR(vop->dclk_rst)) { 1463 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1464 ret = PTR_ERR(vop->dclk_rst); 1465 goto err_disable_aclk; 1466 } 1467 reset_control_assert(vop->dclk_rst); 1468 usleep_range(10, 20); 1469 reset_control_deassert(vop->dclk_rst); 1470 1471 clk_disable(vop->hclk); 1472 clk_disable(vop->aclk); 1473 1474 vop->is_enabled = false; 1475 1476 pm_runtime_put_sync(vop->dev); 1477 1478 return 0; 1479 1480 err_disable_aclk: 1481 clk_disable_unprepare(vop->aclk); 1482 err_disable_hclk: 1483 clk_disable_unprepare(vop->hclk); 1484 err_unprepare_dclk: 1485 clk_unprepare(vop->dclk); 1486 err_put_pm_runtime: 1487 pm_runtime_put_sync(vop->dev); 1488 return ret; 1489 } 1490 1491 /* 1492 * Initialize the vop->win array elements. 1493 */ 1494 static void vop_win_init(struct vop *vop) 1495 { 1496 const struct vop_data *vop_data = vop->data; 1497 unsigned int i; 1498 1499 for (i = 0; i < vop_data->win_size; i++) { 1500 struct vop_win *vop_win = &vop->win[i]; 1501 const struct vop_win_data *win_data = &vop_data->win[i]; 1502 1503 vop_win->data = win_data; 1504 vop_win->vop = vop; 1505 } 1506 } 1507 1508 /** 1509 * rockchip_drm_wait_vact_end 1510 * @crtc: CRTC to enable line flag 1511 * @mstimeout: millisecond for timeout 1512 * 1513 * Wait for vact_end line flag irq or timeout. 1514 * 1515 * Returns: 1516 * Zero on success, negative errno on failure. 1517 */ 1518 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1519 { 1520 struct vop *vop = to_vop(crtc); 1521 unsigned long jiffies_left; 1522 int ret = 0; 1523 1524 if (!crtc || !vop->is_enabled) 1525 return -ENODEV; 1526 1527 mutex_lock(&vop->vop_lock); 1528 if (mstimeout <= 0) { 1529 ret = -EINVAL; 1530 goto out; 1531 } 1532 1533 if (vop_line_flag_irq_is_enabled(vop)) { 1534 ret = -EBUSY; 1535 goto out; 1536 } 1537 1538 reinit_completion(&vop->line_flag_completion); 1539 vop_line_flag_irq_enable(vop); 1540 1541 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1542 msecs_to_jiffies(mstimeout)); 1543 vop_line_flag_irq_disable(vop); 1544 1545 if (jiffies_left == 0) { 1546 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1547 ret = -ETIMEDOUT; 1548 goto out; 1549 } 1550 1551 out: 1552 mutex_unlock(&vop->vop_lock); 1553 return ret; 1554 } 1555 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1556 1557 static int vop_bind(struct device *dev, struct device *master, void *data) 1558 { 1559 struct platform_device *pdev = to_platform_device(dev); 1560 const struct vop_data *vop_data; 1561 struct drm_device *drm_dev = data; 1562 struct vop *vop; 1563 struct resource *res; 1564 size_t alloc_size; 1565 int ret, irq; 1566 1567 vop_data = of_device_get_match_data(dev); 1568 if (!vop_data) 1569 return -ENODEV; 1570 1571 /* Allocate vop struct and its vop_win array */ 1572 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1573 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1574 if (!vop) 1575 return -ENOMEM; 1576 1577 vop->dev = dev; 1578 vop->data = vop_data; 1579 vop->drm_dev = drm_dev; 1580 dev_set_drvdata(dev, vop); 1581 1582 vop_win_init(vop); 1583 1584 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1585 vop->len = resource_size(res); 1586 vop->regs = devm_ioremap_resource(dev, res); 1587 if (IS_ERR(vop->regs)) 1588 return PTR_ERR(vop->regs); 1589 1590 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1591 if (!vop->regsbak) 1592 return -ENOMEM; 1593 1594 irq = platform_get_irq(pdev, 0); 1595 if (irq < 0) { 1596 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1597 return irq; 1598 } 1599 vop->irq = (unsigned int)irq; 1600 1601 spin_lock_init(&vop->reg_lock); 1602 spin_lock_init(&vop->irq_lock); 1603 mutex_init(&vop->vop_lock); 1604 1605 ret = vop_create_crtc(vop); 1606 if (ret) 1607 return ret; 1608 1609 pm_runtime_enable(&pdev->dev); 1610 1611 ret = vop_initial(vop); 1612 if (ret < 0) { 1613 DRM_DEV_ERROR(&pdev->dev, 1614 "cannot initial vop dev - err %d\n", ret); 1615 goto err_disable_pm_runtime; 1616 } 1617 1618 ret = devm_request_irq(dev, vop->irq, vop_isr, 1619 IRQF_SHARED, dev_name(dev), vop); 1620 if (ret) 1621 goto err_disable_pm_runtime; 1622 1623 return 0; 1624 1625 err_disable_pm_runtime: 1626 pm_runtime_disable(&pdev->dev); 1627 vop_destroy_crtc(vop); 1628 return ret; 1629 } 1630 1631 static void vop_unbind(struct device *dev, struct device *master, void *data) 1632 { 1633 struct vop *vop = dev_get_drvdata(dev); 1634 1635 pm_runtime_disable(dev); 1636 vop_destroy_crtc(vop); 1637 1638 clk_unprepare(vop->aclk); 1639 clk_unprepare(vop->hclk); 1640 clk_unprepare(vop->dclk); 1641 } 1642 1643 const struct component_ops vop_component_ops = { 1644 .bind = vop_bind, 1645 .unbind = vop_unbind, 1646 }; 1647 EXPORT_SYMBOL_GPL(vop_component_ops); 1648