1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #ifdef CONFIG_DRM_ANALOGIX_DP 24 #include <drm/bridge/analogix_dp.h> 25 #endif 26 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/platform_device.h> 30 #include <linux/clk.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/component.h> 36 #include <linux/overflow.h> 37 38 #include <linux/reset.h> 39 #include <linux/delay.h> 40 41 #include "rockchip_drm_drv.h" 42 #include "rockchip_drm_gem.h" 43 #include "rockchip_drm_fb.h" 44 #include "rockchip_drm_psr.h" 45 #include "rockchip_drm_vop.h" 46 #include "rockchip_rgb.h" 47 48 #define VOP_WIN_SET(x, win, name, v) \ 49 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 50 #define VOP_SCL_SET(x, win, name, v) \ 51 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 52 #define VOP_SCL_SET_EXT(x, win, name, v) \ 53 vop_reg_set(vop, &win->phy->scl->ext->name, \ 54 win->base, ~0, v, #name) 55 56 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 57 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 58 59 #define VOP_REG_SET(vop, group, name, v) \ 60 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 61 62 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 63 do { \ 64 int i, reg = 0, mask = 0; \ 65 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 66 if (vop->data->intr->intrs[i] & type) { \ 67 reg |= (v) << i; \ 68 mask |= 1 << i; \ 69 } \ 70 } \ 71 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 72 } while (0) 73 #define VOP_INTR_GET_TYPE(vop, name, type) \ 74 vop_get_intr_type(vop, &vop->data->intr->name, type) 75 76 #define VOP_WIN_GET(x, win, name) \ 77 vop_read_reg(x, win->offset, win->phy->name) 78 79 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 80 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 81 82 #define VOP_WIN_TO_INDEX(vop_win) \ 83 ((vop_win) - (vop_win)->vop->win) 84 85 #define to_vop(x) container_of(x, struct vop, crtc) 86 #define to_vop_win(x) container_of(x, struct vop_win, base) 87 88 enum vop_pending { 89 VOP_PENDING_FB_UNREF, 90 }; 91 92 struct vop_win { 93 struct drm_plane base; 94 const struct vop_win_data *data; 95 struct vop *vop; 96 }; 97 98 struct rockchip_rgb; 99 struct vop { 100 struct drm_crtc crtc; 101 struct device *dev; 102 struct drm_device *drm_dev; 103 bool is_enabled; 104 105 struct completion dsp_hold_completion; 106 107 /* protected by dev->event_lock */ 108 struct drm_pending_vblank_event *event; 109 110 struct drm_flip_work fb_unref_work; 111 unsigned long pending; 112 113 struct completion line_flag_completion; 114 115 const struct vop_data *data; 116 117 uint32_t *regsbak; 118 void __iomem *regs; 119 120 /* physical map length of vop register */ 121 uint32_t len; 122 123 /* one time only one process allowed to config the register */ 124 spinlock_t reg_lock; 125 /* lock vop irq reg */ 126 spinlock_t irq_lock; 127 /* protects crtc enable/disable */ 128 struct mutex vop_lock; 129 130 unsigned int irq; 131 132 /* vop AHP clk */ 133 struct clk *hclk; 134 /* vop dclk */ 135 struct clk *dclk; 136 /* vop share memory frequency */ 137 struct clk *aclk; 138 139 /* vop dclk reset */ 140 struct reset_control *dclk_rst; 141 142 /* optional internal rgb encoder */ 143 struct rockchip_rgb *rgb; 144 145 struct vop_win win[]; 146 }; 147 148 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 149 { 150 writel(v, vop->regs + offset); 151 vop->regsbak[offset >> 2] = v; 152 } 153 154 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 155 { 156 return readl(vop->regs + offset); 157 } 158 159 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 160 const struct vop_reg *reg) 161 { 162 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 163 } 164 165 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 166 uint32_t _offset, uint32_t _mask, uint32_t v, 167 const char *reg_name) 168 { 169 int offset, mask, shift; 170 171 if (!reg || !reg->mask) { 172 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 173 return; 174 } 175 176 offset = reg->offset + _offset; 177 mask = reg->mask & _mask; 178 shift = reg->shift; 179 180 if (reg->write_mask) { 181 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 182 } else { 183 uint32_t cached_val = vop->regsbak[offset >> 2]; 184 185 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 186 vop->regsbak[offset >> 2] = v; 187 } 188 189 if (reg->relaxed) 190 writel_relaxed(v, vop->regs + offset); 191 else 192 writel(v, vop->regs + offset); 193 } 194 195 static inline uint32_t vop_get_intr_type(struct vop *vop, 196 const struct vop_reg *reg, int type) 197 { 198 uint32_t i, ret = 0; 199 uint32_t regs = vop_read_reg(vop, 0, reg); 200 201 for (i = 0; i < vop->data->intr->nintrs; i++) { 202 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 203 ret |= vop->data->intr->intrs[i]; 204 } 205 206 return ret; 207 } 208 209 static inline void vop_cfg_done(struct vop *vop) 210 { 211 VOP_REG_SET(vop, common, cfg_done, 1); 212 } 213 214 static bool has_rb_swapped(uint32_t format) 215 { 216 switch (format) { 217 case DRM_FORMAT_XBGR8888: 218 case DRM_FORMAT_ABGR8888: 219 case DRM_FORMAT_BGR888: 220 case DRM_FORMAT_BGR565: 221 return true; 222 default: 223 return false; 224 } 225 } 226 227 static enum vop_data_format vop_convert_format(uint32_t format) 228 { 229 switch (format) { 230 case DRM_FORMAT_XRGB8888: 231 case DRM_FORMAT_ARGB8888: 232 case DRM_FORMAT_XBGR8888: 233 case DRM_FORMAT_ABGR8888: 234 return VOP_FMT_ARGB8888; 235 case DRM_FORMAT_RGB888: 236 case DRM_FORMAT_BGR888: 237 return VOP_FMT_RGB888; 238 case DRM_FORMAT_RGB565: 239 case DRM_FORMAT_BGR565: 240 return VOP_FMT_RGB565; 241 case DRM_FORMAT_NV12: 242 return VOP_FMT_YUV420SP; 243 case DRM_FORMAT_NV16: 244 return VOP_FMT_YUV422SP; 245 case DRM_FORMAT_NV24: 246 return VOP_FMT_YUV444SP; 247 default: 248 DRM_ERROR("unsupported format[%08x]\n", format); 249 return -EINVAL; 250 } 251 } 252 253 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 254 uint32_t dst, bool is_horizontal, 255 int vsu_mode, int *vskiplines) 256 { 257 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 258 259 if (vskiplines) 260 *vskiplines = 0; 261 262 if (is_horizontal) { 263 if (mode == SCALE_UP) 264 val = GET_SCL_FT_BIC(src, dst); 265 else if (mode == SCALE_DOWN) 266 val = GET_SCL_FT_BILI_DN(src, dst); 267 } else { 268 if (mode == SCALE_UP) { 269 if (vsu_mode == SCALE_UP_BIL) 270 val = GET_SCL_FT_BILI_UP(src, dst); 271 else 272 val = GET_SCL_FT_BIC(src, dst); 273 } else if (mode == SCALE_DOWN) { 274 if (vskiplines) { 275 *vskiplines = scl_get_vskiplines(src, dst); 276 val = scl_get_bili_dn_vskip(src, dst, 277 *vskiplines); 278 } else { 279 val = GET_SCL_FT_BILI_DN(src, dst); 280 } 281 } 282 } 283 284 return val; 285 } 286 287 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 288 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 289 uint32_t dst_h, uint32_t pixel_format) 290 { 291 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 292 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 293 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 294 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 295 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 296 const struct drm_format_info *info; 297 bool is_yuv = false; 298 uint16_t cbcr_src_w = src_w / hsub; 299 uint16_t cbcr_src_h = src_h / vsub; 300 uint16_t vsu_mode; 301 uint16_t lb_mode; 302 uint32_t val; 303 int vskiplines; 304 305 info = drm_format_info(pixel_format); 306 307 if (info->is_yuv) 308 is_yuv = true; 309 310 if (dst_w > 3840) { 311 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 312 return; 313 } 314 315 if (!win->phy->scl->ext) { 316 VOP_SCL_SET(vop, win, scale_yrgb_x, 317 scl_cal_scale2(src_w, dst_w)); 318 VOP_SCL_SET(vop, win, scale_yrgb_y, 319 scl_cal_scale2(src_h, dst_h)); 320 if (is_yuv) { 321 VOP_SCL_SET(vop, win, scale_cbcr_x, 322 scl_cal_scale2(cbcr_src_w, dst_w)); 323 VOP_SCL_SET(vop, win, scale_cbcr_y, 324 scl_cal_scale2(cbcr_src_h, dst_h)); 325 } 326 return; 327 } 328 329 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 330 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 331 332 if (is_yuv) { 333 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 334 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 335 if (cbcr_hor_scl_mode == SCALE_DOWN) 336 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 337 else 338 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 339 } else { 340 if (yrgb_hor_scl_mode == SCALE_DOWN) 341 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 342 else 343 lb_mode = scl_vop_cal_lb_mode(src_w, false); 344 } 345 346 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 347 if (lb_mode == LB_RGB_3840X2) { 348 if (yrgb_ver_scl_mode != SCALE_NONE) { 349 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 350 return; 351 } 352 if (cbcr_ver_scl_mode != SCALE_NONE) { 353 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 354 return; 355 } 356 vsu_mode = SCALE_UP_BIL; 357 } else if (lb_mode == LB_RGB_2560X4) { 358 vsu_mode = SCALE_UP_BIL; 359 } else { 360 vsu_mode = SCALE_UP_BIC; 361 } 362 363 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 364 true, 0, NULL); 365 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 366 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 367 false, vsu_mode, &vskiplines); 368 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 369 370 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 371 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 372 373 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 374 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 375 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 376 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 377 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 378 if (is_yuv) { 379 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 380 dst_w, true, 0, NULL); 381 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 382 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 383 dst_h, false, vsu_mode, &vskiplines); 384 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 385 386 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 387 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 388 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 389 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 390 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 391 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 392 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 393 } 394 } 395 396 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 397 { 398 unsigned long flags; 399 400 if (WARN_ON(!vop->is_enabled)) 401 return; 402 403 spin_lock_irqsave(&vop->irq_lock, flags); 404 405 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 406 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 407 408 spin_unlock_irqrestore(&vop->irq_lock, flags); 409 } 410 411 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 412 { 413 unsigned long flags; 414 415 if (WARN_ON(!vop->is_enabled)) 416 return; 417 418 spin_lock_irqsave(&vop->irq_lock, flags); 419 420 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 421 422 spin_unlock_irqrestore(&vop->irq_lock, flags); 423 } 424 425 /* 426 * (1) each frame starts at the start of the Vsync pulse which is signaled by 427 * the "FRAME_SYNC" interrupt. 428 * (2) the active data region of each frame ends at dsp_vact_end 429 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 430 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 431 * 432 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 433 * Interrupts 434 * LINE_FLAG -------------------------------+ 435 * FRAME_SYNC ----+ | 436 * | | 437 * v v 438 * | Vsync | Vbp | Vactive | Vfp | 439 * ^ ^ ^ ^ 440 * | | | | 441 * | | | | 442 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 443 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 444 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 445 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 446 */ 447 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 448 { 449 uint32_t line_flag_irq; 450 unsigned long flags; 451 452 spin_lock_irqsave(&vop->irq_lock, flags); 453 454 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 455 456 spin_unlock_irqrestore(&vop->irq_lock, flags); 457 458 return !!line_flag_irq; 459 } 460 461 static void vop_line_flag_irq_enable(struct vop *vop) 462 { 463 unsigned long flags; 464 465 if (WARN_ON(!vop->is_enabled)) 466 return; 467 468 spin_lock_irqsave(&vop->irq_lock, flags); 469 470 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 471 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 472 473 spin_unlock_irqrestore(&vop->irq_lock, flags); 474 } 475 476 static void vop_line_flag_irq_disable(struct vop *vop) 477 { 478 unsigned long flags; 479 480 if (WARN_ON(!vop->is_enabled)) 481 return; 482 483 spin_lock_irqsave(&vop->irq_lock, flags); 484 485 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 486 487 spin_unlock_irqrestore(&vop->irq_lock, flags); 488 } 489 490 static int vop_core_clks_enable(struct vop *vop) 491 { 492 int ret; 493 494 ret = clk_enable(vop->hclk); 495 if (ret < 0) 496 return ret; 497 498 ret = clk_enable(vop->aclk); 499 if (ret < 0) 500 goto err_disable_hclk; 501 502 return 0; 503 504 err_disable_hclk: 505 clk_disable(vop->hclk); 506 return ret; 507 } 508 509 static void vop_core_clks_disable(struct vop *vop) 510 { 511 clk_disable(vop->aclk); 512 clk_disable(vop->hclk); 513 } 514 515 static int vop_enable(struct drm_crtc *crtc) 516 { 517 struct vop *vop = to_vop(crtc); 518 int ret, i; 519 520 ret = pm_runtime_get_sync(vop->dev); 521 if (ret < 0) { 522 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 523 return ret; 524 } 525 526 ret = vop_core_clks_enable(vop); 527 if (WARN_ON(ret < 0)) 528 goto err_put_pm_runtime; 529 530 ret = clk_enable(vop->dclk); 531 if (WARN_ON(ret < 0)) 532 goto err_disable_core; 533 534 /* 535 * Slave iommu shares power, irq and clock with vop. It was associated 536 * automatically with this master device via common driver code. 537 * Now that we have enabled the clock we attach it to the shared drm 538 * mapping. 539 */ 540 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 541 if (ret) { 542 DRM_DEV_ERROR(vop->dev, 543 "failed to attach dma mapping, %d\n", ret); 544 goto err_disable_dclk; 545 } 546 547 spin_lock(&vop->reg_lock); 548 for (i = 0; i < vop->len; i += 4) 549 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 550 551 /* 552 * We need to make sure that all windows are disabled before we 553 * enable the crtc. Otherwise we might try to scan from a destroyed 554 * buffer later. 555 */ 556 for (i = 0; i < vop->data->win_size; i++) { 557 struct vop_win *vop_win = &vop->win[i]; 558 const struct vop_win_data *win = vop_win->data; 559 560 VOP_WIN_SET(vop, win, enable, 0); 561 } 562 spin_unlock(&vop->reg_lock); 563 564 vop_cfg_done(vop); 565 566 /* 567 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 568 */ 569 vop->is_enabled = true; 570 571 spin_lock(&vop->reg_lock); 572 573 VOP_REG_SET(vop, common, standby, 1); 574 575 spin_unlock(&vop->reg_lock); 576 577 drm_crtc_vblank_on(crtc); 578 579 return 0; 580 581 err_disable_dclk: 582 clk_disable(vop->dclk); 583 err_disable_core: 584 vop_core_clks_disable(vop); 585 err_put_pm_runtime: 586 pm_runtime_put_sync(vop->dev); 587 return ret; 588 } 589 590 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 591 struct drm_crtc_state *old_state) 592 { 593 struct vop *vop = to_vop(crtc); 594 595 WARN_ON(vop->event); 596 597 mutex_lock(&vop->vop_lock); 598 drm_crtc_vblank_off(crtc); 599 600 /* 601 * Vop standby will take effect at end of current frame, 602 * if dsp hold valid irq happen, it means standby complete. 603 * 604 * we must wait standby complete when we want to disable aclk, 605 * if not, memory bus maybe dead. 606 */ 607 reinit_completion(&vop->dsp_hold_completion); 608 vop_dsp_hold_valid_irq_enable(vop); 609 610 spin_lock(&vop->reg_lock); 611 612 VOP_REG_SET(vop, common, standby, 1); 613 614 spin_unlock(&vop->reg_lock); 615 616 wait_for_completion(&vop->dsp_hold_completion); 617 618 vop_dsp_hold_valid_irq_disable(vop); 619 620 vop->is_enabled = false; 621 622 /* 623 * vop standby complete, so iommu detach is safe. 624 */ 625 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 626 627 clk_disable(vop->dclk); 628 vop_core_clks_disable(vop); 629 pm_runtime_put(vop->dev); 630 mutex_unlock(&vop->vop_lock); 631 632 if (crtc->state->event && !crtc->state->active) { 633 spin_lock_irq(&crtc->dev->event_lock); 634 drm_crtc_send_vblank_event(crtc, crtc->state->event); 635 spin_unlock_irq(&crtc->dev->event_lock); 636 637 crtc->state->event = NULL; 638 } 639 } 640 641 static void vop_plane_destroy(struct drm_plane *plane) 642 { 643 drm_plane_cleanup(plane); 644 } 645 646 static int vop_plane_atomic_check(struct drm_plane *plane, 647 struct drm_plane_state *state) 648 { 649 struct drm_crtc *crtc = state->crtc; 650 struct drm_crtc_state *crtc_state; 651 struct drm_framebuffer *fb = state->fb; 652 struct vop_win *vop_win = to_vop_win(plane); 653 const struct vop_win_data *win = vop_win->data; 654 int ret; 655 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 656 DRM_PLANE_HELPER_NO_SCALING; 657 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 658 DRM_PLANE_HELPER_NO_SCALING; 659 660 if (!crtc || !fb) 661 return 0; 662 663 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 664 if (WARN_ON(!crtc_state)) 665 return -EINVAL; 666 667 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 668 min_scale, max_scale, 669 true, true); 670 if (ret) 671 return ret; 672 673 if (!state->visible) 674 return 0; 675 676 ret = vop_convert_format(fb->format->format); 677 if (ret < 0) 678 return ret; 679 680 /* 681 * Src.x1 can be odd when do clip, but yuv plane start point 682 * need align with 2 pixel. 683 */ 684 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 685 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 686 return -EINVAL; 687 } 688 689 return 0; 690 } 691 692 static void vop_plane_atomic_disable(struct drm_plane *plane, 693 struct drm_plane_state *old_state) 694 { 695 struct vop_win *vop_win = to_vop_win(plane); 696 const struct vop_win_data *win = vop_win->data; 697 struct vop *vop = to_vop(old_state->crtc); 698 699 if (!old_state->crtc) 700 return; 701 702 spin_lock(&vop->reg_lock); 703 704 VOP_WIN_SET(vop, win, enable, 0); 705 706 spin_unlock(&vop->reg_lock); 707 } 708 709 static void vop_plane_atomic_update(struct drm_plane *plane, 710 struct drm_plane_state *old_state) 711 { 712 struct drm_plane_state *state = plane->state; 713 struct drm_crtc *crtc = state->crtc; 714 struct vop_win *vop_win = to_vop_win(plane); 715 const struct vop_win_data *win = vop_win->data; 716 struct vop *vop = to_vop(state->crtc); 717 struct drm_framebuffer *fb = state->fb; 718 unsigned int actual_w, actual_h; 719 unsigned int dsp_stx, dsp_sty; 720 uint32_t act_info, dsp_info, dsp_st; 721 struct drm_rect *src = &state->src; 722 struct drm_rect *dest = &state->dst; 723 struct drm_gem_object *obj, *uv_obj; 724 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 725 unsigned long offset; 726 dma_addr_t dma_addr; 727 uint32_t val; 728 bool rb_swap; 729 int win_index = VOP_WIN_TO_INDEX(vop_win); 730 int format; 731 732 /* 733 * can't update plane when vop is disabled. 734 */ 735 if (WARN_ON(!crtc)) 736 return; 737 738 if (WARN_ON(!vop->is_enabled)) 739 return; 740 741 if (!state->visible) { 742 vop_plane_atomic_disable(plane, old_state); 743 return; 744 } 745 746 obj = fb->obj[0]; 747 rk_obj = to_rockchip_obj(obj); 748 749 actual_w = drm_rect_width(src) >> 16; 750 actual_h = drm_rect_height(src) >> 16; 751 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 752 753 dsp_info = (drm_rect_height(dest) - 1) << 16; 754 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 755 756 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 757 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 758 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 759 760 offset = (src->x1 >> 16) * fb->format->cpp[0]; 761 offset += (src->y1 >> 16) * fb->pitches[0]; 762 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 763 764 format = vop_convert_format(fb->format->format); 765 766 spin_lock(&vop->reg_lock); 767 768 VOP_WIN_SET(vop, win, format, format); 769 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 770 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 771 if (fb->format->is_yuv) { 772 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 773 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 774 int bpp = fb->format->cpp[1]; 775 776 uv_obj = fb->obj[1]; 777 rk_uv_obj = to_rockchip_obj(uv_obj); 778 779 offset = (src->x1 >> 16) * bpp / hsub; 780 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 781 782 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 783 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 784 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 785 } 786 787 if (win->phy->scl) 788 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 789 drm_rect_width(dest), drm_rect_height(dest), 790 fb->format->format); 791 792 VOP_WIN_SET(vop, win, act_info, act_info); 793 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 794 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 795 796 rb_swap = has_rb_swapped(fb->format->format); 797 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 798 799 /* 800 * Blending win0 with the background color doesn't seem to work 801 * correctly. We only get the background color, no matter the contents 802 * of the win0 framebuffer. However, blending pre-multiplied color 803 * with the default opaque black default background color is a no-op, 804 * so we can just disable blending to get the correct result. 805 */ 806 if (fb->format->has_alpha && win_index > 0) { 807 VOP_WIN_SET(vop, win, dst_alpha_ctl, 808 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 809 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 810 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 811 SRC_BLEND_M0(ALPHA_PER_PIX) | 812 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 813 SRC_FACTOR_M0(ALPHA_ONE); 814 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 815 } else { 816 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 817 } 818 819 VOP_WIN_SET(vop, win, enable, 1); 820 spin_unlock(&vop->reg_lock); 821 } 822 823 static const struct drm_plane_helper_funcs plane_helper_funcs = { 824 .atomic_check = vop_plane_atomic_check, 825 .atomic_update = vop_plane_atomic_update, 826 .atomic_disable = vop_plane_atomic_disable, 827 .prepare_fb = drm_gem_fb_prepare_fb, 828 }; 829 830 static const struct drm_plane_funcs vop_plane_funcs = { 831 .update_plane = drm_atomic_helper_update_plane, 832 .disable_plane = drm_atomic_helper_disable_plane, 833 .destroy = vop_plane_destroy, 834 .reset = drm_atomic_helper_plane_reset, 835 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 836 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 837 }; 838 839 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 840 { 841 struct vop *vop = to_vop(crtc); 842 unsigned long flags; 843 844 if (WARN_ON(!vop->is_enabled)) 845 return -EPERM; 846 847 spin_lock_irqsave(&vop->irq_lock, flags); 848 849 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 850 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 851 852 spin_unlock_irqrestore(&vop->irq_lock, flags); 853 854 return 0; 855 } 856 857 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 858 { 859 struct vop *vop = to_vop(crtc); 860 unsigned long flags; 861 862 if (WARN_ON(!vop->is_enabled)) 863 return; 864 865 spin_lock_irqsave(&vop->irq_lock, flags); 866 867 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 868 869 spin_unlock_irqrestore(&vop->irq_lock, flags); 870 } 871 872 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 873 const struct drm_display_mode *mode, 874 struct drm_display_mode *adjusted_mode) 875 { 876 struct vop *vop = to_vop(crtc); 877 878 adjusted_mode->clock = 879 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 880 881 return true; 882 } 883 884 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 885 struct drm_crtc_state *old_state) 886 { 887 struct vop *vop = to_vop(crtc); 888 const struct vop_data *vop_data = vop->data; 889 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 890 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 891 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 892 u16 hdisplay = adjusted_mode->hdisplay; 893 u16 htotal = adjusted_mode->htotal; 894 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 895 u16 hact_end = hact_st + hdisplay; 896 u16 vdisplay = adjusted_mode->vdisplay; 897 u16 vtotal = adjusted_mode->vtotal; 898 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 899 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 900 u16 vact_end = vact_st + vdisplay; 901 uint32_t pin_pol, val; 902 int ret; 903 904 mutex_lock(&vop->vop_lock); 905 906 WARN_ON(vop->event); 907 908 ret = vop_enable(crtc); 909 if (ret) { 910 mutex_unlock(&vop->vop_lock); 911 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 912 return; 913 } 914 915 pin_pol = BIT(DCLK_INVERT); 916 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 917 BIT(HSYNC_POSITIVE) : 0; 918 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 919 BIT(VSYNC_POSITIVE) : 0; 920 VOP_REG_SET(vop, output, pin_pol, pin_pol); 921 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 922 923 switch (s->output_type) { 924 case DRM_MODE_CONNECTOR_LVDS: 925 VOP_REG_SET(vop, output, rgb_en, 1); 926 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 927 break; 928 case DRM_MODE_CONNECTOR_eDP: 929 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 930 VOP_REG_SET(vop, output, edp_en, 1); 931 break; 932 case DRM_MODE_CONNECTOR_HDMIA: 933 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 934 VOP_REG_SET(vop, output, hdmi_en, 1); 935 break; 936 case DRM_MODE_CONNECTOR_DSI: 937 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 938 VOP_REG_SET(vop, output, mipi_en, 1); 939 VOP_REG_SET(vop, output, mipi_dual_channel_en, 940 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 941 break; 942 case DRM_MODE_CONNECTOR_DisplayPort: 943 pin_pol &= ~BIT(DCLK_INVERT); 944 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 945 VOP_REG_SET(vop, output, dp_en, 1); 946 break; 947 default: 948 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 949 s->output_type); 950 } 951 952 /* 953 * if vop is not support RGB10 output, need force RGB10 to RGB888. 954 */ 955 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 956 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 957 s->output_mode = ROCKCHIP_OUT_MODE_P888; 958 959 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8) 960 VOP_REG_SET(vop, common, pre_dither_down, 1); 961 else 962 VOP_REG_SET(vop, common, pre_dither_down, 0); 963 964 VOP_REG_SET(vop, common, out_mode, s->output_mode); 965 966 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 967 val = hact_st << 16; 968 val |= hact_end; 969 VOP_REG_SET(vop, modeset, hact_st_end, val); 970 VOP_REG_SET(vop, modeset, hpost_st_end, val); 971 972 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 973 val = vact_st << 16; 974 val |= vact_end; 975 VOP_REG_SET(vop, modeset, vact_st_end, val); 976 VOP_REG_SET(vop, modeset, vpost_st_end, val); 977 978 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 979 980 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 981 982 VOP_REG_SET(vop, common, standby, 0); 983 mutex_unlock(&vop->vop_lock); 984 } 985 986 static bool vop_fs_irq_is_pending(struct vop *vop) 987 { 988 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 989 } 990 991 static void vop_wait_for_irq_handler(struct vop *vop) 992 { 993 bool pending; 994 int ret; 995 996 /* 997 * Spin until frame start interrupt status bit goes low, which means 998 * that interrupt handler was invoked and cleared it. The timeout of 999 * 10 msecs is really too long, but it is just a safety measure if 1000 * something goes really wrong. The wait will only happen in the very 1001 * unlikely case of a vblank happening exactly at the same time and 1002 * shouldn't exceed microseconds range. 1003 */ 1004 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1005 !pending, 0, 10 * 1000); 1006 if (ret) 1007 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1008 1009 synchronize_irq(vop->irq); 1010 } 1011 1012 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1013 struct drm_crtc_state *old_crtc_state) 1014 { 1015 struct drm_atomic_state *old_state = old_crtc_state->state; 1016 struct drm_plane_state *old_plane_state, *new_plane_state; 1017 struct vop *vop = to_vop(crtc); 1018 struct drm_plane *plane; 1019 int i; 1020 1021 if (WARN_ON(!vop->is_enabled)) 1022 return; 1023 1024 spin_lock(&vop->reg_lock); 1025 1026 vop_cfg_done(vop); 1027 1028 spin_unlock(&vop->reg_lock); 1029 1030 /* 1031 * There is a (rather unlikely) possiblity that a vblank interrupt 1032 * fired before we set the cfg_done bit. To avoid spuriously 1033 * signalling flip completion we need to wait for it to finish. 1034 */ 1035 vop_wait_for_irq_handler(vop); 1036 1037 spin_lock_irq(&crtc->dev->event_lock); 1038 if (crtc->state->event) { 1039 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1040 WARN_ON(vop->event); 1041 1042 vop->event = crtc->state->event; 1043 crtc->state->event = NULL; 1044 } 1045 spin_unlock_irq(&crtc->dev->event_lock); 1046 1047 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1048 new_plane_state, i) { 1049 if (!old_plane_state->fb) 1050 continue; 1051 1052 if (old_plane_state->fb == new_plane_state->fb) 1053 continue; 1054 1055 drm_framebuffer_get(old_plane_state->fb); 1056 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1057 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1058 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1059 } 1060 } 1061 1062 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1063 .mode_fixup = vop_crtc_mode_fixup, 1064 .atomic_flush = vop_crtc_atomic_flush, 1065 .atomic_enable = vop_crtc_atomic_enable, 1066 .atomic_disable = vop_crtc_atomic_disable, 1067 }; 1068 1069 static void vop_crtc_destroy(struct drm_crtc *crtc) 1070 { 1071 drm_crtc_cleanup(crtc); 1072 } 1073 1074 static void vop_crtc_reset(struct drm_crtc *crtc) 1075 { 1076 if (crtc->state) 1077 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1078 kfree(crtc->state); 1079 1080 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1081 if (crtc->state) 1082 crtc->state->crtc = crtc; 1083 } 1084 1085 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1086 { 1087 struct rockchip_crtc_state *rockchip_state; 1088 1089 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1090 if (!rockchip_state) 1091 return NULL; 1092 1093 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1094 return &rockchip_state->base; 1095 } 1096 1097 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1098 struct drm_crtc_state *state) 1099 { 1100 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1101 1102 __drm_atomic_helper_crtc_destroy_state(&s->base); 1103 kfree(s); 1104 } 1105 1106 #ifdef CONFIG_DRM_ANALOGIX_DP 1107 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1108 { 1109 struct drm_connector *connector; 1110 struct drm_connector_list_iter conn_iter; 1111 1112 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1113 drm_for_each_connector_iter(connector, &conn_iter) { 1114 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1115 drm_connector_list_iter_end(&conn_iter); 1116 return connector; 1117 } 1118 } 1119 drm_connector_list_iter_end(&conn_iter); 1120 1121 return NULL; 1122 } 1123 1124 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1125 const char *source_name) 1126 { 1127 struct vop *vop = to_vop(crtc); 1128 struct drm_connector *connector; 1129 int ret; 1130 1131 connector = vop_get_edp_connector(vop); 1132 if (!connector) 1133 return -EINVAL; 1134 1135 if (source_name && strcmp(source_name, "auto") == 0) 1136 ret = analogix_dp_start_crc(connector); 1137 else if (!source_name) 1138 ret = analogix_dp_stop_crc(connector); 1139 else 1140 ret = -EINVAL; 1141 1142 return ret; 1143 } 1144 1145 static int 1146 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1147 size_t *values_cnt) 1148 { 1149 if (source_name && strcmp(source_name, "auto") != 0) 1150 return -EINVAL; 1151 1152 *values_cnt = 3; 1153 return 0; 1154 } 1155 1156 #else 1157 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1158 const char *source_name) 1159 { 1160 return -ENODEV; 1161 } 1162 1163 static int 1164 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1165 size_t *values_cnt) 1166 { 1167 return -ENODEV; 1168 } 1169 #endif 1170 1171 static const struct drm_crtc_funcs vop_crtc_funcs = { 1172 .set_config = drm_atomic_helper_set_config, 1173 .page_flip = drm_atomic_helper_page_flip, 1174 .destroy = vop_crtc_destroy, 1175 .reset = vop_crtc_reset, 1176 .atomic_duplicate_state = vop_crtc_duplicate_state, 1177 .atomic_destroy_state = vop_crtc_destroy_state, 1178 .enable_vblank = vop_crtc_enable_vblank, 1179 .disable_vblank = vop_crtc_disable_vblank, 1180 .set_crc_source = vop_crtc_set_crc_source, 1181 .verify_crc_source = vop_crtc_verify_crc_source, 1182 }; 1183 1184 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1185 { 1186 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1187 struct drm_framebuffer *fb = val; 1188 1189 drm_crtc_vblank_put(&vop->crtc); 1190 drm_framebuffer_put(fb); 1191 } 1192 1193 static void vop_handle_vblank(struct vop *vop) 1194 { 1195 struct drm_device *drm = vop->drm_dev; 1196 struct drm_crtc *crtc = &vop->crtc; 1197 1198 spin_lock(&drm->event_lock); 1199 if (vop->event) { 1200 drm_crtc_send_vblank_event(crtc, vop->event); 1201 drm_crtc_vblank_put(crtc); 1202 vop->event = NULL; 1203 } 1204 spin_unlock(&drm->event_lock); 1205 1206 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1207 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1208 } 1209 1210 static irqreturn_t vop_isr(int irq, void *data) 1211 { 1212 struct vop *vop = data; 1213 struct drm_crtc *crtc = &vop->crtc; 1214 uint32_t active_irqs; 1215 int ret = IRQ_NONE; 1216 1217 /* 1218 * The irq is shared with the iommu. If the runtime-pm state of the 1219 * vop-device is disabled the irq has to be targeted at the iommu. 1220 */ 1221 if (!pm_runtime_get_if_in_use(vop->dev)) 1222 return IRQ_NONE; 1223 1224 if (vop_core_clks_enable(vop)) { 1225 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1226 goto out; 1227 } 1228 1229 /* 1230 * interrupt register has interrupt status, enable and clear bits, we 1231 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1232 */ 1233 spin_lock(&vop->irq_lock); 1234 1235 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1236 /* Clear all active interrupt sources */ 1237 if (active_irqs) 1238 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1239 1240 spin_unlock(&vop->irq_lock); 1241 1242 /* This is expected for vop iommu irqs, since the irq is shared */ 1243 if (!active_irqs) 1244 goto out_disable; 1245 1246 if (active_irqs & DSP_HOLD_VALID_INTR) { 1247 complete(&vop->dsp_hold_completion); 1248 active_irqs &= ~DSP_HOLD_VALID_INTR; 1249 ret = IRQ_HANDLED; 1250 } 1251 1252 if (active_irqs & LINE_FLAG_INTR) { 1253 complete(&vop->line_flag_completion); 1254 active_irqs &= ~LINE_FLAG_INTR; 1255 ret = IRQ_HANDLED; 1256 } 1257 1258 if (active_irqs & FS_INTR) { 1259 drm_crtc_handle_vblank(crtc); 1260 vop_handle_vblank(vop); 1261 active_irqs &= ~FS_INTR; 1262 ret = IRQ_HANDLED; 1263 } 1264 1265 /* Unhandled irqs are spurious. */ 1266 if (active_irqs) 1267 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1268 active_irqs); 1269 1270 out_disable: 1271 vop_core_clks_disable(vop); 1272 out: 1273 pm_runtime_put(vop->dev); 1274 return ret; 1275 } 1276 1277 static int vop_create_crtc(struct vop *vop) 1278 { 1279 const struct vop_data *vop_data = vop->data; 1280 struct device *dev = vop->dev; 1281 struct drm_device *drm_dev = vop->drm_dev; 1282 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1283 struct drm_crtc *crtc = &vop->crtc; 1284 struct device_node *port; 1285 int ret; 1286 int i; 1287 1288 /* 1289 * Create drm_plane for primary and cursor planes first, since we need 1290 * to pass them to drm_crtc_init_with_planes, which sets the 1291 * "possible_crtcs" to the newly initialized crtc. 1292 */ 1293 for (i = 0; i < vop_data->win_size; i++) { 1294 struct vop_win *vop_win = &vop->win[i]; 1295 const struct vop_win_data *win_data = vop_win->data; 1296 1297 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1298 win_data->type != DRM_PLANE_TYPE_CURSOR) 1299 continue; 1300 1301 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1302 0, &vop_plane_funcs, 1303 win_data->phy->data_formats, 1304 win_data->phy->nformats, 1305 NULL, win_data->type, NULL); 1306 if (ret) { 1307 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1308 ret); 1309 goto err_cleanup_planes; 1310 } 1311 1312 plane = &vop_win->base; 1313 drm_plane_helper_add(plane, &plane_helper_funcs); 1314 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1315 primary = plane; 1316 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1317 cursor = plane; 1318 } 1319 1320 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1321 &vop_crtc_funcs, NULL); 1322 if (ret) 1323 goto err_cleanup_planes; 1324 1325 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1326 1327 /* 1328 * Create drm_planes for overlay windows with possible_crtcs restricted 1329 * to the newly created crtc. 1330 */ 1331 for (i = 0; i < vop_data->win_size; i++) { 1332 struct vop_win *vop_win = &vop->win[i]; 1333 const struct vop_win_data *win_data = vop_win->data; 1334 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1335 1336 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1337 continue; 1338 1339 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1340 possible_crtcs, 1341 &vop_plane_funcs, 1342 win_data->phy->data_formats, 1343 win_data->phy->nformats, 1344 NULL, win_data->type, NULL); 1345 if (ret) { 1346 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1347 ret); 1348 goto err_cleanup_crtc; 1349 } 1350 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1351 } 1352 1353 port = of_get_child_by_name(dev->of_node, "port"); 1354 if (!port) { 1355 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1356 dev->of_node); 1357 ret = -ENOENT; 1358 goto err_cleanup_crtc; 1359 } 1360 1361 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1362 vop_fb_unref_worker); 1363 1364 init_completion(&vop->dsp_hold_completion); 1365 init_completion(&vop->line_flag_completion); 1366 crtc->port = port; 1367 1368 return 0; 1369 1370 err_cleanup_crtc: 1371 drm_crtc_cleanup(crtc); 1372 err_cleanup_planes: 1373 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1374 head) 1375 drm_plane_cleanup(plane); 1376 return ret; 1377 } 1378 1379 static void vop_destroy_crtc(struct vop *vop) 1380 { 1381 struct drm_crtc *crtc = &vop->crtc; 1382 struct drm_device *drm_dev = vop->drm_dev; 1383 struct drm_plane *plane, *tmp; 1384 1385 of_node_put(crtc->port); 1386 1387 /* 1388 * We need to cleanup the planes now. Why? 1389 * 1390 * The planes are "&vop->win[i].base". That means the memory is 1391 * all part of the big "struct vop" chunk of memory. That memory 1392 * was devm allocated and associated with this component. We need to 1393 * free it ourselves before vop_unbind() finishes. 1394 */ 1395 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1396 head) 1397 vop_plane_destroy(plane); 1398 1399 /* 1400 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1401 * references the CRTC. 1402 */ 1403 drm_crtc_cleanup(crtc); 1404 drm_flip_work_cleanup(&vop->fb_unref_work); 1405 } 1406 1407 static int vop_initial(struct vop *vop) 1408 { 1409 const struct vop_data *vop_data = vop->data; 1410 struct reset_control *ahb_rst; 1411 int i, ret; 1412 1413 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1414 if (IS_ERR(vop->hclk)) { 1415 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1416 return PTR_ERR(vop->hclk); 1417 } 1418 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1419 if (IS_ERR(vop->aclk)) { 1420 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1421 return PTR_ERR(vop->aclk); 1422 } 1423 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1424 if (IS_ERR(vop->dclk)) { 1425 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1426 return PTR_ERR(vop->dclk); 1427 } 1428 1429 ret = pm_runtime_get_sync(vop->dev); 1430 if (ret < 0) { 1431 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1432 return ret; 1433 } 1434 1435 ret = clk_prepare(vop->dclk); 1436 if (ret < 0) { 1437 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1438 goto err_put_pm_runtime; 1439 } 1440 1441 /* Enable both the hclk and aclk to setup the vop */ 1442 ret = clk_prepare_enable(vop->hclk); 1443 if (ret < 0) { 1444 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1445 goto err_unprepare_dclk; 1446 } 1447 1448 ret = clk_prepare_enable(vop->aclk); 1449 if (ret < 0) { 1450 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1451 goto err_disable_hclk; 1452 } 1453 1454 /* 1455 * do hclk_reset, reset all vop registers. 1456 */ 1457 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1458 if (IS_ERR(ahb_rst)) { 1459 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1460 ret = PTR_ERR(ahb_rst); 1461 goto err_disable_aclk; 1462 } 1463 reset_control_assert(ahb_rst); 1464 usleep_range(10, 20); 1465 reset_control_deassert(ahb_rst); 1466 1467 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1468 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1469 1470 for (i = 0; i < vop->len; i += sizeof(u32)) 1471 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1472 1473 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1474 VOP_REG_SET(vop, common, dsp_blank, 0); 1475 1476 for (i = 0; i < vop_data->win_size; i++) { 1477 const struct vop_win_data *win = &vop_data->win[i]; 1478 int channel = i * 2 + 1; 1479 1480 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1481 VOP_WIN_SET(vop, win, enable, 0); 1482 VOP_WIN_SET(vop, win, gate, 1); 1483 } 1484 1485 vop_cfg_done(vop); 1486 1487 /* 1488 * do dclk_reset, let all config take affect. 1489 */ 1490 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1491 if (IS_ERR(vop->dclk_rst)) { 1492 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1493 ret = PTR_ERR(vop->dclk_rst); 1494 goto err_disable_aclk; 1495 } 1496 reset_control_assert(vop->dclk_rst); 1497 usleep_range(10, 20); 1498 reset_control_deassert(vop->dclk_rst); 1499 1500 clk_disable(vop->hclk); 1501 clk_disable(vop->aclk); 1502 1503 vop->is_enabled = false; 1504 1505 pm_runtime_put_sync(vop->dev); 1506 1507 return 0; 1508 1509 err_disable_aclk: 1510 clk_disable_unprepare(vop->aclk); 1511 err_disable_hclk: 1512 clk_disable_unprepare(vop->hclk); 1513 err_unprepare_dclk: 1514 clk_unprepare(vop->dclk); 1515 err_put_pm_runtime: 1516 pm_runtime_put_sync(vop->dev); 1517 return ret; 1518 } 1519 1520 /* 1521 * Initialize the vop->win array elements. 1522 */ 1523 static void vop_win_init(struct vop *vop) 1524 { 1525 const struct vop_data *vop_data = vop->data; 1526 unsigned int i; 1527 1528 for (i = 0; i < vop_data->win_size; i++) { 1529 struct vop_win *vop_win = &vop->win[i]; 1530 const struct vop_win_data *win_data = &vop_data->win[i]; 1531 1532 vop_win->data = win_data; 1533 vop_win->vop = vop; 1534 } 1535 } 1536 1537 /** 1538 * rockchip_drm_wait_vact_end 1539 * @crtc: CRTC to enable line flag 1540 * @mstimeout: millisecond for timeout 1541 * 1542 * Wait for vact_end line flag irq or timeout. 1543 * 1544 * Returns: 1545 * Zero on success, negative errno on failure. 1546 */ 1547 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1548 { 1549 struct vop *vop = to_vop(crtc); 1550 unsigned long jiffies_left; 1551 int ret = 0; 1552 1553 if (!crtc || !vop->is_enabled) 1554 return -ENODEV; 1555 1556 mutex_lock(&vop->vop_lock); 1557 if (mstimeout <= 0) { 1558 ret = -EINVAL; 1559 goto out; 1560 } 1561 1562 if (vop_line_flag_irq_is_enabled(vop)) { 1563 ret = -EBUSY; 1564 goto out; 1565 } 1566 1567 reinit_completion(&vop->line_flag_completion); 1568 vop_line_flag_irq_enable(vop); 1569 1570 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1571 msecs_to_jiffies(mstimeout)); 1572 vop_line_flag_irq_disable(vop); 1573 1574 if (jiffies_left == 0) { 1575 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1576 ret = -ETIMEDOUT; 1577 goto out; 1578 } 1579 1580 out: 1581 mutex_unlock(&vop->vop_lock); 1582 return ret; 1583 } 1584 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1585 1586 static int vop_bind(struct device *dev, struct device *master, void *data) 1587 { 1588 struct platform_device *pdev = to_platform_device(dev); 1589 const struct vop_data *vop_data; 1590 struct drm_device *drm_dev = data; 1591 struct vop *vop; 1592 struct resource *res; 1593 int ret, irq; 1594 1595 vop_data = of_device_get_match_data(dev); 1596 if (!vop_data) 1597 return -ENODEV; 1598 1599 /* Allocate vop struct and its vop_win array */ 1600 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 1601 GFP_KERNEL); 1602 if (!vop) 1603 return -ENOMEM; 1604 1605 vop->dev = dev; 1606 vop->data = vop_data; 1607 vop->drm_dev = drm_dev; 1608 dev_set_drvdata(dev, vop); 1609 1610 vop_win_init(vop); 1611 1612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1613 vop->len = resource_size(res); 1614 vop->regs = devm_ioremap_resource(dev, res); 1615 if (IS_ERR(vop->regs)) 1616 return PTR_ERR(vop->regs); 1617 1618 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1619 if (!vop->regsbak) 1620 return -ENOMEM; 1621 1622 irq = platform_get_irq(pdev, 0); 1623 if (irq < 0) { 1624 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1625 return irq; 1626 } 1627 vop->irq = (unsigned int)irq; 1628 1629 spin_lock_init(&vop->reg_lock); 1630 spin_lock_init(&vop->irq_lock); 1631 mutex_init(&vop->vop_lock); 1632 1633 ret = vop_create_crtc(vop); 1634 if (ret) 1635 return ret; 1636 1637 pm_runtime_enable(&pdev->dev); 1638 1639 ret = vop_initial(vop); 1640 if (ret < 0) { 1641 DRM_DEV_ERROR(&pdev->dev, 1642 "cannot initial vop dev - err %d\n", ret); 1643 goto err_disable_pm_runtime; 1644 } 1645 1646 ret = devm_request_irq(dev, vop->irq, vop_isr, 1647 IRQF_SHARED, dev_name(dev), vop); 1648 if (ret) 1649 goto err_disable_pm_runtime; 1650 1651 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 1652 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 1653 if (IS_ERR(vop->rgb)) { 1654 ret = PTR_ERR(vop->rgb); 1655 goto err_disable_pm_runtime; 1656 } 1657 } 1658 1659 return 0; 1660 1661 err_disable_pm_runtime: 1662 pm_runtime_disable(&pdev->dev); 1663 vop_destroy_crtc(vop); 1664 return ret; 1665 } 1666 1667 static void vop_unbind(struct device *dev, struct device *master, void *data) 1668 { 1669 struct vop *vop = dev_get_drvdata(dev); 1670 1671 if (vop->rgb) 1672 rockchip_rgb_fini(vop->rgb); 1673 1674 pm_runtime_disable(dev); 1675 vop_destroy_crtc(vop); 1676 1677 clk_unprepare(vop->aclk); 1678 clk_unprepare(vop->hclk); 1679 clk_unprepare(vop->dclk); 1680 } 1681 1682 const struct component_ops vop_component_ops = { 1683 .bind = vop_bind, 1684 .unbind = vop_unbind, 1685 }; 1686 EXPORT_SYMBOL_GPL(vop_component_ops); 1687