1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_plane_helper.h> 22 #ifdef CONFIG_DRM_ANALOGIX_DP 23 #include <drm/bridge/analogix_dp.h> 24 #endif 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/iopoll.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/component.h> 35 36 #include <linux/reset.h> 37 #include <linux/delay.h> 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_psr.h" 43 #include "rockchip_drm_vop.h" 44 45 #define VOP_WIN_SET(x, win, name, v) \ 46 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET(x, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 49 #define VOP_SCL_SET_EXT(x, win, name, v) \ 50 vop_reg_set(vop, &win->phy->scl->ext->name, \ 51 win->base, ~0, v, #name) 52 53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 54 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 55 56 #define VOP_REG_SET(vop, group, name, v) \ 57 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58 59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60 do { \ 61 int i, reg = 0, mask = 0; \ 62 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63 if (vop->data->intr->intrs[i] & type) { \ 64 reg |= (v) << i; \ 65 mask |= 1 << i; \ 66 } \ 67 } \ 68 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69 } while (0) 70 #define VOP_INTR_GET_TYPE(vop, name, type) \ 71 vop_get_intr_type(vop, &vop->data->intr->name, type) 72 73 #define VOP_WIN_GET(x, win, name) \ 74 vop_read_reg(x, win->offset, win->phy->name) 75 76 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 77 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 78 79 #define to_vop(x) container_of(x, struct vop, crtc) 80 #define to_vop_win(x) container_of(x, struct vop_win, base) 81 82 enum vop_pending { 83 VOP_PENDING_FB_UNREF, 84 }; 85 86 struct vop_win { 87 struct drm_plane base; 88 const struct vop_win_data *data; 89 struct vop *vop; 90 }; 91 92 struct vop { 93 struct drm_crtc crtc; 94 struct device *dev; 95 struct drm_device *drm_dev; 96 bool is_enabled; 97 98 struct completion dsp_hold_completion; 99 100 /* protected by dev->event_lock */ 101 struct drm_pending_vblank_event *event; 102 103 struct drm_flip_work fb_unref_work; 104 unsigned long pending; 105 106 struct completion line_flag_completion; 107 108 const struct vop_data *data; 109 110 uint32_t *regsbak; 111 void __iomem *regs; 112 113 /* physical map length of vop register */ 114 uint32_t len; 115 116 /* one time only one process allowed to config the register */ 117 spinlock_t reg_lock; 118 /* lock vop irq reg */ 119 spinlock_t irq_lock; 120 121 unsigned int irq; 122 123 /* vop AHP clk */ 124 struct clk *hclk; 125 /* vop dclk */ 126 struct clk *dclk; 127 /* vop share memory frequency */ 128 struct clk *aclk; 129 130 /* vop dclk reset */ 131 struct reset_control *dclk_rst; 132 133 struct vop_win win[]; 134 }; 135 136 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 137 { 138 writel(v, vop->regs + offset); 139 vop->regsbak[offset >> 2] = v; 140 } 141 142 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 143 { 144 return readl(vop->regs + offset); 145 } 146 147 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 148 const struct vop_reg *reg) 149 { 150 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 151 } 152 153 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 154 uint32_t _offset, uint32_t _mask, uint32_t v, 155 const char *reg_name) 156 { 157 int offset, mask, shift; 158 159 if (!reg || !reg->mask) { 160 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 161 return; 162 } 163 164 offset = reg->offset + _offset; 165 mask = reg->mask & _mask; 166 shift = reg->shift; 167 168 if (reg->write_mask) { 169 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 170 } else { 171 uint32_t cached_val = vop->regsbak[offset >> 2]; 172 173 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 174 vop->regsbak[offset >> 2] = v; 175 } 176 177 if (reg->relaxed) 178 writel_relaxed(v, vop->regs + offset); 179 else 180 writel(v, vop->regs + offset); 181 } 182 183 static inline uint32_t vop_get_intr_type(struct vop *vop, 184 const struct vop_reg *reg, int type) 185 { 186 uint32_t i, ret = 0; 187 uint32_t regs = vop_read_reg(vop, 0, reg); 188 189 for (i = 0; i < vop->data->intr->nintrs; i++) { 190 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 191 ret |= vop->data->intr->intrs[i]; 192 } 193 194 return ret; 195 } 196 197 static inline void vop_cfg_done(struct vop *vop) 198 { 199 VOP_REG_SET(vop, common, cfg_done, 1); 200 } 201 202 static bool has_rb_swapped(uint32_t format) 203 { 204 switch (format) { 205 case DRM_FORMAT_XBGR8888: 206 case DRM_FORMAT_ABGR8888: 207 case DRM_FORMAT_BGR888: 208 case DRM_FORMAT_BGR565: 209 return true; 210 default: 211 return false; 212 } 213 } 214 215 static enum vop_data_format vop_convert_format(uint32_t format) 216 { 217 switch (format) { 218 case DRM_FORMAT_XRGB8888: 219 case DRM_FORMAT_ARGB8888: 220 case DRM_FORMAT_XBGR8888: 221 case DRM_FORMAT_ABGR8888: 222 return VOP_FMT_ARGB8888; 223 case DRM_FORMAT_RGB888: 224 case DRM_FORMAT_BGR888: 225 return VOP_FMT_RGB888; 226 case DRM_FORMAT_RGB565: 227 case DRM_FORMAT_BGR565: 228 return VOP_FMT_RGB565; 229 case DRM_FORMAT_NV12: 230 return VOP_FMT_YUV420SP; 231 case DRM_FORMAT_NV16: 232 return VOP_FMT_YUV422SP; 233 case DRM_FORMAT_NV24: 234 return VOP_FMT_YUV444SP; 235 default: 236 DRM_ERROR("unsupported format[%08x]\n", format); 237 return -EINVAL; 238 } 239 } 240 241 static bool is_yuv_support(uint32_t format) 242 { 243 switch (format) { 244 case DRM_FORMAT_NV12: 245 case DRM_FORMAT_NV16: 246 case DRM_FORMAT_NV24: 247 return true; 248 default: 249 return false; 250 } 251 } 252 253 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 254 uint32_t dst, bool is_horizontal, 255 int vsu_mode, int *vskiplines) 256 { 257 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 258 259 if (vskiplines) 260 *vskiplines = 0; 261 262 if (is_horizontal) { 263 if (mode == SCALE_UP) 264 val = GET_SCL_FT_BIC(src, dst); 265 else if (mode == SCALE_DOWN) 266 val = GET_SCL_FT_BILI_DN(src, dst); 267 } else { 268 if (mode == SCALE_UP) { 269 if (vsu_mode == SCALE_UP_BIL) 270 val = GET_SCL_FT_BILI_UP(src, dst); 271 else 272 val = GET_SCL_FT_BIC(src, dst); 273 } else if (mode == SCALE_DOWN) { 274 if (vskiplines) { 275 *vskiplines = scl_get_vskiplines(src, dst); 276 val = scl_get_bili_dn_vskip(src, dst, 277 *vskiplines); 278 } else { 279 val = GET_SCL_FT_BILI_DN(src, dst); 280 } 281 } 282 } 283 284 return val; 285 } 286 287 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 288 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 289 uint32_t dst_h, uint32_t pixel_format) 290 { 291 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 292 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 293 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 294 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 295 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 296 bool is_yuv = is_yuv_support(pixel_format); 297 uint16_t cbcr_src_w = src_w / hsub; 298 uint16_t cbcr_src_h = src_h / vsub; 299 uint16_t vsu_mode; 300 uint16_t lb_mode; 301 uint32_t val; 302 int vskiplines; 303 304 if (dst_w > 3840) { 305 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 306 return; 307 } 308 309 if (!win->phy->scl->ext) { 310 VOP_SCL_SET(vop, win, scale_yrgb_x, 311 scl_cal_scale2(src_w, dst_w)); 312 VOP_SCL_SET(vop, win, scale_yrgb_y, 313 scl_cal_scale2(src_h, dst_h)); 314 if (is_yuv) { 315 VOP_SCL_SET(vop, win, scale_cbcr_x, 316 scl_cal_scale2(cbcr_src_w, dst_w)); 317 VOP_SCL_SET(vop, win, scale_cbcr_y, 318 scl_cal_scale2(cbcr_src_h, dst_h)); 319 } 320 return; 321 } 322 323 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 324 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 325 326 if (is_yuv) { 327 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 328 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 329 if (cbcr_hor_scl_mode == SCALE_DOWN) 330 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 331 else 332 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 333 } else { 334 if (yrgb_hor_scl_mode == SCALE_DOWN) 335 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 336 else 337 lb_mode = scl_vop_cal_lb_mode(src_w, false); 338 } 339 340 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 341 if (lb_mode == LB_RGB_3840X2) { 342 if (yrgb_ver_scl_mode != SCALE_NONE) { 343 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 344 return; 345 } 346 if (cbcr_ver_scl_mode != SCALE_NONE) { 347 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 348 return; 349 } 350 vsu_mode = SCALE_UP_BIL; 351 } else if (lb_mode == LB_RGB_2560X4) { 352 vsu_mode = SCALE_UP_BIL; 353 } else { 354 vsu_mode = SCALE_UP_BIC; 355 } 356 357 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 358 true, 0, NULL); 359 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 360 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 361 false, vsu_mode, &vskiplines); 362 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 363 364 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 365 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 366 367 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 368 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 369 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 370 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 371 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 372 if (is_yuv) { 373 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 374 dst_w, true, 0, NULL); 375 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 376 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 377 dst_h, false, vsu_mode, &vskiplines); 378 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 379 380 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 381 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 382 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 383 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 384 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 385 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 386 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 387 } 388 } 389 390 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 391 { 392 unsigned long flags; 393 394 if (WARN_ON(!vop->is_enabled)) 395 return; 396 397 spin_lock_irqsave(&vop->irq_lock, flags); 398 399 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 400 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 401 402 spin_unlock_irqrestore(&vop->irq_lock, flags); 403 } 404 405 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 406 { 407 unsigned long flags; 408 409 if (WARN_ON(!vop->is_enabled)) 410 return; 411 412 spin_lock_irqsave(&vop->irq_lock, flags); 413 414 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 415 416 spin_unlock_irqrestore(&vop->irq_lock, flags); 417 } 418 419 /* 420 * (1) each frame starts at the start of the Vsync pulse which is signaled by 421 * the "FRAME_SYNC" interrupt. 422 * (2) the active data region of each frame ends at dsp_vact_end 423 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 424 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 425 * 426 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 427 * Interrupts 428 * LINE_FLAG -------------------------------+ 429 * FRAME_SYNC ----+ | 430 * | | 431 * v v 432 * | Vsync | Vbp | Vactive | Vfp | 433 * ^ ^ ^ ^ 434 * | | | | 435 * | | | | 436 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 437 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 438 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 439 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 440 */ 441 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 442 { 443 uint32_t line_flag_irq; 444 unsigned long flags; 445 446 spin_lock_irqsave(&vop->irq_lock, flags); 447 448 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 449 450 spin_unlock_irqrestore(&vop->irq_lock, flags); 451 452 return !!line_flag_irq; 453 } 454 455 static void vop_line_flag_irq_enable(struct vop *vop) 456 { 457 unsigned long flags; 458 459 if (WARN_ON(!vop->is_enabled)) 460 return; 461 462 spin_lock_irqsave(&vop->irq_lock, flags); 463 464 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 465 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 466 467 spin_unlock_irqrestore(&vop->irq_lock, flags); 468 } 469 470 static void vop_line_flag_irq_disable(struct vop *vop) 471 { 472 unsigned long flags; 473 474 if (WARN_ON(!vop->is_enabled)) 475 return; 476 477 spin_lock_irqsave(&vop->irq_lock, flags); 478 479 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 480 481 spin_unlock_irqrestore(&vop->irq_lock, flags); 482 } 483 484 static int vop_enable(struct drm_crtc *crtc) 485 { 486 struct vop *vop = to_vop(crtc); 487 int ret, i; 488 489 ret = pm_runtime_get_sync(vop->dev); 490 if (ret < 0) { 491 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 492 return ret; 493 } 494 495 ret = clk_enable(vop->hclk); 496 if (WARN_ON(ret < 0)) 497 goto err_put_pm_runtime; 498 499 ret = clk_enable(vop->dclk); 500 if (WARN_ON(ret < 0)) 501 goto err_disable_hclk; 502 503 ret = clk_enable(vop->aclk); 504 if (WARN_ON(ret < 0)) 505 goto err_disable_dclk; 506 507 /* 508 * Slave iommu shares power, irq and clock with vop. It was associated 509 * automatically with this master device via common driver code. 510 * Now that we have enabled the clock we attach it to the shared drm 511 * mapping. 512 */ 513 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 514 if (ret) { 515 DRM_DEV_ERROR(vop->dev, 516 "failed to attach dma mapping, %d\n", ret); 517 goto err_disable_aclk; 518 } 519 520 memcpy(vop->regs, vop->regsbak, vop->len); 521 /* 522 * We need to make sure that all windows are disabled before we 523 * enable the crtc. Otherwise we might try to scan from a destroyed 524 * buffer later. 525 */ 526 for (i = 0; i < vop->data->win_size; i++) { 527 struct vop_win *vop_win = &vop->win[i]; 528 const struct vop_win_data *win = vop_win->data; 529 530 spin_lock(&vop->reg_lock); 531 VOP_WIN_SET(vop, win, enable, 0); 532 spin_unlock(&vop->reg_lock); 533 } 534 535 vop_cfg_done(vop); 536 537 /* 538 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 539 */ 540 vop->is_enabled = true; 541 542 spin_lock(&vop->reg_lock); 543 544 VOP_REG_SET(vop, common, standby, 1); 545 546 spin_unlock(&vop->reg_lock); 547 548 enable_irq(vop->irq); 549 550 drm_crtc_vblank_on(crtc); 551 552 return 0; 553 554 err_disable_aclk: 555 clk_disable(vop->aclk); 556 err_disable_dclk: 557 clk_disable(vop->dclk); 558 err_disable_hclk: 559 clk_disable(vop->hclk); 560 err_put_pm_runtime: 561 pm_runtime_put_sync(vop->dev); 562 return ret; 563 } 564 565 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 566 struct drm_crtc_state *old_state) 567 { 568 struct vop *vop = to_vop(crtc); 569 570 WARN_ON(vop->event); 571 572 drm_crtc_vblank_off(crtc); 573 574 /* 575 * Vop standby will take effect at end of current frame, 576 * if dsp hold valid irq happen, it means standby complete. 577 * 578 * we must wait standby complete when we want to disable aclk, 579 * if not, memory bus maybe dead. 580 */ 581 reinit_completion(&vop->dsp_hold_completion); 582 vop_dsp_hold_valid_irq_enable(vop); 583 584 spin_lock(&vop->reg_lock); 585 586 VOP_REG_SET(vop, common, standby, 1); 587 588 spin_unlock(&vop->reg_lock); 589 590 wait_for_completion(&vop->dsp_hold_completion); 591 592 vop_dsp_hold_valid_irq_disable(vop); 593 594 disable_irq(vop->irq); 595 596 vop->is_enabled = false; 597 598 /* 599 * vop standby complete, so iommu detach is safe. 600 */ 601 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 602 603 clk_disable(vop->dclk); 604 clk_disable(vop->aclk); 605 clk_disable(vop->hclk); 606 pm_runtime_put(vop->dev); 607 608 if (crtc->state->event && !crtc->state->active) { 609 spin_lock_irq(&crtc->dev->event_lock); 610 drm_crtc_send_vblank_event(crtc, crtc->state->event); 611 spin_unlock_irq(&crtc->dev->event_lock); 612 613 crtc->state->event = NULL; 614 } 615 } 616 617 static void vop_plane_destroy(struct drm_plane *plane) 618 { 619 drm_plane_cleanup(plane); 620 } 621 622 static int vop_plane_atomic_check(struct drm_plane *plane, 623 struct drm_plane_state *state) 624 { 625 struct drm_crtc *crtc = state->crtc; 626 struct drm_crtc_state *crtc_state; 627 struct drm_framebuffer *fb = state->fb; 628 struct vop_win *vop_win = to_vop_win(plane); 629 const struct vop_win_data *win = vop_win->data; 630 int ret; 631 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 632 DRM_PLANE_HELPER_NO_SCALING; 633 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 634 DRM_PLANE_HELPER_NO_SCALING; 635 636 if (!crtc || !fb) 637 return 0; 638 639 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 640 if (WARN_ON(!crtc_state)) 641 return -EINVAL; 642 643 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 644 min_scale, max_scale, 645 true, true); 646 if (ret) 647 return ret; 648 649 if (!state->visible) 650 return 0; 651 652 ret = vop_convert_format(fb->format->format); 653 if (ret < 0) 654 return ret; 655 656 /* 657 * Src.x1 can be odd when do clip, but yuv plane start point 658 * need align with 2 pixel. 659 */ 660 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) { 661 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 662 return -EINVAL; 663 } 664 665 return 0; 666 } 667 668 static void vop_plane_atomic_disable(struct drm_plane *plane, 669 struct drm_plane_state *old_state) 670 { 671 struct vop_win *vop_win = to_vop_win(plane); 672 const struct vop_win_data *win = vop_win->data; 673 struct vop *vop = to_vop(old_state->crtc); 674 675 if (!old_state->crtc) 676 return; 677 678 spin_lock(&vop->reg_lock); 679 680 VOP_WIN_SET(vop, win, enable, 0); 681 682 spin_unlock(&vop->reg_lock); 683 } 684 685 static void vop_plane_atomic_update(struct drm_plane *plane, 686 struct drm_plane_state *old_state) 687 { 688 struct drm_plane_state *state = plane->state; 689 struct drm_crtc *crtc = state->crtc; 690 struct vop_win *vop_win = to_vop_win(plane); 691 const struct vop_win_data *win = vop_win->data; 692 struct vop *vop = to_vop(state->crtc); 693 struct drm_framebuffer *fb = state->fb; 694 unsigned int actual_w, actual_h; 695 unsigned int dsp_stx, dsp_sty; 696 uint32_t act_info, dsp_info, dsp_st; 697 struct drm_rect *src = &state->src; 698 struct drm_rect *dest = &state->dst; 699 struct drm_gem_object *obj, *uv_obj; 700 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 701 unsigned long offset; 702 dma_addr_t dma_addr; 703 uint32_t val; 704 bool rb_swap; 705 int format; 706 707 /* 708 * can't update plane when vop is disabled. 709 */ 710 if (WARN_ON(!crtc)) 711 return; 712 713 if (WARN_ON(!vop->is_enabled)) 714 return; 715 716 if (!state->visible) { 717 vop_plane_atomic_disable(plane, old_state); 718 return; 719 } 720 721 obj = rockchip_fb_get_gem_obj(fb, 0); 722 rk_obj = to_rockchip_obj(obj); 723 724 actual_w = drm_rect_width(src) >> 16; 725 actual_h = drm_rect_height(src) >> 16; 726 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 727 728 dsp_info = (drm_rect_height(dest) - 1) << 16; 729 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 730 731 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 732 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 733 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 734 735 offset = (src->x1 >> 16) * fb->format->cpp[0]; 736 offset += (src->y1 >> 16) * fb->pitches[0]; 737 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 738 739 format = vop_convert_format(fb->format->format); 740 741 spin_lock(&vop->reg_lock); 742 743 VOP_WIN_SET(vop, win, format, format); 744 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 745 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 746 if (is_yuv_support(fb->format->format)) { 747 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 748 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 749 int bpp = fb->format->cpp[1]; 750 751 uv_obj = rockchip_fb_get_gem_obj(fb, 1); 752 rk_uv_obj = to_rockchip_obj(uv_obj); 753 754 offset = (src->x1 >> 16) * bpp / hsub; 755 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 756 757 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 758 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 759 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 760 } 761 762 if (win->phy->scl) 763 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 764 drm_rect_width(dest), drm_rect_height(dest), 765 fb->format->format); 766 767 VOP_WIN_SET(vop, win, act_info, act_info); 768 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 769 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 770 771 rb_swap = has_rb_swapped(fb->format->format); 772 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 773 774 if (fb->format->has_alpha) { 775 VOP_WIN_SET(vop, win, dst_alpha_ctl, 776 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 777 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 778 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 779 SRC_BLEND_M0(ALPHA_PER_PIX) | 780 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 781 SRC_FACTOR_M0(ALPHA_ONE); 782 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 783 } else { 784 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 785 } 786 787 VOP_WIN_SET(vop, win, enable, 1); 788 spin_unlock(&vop->reg_lock); 789 } 790 791 static const struct drm_plane_helper_funcs plane_helper_funcs = { 792 .atomic_check = vop_plane_atomic_check, 793 .atomic_update = vop_plane_atomic_update, 794 .atomic_disable = vop_plane_atomic_disable, 795 }; 796 797 static const struct drm_plane_funcs vop_plane_funcs = { 798 .update_plane = drm_atomic_helper_update_plane, 799 .disable_plane = drm_atomic_helper_disable_plane, 800 .destroy = vop_plane_destroy, 801 .reset = drm_atomic_helper_plane_reset, 802 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 803 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 804 }; 805 806 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 807 { 808 struct vop *vop = to_vop(crtc); 809 unsigned long flags; 810 811 if (WARN_ON(!vop->is_enabled)) 812 return -EPERM; 813 814 spin_lock_irqsave(&vop->irq_lock, flags); 815 816 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 817 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 818 819 spin_unlock_irqrestore(&vop->irq_lock, flags); 820 821 return 0; 822 } 823 824 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 825 { 826 struct vop *vop = to_vop(crtc); 827 unsigned long flags; 828 829 if (WARN_ON(!vop->is_enabled)) 830 return; 831 832 spin_lock_irqsave(&vop->irq_lock, flags); 833 834 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 835 836 spin_unlock_irqrestore(&vop->irq_lock, flags); 837 } 838 839 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 840 const struct drm_display_mode *mode, 841 struct drm_display_mode *adjusted_mode) 842 { 843 struct vop *vop = to_vop(crtc); 844 845 adjusted_mode->clock = 846 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 847 848 return true; 849 } 850 851 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 852 struct drm_crtc_state *old_state) 853 { 854 struct vop *vop = to_vop(crtc); 855 const struct vop_data *vop_data = vop->data; 856 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 857 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 858 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 859 u16 hdisplay = adjusted_mode->hdisplay; 860 u16 htotal = adjusted_mode->htotal; 861 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 862 u16 hact_end = hact_st + hdisplay; 863 u16 vdisplay = adjusted_mode->vdisplay; 864 u16 vtotal = adjusted_mode->vtotal; 865 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 866 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 867 u16 vact_end = vact_st + vdisplay; 868 uint32_t pin_pol, val; 869 int ret; 870 871 WARN_ON(vop->event); 872 873 ret = vop_enable(crtc); 874 if (ret) { 875 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 876 return; 877 } 878 879 pin_pol = BIT(DCLK_INVERT); 880 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 881 BIT(HSYNC_POSITIVE) : 0; 882 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 883 BIT(VSYNC_POSITIVE) : 0; 884 VOP_REG_SET(vop, output, pin_pol, pin_pol); 885 886 switch (s->output_type) { 887 case DRM_MODE_CONNECTOR_LVDS: 888 VOP_REG_SET(vop, output, rgb_en, 1); 889 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 890 break; 891 case DRM_MODE_CONNECTOR_eDP: 892 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 893 VOP_REG_SET(vop, output, edp_en, 1); 894 break; 895 case DRM_MODE_CONNECTOR_HDMIA: 896 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 897 VOP_REG_SET(vop, output, hdmi_en, 1); 898 break; 899 case DRM_MODE_CONNECTOR_DSI: 900 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 901 VOP_REG_SET(vop, output, mipi_en, 1); 902 break; 903 case DRM_MODE_CONNECTOR_DisplayPort: 904 pin_pol &= ~BIT(DCLK_INVERT); 905 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 906 VOP_REG_SET(vop, output, dp_en, 1); 907 break; 908 default: 909 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 910 s->output_type); 911 } 912 913 /* 914 * if vop is not support RGB10 output, need force RGB10 to RGB888. 915 */ 916 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 917 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 918 s->output_mode = ROCKCHIP_OUT_MODE_P888; 919 VOP_REG_SET(vop, common, out_mode, s->output_mode); 920 921 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 922 val = hact_st << 16; 923 val |= hact_end; 924 VOP_REG_SET(vop, modeset, hact_st_end, val); 925 VOP_REG_SET(vop, modeset, hpost_st_end, val); 926 927 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 928 val = vact_st << 16; 929 val |= vact_end; 930 VOP_REG_SET(vop, modeset, vact_st_end, val); 931 VOP_REG_SET(vop, modeset, vpost_st_end, val); 932 933 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 934 935 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 936 937 VOP_REG_SET(vop, common, standby, 0); 938 } 939 940 static bool vop_fs_irq_is_pending(struct vop *vop) 941 { 942 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 943 } 944 945 static void vop_wait_for_irq_handler(struct vop *vop) 946 { 947 bool pending; 948 int ret; 949 950 /* 951 * Spin until frame start interrupt status bit goes low, which means 952 * that interrupt handler was invoked and cleared it. The timeout of 953 * 10 msecs is really too long, but it is just a safety measure if 954 * something goes really wrong. The wait will only happen in the very 955 * unlikely case of a vblank happening exactly at the same time and 956 * shouldn't exceed microseconds range. 957 */ 958 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 959 !pending, 0, 10 * 1000); 960 if (ret) 961 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 962 963 synchronize_irq(vop->irq); 964 } 965 966 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 967 struct drm_crtc_state *old_crtc_state) 968 { 969 struct drm_atomic_state *old_state = old_crtc_state->state; 970 struct drm_plane_state *old_plane_state, *new_plane_state; 971 struct vop *vop = to_vop(crtc); 972 struct drm_plane *plane; 973 int i; 974 975 if (WARN_ON(!vop->is_enabled)) 976 return; 977 978 spin_lock(&vop->reg_lock); 979 980 vop_cfg_done(vop); 981 982 spin_unlock(&vop->reg_lock); 983 984 /* 985 * There is a (rather unlikely) possiblity that a vblank interrupt 986 * fired before we set the cfg_done bit. To avoid spuriously 987 * signalling flip completion we need to wait for it to finish. 988 */ 989 vop_wait_for_irq_handler(vop); 990 991 spin_lock_irq(&crtc->dev->event_lock); 992 if (crtc->state->event) { 993 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 994 WARN_ON(vop->event); 995 996 vop->event = crtc->state->event; 997 crtc->state->event = NULL; 998 } 999 spin_unlock_irq(&crtc->dev->event_lock); 1000 1001 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1002 new_plane_state, i) { 1003 if (!old_plane_state->fb) 1004 continue; 1005 1006 if (old_plane_state->fb == new_plane_state->fb) 1007 continue; 1008 1009 drm_framebuffer_get(old_plane_state->fb); 1010 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1011 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1012 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1013 } 1014 } 1015 1016 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1017 struct drm_crtc_state *old_crtc_state) 1018 { 1019 rockchip_drm_psr_flush(crtc); 1020 } 1021 1022 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1023 .mode_fixup = vop_crtc_mode_fixup, 1024 .atomic_flush = vop_crtc_atomic_flush, 1025 .atomic_begin = vop_crtc_atomic_begin, 1026 .atomic_enable = vop_crtc_atomic_enable, 1027 .atomic_disable = vop_crtc_atomic_disable, 1028 }; 1029 1030 static void vop_crtc_destroy(struct drm_crtc *crtc) 1031 { 1032 drm_crtc_cleanup(crtc); 1033 } 1034 1035 static void vop_crtc_reset(struct drm_crtc *crtc) 1036 { 1037 if (crtc->state) 1038 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1039 kfree(crtc->state); 1040 1041 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1042 if (crtc->state) 1043 crtc->state->crtc = crtc; 1044 } 1045 1046 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1047 { 1048 struct rockchip_crtc_state *rockchip_state; 1049 1050 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1051 if (!rockchip_state) 1052 return NULL; 1053 1054 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1055 return &rockchip_state->base; 1056 } 1057 1058 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1059 struct drm_crtc_state *state) 1060 { 1061 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1062 1063 __drm_atomic_helper_crtc_destroy_state(&s->base); 1064 kfree(s); 1065 } 1066 1067 #ifdef CONFIG_DRM_ANALOGIX_DP 1068 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1069 { 1070 struct drm_connector *connector; 1071 struct drm_connector_list_iter conn_iter; 1072 1073 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1074 drm_for_each_connector_iter(connector, &conn_iter) { 1075 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1076 drm_connector_list_iter_end(&conn_iter); 1077 return connector; 1078 } 1079 } 1080 drm_connector_list_iter_end(&conn_iter); 1081 1082 return NULL; 1083 } 1084 1085 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1086 const char *source_name, size_t *values_cnt) 1087 { 1088 struct vop *vop = to_vop(crtc); 1089 struct drm_connector *connector; 1090 int ret; 1091 1092 connector = vop_get_edp_connector(vop); 1093 if (!connector) 1094 return -EINVAL; 1095 1096 *values_cnt = 3; 1097 1098 if (source_name && strcmp(source_name, "auto") == 0) 1099 ret = analogix_dp_start_crc(connector); 1100 else if (!source_name) 1101 ret = analogix_dp_stop_crc(connector); 1102 else 1103 ret = -EINVAL; 1104 1105 return ret; 1106 } 1107 #else 1108 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1109 const char *source_name, size_t *values_cnt) 1110 { 1111 return -ENODEV; 1112 } 1113 #endif 1114 1115 static const struct drm_crtc_funcs vop_crtc_funcs = { 1116 .set_config = drm_atomic_helper_set_config, 1117 .page_flip = drm_atomic_helper_page_flip, 1118 .destroy = vop_crtc_destroy, 1119 .reset = vop_crtc_reset, 1120 .atomic_duplicate_state = vop_crtc_duplicate_state, 1121 .atomic_destroy_state = vop_crtc_destroy_state, 1122 .enable_vblank = vop_crtc_enable_vblank, 1123 .disable_vblank = vop_crtc_disable_vblank, 1124 .set_crc_source = vop_crtc_set_crc_source, 1125 }; 1126 1127 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1128 { 1129 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1130 struct drm_framebuffer *fb = val; 1131 1132 drm_crtc_vblank_put(&vop->crtc); 1133 drm_framebuffer_put(fb); 1134 } 1135 1136 static void vop_handle_vblank(struct vop *vop) 1137 { 1138 struct drm_device *drm = vop->drm_dev; 1139 struct drm_crtc *crtc = &vop->crtc; 1140 unsigned long flags; 1141 1142 spin_lock_irqsave(&drm->event_lock, flags); 1143 if (vop->event) { 1144 drm_crtc_send_vblank_event(crtc, vop->event); 1145 drm_crtc_vblank_put(crtc); 1146 vop->event = NULL; 1147 } 1148 spin_unlock_irqrestore(&drm->event_lock, flags); 1149 1150 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1151 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1152 } 1153 1154 static irqreturn_t vop_isr(int irq, void *data) 1155 { 1156 struct vop *vop = data; 1157 struct drm_crtc *crtc = &vop->crtc; 1158 uint32_t active_irqs; 1159 unsigned long flags; 1160 int ret = IRQ_NONE; 1161 1162 /* 1163 * interrupt register has interrupt status, enable and clear bits, we 1164 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1165 */ 1166 spin_lock_irqsave(&vop->irq_lock, flags); 1167 1168 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1169 /* Clear all active interrupt sources */ 1170 if (active_irqs) 1171 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1172 1173 spin_unlock_irqrestore(&vop->irq_lock, flags); 1174 1175 /* This is expected for vop iommu irqs, since the irq is shared */ 1176 if (!active_irqs) 1177 return IRQ_NONE; 1178 1179 if (active_irqs & DSP_HOLD_VALID_INTR) { 1180 complete(&vop->dsp_hold_completion); 1181 active_irqs &= ~DSP_HOLD_VALID_INTR; 1182 ret = IRQ_HANDLED; 1183 } 1184 1185 if (active_irqs & LINE_FLAG_INTR) { 1186 complete(&vop->line_flag_completion); 1187 active_irqs &= ~LINE_FLAG_INTR; 1188 ret = IRQ_HANDLED; 1189 } 1190 1191 if (active_irqs & FS_INTR) { 1192 drm_crtc_handle_vblank(crtc); 1193 vop_handle_vblank(vop); 1194 active_irqs &= ~FS_INTR; 1195 ret = IRQ_HANDLED; 1196 } 1197 1198 /* Unhandled irqs are spurious. */ 1199 if (active_irqs) 1200 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1201 active_irqs); 1202 1203 return ret; 1204 } 1205 1206 static int vop_create_crtc(struct vop *vop) 1207 { 1208 const struct vop_data *vop_data = vop->data; 1209 struct device *dev = vop->dev; 1210 struct drm_device *drm_dev = vop->drm_dev; 1211 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1212 struct drm_crtc *crtc = &vop->crtc; 1213 struct device_node *port; 1214 int ret; 1215 int i; 1216 1217 /* 1218 * Create drm_plane for primary and cursor planes first, since we need 1219 * to pass them to drm_crtc_init_with_planes, which sets the 1220 * "possible_crtcs" to the newly initialized crtc. 1221 */ 1222 for (i = 0; i < vop_data->win_size; i++) { 1223 struct vop_win *vop_win = &vop->win[i]; 1224 const struct vop_win_data *win_data = vop_win->data; 1225 1226 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1227 win_data->type != DRM_PLANE_TYPE_CURSOR) 1228 continue; 1229 1230 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1231 0, &vop_plane_funcs, 1232 win_data->phy->data_formats, 1233 win_data->phy->nformats, 1234 NULL, win_data->type, NULL); 1235 if (ret) { 1236 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1237 ret); 1238 goto err_cleanup_planes; 1239 } 1240 1241 plane = &vop_win->base; 1242 drm_plane_helper_add(plane, &plane_helper_funcs); 1243 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1244 primary = plane; 1245 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1246 cursor = plane; 1247 } 1248 1249 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1250 &vop_crtc_funcs, NULL); 1251 if (ret) 1252 goto err_cleanup_planes; 1253 1254 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1255 1256 /* 1257 * Create drm_planes for overlay windows with possible_crtcs restricted 1258 * to the newly created crtc. 1259 */ 1260 for (i = 0; i < vop_data->win_size; i++) { 1261 struct vop_win *vop_win = &vop->win[i]; 1262 const struct vop_win_data *win_data = vop_win->data; 1263 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1264 1265 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1266 continue; 1267 1268 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1269 possible_crtcs, 1270 &vop_plane_funcs, 1271 win_data->phy->data_formats, 1272 win_data->phy->nformats, 1273 NULL, win_data->type, NULL); 1274 if (ret) { 1275 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1276 ret); 1277 goto err_cleanup_crtc; 1278 } 1279 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1280 } 1281 1282 port = of_get_child_by_name(dev->of_node, "port"); 1283 if (!port) { 1284 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1285 dev->of_node); 1286 ret = -ENOENT; 1287 goto err_cleanup_crtc; 1288 } 1289 1290 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1291 vop_fb_unref_worker); 1292 1293 init_completion(&vop->dsp_hold_completion); 1294 init_completion(&vop->line_flag_completion); 1295 crtc->port = port; 1296 1297 return 0; 1298 1299 err_cleanup_crtc: 1300 drm_crtc_cleanup(crtc); 1301 err_cleanup_planes: 1302 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1303 head) 1304 drm_plane_cleanup(plane); 1305 return ret; 1306 } 1307 1308 static void vop_destroy_crtc(struct vop *vop) 1309 { 1310 struct drm_crtc *crtc = &vop->crtc; 1311 struct drm_device *drm_dev = vop->drm_dev; 1312 struct drm_plane *plane, *tmp; 1313 1314 of_node_put(crtc->port); 1315 1316 /* 1317 * We need to cleanup the planes now. Why? 1318 * 1319 * The planes are "&vop->win[i].base". That means the memory is 1320 * all part of the big "struct vop" chunk of memory. That memory 1321 * was devm allocated and associated with this component. We need to 1322 * free it ourselves before vop_unbind() finishes. 1323 */ 1324 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1325 head) 1326 vop_plane_destroy(plane); 1327 1328 /* 1329 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1330 * references the CRTC. 1331 */ 1332 drm_crtc_cleanup(crtc); 1333 drm_flip_work_cleanup(&vop->fb_unref_work); 1334 } 1335 1336 static int vop_initial(struct vop *vop) 1337 { 1338 const struct vop_data *vop_data = vop->data; 1339 struct reset_control *ahb_rst; 1340 int i, ret; 1341 1342 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1343 if (IS_ERR(vop->hclk)) { 1344 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1345 return PTR_ERR(vop->hclk); 1346 } 1347 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1348 if (IS_ERR(vop->aclk)) { 1349 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1350 return PTR_ERR(vop->aclk); 1351 } 1352 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1353 if (IS_ERR(vop->dclk)) { 1354 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1355 return PTR_ERR(vop->dclk); 1356 } 1357 1358 ret = pm_runtime_get_sync(vop->dev); 1359 if (ret < 0) { 1360 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1361 return ret; 1362 } 1363 1364 ret = clk_prepare(vop->dclk); 1365 if (ret < 0) { 1366 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1367 goto err_put_pm_runtime; 1368 } 1369 1370 /* Enable both the hclk and aclk to setup the vop */ 1371 ret = clk_prepare_enable(vop->hclk); 1372 if (ret < 0) { 1373 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1374 goto err_unprepare_dclk; 1375 } 1376 1377 ret = clk_prepare_enable(vop->aclk); 1378 if (ret < 0) { 1379 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1380 goto err_disable_hclk; 1381 } 1382 1383 /* 1384 * do hclk_reset, reset all vop registers. 1385 */ 1386 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1387 if (IS_ERR(ahb_rst)) { 1388 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1389 ret = PTR_ERR(ahb_rst); 1390 goto err_disable_aclk; 1391 } 1392 reset_control_assert(ahb_rst); 1393 usleep_range(10, 20); 1394 reset_control_deassert(ahb_rst); 1395 1396 memcpy(vop->regsbak, vop->regs, vop->len); 1397 1398 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1399 VOP_REG_SET(vop, common, dsp_blank, 0); 1400 1401 for (i = 0; i < vop_data->win_size; i++) { 1402 const struct vop_win_data *win = &vop_data->win[i]; 1403 int channel = i * 2 + 1; 1404 1405 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1406 VOP_WIN_SET(vop, win, enable, 0); 1407 VOP_WIN_SET(vop, win, gate, 1); 1408 } 1409 1410 vop_cfg_done(vop); 1411 1412 /* 1413 * do dclk_reset, let all config take affect. 1414 */ 1415 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1416 if (IS_ERR(vop->dclk_rst)) { 1417 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1418 ret = PTR_ERR(vop->dclk_rst); 1419 goto err_disable_aclk; 1420 } 1421 reset_control_assert(vop->dclk_rst); 1422 usleep_range(10, 20); 1423 reset_control_deassert(vop->dclk_rst); 1424 1425 clk_disable(vop->hclk); 1426 clk_disable(vop->aclk); 1427 1428 vop->is_enabled = false; 1429 1430 pm_runtime_put_sync(vop->dev); 1431 1432 return 0; 1433 1434 err_disable_aclk: 1435 clk_disable_unprepare(vop->aclk); 1436 err_disable_hclk: 1437 clk_disable_unprepare(vop->hclk); 1438 err_unprepare_dclk: 1439 clk_unprepare(vop->dclk); 1440 err_put_pm_runtime: 1441 pm_runtime_put_sync(vop->dev); 1442 return ret; 1443 } 1444 1445 /* 1446 * Initialize the vop->win array elements. 1447 */ 1448 static void vop_win_init(struct vop *vop) 1449 { 1450 const struct vop_data *vop_data = vop->data; 1451 unsigned int i; 1452 1453 for (i = 0; i < vop_data->win_size; i++) { 1454 struct vop_win *vop_win = &vop->win[i]; 1455 const struct vop_win_data *win_data = &vop_data->win[i]; 1456 1457 vop_win->data = win_data; 1458 vop_win->vop = vop; 1459 } 1460 } 1461 1462 /** 1463 * rockchip_drm_wait_vact_end 1464 * @crtc: CRTC to enable line flag 1465 * @mstimeout: millisecond for timeout 1466 * 1467 * Wait for vact_end line flag irq or timeout. 1468 * 1469 * Returns: 1470 * Zero on success, negative errno on failure. 1471 */ 1472 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1473 { 1474 struct vop *vop = to_vop(crtc); 1475 unsigned long jiffies_left; 1476 1477 if (!crtc || !vop->is_enabled) 1478 return -ENODEV; 1479 1480 if (mstimeout <= 0) 1481 return -EINVAL; 1482 1483 if (vop_line_flag_irq_is_enabled(vop)) 1484 return -EBUSY; 1485 1486 reinit_completion(&vop->line_flag_completion); 1487 vop_line_flag_irq_enable(vop); 1488 1489 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1490 msecs_to_jiffies(mstimeout)); 1491 vop_line_flag_irq_disable(vop); 1492 1493 if (jiffies_left == 0) { 1494 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1495 return -ETIMEDOUT; 1496 } 1497 1498 return 0; 1499 } 1500 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1501 1502 static int vop_bind(struct device *dev, struct device *master, void *data) 1503 { 1504 struct platform_device *pdev = to_platform_device(dev); 1505 const struct vop_data *vop_data; 1506 struct drm_device *drm_dev = data; 1507 struct vop *vop; 1508 struct resource *res; 1509 size_t alloc_size; 1510 int ret, irq; 1511 1512 vop_data = of_device_get_match_data(dev); 1513 if (!vop_data) 1514 return -ENODEV; 1515 1516 /* Allocate vop struct and its vop_win array */ 1517 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1518 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1519 if (!vop) 1520 return -ENOMEM; 1521 1522 vop->dev = dev; 1523 vop->data = vop_data; 1524 vop->drm_dev = drm_dev; 1525 dev_set_drvdata(dev, vop); 1526 1527 vop_win_init(vop); 1528 1529 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1530 vop->len = resource_size(res); 1531 vop->regs = devm_ioremap_resource(dev, res); 1532 if (IS_ERR(vop->regs)) 1533 return PTR_ERR(vop->regs); 1534 1535 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1536 if (!vop->regsbak) 1537 return -ENOMEM; 1538 1539 irq = platform_get_irq(pdev, 0); 1540 if (irq < 0) { 1541 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1542 return irq; 1543 } 1544 vop->irq = (unsigned int)irq; 1545 1546 spin_lock_init(&vop->reg_lock); 1547 spin_lock_init(&vop->irq_lock); 1548 1549 ret = devm_request_irq(dev, vop->irq, vop_isr, 1550 IRQF_SHARED, dev_name(dev), vop); 1551 if (ret) 1552 return ret; 1553 1554 /* IRQ is initially disabled; it gets enabled in power_on */ 1555 disable_irq(vop->irq); 1556 1557 ret = vop_create_crtc(vop); 1558 if (ret) 1559 goto err_enable_irq; 1560 1561 pm_runtime_enable(&pdev->dev); 1562 1563 ret = vop_initial(vop); 1564 if (ret < 0) { 1565 DRM_DEV_ERROR(&pdev->dev, 1566 "cannot initial vop dev - err %d\n", ret); 1567 goto err_disable_pm_runtime; 1568 } 1569 1570 return 0; 1571 1572 err_disable_pm_runtime: 1573 pm_runtime_disable(&pdev->dev); 1574 vop_destroy_crtc(vop); 1575 err_enable_irq: 1576 enable_irq(vop->irq); /* To balance out the disable_irq above */ 1577 return ret; 1578 } 1579 1580 static void vop_unbind(struct device *dev, struct device *master, void *data) 1581 { 1582 struct vop *vop = dev_get_drvdata(dev); 1583 1584 pm_runtime_disable(dev); 1585 vop_destroy_crtc(vop); 1586 1587 clk_unprepare(vop->aclk); 1588 clk_unprepare(vop->hclk); 1589 clk_unprepare(vop->dclk); 1590 } 1591 1592 const struct component_ops vop_component_ops = { 1593 .bind = vop_bind, 1594 .unbind = vop_unbind, 1595 }; 1596 EXPORT_SYMBOL_GPL(vop_component_ops); 1597