12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 202048e328SMark Yao #include <drm/drm_plane_helper.h> 212048e328SMark Yao 222048e328SMark Yao #include <linux/kernel.h> 2300fe6148SPaul Gortmaker #include <linux/module.h> 242048e328SMark Yao #include <linux/platform_device.h> 252048e328SMark Yao #include <linux/clk.h> 262048e328SMark Yao #include <linux/of.h> 272048e328SMark Yao #include <linux/of_device.h> 282048e328SMark Yao #include <linux/pm_runtime.h> 292048e328SMark Yao #include <linux/component.h> 302048e328SMark Yao 312048e328SMark Yao #include <linux/reset.h> 322048e328SMark Yao #include <linux/delay.h> 332048e328SMark Yao 342048e328SMark Yao #include "rockchip_drm_drv.h" 352048e328SMark Yao #include "rockchip_drm_gem.h" 362048e328SMark Yao #include "rockchip_drm_fb.h" 375182c1a5SYakir Yang #include "rockchip_drm_psr.h" 382048e328SMark Yao #include "rockchip_drm_vop.h" 392048e328SMark Yao 40d49463ecSMark Yao #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ 41d49463ecSMark Yao vop_mask_write(x, off, mask, shift, v, write_mask, true) 42d49463ecSMark Yao 43d49463ecSMark Yao #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ 44d49463ecSMark Yao vop_mask_write(x, off, mask, shift, v, write_mask, false) 452048e328SMark Yao 462048e328SMark Yao #define REG_SET(x, base, reg, v, mode) \ 47d49463ecSMark Yao __REG_SET_##mode(x, base + reg.offset, \ 48d49463ecSMark Yao reg.mask, reg.shift, v, reg.write_mask) 49c7647f86SJohn Keeping #define REG_SET_MASK(x, base, reg, mask, v, mode) \ 50d49463ecSMark Yao __REG_SET_##mode(x, base + reg.offset, \ 51d49463ecSMark Yao mask, reg.shift, v, reg.write_mask) 522048e328SMark Yao 532048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 542048e328SMark Yao REG_SET(x, win->base, win->phy->name, v, RELAXED) 554c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 564c156c21SMark Yao REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 571194fffbSMark Yao #define VOP_SCL_SET_EXT(x, win, name, v) \ 581194fffbSMark Yao REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) 592048e328SMark Yao #define VOP_CTRL_SET(x, name, v) \ 602048e328SMark Yao REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 612048e328SMark Yao 62dbb3d944SMark Yao #define VOP_INTR_GET(vop, name) \ 63dbb3d944SMark Yao vop_read_reg(vop, 0, &vop->data->ctrl->name) 64dbb3d944SMark Yao 65c7647f86SJohn Keeping #define VOP_INTR_SET(vop, name, mask, v) \ 66c7647f86SJohn Keeping REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) 67dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 68dbb3d944SMark Yao do { \ 69c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 70dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 71c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 72dbb3d944SMark Yao reg |= (v) << i; \ 73c7647f86SJohn Keeping mask |= 1 << i; \ 74dbb3d944SMark Yao } \ 75c7647f86SJohn Keeping } \ 76c7647f86SJohn Keeping VOP_INTR_SET(vop, name, mask, reg); \ 77dbb3d944SMark Yao } while (0) 78dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 79dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 80dbb3d944SMark Yao 812048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 822048e328SMark Yao vop_read_reg(x, win->base, &win->phy->name) 832048e328SMark Yao 842048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 852048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 862048e328SMark Yao 872048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 882048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 8963ebb9faSMark Yao #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) 902048e328SMark Yao 9163ebb9faSMark Yao struct vop_plane_state { 9263ebb9faSMark Yao struct drm_plane_state base; 9363ebb9faSMark Yao int format; 942048e328SMark Yao dma_addr_t yrgb_mst; 9563ebb9faSMark Yao bool enable; 962048e328SMark Yao }; 972048e328SMark Yao 982048e328SMark Yao struct vop_win { 992048e328SMark Yao struct drm_plane base; 1002048e328SMark Yao const struct vop_win_data *data; 1012048e328SMark Yao struct vop *vop; 1022048e328SMark Yao 1034f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 1044f9d39a7SDaniel Vetter bool enable; 1054f9d39a7SDaniel Vetter dma_addr_t yrgb_mst; 1062048e328SMark Yao }; 1072048e328SMark Yao 1082048e328SMark Yao struct vop { 1092048e328SMark Yao struct drm_crtc crtc; 1102048e328SMark Yao struct device *dev; 1112048e328SMark Yao struct drm_device *drm_dev; 11231e980c5SMark Yao bool is_enabled; 1135b680403SSean Paul bool vblank_active; 1142048e328SMark Yao 1152048e328SMark Yao /* mutex vsync_ work */ 1162048e328SMark Yao struct mutex vsync_mutex; 1172048e328SMark Yao bool vsync_work_pending; 1181067219bSMark Yao struct completion dsp_hold_completion; 11963ebb9faSMark Yao struct completion wait_update_complete; 1204f9d39a7SDaniel Vetter 1214f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 12263ebb9faSMark Yao struct drm_pending_vblank_event *event; 1232048e328SMark Yao 12469c34e41SYakir Yang struct completion line_flag_completion; 12569c34e41SYakir Yang 1262048e328SMark Yao const struct vop_data *data; 1272048e328SMark Yao 1282048e328SMark Yao uint32_t *regsbak; 1292048e328SMark Yao void __iomem *regs; 1302048e328SMark Yao 1312048e328SMark Yao /* physical map length of vop register */ 1322048e328SMark Yao uint32_t len; 1332048e328SMark Yao 1342048e328SMark Yao /* one time only one process allowed to config the register */ 1352048e328SMark Yao spinlock_t reg_lock; 1362048e328SMark Yao /* lock vop irq reg */ 1372048e328SMark Yao spinlock_t irq_lock; 1382048e328SMark Yao 1392048e328SMark Yao unsigned int irq; 1402048e328SMark Yao 1412048e328SMark Yao /* vop AHP clk */ 1422048e328SMark Yao struct clk *hclk; 1432048e328SMark Yao /* vop dclk */ 1442048e328SMark Yao struct clk *dclk; 1452048e328SMark Yao /* vop share memory frequency */ 1462048e328SMark Yao struct clk *aclk; 1472048e328SMark Yao 1482048e328SMark Yao /* vop dclk reset */ 1492048e328SMark Yao struct reset_control *dclk_rst; 1502048e328SMark Yao 1512048e328SMark Yao struct vop_win win[]; 1522048e328SMark Yao }; 1532048e328SMark Yao 1542048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1552048e328SMark Yao { 1562048e328SMark Yao writel(v, vop->regs + offset); 1572048e328SMark Yao vop->regsbak[offset >> 2] = v; 1582048e328SMark Yao } 1592048e328SMark Yao 1602048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1612048e328SMark Yao { 1622048e328SMark Yao return readl(vop->regs + offset); 1632048e328SMark Yao } 1642048e328SMark Yao 1652048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1662048e328SMark Yao const struct vop_reg *reg) 1672048e328SMark Yao { 1682048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1692048e328SMark Yao } 1702048e328SMark Yao 1712048e328SMark Yao static inline void vop_mask_write(struct vop *vop, uint32_t offset, 172d49463ecSMark Yao uint32_t mask, uint32_t shift, uint32_t v, 173d49463ecSMark Yao bool write_mask, bool relaxed) 1742048e328SMark Yao { 175d49463ecSMark Yao if (!mask) 176d49463ecSMark Yao return; 177d49463ecSMark Yao 178d49463ecSMark Yao if (write_mask) { 179d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 180d49463ecSMark Yao } else { 1812048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1822048e328SMark Yao 183d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 184d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 1852048e328SMark Yao } 1862048e328SMark Yao 187d49463ecSMark Yao if (relaxed) 188d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 189d49463ecSMark Yao else 190d49463ecSMark Yao writel(v, vop->regs + offset); 1912048e328SMark Yao } 1922048e328SMark Yao 193dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 194dbb3d944SMark Yao const struct vop_reg *reg, int type) 195dbb3d944SMark Yao { 196dbb3d944SMark Yao uint32_t i, ret = 0; 197dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 198dbb3d944SMark Yao 199dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 200dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 201dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 202dbb3d944SMark Yao } 203dbb3d944SMark Yao 204dbb3d944SMark Yao return ret; 205dbb3d944SMark Yao } 206dbb3d944SMark Yao 2070cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2080cf33fe3SMark Yao { 2090cf33fe3SMark Yao VOP_CTRL_SET(vop, cfg_done, 1); 2100cf33fe3SMark Yao } 2110cf33fe3SMark Yao 21285a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 21385a359f2STomasz Figa { 21485a359f2STomasz Figa switch (format) { 21585a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 21685a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 21785a359f2STomasz Figa case DRM_FORMAT_BGR888: 21885a359f2STomasz Figa case DRM_FORMAT_BGR565: 21985a359f2STomasz Figa return true; 22085a359f2STomasz Figa default: 22185a359f2STomasz Figa return false; 22285a359f2STomasz Figa } 22385a359f2STomasz Figa } 22485a359f2STomasz Figa 2252048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2262048e328SMark Yao { 2272048e328SMark Yao switch (format) { 2282048e328SMark Yao case DRM_FORMAT_XRGB8888: 2292048e328SMark Yao case DRM_FORMAT_ARGB8888: 23085a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 23185a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2322048e328SMark Yao return VOP_FMT_ARGB8888; 2332048e328SMark Yao case DRM_FORMAT_RGB888: 23485a359f2STomasz Figa case DRM_FORMAT_BGR888: 2352048e328SMark Yao return VOP_FMT_RGB888; 2362048e328SMark Yao case DRM_FORMAT_RGB565: 23785a359f2STomasz Figa case DRM_FORMAT_BGR565: 2382048e328SMark Yao return VOP_FMT_RGB565; 2392048e328SMark Yao case DRM_FORMAT_NV12: 2402048e328SMark Yao return VOP_FMT_YUV420SP; 2412048e328SMark Yao case DRM_FORMAT_NV16: 2422048e328SMark Yao return VOP_FMT_YUV422SP; 2432048e328SMark Yao case DRM_FORMAT_NV24: 2442048e328SMark Yao return VOP_FMT_YUV444SP; 2452048e328SMark Yao default: 246ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2472048e328SMark Yao return -EINVAL; 2482048e328SMark Yao } 2492048e328SMark Yao } 2502048e328SMark Yao 25184c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 25284c7f8caSMark Yao { 25384c7f8caSMark Yao switch (format) { 25484c7f8caSMark Yao case DRM_FORMAT_NV12: 25584c7f8caSMark Yao case DRM_FORMAT_NV16: 25684c7f8caSMark Yao case DRM_FORMAT_NV24: 25784c7f8caSMark Yao return true; 25884c7f8caSMark Yao default: 25984c7f8caSMark Yao return false; 26084c7f8caSMark Yao } 26184c7f8caSMark Yao } 26284c7f8caSMark Yao 2632048e328SMark Yao static bool is_alpha_support(uint32_t format) 2642048e328SMark Yao { 2652048e328SMark Yao switch (format) { 2662048e328SMark Yao case DRM_FORMAT_ARGB8888: 26785a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2682048e328SMark Yao return true; 2692048e328SMark Yao default: 2702048e328SMark Yao return false; 2712048e328SMark Yao } 2722048e328SMark Yao } 2732048e328SMark Yao 2744c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2754c156c21SMark Yao uint32_t dst, bool is_horizontal, 2764c156c21SMark Yao int vsu_mode, int *vskiplines) 2774c156c21SMark Yao { 2784c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2794c156c21SMark Yao 2804c156c21SMark Yao if (is_horizontal) { 2814c156c21SMark Yao if (mode == SCALE_UP) 2824c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2834c156c21SMark Yao else if (mode == SCALE_DOWN) 2844c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2854c156c21SMark Yao } else { 2864c156c21SMark Yao if (mode == SCALE_UP) { 2874c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2884c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2894c156c21SMark Yao else 2904c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2914c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2924c156c21SMark Yao if (vskiplines) { 2934c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 2944c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 2954c156c21SMark Yao *vskiplines); 2964c156c21SMark Yao } else { 2974c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2984c156c21SMark Yao } 2994c156c21SMark Yao } 3004c156c21SMark Yao } 3014c156c21SMark Yao 3024c156c21SMark Yao return val; 3034c156c21SMark Yao } 3044c156c21SMark Yao 3054c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3064c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3074c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 3084c156c21SMark Yao { 3094c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3104c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3114c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 3124c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 3134c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 3144c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 3154c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 3164c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 3174c156c21SMark Yao uint16_t vsu_mode; 3184c156c21SMark Yao uint16_t lb_mode; 3194c156c21SMark Yao uint32_t val; 3202db00cf5SMark Yao int vskiplines = 0; 3214c156c21SMark Yao 3224c156c21SMark Yao if (dst_w > 3840) { 323ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3244c156c21SMark Yao return; 3254c156c21SMark Yao } 3264c156c21SMark Yao 3271194fffbSMark Yao if (!win->phy->scl->ext) { 3281194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3291194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3301194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3311194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3321194fffbSMark Yao if (is_yuv) { 3331194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 334ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3351194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 336ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3371194fffbSMark Yao } 3381194fffbSMark Yao return; 3391194fffbSMark Yao } 3401194fffbSMark Yao 3414c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3424c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3434c156c21SMark Yao 3444c156c21SMark Yao if (is_yuv) { 3454c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3464c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3474c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3484c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3494c156c21SMark Yao else 3504c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3514c156c21SMark Yao } else { 3524c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3534c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3544c156c21SMark Yao else 3554c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3564c156c21SMark Yao } 3574c156c21SMark Yao 3581194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3594c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3604c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 361ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3624c156c21SMark Yao return; 3634c156c21SMark Yao } 3644c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 365ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3664c156c21SMark Yao return; 3674c156c21SMark Yao } 3684c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3694c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3704c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3714c156c21SMark Yao } else { 3724c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3734c156c21SMark Yao } 3744c156c21SMark Yao 3754c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3764c156c21SMark Yao true, 0, NULL); 3774c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3784c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3794c156c21SMark Yao false, vsu_mode, &vskiplines); 3804c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3814c156c21SMark Yao 3821194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3831194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3844c156c21SMark Yao 3851194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3861194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3871194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3881194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3891194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3904c156c21SMark Yao if (is_yuv) { 3914c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3924c156c21SMark Yao dst_w, true, 0, NULL); 3934c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 3944c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 3954c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 3964c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 3974c156c21SMark Yao 3981194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 3991194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4001194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4011194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4021194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4031194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4041194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4054c156c21SMark Yao } 4064c156c21SMark Yao } 4074c156c21SMark Yao 4081067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4091067219bSMark Yao { 4101067219bSMark Yao unsigned long flags; 4111067219bSMark Yao 4121067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4131067219bSMark Yao return; 4141067219bSMark Yao 4151067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4161067219bSMark Yao 417fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 418dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4191067219bSMark Yao 4201067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4211067219bSMark Yao } 4221067219bSMark Yao 4231067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4241067219bSMark Yao { 4251067219bSMark Yao unsigned long flags; 4261067219bSMark Yao 4271067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4281067219bSMark Yao return; 4291067219bSMark Yao 4301067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4311067219bSMark Yao 432dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4331067219bSMark Yao 4341067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4351067219bSMark Yao } 4361067219bSMark Yao 43769c34e41SYakir Yang /* 43869c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 43969c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 44069c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 44169c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 44269c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 44369c34e41SYakir Yang * 44469c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 44569c34e41SYakir Yang * Interrupts 44669c34e41SYakir Yang * LINE_FLAG -------------------------------+ 44769c34e41SYakir Yang * FRAME_SYNC ----+ | 44869c34e41SYakir Yang * | | 44969c34e41SYakir Yang * v v 45069c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 45169c34e41SYakir Yang * ^ ^ ^ ^ 45269c34e41SYakir Yang * | | | | 45369c34e41SYakir Yang * | | | | 45469c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 45569c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 45669c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 45769c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 45869c34e41SYakir Yang */ 45969c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 46069c34e41SYakir Yang { 46169c34e41SYakir Yang uint32_t line_flag_irq; 46269c34e41SYakir Yang unsigned long flags; 46369c34e41SYakir Yang 46469c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 46569c34e41SYakir Yang 46669c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 46769c34e41SYakir Yang 46869c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 46969c34e41SYakir Yang 47069c34e41SYakir Yang return !!line_flag_irq; 47169c34e41SYakir Yang } 47269c34e41SYakir Yang 47369c34e41SYakir Yang static void vop_line_flag_irq_enable(struct vop *vop, int line_num) 47469c34e41SYakir Yang { 47569c34e41SYakir Yang unsigned long flags; 47669c34e41SYakir Yang 47769c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 47869c34e41SYakir Yang return; 47969c34e41SYakir Yang 48069c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 48169c34e41SYakir Yang 48269c34e41SYakir Yang VOP_CTRL_SET(vop, line_flag_num[0], line_num); 483fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 48469c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 48569c34e41SYakir Yang 48669c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 48769c34e41SYakir Yang } 48869c34e41SYakir Yang 48969c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 49069c34e41SYakir Yang { 49169c34e41SYakir Yang unsigned long flags; 49269c34e41SYakir Yang 49369c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 49469c34e41SYakir Yang return; 49569c34e41SYakir Yang 49669c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 49769c34e41SYakir Yang 49869c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 49969c34e41SYakir Yang 50069c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 50169c34e41SYakir Yang } 50269c34e41SYakir Yang 50339a9ad8fSSean Paul static int vop_enable(struct drm_crtc *crtc) 5042048e328SMark Yao { 5052048e328SMark Yao struct vop *vop = to_vop(crtc); 5062048e328SMark Yao int ret; 5072048e328SMark Yao 5085d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5095d82d1a7SMark Yao if (ret < 0) { 5105d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 51139a9ad8fSSean Paul goto err_put_pm_runtime; 5125d82d1a7SMark Yao } 5135d82d1a7SMark Yao 5142048e328SMark Yao ret = clk_enable(vop->hclk); 51539a9ad8fSSean Paul if (WARN_ON(ret < 0)) 51639a9ad8fSSean Paul goto err_put_pm_runtime; 5172048e328SMark Yao 5182048e328SMark Yao ret = clk_enable(vop->dclk); 51939a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5202048e328SMark Yao goto err_disable_hclk; 5212048e328SMark Yao 5222048e328SMark Yao ret = clk_enable(vop->aclk); 52339a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5242048e328SMark Yao goto err_disable_dclk; 5252048e328SMark Yao 5262048e328SMark Yao /* 5272048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5282048e328SMark Yao * automatically with this master device via common driver code. 5292048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5302048e328SMark Yao * mapping. 5312048e328SMark Yao */ 5322048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5332048e328SMark Yao if (ret) { 5342048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 5352048e328SMark Yao goto err_disable_aclk; 5362048e328SMark Yao } 5372048e328SMark Yao 53877faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 53952ab7891SMark Yao /* 54052ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 54152ab7891SMark Yao */ 54252ab7891SMark Yao vop->is_enabled = true; 54352ab7891SMark Yao 5442048e328SMark Yao spin_lock(&vop->reg_lock); 5452048e328SMark Yao 5462048e328SMark Yao VOP_CTRL_SET(vop, standby, 0); 5472048e328SMark Yao 5482048e328SMark Yao spin_unlock(&vop->reg_lock); 5492048e328SMark Yao 5502048e328SMark Yao enable_irq(vop->irq); 5512048e328SMark Yao 552b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 5532048e328SMark Yao 55439a9ad8fSSean Paul return 0; 5552048e328SMark Yao 5562048e328SMark Yao err_disable_aclk: 5572048e328SMark Yao clk_disable(vop->aclk); 5582048e328SMark Yao err_disable_dclk: 5592048e328SMark Yao clk_disable(vop->dclk); 5602048e328SMark Yao err_disable_hclk: 5612048e328SMark Yao clk_disable(vop->hclk); 56239a9ad8fSSean Paul err_put_pm_runtime: 56339a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 56439a9ad8fSSean Paul return ret; 5652048e328SMark Yao } 5662048e328SMark Yao 5670ad3675dSMark Yao static void vop_crtc_disable(struct drm_crtc *crtc) 5682048e328SMark Yao { 5692048e328SMark Yao struct vop *vop = to_vop(crtc); 5703ed6c649STomeu Vizoso int i; 5712048e328SMark Yao 572893b6cadSDaniel Vetter WARN_ON(vop->event); 573893b6cadSDaniel Vetter 574b883c9baSSean Paul rockchip_drm_psr_deactivate(&vop->crtc); 575b883c9baSSean Paul 5763ed6c649STomeu Vizoso /* 5773ed6c649STomeu Vizoso * We need to make sure that all windows are disabled before we 5783ed6c649STomeu Vizoso * disable that crtc. Otherwise we might try to scan from a destroyed 5793ed6c649STomeu Vizoso * buffer later. 5803ed6c649STomeu Vizoso */ 5813ed6c649STomeu Vizoso for (i = 0; i < vop->data->win_size; i++) { 5823ed6c649STomeu Vizoso struct vop_win *vop_win = &vop->win[i]; 5833ed6c649STomeu Vizoso const struct vop_win_data *win = vop_win->data; 5843ed6c649STomeu Vizoso 5853ed6c649STomeu Vizoso spin_lock(&vop->reg_lock); 5863ed6c649STomeu Vizoso VOP_WIN_SET(vop, win, enable, 0); 5873ed6c649STomeu Vizoso spin_unlock(&vop->reg_lock); 5883ed6c649STomeu Vizoso } 5893ed6c649STomeu Vizoso 590b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 5912048e328SMark Yao 5922048e328SMark Yao /* 5931067219bSMark Yao * Vop standby will take effect at end of current frame, 5941067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5951067219bSMark Yao * 5961067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5971067219bSMark Yao * if not, memory bus maybe dead. 5982048e328SMark Yao */ 5991067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 6001067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 6011067219bSMark Yao 6022048e328SMark Yao spin_lock(&vop->reg_lock); 6032048e328SMark Yao 6042048e328SMark Yao VOP_CTRL_SET(vop, standby, 1); 6052048e328SMark Yao 6062048e328SMark Yao spin_unlock(&vop->reg_lock); 60752ab7891SMark Yao 6081067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 6092048e328SMark Yao 6101067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6111067219bSMark Yao 6121067219bSMark Yao disable_irq(vop->irq); 6131067219bSMark Yao 6141067219bSMark Yao vop->is_enabled = false; 6151067219bSMark Yao 6161067219bSMark Yao /* 6171067219bSMark Yao * vop standby complete, so iommu detach is safe. 6181067219bSMark Yao */ 6192048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6202048e328SMark Yao 6211067219bSMark Yao clk_disable(vop->dclk); 6222048e328SMark Yao clk_disable(vop->aclk); 6232048e328SMark Yao clk_disable(vop->hclk); 6245d82d1a7SMark Yao pm_runtime_put(vop->dev); 625893b6cadSDaniel Vetter 626893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 627893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 628893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 629893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 630893b6cadSDaniel Vetter 631893b6cadSDaniel Vetter crtc->state->event = NULL; 632893b6cadSDaniel Vetter } 6332048e328SMark Yao } 6342048e328SMark Yao 63563ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 6362048e328SMark Yao { 63763ebb9faSMark Yao drm_plane_cleanup(plane); 6382048e328SMark Yao } 6392048e328SMark Yao 64044d0237aSMark Yao static int vop_plane_prepare_fb(struct drm_plane *plane, 6411832040dSChris Wilson struct drm_plane_state *new_state) 64244d0237aSMark Yao { 64344d0237aSMark Yao if (plane->state->fb) 64444d0237aSMark Yao drm_framebuffer_reference(plane->state->fb); 64544d0237aSMark Yao 64644d0237aSMark Yao return 0; 64744d0237aSMark Yao } 64844d0237aSMark Yao 64944d0237aSMark Yao static void vop_plane_cleanup_fb(struct drm_plane *plane, 6501832040dSChris Wilson struct drm_plane_state *old_state) 65144d0237aSMark Yao { 65244d0237aSMark Yao if (old_state->fb) 65344d0237aSMark Yao drm_framebuffer_unreference(old_state->fb); 65444d0237aSMark Yao } 65544d0237aSMark Yao 65663ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 65763ebb9faSMark Yao struct drm_plane_state *state) 6582048e328SMark Yao { 65963ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 66092915da6SJohn Keeping struct drm_crtc_state *crtc_state; 66163ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 6622048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 66363ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 6642048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6652048e328SMark Yao int ret; 66663ebb9faSMark Yao struct drm_rect clip; 6674c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 6684c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6694c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 6704c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6712048e328SMark Yao 67263ebb9faSMark Yao if (!crtc || !fb) 67363ebb9faSMark Yao goto out_disable; 67492915da6SJohn Keeping 67592915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 67692915da6SJohn Keeping if (WARN_ON(!crtc_state)) 67792915da6SJohn Keeping return -EINVAL; 67892915da6SJohn Keeping 67963ebb9faSMark Yao clip.x1 = 0; 68063ebb9faSMark Yao clip.y1 = 0; 68192915da6SJohn Keeping clip.x2 = crtc_state->adjusted_mode.hdisplay; 68292915da6SJohn Keeping clip.y2 = crtc_state->adjusted_mode.vdisplay; 68363ebb9faSMark Yao 684f9b96be0SVille Syrjälä ret = drm_plane_helper_check_state(state, &clip, 685f9b96be0SVille Syrjälä min_scale, max_scale, 686f9b96be0SVille Syrjälä true, true); 6872048e328SMark Yao if (ret) 6882048e328SMark Yao return ret; 6892048e328SMark Yao 690f9b96be0SVille Syrjälä if (!state->visible) 69163ebb9faSMark Yao goto out_disable; 6922048e328SMark Yao 69363ebb9faSMark Yao vop_plane_state->format = vop_convert_format(fb->pixel_format); 69463ebb9faSMark Yao if (vop_plane_state->format < 0) 69563ebb9faSMark Yao return vop_plane_state->format; 69684c7f8caSMark Yao 69784c7f8caSMark Yao /* 69884c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 69984c7f8caSMark Yao * need align with 2 pixel. 70084c7f8caSMark Yao */ 701f9b96be0SVille Syrjälä if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2)) 70263ebb9faSMark Yao return -EINVAL; 70363ebb9faSMark Yao 70463ebb9faSMark Yao vop_plane_state->enable = true; 70563ebb9faSMark Yao 70663ebb9faSMark Yao return 0; 70763ebb9faSMark Yao 70863ebb9faSMark Yao out_disable: 70963ebb9faSMark Yao vop_plane_state->enable = false; 71063ebb9faSMark Yao return 0; 71184c7f8caSMark Yao } 71284c7f8caSMark Yao 71363ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 71463ebb9faSMark Yao struct drm_plane_state *old_state) 71563ebb9faSMark Yao { 71663ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); 71763ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 71863ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 71963ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 7202048e328SMark Yao 72163ebb9faSMark Yao if (!old_state->crtc) 72263ebb9faSMark Yao return; 7232048e328SMark Yao 7244f9d39a7SDaniel Vetter spin_lock_irq(&plane->dev->event_lock); 7254f9d39a7SDaniel Vetter vop_win->enable = false; 7264f9d39a7SDaniel Vetter vop_win->yrgb_mst = 0; 7274f9d39a7SDaniel Vetter spin_unlock_irq(&plane->dev->event_lock); 7284f9d39a7SDaniel Vetter 72963ebb9faSMark Yao spin_lock(&vop->reg_lock); 7302048e328SMark Yao 73163ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 7322048e328SMark Yao 73363ebb9faSMark Yao spin_unlock(&vop->reg_lock); 73463ebb9faSMark Yao 73563ebb9faSMark Yao vop_plane_state->enable = false; 73663ebb9faSMark Yao } 73763ebb9faSMark Yao 73863ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 73963ebb9faSMark Yao struct drm_plane_state *old_state) 74063ebb9faSMark Yao { 74163ebb9faSMark Yao struct drm_plane_state *state = plane->state; 74263ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 74363ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 74463ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 74563ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 74663ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 74763ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 74863ebb9faSMark Yao unsigned int actual_w, actual_h; 74963ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 75063ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 751ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 752ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 75363ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 75463ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 75563ebb9faSMark Yao unsigned long offset; 75663ebb9faSMark Yao dma_addr_t dma_addr; 75763ebb9faSMark Yao uint32_t val; 75863ebb9faSMark Yao bool rb_swap; 75963ebb9faSMark Yao 76063ebb9faSMark Yao /* 76163ebb9faSMark Yao * can't update plane when vop is disabled. 76263ebb9faSMark Yao */ 7634f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 76463ebb9faSMark Yao return; 76563ebb9faSMark Yao 76663ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 76763ebb9faSMark Yao return; 76863ebb9faSMark Yao 76963ebb9faSMark Yao if (!vop_plane_state->enable) { 77063ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 77163ebb9faSMark Yao return; 77263ebb9faSMark Yao } 77363ebb9faSMark Yao 77463ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 77563ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 77663ebb9faSMark Yao 77763ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 77863ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 77963ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 78063ebb9faSMark Yao 78163ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 78263ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 78363ebb9faSMark Yao 78463ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 78563ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 78663ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 78763ebb9faSMark Yao 78863ebb9faSMark Yao offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 78963ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 79063ebb9faSMark Yao vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 79163ebb9faSMark Yao 7924f9d39a7SDaniel Vetter spin_lock_irq(&plane->dev->event_lock); 7934f9d39a7SDaniel Vetter vop_win->enable = true; 7944f9d39a7SDaniel Vetter vop_win->yrgb_mst = vop_plane_state->yrgb_mst; 7954f9d39a7SDaniel Vetter spin_unlock_irq(&plane->dev->event_lock); 7964f9d39a7SDaniel Vetter 79763ebb9faSMark Yao spin_lock(&vop->reg_lock); 79863ebb9faSMark Yao 79963ebb9faSMark Yao VOP_WIN_SET(vop, win, format, vop_plane_state->format); 80063ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 80163ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); 80263ebb9faSMark Yao if (is_yuv_support(fb->pixel_format)) { 80384c7f8caSMark Yao int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 80484c7f8caSMark Yao int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 80584c7f8caSMark Yao int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 80684c7f8caSMark Yao 80784c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 80884c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 80984c7f8caSMark Yao 81063ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 81163ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 81284c7f8caSMark Yao 81363ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 81463ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 81563ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 81684c7f8caSMark Yao } 8174c156c21SMark Yao 8184c156c21SMark Yao if (win->phy->scl) 8194c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 82063ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 8214c156c21SMark Yao fb->pixel_format); 8224c156c21SMark Yao 82363ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 82463ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 82563ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 8264c156c21SMark Yao 82763ebb9faSMark Yao rb_swap = has_rb_swapped(fb->pixel_format); 82885a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 8292048e328SMark Yao 83063ebb9faSMark Yao if (is_alpha_support(fb->pixel_format)) { 8312048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 8322048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 8332048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 8342048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 8352048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 8362048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 8372048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 8382048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 8392048e328SMark Yao } else { 8402048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 8412048e328SMark Yao } 8422048e328SMark Yao 8432048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 8442048e328SMark Yao spin_unlock(&vop->reg_lock); 8452048e328SMark Yao } 8462048e328SMark Yao 84763ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 84844d0237aSMark Yao .prepare_fb = vop_plane_prepare_fb, 84944d0237aSMark Yao .cleanup_fb = vop_plane_cleanup_fb, 85063ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 85163ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 85263ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 85363ebb9faSMark Yao }; 85463ebb9faSMark Yao 8558ff490aeSJohn Keeping static void vop_atomic_plane_reset(struct drm_plane *plane) 8562048e328SMark Yao { 85763ebb9faSMark Yao struct vop_plane_state *vop_plane_state = 85863ebb9faSMark Yao to_vop_plane_state(plane->state); 85963ebb9faSMark Yao 86063ebb9faSMark Yao if (plane->state && plane->state->fb) 86163ebb9faSMark Yao drm_framebuffer_unreference(plane->state->fb); 86263ebb9faSMark Yao 86363ebb9faSMark Yao kfree(vop_plane_state); 86463ebb9faSMark Yao vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); 86563ebb9faSMark Yao if (!vop_plane_state) 86663ebb9faSMark Yao return; 86763ebb9faSMark Yao 86863ebb9faSMark Yao plane->state = &vop_plane_state->base; 86963ebb9faSMark Yao plane->state->plane = plane; 8702048e328SMark Yao } 8712048e328SMark Yao 8728ff490aeSJohn Keeping static struct drm_plane_state * 87363ebb9faSMark Yao vop_atomic_plane_duplicate_state(struct drm_plane *plane) 8742048e328SMark Yao { 87563ebb9faSMark Yao struct vop_plane_state *old_vop_plane_state; 87663ebb9faSMark Yao struct vop_plane_state *vop_plane_state; 8772048e328SMark Yao 87863ebb9faSMark Yao if (WARN_ON(!plane->state)) 87963ebb9faSMark Yao return NULL; 8802048e328SMark Yao 88163ebb9faSMark Yao old_vop_plane_state = to_vop_plane_state(plane->state); 88263ebb9faSMark Yao vop_plane_state = kmemdup(old_vop_plane_state, 88363ebb9faSMark Yao sizeof(*vop_plane_state), GFP_KERNEL); 88463ebb9faSMark Yao if (!vop_plane_state) 88563ebb9faSMark Yao return NULL; 88663ebb9faSMark Yao 88763ebb9faSMark Yao __drm_atomic_helper_plane_duplicate_state(plane, 88863ebb9faSMark Yao &vop_plane_state->base); 88963ebb9faSMark Yao 89063ebb9faSMark Yao return &vop_plane_state->base; 8912048e328SMark Yao } 8922048e328SMark Yao 89363ebb9faSMark Yao static void vop_atomic_plane_destroy_state(struct drm_plane *plane, 89463ebb9faSMark Yao struct drm_plane_state *state) 8952048e328SMark Yao { 89663ebb9faSMark Yao struct vop_plane_state *vop_state = to_vop_plane_state(state); 8972048e328SMark Yao 8982f701695SDaniel Vetter __drm_atomic_helper_plane_destroy_state(state); 8992048e328SMark Yao 90063ebb9faSMark Yao kfree(vop_state); 9012048e328SMark Yao } 9022048e328SMark Yao 9032048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 90463ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 90563ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 9062048e328SMark Yao .destroy = vop_plane_destroy, 90763ebb9faSMark Yao .reset = vop_atomic_plane_reset, 90863ebb9faSMark Yao .atomic_duplicate_state = vop_atomic_plane_duplicate_state, 90963ebb9faSMark Yao .atomic_destroy_state = vop_atomic_plane_destroy_state, 9102048e328SMark Yao }; 9112048e328SMark Yao 9122048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 9132048e328SMark Yao { 9142048e328SMark Yao struct vop *vop = to_vop(crtc); 9152048e328SMark Yao unsigned long flags; 9162048e328SMark Yao 91763ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 9182048e328SMark Yao return -EPERM; 9192048e328SMark Yao 9202048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 9212048e328SMark Yao 922fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 923dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 9242048e328SMark Yao 9252048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 9262048e328SMark Yao 9272048e328SMark Yao return 0; 9282048e328SMark Yao } 9292048e328SMark Yao 9302048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 9312048e328SMark Yao { 9322048e328SMark Yao struct vop *vop = to_vop(crtc); 9332048e328SMark Yao unsigned long flags; 9342048e328SMark Yao 93563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 9362048e328SMark Yao return; 93731e980c5SMark Yao 9382048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 939dbb3d944SMark Yao 940dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 941dbb3d944SMark Yao 9422048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 9432048e328SMark Yao } 9442048e328SMark Yao 94563ebb9faSMark Yao static void vop_crtc_wait_for_update(struct drm_crtc *crtc) 94663ebb9faSMark Yao { 94763ebb9faSMark Yao struct vop *vop = to_vop(crtc); 94863ebb9faSMark Yao 94963ebb9faSMark Yao reinit_completion(&vop->wait_update_complete); 95063ebb9faSMark Yao WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); 95163ebb9faSMark Yao } 95263ebb9faSMark Yao 9532048e328SMark Yao static const struct rockchip_crtc_funcs private_crtc_funcs = { 9542048e328SMark Yao .enable_vblank = vop_crtc_enable_vblank, 9552048e328SMark Yao .disable_vblank = vop_crtc_disable_vblank, 95663ebb9faSMark Yao .wait_for_update = vop_crtc_wait_for_update, 9572048e328SMark Yao }; 9582048e328SMark Yao 9592048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 9602048e328SMark Yao const struct drm_display_mode *mode, 9612048e328SMark Yao struct drm_display_mode *adjusted_mode) 9622048e328SMark Yao { 963b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 964b59b8de3SChris Zhong 965b59b8de3SChris Zhong adjusted_mode->clock = 966b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 967b59b8de3SChris Zhong 9682048e328SMark Yao return true; 9692048e328SMark Yao } 9702048e328SMark Yao 97163ebb9faSMark Yao static void vop_crtc_enable(struct drm_crtc *crtc) 9722048e328SMark Yao { 9732048e328SMark Yao struct vop *vop = to_vop(crtc); 9744e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 97563ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 9762048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 9772048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 9782048e328SMark Yao u16 htotal = adjusted_mode->htotal; 9792048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 9802048e328SMark Yao u16 hact_end = hact_st + hdisplay; 9812048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 9822048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 9832048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 9842048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 9852048e328SMark Yao u16 vact_end = vact_st + vdisplay; 9860a63bfd0SMark Yao uint32_t pin_pol, val; 98739a9ad8fSSean Paul int ret; 9882048e328SMark Yao 989893b6cadSDaniel Vetter WARN_ON(vop->event); 990893b6cadSDaniel Vetter 99139a9ad8fSSean Paul ret = vop_enable(crtc); 99239a9ad8fSSean Paul if (ret) { 99339a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 99439a9ad8fSSean Paul return; 99539a9ad8fSSean Paul } 99639a9ad8fSSean Paul 9972048e328SMark Yao /* 998ce3887edSMark Yao * If dclk rate is zero, mean that scanout is stop, 999ce3887edSMark Yao * we don't need wait any more. 10002048e328SMark Yao */ 1001ce3887edSMark Yao if (clk_get_rate(vop->dclk)) { 1002ce3887edSMark Yao /* 1003ce3887edSMark Yao * Rk3288 vop timing register is immediately, when configure 1004ce3887edSMark Yao * display timing on display time, may cause tearing. 1005ce3887edSMark Yao * 1006ce3887edSMark Yao * Vop standby will take effect at end of current frame, 1007ce3887edSMark Yao * if dsp hold valid irq happen, it means standby complete. 1008ce3887edSMark Yao * 1009ce3887edSMark Yao * mode set: 1010ce3887edSMark Yao * standby and wait complete --> |---- 1011ce3887edSMark Yao * | display time 1012ce3887edSMark Yao * |---- 1013ce3887edSMark Yao * |---> dsp hold irq 1014ce3887edSMark Yao * configure display timing --> | 1015ce3887edSMark Yao * standby exit | 1016ce3887edSMark Yao * | new frame start. 1017ce3887edSMark Yao */ 1018ce3887edSMark Yao 1019ce3887edSMark Yao reinit_completion(&vop->dsp_hold_completion); 1020ce3887edSMark Yao vop_dsp_hold_valid_irq_enable(vop); 1021ce3887edSMark Yao 1022ce3887edSMark Yao spin_lock(&vop->reg_lock); 1023ce3887edSMark Yao 1024ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 1); 1025ce3887edSMark Yao 1026ce3887edSMark Yao spin_unlock(&vop->reg_lock); 1027ce3887edSMark Yao 1028ce3887edSMark Yao wait_for_completion(&vop->dsp_hold_completion); 1029ce3887edSMark Yao 1030ce3887edSMark Yao vop_dsp_hold_valid_irq_disable(vop); 1031ce3887edSMark Yao } 10322048e328SMark Yao 10330a63bfd0SMark Yao pin_pol = 0x8; 10340a63bfd0SMark Yao pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 10350a63bfd0SMark Yao pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 10360a63bfd0SMark Yao VOP_CTRL_SET(vop, pin_pol, pin_pol); 10370a63bfd0SMark Yao 10384e257d9eSMark Yao switch (s->output_type) { 10394e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 10404e257d9eSMark Yao VOP_CTRL_SET(vop, rgb_en, 1); 10410a63bfd0SMark Yao VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); 10424e257d9eSMark Yao break; 10434e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 10440a63bfd0SMark Yao VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); 10454e257d9eSMark Yao VOP_CTRL_SET(vop, edp_en, 1); 10464e257d9eSMark Yao break; 10474e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 10480a63bfd0SMark Yao VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); 10494e257d9eSMark Yao VOP_CTRL_SET(vop, hdmi_en, 1); 10504e257d9eSMark Yao break; 10514e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 10520a63bfd0SMark Yao VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); 10534e257d9eSMark Yao VOP_CTRL_SET(vop, mipi_en, 1); 10544e257d9eSMark Yao break; 10554e257d9eSMark Yao default: 1056ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1057ee4d7899SSean Paul s->output_type); 10584e257d9eSMark Yao } 10594e257d9eSMark Yao VOP_CTRL_SET(vop, out_mode, s->output_mode); 10602048e328SMark Yao 10612048e328SMark Yao VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 10622048e328SMark Yao val = hact_st << 16; 10632048e328SMark Yao val |= hact_end; 10642048e328SMark Yao VOP_CTRL_SET(vop, hact_st_end, val); 10652048e328SMark Yao VOP_CTRL_SET(vop, hpost_st_end, val); 10662048e328SMark Yao 10672048e328SMark Yao VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 10682048e328SMark Yao val = vact_st << 16; 10692048e328SMark Yao val |= vact_end; 10702048e328SMark Yao VOP_CTRL_SET(vop, vact_st_end, val); 10712048e328SMark Yao VOP_CTRL_SET(vop, vpost_st_end, val); 10722048e328SMark Yao 10732048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1074ce3887edSMark Yao 1075ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 0); 1076b883c9baSSean Paul 1077b883c9baSSean Paul rockchip_drm_psr_activate(&vop->crtc); 10782048e328SMark Yao } 10792048e328SMark Yao 108063ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 108163ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 108263ebb9faSMark Yao { 108363ebb9faSMark Yao struct vop *vop = to_vop(crtc); 108463ebb9faSMark Yao 108563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 108663ebb9faSMark Yao return; 108763ebb9faSMark Yao 108863ebb9faSMark Yao spin_lock(&vop->reg_lock); 108963ebb9faSMark Yao 109063ebb9faSMark Yao vop_cfg_done(vop); 109163ebb9faSMark Yao 109263ebb9faSMark Yao spin_unlock(&vop->reg_lock); 109363ebb9faSMark Yao } 109463ebb9faSMark Yao 109563ebb9faSMark Yao static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 109663ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 109763ebb9faSMark Yao { 109863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 109963ebb9faSMark Yao 1100b883c9baSSean Paul rockchip_drm_psr_flush(crtc); 1101b883c9baSSean Paul 1102893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 11035b680403SSean Paul vop->vblank_active = true; 110463ebb9faSMark Yao WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1105893b6cadSDaniel Vetter WARN_ON(vop->event); 110663ebb9faSMark Yao 11075b680403SSean Paul if (crtc->state->event) { 110863ebb9faSMark Yao vop->event = crtc->state->event; 110963ebb9faSMark Yao crtc->state->event = NULL; 111063ebb9faSMark Yao } 1111893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 11122048e328SMark Yao } 11132048e328SMark Yao 11142048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 11150ad3675dSMark Yao .enable = vop_crtc_enable, 11160ad3675dSMark Yao .disable = vop_crtc_disable, 11172048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 111863ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 111963ebb9faSMark Yao .atomic_begin = vop_crtc_atomic_begin, 11202048e328SMark Yao }; 11212048e328SMark Yao 11222048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 11232048e328SMark Yao { 11242048e328SMark Yao drm_crtc_cleanup(crtc); 11252048e328SMark Yao } 11262048e328SMark Yao 1127dc0b408fSJohn Keeping static void vop_crtc_reset(struct drm_crtc *crtc) 1128dc0b408fSJohn Keeping { 1129dc0b408fSJohn Keeping if (crtc->state) 1130dc0b408fSJohn Keeping __drm_atomic_helper_crtc_destroy_state(crtc->state); 1131dc0b408fSJohn Keeping kfree(crtc->state); 1132dc0b408fSJohn Keeping 1133dc0b408fSJohn Keeping crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1134dc0b408fSJohn Keeping if (crtc->state) 1135dc0b408fSJohn Keeping crtc->state->crtc = crtc; 1136dc0b408fSJohn Keeping } 1137dc0b408fSJohn Keeping 11384e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 11394e257d9eSMark Yao { 11404e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 11414e257d9eSMark Yao 11424e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 11434e257d9eSMark Yao if (!rockchip_state) 11444e257d9eSMark Yao return NULL; 11454e257d9eSMark Yao 11464e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 11474e257d9eSMark Yao return &rockchip_state->base; 11484e257d9eSMark Yao } 11494e257d9eSMark Yao 11504e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 11514e257d9eSMark Yao struct drm_crtc_state *state) 11524e257d9eSMark Yao { 11534e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 11544e257d9eSMark Yao 1155ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 11564e257d9eSMark Yao kfree(s); 11574e257d9eSMark Yao } 11584e257d9eSMark Yao 11592048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 116063ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 116163ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 11622048e328SMark Yao .destroy = vop_crtc_destroy, 1163dc0b408fSJohn Keeping .reset = vop_crtc_reset, 11644e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 11654e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 11662048e328SMark Yao }; 11672048e328SMark Yao 116863ebb9faSMark Yao static bool vop_win_pending_is_complete(struct vop_win *vop_win) 11692048e328SMark Yao { 11702048e328SMark Yao dma_addr_t yrgb_mst; 11712048e328SMark Yao 11724f9d39a7SDaniel Vetter if (!vop_win->enable) 117363ebb9faSMark Yao return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; 117463ebb9faSMark Yao 11752048e328SMark Yao yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 11762048e328SMark Yao 11774f9d39a7SDaniel Vetter return yrgb_mst == vop_win->yrgb_mst; 11782048e328SMark Yao } 11792048e328SMark Yao 118063ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 11812048e328SMark Yao { 118263ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 118363ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 118463ebb9faSMark Yao unsigned long flags; 118563ebb9faSMark Yao int i; 11862048e328SMark Yao 118763ebb9faSMark Yao for (i = 0; i < vop->data->win_size; i++) { 118863ebb9faSMark Yao if (!vop_win_pending_is_complete(&vop->win[i])) 11892048e328SMark Yao return; 11902048e328SMark Yao } 11912048e328SMark Yao 119263ebb9faSMark Yao spin_lock_irqsave(&drm->event_lock, flags); 1193893b6cadSDaniel Vetter if (vop->event) { 119463ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 119563ebb9faSMark Yao vop->event = NULL; 119663ebb9faSMark Yao 11972048e328SMark Yao } 11985b680403SSean Paul if (vop->vblank_active) { 11995b680403SSean Paul vop->vblank_active = false; 12005b680403SSean Paul drm_crtc_vblank_put(crtc); 12015b680403SSean Paul } 1202893b6cadSDaniel Vetter spin_unlock_irqrestore(&drm->event_lock, flags); 1203893b6cadSDaniel Vetter 120463ebb9faSMark Yao if (!completion_done(&vop->wait_update_complete)) 120563ebb9faSMark Yao complete(&vop->wait_update_complete); 12062048e328SMark Yao } 12072048e328SMark Yao 12082048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 12092048e328SMark Yao { 12102048e328SMark Yao struct vop *vop = data; 1211b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1212dbb3d944SMark Yao uint32_t active_irqs; 12132048e328SMark Yao unsigned long flags; 12141067219bSMark Yao int ret = IRQ_NONE; 12152048e328SMark Yao 12162048e328SMark Yao /* 1217dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 12182048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 12192048e328SMark Yao */ 12202048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1221dbb3d944SMark Yao 1222dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 12232048e328SMark Yao /* Clear all active interrupt sources */ 12242048e328SMark Yao if (active_irqs) 1225dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1226dbb3d944SMark Yao 12272048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 12282048e328SMark Yao 12292048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 12302048e328SMark Yao if (!active_irqs) 12312048e328SMark Yao return IRQ_NONE; 12322048e328SMark Yao 12331067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 12341067219bSMark Yao complete(&vop->dsp_hold_completion); 12351067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 12361067219bSMark Yao ret = IRQ_HANDLED; 12372048e328SMark Yao } 12382048e328SMark Yao 123969c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 124069c34e41SYakir Yang complete(&vop->line_flag_completion); 124169c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 124269c34e41SYakir Yang ret = IRQ_HANDLED; 124369c34e41SYakir Yang } 124469c34e41SYakir Yang 12451067219bSMark Yao if (active_irqs & FS_INTR) { 1246b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 124763ebb9faSMark Yao vop_handle_vblank(vop); 12481067219bSMark Yao active_irqs &= ~FS_INTR; 124963ebb9faSMark Yao ret = IRQ_HANDLED; 12501067219bSMark Yao } 12512048e328SMark Yao 12521067219bSMark Yao /* Unhandled irqs are spurious. */ 12531067219bSMark Yao if (active_irqs) 1254ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1255ee4d7899SSean Paul active_irqs); 12561067219bSMark Yao 12571067219bSMark Yao return ret; 12582048e328SMark Yao } 12592048e328SMark Yao 12602048e328SMark Yao static int vop_create_crtc(struct vop *vop) 12612048e328SMark Yao { 12622048e328SMark Yao const struct vop_data *vop_data = vop->data; 12632048e328SMark Yao struct device *dev = vop->dev; 12642048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1265328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 12662048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12672048e328SMark Yao struct device_node *port; 12682048e328SMark Yao int ret; 12692048e328SMark Yao int i; 12702048e328SMark Yao 12712048e328SMark Yao /* 12722048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 12732048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 12742048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 12752048e328SMark Yao */ 12762048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12772048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12782048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12792048e328SMark Yao 12802048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 12812048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 12822048e328SMark Yao continue; 12832048e328SMark Yao 12842048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12852048e328SMark Yao 0, &vop_plane_funcs, 12862048e328SMark Yao win_data->phy->data_formats, 12872048e328SMark Yao win_data->phy->nformats, 1288b0b3b795SVille Syrjälä win_data->type, NULL); 12892048e328SMark Yao if (ret) { 1290ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1291ee4d7899SSean Paul ret); 12922048e328SMark Yao goto err_cleanup_planes; 12932048e328SMark Yao } 12942048e328SMark Yao 12952048e328SMark Yao plane = &vop_win->base; 129663ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 12972048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 12982048e328SMark Yao primary = plane; 12992048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 13002048e328SMark Yao cursor = plane; 13012048e328SMark Yao } 13022048e328SMark Yao 13032048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1304f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 13052048e328SMark Yao if (ret) 1306328b51c0SDouglas Anderson goto err_cleanup_planes; 13072048e328SMark Yao 13082048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 13092048e328SMark Yao 13102048e328SMark Yao /* 13112048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 13122048e328SMark Yao * to the newly created crtc. 13132048e328SMark Yao */ 13142048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13152048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13162048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 13172048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 13182048e328SMark Yao 13192048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 13202048e328SMark Yao continue; 13212048e328SMark Yao 13222048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 13232048e328SMark Yao possible_crtcs, 13242048e328SMark Yao &vop_plane_funcs, 13252048e328SMark Yao win_data->phy->data_formats, 13262048e328SMark Yao win_data->phy->nformats, 1327b0b3b795SVille Syrjälä win_data->type, NULL); 13282048e328SMark Yao if (ret) { 1329ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1330ee4d7899SSean Paul ret); 13312048e328SMark Yao goto err_cleanup_crtc; 13322048e328SMark Yao } 133363ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 13342048e328SMark Yao } 13352048e328SMark Yao 13362048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 13372048e328SMark Yao if (!port) { 1338ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "no port node found in %s\n", 13392048e328SMark Yao dev->of_node->full_name); 1340328b51c0SDouglas Anderson ret = -ENOENT; 13412048e328SMark Yao goto err_cleanup_crtc; 13422048e328SMark Yao } 13432048e328SMark Yao 13441067219bSMark Yao init_completion(&vop->dsp_hold_completion); 134563ebb9faSMark Yao init_completion(&vop->wait_update_complete); 134669c34e41SYakir Yang init_completion(&vop->line_flag_completion); 13472048e328SMark Yao crtc->port = port; 1348b5f7b755SMark Yao rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); 13492048e328SMark Yao 13502048e328SMark Yao return 0; 13512048e328SMark Yao 13522048e328SMark Yao err_cleanup_crtc: 13532048e328SMark Yao drm_crtc_cleanup(crtc); 13542048e328SMark Yao err_cleanup_planes: 1355328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1356328b51c0SDouglas Anderson head) 13572048e328SMark Yao drm_plane_cleanup(plane); 13582048e328SMark Yao return ret; 13592048e328SMark Yao } 13602048e328SMark Yao 13612048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 13622048e328SMark Yao { 13632048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1364328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1365328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 13662048e328SMark Yao 1367b5f7b755SMark Yao rockchip_unregister_crtc_funcs(crtc); 13682048e328SMark Yao of_node_put(crtc->port); 1369328b51c0SDouglas Anderson 1370328b51c0SDouglas Anderson /* 1371328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1372328b51c0SDouglas Anderson * 1373328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1374328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1375328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1376328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1377328b51c0SDouglas Anderson */ 1378328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1379328b51c0SDouglas Anderson head) 1380328b51c0SDouglas Anderson vop_plane_destroy(plane); 1381328b51c0SDouglas Anderson 1382328b51c0SDouglas Anderson /* 1383328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1384328b51c0SDouglas Anderson * references the CRTC. 1385328b51c0SDouglas Anderson */ 13862048e328SMark Yao drm_crtc_cleanup(crtc); 13872048e328SMark Yao } 13882048e328SMark Yao 13892048e328SMark Yao static int vop_initial(struct vop *vop) 13902048e328SMark Yao { 13912048e328SMark Yao const struct vop_data *vop_data = vop->data; 13922048e328SMark Yao const struct vop_reg_data *init_table = vop_data->init_table; 13932048e328SMark Yao struct reset_control *ahb_rst; 13942048e328SMark Yao int i, ret; 13952048e328SMark Yao 13962048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 13972048e328SMark Yao if (IS_ERR(vop->hclk)) { 13982048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 13992048e328SMark Yao return PTR_ERR(vop->hclk); 14002048e328SMark Yao } 14012048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 14022048e328SMark Yao if (IS_ERR(vop->aclk)) { 14032048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 14042048e328SMark Yao return PTR_ERR(vop->aclk); 14052048e328SMark Yao } 14062048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 14072048e328SMark Yao if (IS_ERR(vop->dclk)) { 14082048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 14092048e328SMark Yao return PTR_ERR(vop->dclk); 14102048e328SMark Yao } 14112048e328SMark Yao 14122048e328SMark Yao ret = clk_prepare(vop->dclk); 14132048e328SMark Yao if (ret < 0) { 14142048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 1415d7b53fd9SSjoerd Simons return ret; 14162048e328SMark Yao } 14172048e328SMark Yao 1418d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1419d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 14202048e328SMark Yao if (ret < 0) { 1421d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable hclk\n"); 14222048e328SMark Yao goto err_unprepare_dclk; 14232048e328SMark Yao } 14242048e328SMark Yao 1425d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 14262048e328SMark Yao if (ret < 0) { 1427d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1428d7b53fd9SSjoerd Simons goto err_disable_hclk; 14292048e328SMark Yao } 1430d7b53fd9SSjoerd Simons 14312048e328SMark Yao /* 14322048e328SMark Yao * do hclk_reset, reset all vop registers. 14332048e328SMark Yao */ 14342048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 14352048e328SMark Yao if (IS_ERR(ahb_rst)) { 14362048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 14372048e328SMark Yao ret = PTR_ERR(ahb_rst); 1438d7b53fd9SSjoerd Simons goto err_disable_aclk; 14392048e328SMark Yao } 14402048e328SMark Yao reset_control_assert(ahb_rst); 14412048e328SMark Yao usleep_range(10, 20); 14422048e328SMark Yao reset_control_deassert(ahb_rst); 14432048e328SMark Yao 14442048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 14452048e328SMark Yao 14462048e328SMark Yao for (i = 0; i < vop_data->table_size; i++) 14472048e328SMark Yao vop_writel(vop, init_table[i].offset, init_table[i].value); 14482048e328SMark Yao 14492048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14502048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 14512048e328SMark Yao 14522048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 14532048e328SMark Yao } 14542048e328SMark Yao 14552048e328SMark Yao vop_cfg_done(vop); 14562048e328SMark Yao 14572048e328SMark Yao /* 14582048e328SMark Yao * do dclk_reset, let all config take affect. 14592048e328SMark Yao */ 14602048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 14612048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 14622048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 14632048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1464d7b53fd9SSjoerd Simons goto err_disable_aclk; 14652048e328SMark Yao } 14662048e328SMark Yao reset_control_assert(vop->dclk_rst); 14672048e328SMark Yao usleep_range(10, 20); 14682048e328SMark Yao reset_control_deassert(vop->dclk_rst); 14692048e328SMark Yao 14702048e328SMark Yao clk_disable(vop->hclk); 1471d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 14722048e328SMark Yao 147331e980c5SMark Yao vop->is_enabled = false; 14745b680403SSean Paul vop->vblank_active = false; 14752048e328SMark Yao 14762048e328SMark Yao return 0; 14772048e328SMark Yao 1478d7b53fd9SSjoerd Simons err_disable_aclk: 1479d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 14802048e328SMark Yao err_disable_hclk: 1481d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 14822048e328SMark Yao err_unprepare_dclk: 14832048e328SMark Yao clk_unprepare(vop->dclk); 14842048e328SMark Yao return ret; 14852048e328SMark Yao } 14862048e328SMark Yao 14872048e328SMark Yao /* 14882048e328SMark Yao * Initialize the vop->win array elements. 14892048e328SMark Yao */ 14902048e328SMark Yao static void vop_win_init(struct vop *vop) 14912048e328SMark Yao { 14922048e328SMark Yao const struct vop_data *vop_data = vop->data; 14932048e328SMark Yao unsigned int i; 14942048e328SMark Yao 14952048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14962048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14972048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 14982048e328SMark Yao 14992048e328SMark Yao vop_win->data = win_data; 15002048e328SMark Yao vop_win->vop = vop; 15012048e328SMark Yao } 15022048e328SMark Yao } 15032048e328SMark Yao 150469c34e41SYakir Yang /** 150569c34e41SYakir Yang * rockchip_drm_wait_line_flag - acqiure the give line flag event 150669c34e41SYakir Yang * @crtc: CRTC to enable line flag 150769c34e41SYakir Yang * @line_num: interested line number 150869c34e41SYakir Yang * @mstimeout: millisecond for timeout 150969c34e41SYakir Yang * 151069c34e41SYakir Yang * Driver would hold here until the interested line flag interrupt have 151169c34e41SYakir Yang * happened or timeout to wait. 151269c34e41SYakir Yang * 151369c34e41SYakir Yang * Returns: 151469c34e41SYakir Yang * Zero on success, negative errno on failure. 151569c34e41SYakir Yang */ 151669c34e41SYakir Yang int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num, 151769c34e41SYakir Yang unsigned int mstimeout) 151869c34e41SYakir Yang { 151969c34e41SYakir Yang struct vop *vop = to_vop(crtc); 152069c34e41SYakir Yang unsigned long jiffies_left; 152169c34e41SYakir Yang 152269c34e41SYakir Yang if (!crtc || !vop->is_enabled) 152369c34e41SYakir Yang return -ENODEV; 152469c34e41SYakir Yang 152569c34e41SYakir Yang if (line_num > crtc->mode.vtotal || mstimeout <= 0) 152669c34e41SYakir Yang return -EINVAL; 152769c34e41SYakir Yang 152869c34e41SYakir Yang if (vop_line_flag_irq_is_enabled(vop)) 152969c34e41SYakir Yang return -EBUSY; 153069c34e41SYakir Yang 153169c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 153269c34e41SYakir Yang vop_line_flag_irq_enable(vop, line_num); 153369c34e41SYakir Yang 153469c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 153569c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 153669c34e41SYakir Yang vop_line_flag_irq_disable(vop); 153769c34e41SYakir Yang 153869c34e41SYakir Yang if (jiffies_left == 0) { 153969c34e41SYakir Yang dev_err(vop->dev, "Timeout waiting for IRQ\n"); 154069c34e41SYakir Yang return -ETIMEDOUT; 154169c34e41SYakir Yang } 154269c34e41SYakir Yang 154369c34e41SYakir Yang return 0; 154469c34e41SYakir Yang } 154569c34e41SYakir Yang EXPORT_SYMBOL(rockchip_drm_wait_line_flag); 154669c34e41SYakir Yang 15472048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 15482048e328SMark Yao { 15492048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 15502048e328SMark Yao const struct vop_data *vop_data; 15512048e328SMark Yao struct drm_device *drm_dev = data; 15522048e328SMark Yao struct vop *vop; 15532048e328SMark Yao struct resource *res; 15542048e328SMark Yao size_t alloc_size; 15553ea68922SHeiko Stuebner int ret, irq; 15562048e328SMark Yao 1557a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 15582048e328SMark Yao if (!vop_data) 15592048e328SMark Yao return -ENODEV; 15602048e328SMark Yao 15612048e328SMark Yao /* Allocate vop struct and its vop_win array */ 15622048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 15632048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 15642048e328SMark Yao if (!vop) 15652048e328SMark Yao return -ENOMEM; 15662048e328SMark Yao 15672048e328SMark Yao vop->dev = dev; 15682048e328SMark Yao vop->data = vop_data; 15692048e328SMark Yao vop->drm_dev = drm_dev; 15702048e328SMark Yao dev_set_drvdata(dev, vop); 15712048e328SMark Yao 15722048e328SMark Yao vop_win_init(vop); 15732048e328SMark Yao 15742048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15752048e328SMark Yao vop->len = resource_size(res); 15762048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 15772048e328SMark Yao if (IS_ERR(vop->regs)) 15782048e328SMark Yao return PTR_ERR(vop->regs); 15792048e328SMark Yao 15802048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 15812048e328SMark Yao if (!vop->regsbak) 15822048e328SMark Yao return -ENOMEM; 15832048e328SMark Yao 15842048e328SMark Yao ret = vop_initial(vop); 15852048e328SMark Yao if (ret < 0) { 15862048e328SMark Yao dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 15872048e328SMark Yao return ret; 15882048e328SMark Yao } 15892048e328SMark Yao 15903ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 15913ea68922SHeiko Stuebner if (irq < 0) { 15922048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 15933ea68922SHeiko Stuebner return irq; 15942048e328SMark Yao } 15953ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 15962048e328SMark Yao 15972048e328SMark Yao spin_lock_init(&vop->reg_lock); 15982048e328SMark Yao spin_lock_init(&vop->irq_lock); 15992048e328SMark Yao 16002048e328SMark Yao mutex_init(&vop->vsync_mutex); 16012048e328SMark Yao 160263ebb9faSMark Yao ret = devm_request_irq(dev, vop->irq, vop_isr, 16032048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 16042048e328SMark Yao if (ret) 16052048e328SMark Yao return ret; 16062048e328SMark Yao 16072048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 16082048e328SMark Yao disable_irq(vop->irq); 16092048e328SMark Yao 16102048e328SMark Yao ret = vop_create_crtc(vop); 16112048e328SMark Yao if (ret) 16122048e328SMark Yao return ret; 16132048e328SMark Yao 16142048e328SMark Yao pm_runtime_enable(&pdev->dev); 16155182c1a5SYakir Yang 16162048e328SMark Yao return 0; 16172048e328SMark Yao } 16182048e328SMark Yao 16192048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 16202048e328SMark Yao { 16212048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 16222048e328SMark Yao 16232048e328SMark Yao pm_runtime_disable(dev); 16242048e328SMark Yao vop_destroy_crtc(vop); 16252048e328SMark Yao } 16262048e328SMark Yao 1627a67719d1SMark Yao const struct component_ops vop_component_ops = { 16282048e328SMark Yao .bind = vop_bind, 16292048e328SMark Yao .unbind = vop_unbind, 16302048e328SMark Yao }; 163154255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1632