12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 1815609559SEnric Balletbo i Serra #include <drm/drm_atomic_uapi.h> 192048e328SMark Yao #include <drm/drm_crtc.h> 2047a7eb45STomasz Figa #include <drm/drm_flip_work.h> 2163d5e06aSHeiko Stuebner #include <drm/drm_gem_framebuffer_helper.h> 222048e328SMark Yao #include <drm/drm_plane_helper.h> 23fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 246cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 253190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 266cca3869SSean Paul #endif 272048e328SMark Yao 282048e328SMark Yao #include <linux/kernel.h> 2900fe6148SPaul Gortmaker #include <linux/module.h> 302048e328SMark Yao #include <linux/platform_device.h> 312048e328SMark Yao #include <linux/clk.h> 327caecdbeSTomasz Figa #include <linux/iopoll.h> 332048e328SMark Yao #include <linux/of.h> 342048e328SMark Yao #include <linux/of_device.h> 352048e328SMark Yao #include <linux/pm_runtime.h> 362048e328SMark Yao #include <linux/component.h> 3729adeb4fSGustavo A. R. Silva #include <linux/overflow.h> 382048e328SMark Yao 392048e328SMark Yao #include <linux/reset.h> 402048e328SMark Yao #include <linux/delay.h> 412048e328SMark Yao 422048e328SMark Yao #include "rockchip_drm_drv.h" 432048e328SMark Yao #include "rockchip_drm_gem.h" 442048e328SMark Yao #include "rockchip_drm_fb.h" 455182c1a5SYakir Yang #include "rockchip_drm_psr.h" 462048e328SMark Yao #include "rockchip_drm_vop.h" 471f0f0151SSandy Huang #include "rockchip_rgb.h" 482048e328SMark Yao 492996fb75SEzequiel Garcia #define VOP_WIN_SET(vop, win, name, v) \ 509a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 512996fb75SEzequiel Garcia #define VOP_SCL_SET(vop, win, name, v) \ 529a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 532996fb75SEzequiel Garcia #define VOP_SCL_SET_EXT(vop, win, name, v) \ 549a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 559a61c54bSMark yao win->base, ~0, v, #name) 56ac6560dfSMark yao 572996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 581c21aa8fSDaniele Castagna do { \ 591c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 601c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 611c21aa8fSDaniele Castagna } while (0) 621c21aa8fSDaniele Castagna 632996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 641c21aa8fSDaniele Castagna do { \ 651c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 661c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 671c21aa8fSDaniele Castagna } while (0) 681c21aa8fSDaniele Castagna 69ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 709a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 719a61c54bSMark yao 729a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 739a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 74ac6560dfSMark yao 75dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 76dbb3d944SMark Yao do { \ 77c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 78dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 79c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 80dbb3d944SMark Yao reg |= (v) << i; \ 81c7647f86SJohn Keeping mask |= 1 << i; \ 82dbb3d944SMark Yao } \ 83c7647f86SJohn Keeping } \ 84ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 85dbb3d944SMark Yao } while (0) 86dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 87dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 88dbb3d944SMark Yao 892996fb75SEzequiel Garcia #define VOP_WIN_GET(vop, win, name) \ 902996fb75SEzequiel Garcia vop_read_reg(vop, win->offset, win->phy->name) 912048e328SMark Yao 92677e8bbcSDaniele Castagna #define VOP_WIN_HAS_REG(win, name) \ 93677e8bbcSDaniele Castagna (!!(win->phy->name.mask)) 94677e8bbcSDaniele Castagna 952048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 962048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 972048e328SMark Yao 9858badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 9958badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 10058badaa7SKristian H. Kristensen 1012048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 1022048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 1032048e328SMark Yao 1041c21aa8fSDaniele Castagna /* 1051c21aa8fSDaniele Castagna * The coefficients of the following matrix are all fixed points. 1061c21aa8fSDaniele Castagna * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 1071c21aa8fSDaniele Castagna * They are all represented in two's complement. 1081c21aa8fSDaniele Castagna */ 1091c21aa8fSDaniele Castagna static const uint32_t bt601_yuv2rgb[] = { 1101c21aa8fSDaniele Castagna 0x4A8, 0x0, 0x662, 1111c21aa8fSDaniele Castagna 0x4A8, 0x1E6F, 0x1CBF, 1121c21aa8fSDaniele Castagna 0x4A8, 0x812, 0x0, 1131c21aa8fSDaniele Castagna 0x321168, 0x0877CF, 0x2EB127 1141c21aa8fSDaniele Castagna }; 1151c21aa8fSDaniele Castagna 11647a7eb45STomasz Figa enum vop_pending { 11747a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 11847a7eb45STomasz Figa }; 11947a7eb45STomasz Figa 1202048e328SMark Yao struct vop_win { 1212048e328SMark Yao struct drm_plane base; 1222048e328SMark Yao const struct vop_win_data *data; 1231c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *yuv2yuv_data; 1242048e328SMark Yao struct vop *vop; 1252048e328SMark Yao }; 1262048e328SMark Yao 1271f0f0151SSandy Huang struct rockchip_rgb; 1282048e328SMark Yao struct vop { 1292048e328SMark Yao struct drm_crtc crtc; 1302048e328SMark Yao struct device *dev; 1312048e328SMark Yao struct drm_device *drm_dev; 13231e980c5SMark Yao bool is_enabled; 1332048e328SMark Yao 1341067219bSMark Yao struct completion dsp_hold_completion; 1354f9d39a7SDaniel Vetter 1364f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 13763ebb9faSMark Yao struct drm_pending_vblank_event *event; 1382048e328SMark Yao 13947a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 14047a7eb45STomasz Figa unsigned long pending; 14147a7eb45STomasz Figa 14269c34e41SYakir Yang struct completion line_flag_completion; 14369c34e41SYakir Yang 1442048e328SMark Yao const struct vop_data *data; 1452048e328SMark Yao 1462048e328SMark Yao uint32_t *regsbak; 1472048e328SMark Yao void __iomem *regs; 1482048e328SMark Yao 1492048e328SMark Yao /* physical map length of vop register */ 1502048e328SMark Yao uint32_t len; 1512048e328SMark Yao 1522048e328SMark Yao /* one time only one process allowed to config the register */ 1532048e328SMark Yao spinlock_t reg_lock; 1542048e328SMark Yao /* lock vop irq reg */ 1552048e328SMark Yao spinlock_t irq_lock; 156e334d48bSzain wang /* protects crtc enable/disable */ 157e334d48bSzain wang struct mutex vop_lock; 1582048e328SMark Yao 1592048e328SMark Yao unsigned int irq; 1602048e328SMark Yao 1612048e328SMark Yao /* vop AHP clk */ 1622048e328SMark Yao struct clk *hclk; 1632048e328SMark Yao /* vop dclk */ 1642048e328SMark Yao struct clk *dclk; 1652048e328SMark Yao /* vop share memory frequency */ 1662048e328SMark Yao struct clk *aclk; 1672048e328SMark Yao 1682048e328SMark Yao /* vop dclk reset */ 1692048e328SMark Yao struct reset_control *dclk_rst; 1702048e328SMark Yao 1711f0f0151SSandy Huang /* optional internal rgb encoder */ 1721f0f0151SSandy Huang struct rockchip_rgb *rgb; 1731f0f0151SSandy Huang 1742048e328SMark Yao struct vop_win win[]; 1752048e328SMark Yao }; 1762048e328SMark Yao 1772048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1782048e328SMark Yao { 1792048e328SMark Yao writel(v, vop->regs + offset); 1802048e328SMark Yao vop->regsbak[offset >> 2] = v; 1812048e328SMark Yao } 1822048e328SMark Yao 1832048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1842048e328SMark Yao { 1852048e328SMark Yao return readl(vop->regs + offset); 1862048e328SMark Yao } 1872048e328SMark Yao 1882048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1892048e328SMark Yao const struct vop_reg *reg) 1902048e328SMark Yao { 1912048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1922048e328SMark Yao } 1932048e328SMark Yao 1949a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 1959a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 1969a61c54bSMark yao const char *reg_name) 1972048e328SMark Yao { 1989a61c54bSMark yao int offset, mask, shift; 199d49463ecSMark Yao 2009a61c54bSMark yao if (!reg || !reg->mask) { 201d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 2029a61c54bSMark yao return; 2039a61c54bSMark yao } 2049a61c54bSMark yao 2059a61c54bSMark yao offset = reg->offset + _offset; 2069a61c54bSMark yao mask = reg->mask & _mask; 2079a61c54bSMark yao shift = reg->shift; 2089a61c54bSMark yao 2099a61c54bSMark yao if (reg->write_mask) { 210d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 211d49463ecSMark Yao } else { 2122048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 2132048e328SMark Yao 214d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 215d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 2162048e328SMark Yao } 2172048e328SMark Yao 2189a61c54bSMark yao if (reg->relaxed) 219d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 220d49463ecSMark Yao else 221d49463ecSMark Yao writel(v, vop->regs + offset); 2222048e328SMark Yao } 2232048e328SMark Yao 224dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 225dbb3d944SMark Yao const struct vop_reg *reg, int type) 226dbb3d944SMark Yao { 227dbb3d944SMark Yao uint32_t i, ret = 0; 228dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 229dbb3d944SMark Yao 230dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 231dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 232dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 233dbb3d944SMark Yao } 234dbb3d944SMark Yao 235dbb3d944SMark Yao return ret; 236dbb3d944SMark Yao } 237dbb3d944SMark Yao 2380cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2390cf33fe3SMark Yao { 2409a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2410cf33fe3SMark Yao } 2420cf33fe3SMark Yao 24385a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 24485a359f2STomasz Figa { 24585a359f2STomasz Figa switch (format) { 24685a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 24785a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 24885a359f2STomasz Figa case DRM_FORMAT_BGR888: 24985a359f2STomasz Figa case DRM_FORMAT_BGR565: 25085a359f2STomasz Figa return true; 25185a359f2STomasz Figa default: 25285a359f2STomasz Figa return false; 25385a359f2STomasz Figa } 25485a359f2STomasz Figa } 25585a359f2STomasz Figa 2562048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2572048e328SMark Yao { 2582048e328SMark Yao switch (format) { 2592048e328SMark Yao case DRM_FORMAT_XRGB8888: 2602048e328SMark Yao case DRM_FORMAT_ARGB8888: 26185a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 26285a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2632048e328SMark Yao return VOP_FMT_ARGB8888; 2642048e328SMark Yao case DRM_FORMAT_RGB888: 26585a359f2STomasz Figa case DRM_FORMAT_BGR888: 2662048e328SMark Yao return VOP_FMT_RGB888; 2672048e328SMark Yao case DRM_FORMAT_RGB565: 26885a359f2STomasz Figa case DRM_FORMAT_BGR565: 2692048e328SMark Yao return VOP_FMT_RGB565; 2702048e328SMark Yao case DRM_FORMAT_NV12: 2712048e328SMark Yao return VOP_FMT_YUV420SP; 2722048e328SMark Yao case DRM_FORMAT_NV16: 2732048e328SMark Yao return VOP_FMT_YUV422SP; 2742048e328SMark Yao case DRM_FORMAT_NV24: 2752048e328SMark Yao return VOP_FMT_YUV444SP; 2762048e328SMark Yao default: 277ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2782048e328SMark Yao return -EINVAL; 2792048e328SMark Yao } 2802048e328SMark Yao } 2812048e328SMark Yao 2824c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2834c156c21SMark Yao uint32_t dst, bool is_horizontal, 2844c156c21SMark Yao int vsu_mode, int *vskiplines) 2854c156c21SMark Yao { 2864c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2874c156c21SMark Yao 288ce91d373SJeffy Chen if (vskiplines) 289ce91d373SJeffy Chen *vskiplines = 0; 290ce91d373SJeffy Chen 2914c156c21SMark Yao if (is_horizontal) { 2924c156c21SMark Yao if (mode == SCALE_UP) 2934c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2944c156c21SMark Yao else if (mode == SCALE_DOWN) 2954c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2964c156c21SMark Yao } else { 2974c156c21SMark Yao if (mode == SCALE_UP) { 2984c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2994c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 3004c156c21SMark Yao else 3014c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3024c156c21SMark Yao } else if (mode == SCALE_DOWN) { 3034c156c21SMark Yao if (vskiplines) { 3044c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 3054c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 3064c156c21SMark Yao *vskiplines); 3074c156c21SMark Yao } else { 3084c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3094c156c21SMark Yao } 3104c156c21SMark Yao } 3114c156c21SMark Yao } 3124c156c21SMark Yao 3134c156c21SMark Yao return val; 3144c156c21SMark Yao } 3154c156c21SMark Yao 3164c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3174c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3184c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 3194c156c21SMark Yao { 3204c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3214c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3224c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 3234c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 3244c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 325d8bd23d9SAyan Kumar Halder const struct drm_format_info *info; 326d8bd23d9SAyan Kumar Halder bool is_yuv = false; 3274c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 3284c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 3294c156c21SMark Yao uint16_t vsu_mode; 3304c156c21SMark Yao uint16_t lb_mode; 3314c156c21SMark Yao uint32_t val; 332ce91d373SJeffy Chen int vskiplines; 3334c156c21SMark Yao 334d8bd23d9SAyan Kumar Halder info = drm_format_info(pixel_format); 335d8bd23d9SAyan Kumar Halder 336d8bd23d9SAyan Kumar Halder if (info->is_yuv) 337d8bd23d9SAyan Kumar Halder is_yuv = true; 338d8bd23d9SAyan Kumar Halder 3394c156c21SMark Yao if (dst_w > 3840) { 340ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3414c156c21SMark Yao return; 3424c156c21SMark Yao } 3434c156c21SMark Yao 3441194fffbSMark Yao if (!win->phy->scl->ext) { 3451194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3461194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3471194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3481194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3491194fffbSMark Yao if (is_yuv) { 3501194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 351ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3521194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 353ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3541194fffbSMark Yao } 3551194fffbSMark Yao return; 3561194fffbSMark Yao } 3571194fffbSMark Yao 3584c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3594c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3604c156c21SMark Yao 3614c156c21SMark Yao if (is_yuv) { 3624c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3634c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3644c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3654c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3664c156c21SMark Yao else 3674c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3684c156c21SMark Yao } else { 3694c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3704c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3714c156c21SMark Yao else 3724c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3734c156c21SMark Yao } 3744c156c21SMark Yao 3751194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3764c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3774c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 378ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3794c156c21SMark Yao return; 3804c156c21SMark Yao } 3814c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 382ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3834c156c21SMark Yao return; 3844c156c21SMark Yao } 3854c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3864c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3874c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3884c156c21SMark Yao } else { 3894c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3904c156c21SMark Yao } 3914c156c21SMark Yao 3924c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3934c156c21SMark Yao true, 0, NULL); 3944c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3954c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3964c156c21SMark Yao false, vsu_mode, &vskiplines); 3974c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3984c156c21SMark Yao 3991194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 4001194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 4014c156c21SMark Yao 4021194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 4031194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 4041194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 4051194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 4061194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 4074c156c21SMark Yao if (is_yuv) { 4084c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 4094c156c21SMark Yao dst_w, true, 0, NULL); 4104c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 4114c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 4124c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 4134c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 4144c156c21SMark Yao 4151194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 4161194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4171194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4181194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4191194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4201194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4211194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4224c156c21SMark Yao } 4234c156c21SMark Yao } 4244c156c21SMark Yao 4251067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4261067219bSMark Yao { 4271067219bSMark Yao unsigned long flags; 4281067219bSMark Yao 4291067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4301067219bSMark Yao return; 4311067219bSMark Yao 4321067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4331067219bSMark Yao 434fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 435dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4361067219bSMark Yao 4371067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4381067219bSMark Yao } 4391067219bSMark Yao 4401067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4411067219bSMark Yao { 4421067219bSMark Yao unsigned long flags; 4431067219bSMark Yao 4441067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4451067219bSMark Yao return; 4461067219bSMark Yao 4471067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4481067219bSMark Yao 449dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4501067219bSMark Yao 4511067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4521067219bSMark Yao } 4531067219bSMark Yao 45469c34e41SYakir Yang /* 45569c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 45669c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 45769c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 45869c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 45969c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 46069c34e41SYakir Yang * 46169c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 46269c34e41SYakir Yang * Interrupts 46369c34e41SYakir Yang * LINE_FLAG -------------------------------+ 46469c34e41SYakir Yang * FRAME_SYNC ----+ | 46569c34e41SYakir Yang * | | 46669c34e41SYakir Yang * v v 46769c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 46869c34e41SYakir Yang * ^ ^ ^ ^ 46969c34e41SYakir Yang * | | | | 47069c34e41SYakir Yang * | | | | 47169c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 47269c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 47369c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 47469c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 47569c34e41SYakir Yang */ 47669c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 47769c34e41SYakir Yang { 47869c34e41SYakir Yang uint32_t line_flag_irq; 47969c34e41SYakir Yang unsigned long flags; 48069c34e41SYakir Yang 48169c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 48269c34e41SYakir Yang 48369c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 48469c34e41SYakir Yang 48569c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 48669c34e41SYakir Yang 48769c34e41SYakir Yang return !!line_flag_irq; 48869c34e41SYakir Yang } 48969c34e41SYakir Yang 490459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 49169c34e41SYakir Yang { 49269c34e41SYakir Yang unsigned long flags; 49369c34e41SYakir Yang 49469c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 49569c34e41SYakir Yang return; 49669c34e41SYakir Yang 49769c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 49869c34e41SYakir Yang 499fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 50069c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 50169c34e41SYakir Yang 50269c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 50369c34e41SYakir Yang } 50469c34e41SYakir Yang 50569c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 50669c34e41SYakir Yang { 50769c34e41SYakir Yang unsigned long flags; 50869c34e41SYakir Yang 50969c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 51069c34e41SYakir Yang return; 51169c34e41SYakir Yang 51269c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 51369c34e41SYakir Yang 51469c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 51569c34e41SYakir Yang 51669c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 51769c34e41SYakir Yang } 51869c34e41SYakir Yang 519e2810a71SHeiko Stuebner static int vop_core_clks_enable(struct vop *vop) 520e2810a71SHeiko Stuebner { 521e2810a71SHeiko Stuebner int ret; 522e2810a71SHeiko Stuebner 523e2810a71SHeiko Stuebner ret = clk_enable(vop->hclk); 524e2810a71SHeiko Stuebner if (ret < 0) 525e2810a71SHeiko Stuebner return ret; 526e2810a71SHeiko Stuebner 527e2810a71SHeiko Stuebner ret = clk_enable(vop->aclk); 528e2810a71SHeiko Stuebner if (ret < 0) 529e2810a71SHeiko Stuebner goto err_disable_hclk; 530e2810a71SHeiko Stuebner 531e2810a71SHeiko Stuebner return 0; 532e2810a71SHeiko Stuebner 533e2810a71SHeiko Stuebner err_disable_hclk: 534e2810a71SHeiko Stuebner clk_disable(vop->hclk); 535e2810a71SHeiko Stuebner return ret; 536e2810a71SHeiko Stuebner } 537e2810a71SHeiko Stuebner 538e2810a71SHeiko Stuebner static void vop_core_clks_disable(struct vop *vop) 539e2810a71SHeiko Stuebner { 540e2810a71SHeiko Stuebner clk_disable(vop->aclk); 541e2810a71SHeiko Stuebner clk_disable(vop->hclk); 542e2810a71SHeiko Stuebner } 543e2810a71SHeiko Stuebner 544e9abc611SJonas Karlman static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) 545e9abc611SJonas Karlman { 546e9abc611SJonas Karlman if (win->phy->scl && win->phy->scl->ext) { 547e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 548e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 549e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 550e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 551e9abc611SJonas Karlman } 552e9abc611SJonas Karlman 553e9abc611SJonas Karlman VOP_WIN_SET(vop, win, enable, 0); 554e9abc611SJonas Karlman } 555e9abc611SJonas Karlman 55639a9ad8fSSean Paul static int vop_enable(struct drm_crtc *crtc) 5572048e328SMark Yao { 5582048e328SMark Yao struct vop *vop = to_vop(crtc); 55964d77564SMark yao int ret, i; 5602048e328SMark Yao 5615d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5625d82d1a7SMark Yao if (ret < 0) { 563d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 5645e570373SJeffy Chen return ret; 5655d82d1a7SMark Yao } 5665d82d1a7SMark Yao 567e2810a71SHeiko Stuebner ret = vop_core_clks_enable(vop); 56839a9ad8fSSean Paul if (WARN_ON(ret < 0)) 56939a9ad8fSSean Paul goto err_put_pm_runtime; 5702048e328SMark Yao 5712048e328SMark Yao ret = clk_enable(vop->dclk); 57239a9ad8fSSean Paul if (WARN_ON(ret < 0)) 573e2810a71SHeiko Stuebner goto err_disable_core; 5742048e328SMark Yao 5752048e328SMark Yao /* 5762048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5772048e328SMark Yao * automatically with this master device via common driver code. 5782048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5792048e328SMark Yao * mapping. 5802048e328SMark Yao */ 5812048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5822048e328SMark Yao if (ret) { 583d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 584d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 585e2810a71SHeiko Stuebner goto err_disable_dclk; 5862048e328SMark Yao } 5872048e328SMark Yao 58876f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 58976f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 59076f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 59176f1416eSMarc Zyngier 59264d77564SMark yao /* 59364d77564SMark yao * We need to make sure that all windows are disabled before we 59464d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 59564d77564SMark yao * buffer later. 59664d77564SMark yao */ 59764d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 59864d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 59964d77564SMark yao const struct vop_win_data *win = vop_win->data; 60064d77564SMark yao 601e9abc611SJonas Karlman vop_win_disable(vop, win); 60264d77564SMark yao } 60376f1416eSMarc Zyngier spin_unlock(&vop->reg_lock); 60464d77564SMark yao 60517a794d7SChris Zhong vop_cfg_done(vop); 60617a794d7SChris Zhong 60752ab7891SMark Yao /* 60852ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 60952ab7891SMark Yao */ 61052ab7891SMark Yao vop->is_enabled = true; 61152ab7891SMark Yao 6122048e328SMark Yao spin_lock(&vop->reg_lock); 6132048e328SMark Yao 6149a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6152048e328SMark Yao 6162048e328SMark Yao spin_unlock(&vop->reg_lock); 6172048e328SMark Yao 618b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6192048e328SMark Yao 62039a9ad8fSSean Paul return 0; 6212048e328SMark Yao 6222048e328SMark Yao err_disable_dclk: 6232048e328SMark Yao clk_disable(vop->dclk); 624e2810a71SHeiko Stuebner err_disable_core: 625e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 62639a9ad8fSSean Paul err_put_pm_runtime: 62739a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 62839a9ad8fSSean Paul return ret; 6292048e328SMark Yao } 6302048e328SMark Yao 63164581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 63264581714SLaurent Pinchart struct drm_crtc_state *old_state) 6332048e328SMark Yao { 6342048e328SMark Yao struct vop *vop = to_vop(crtc); 6352048e328SMark Yao 636893b6cadSDaniel Vetter WARN_ON(vop->event); 637893b6cadSDaniel Vetter 638e334d48bSzain wang mutex_lock(&vop->vop_lock); 639b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 6402048e328SMark Yao 6412048e328SMark Yao /* 6421067219bSMark Yao * Vop standby will take effect at end of current frame, 6431067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 6441067219bSMark Yao * 6451067219bSMark Yao * we must wait standby complete when we want to disable aclk, 6461067219bSMark Yao * if not, memory bus maybe dead. 6472048e328SMark Yao */ 6481067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 6491067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 6501067219bSMark Yao 6512048e328SMark Yao spin_lock(&vop->reg_lock); 6522048e328SMark Yao 6539a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6542048e328SMark Yao 6552048e328SMark Yao spin_unlock(&vop->reg_lock); 65652ab7891SMark Yao 6571067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 6582048e328SMark Yao 6591067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6601067219bSMark Yao 6611067219bSMark Yao vop->is_enabled = false; 6621067219bSMark Yao 6631067219bSMark Yao /* 6641067219bSMark Yao * vop standby complete, so iommu detach is safe. 6651067219bSMark Yao */ 6662048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6672048e328SMark Yao 6681067219bSMark Yao clk_disable(vop->dclk); 669e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 6705d82d1a7SMark Yao pm_runtime_put(vop->dev); 671e334d48bSzain wang mutex_unlock(&vop->vop_lock); 672893b6cadSDaniel Vetter 673893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 674893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 675893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 676893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 677893b6cadSDaniel Vetter 678893b6cadSDaniel Vetter crtc->state->event = NULL; 679893b6cadSDaniel Vetter } 6802048e328SMark Yao } 6812048e328SMark Yao 68263ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 6832048e328SMark Yao { 68463ebb9faSMark Yao drm_plane_cleanup(plane); 6852048e328SMark Yao } 6862048e328SMark Yao 68763ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 68863ebb9faSMark Yao struct drm_plane_state *state) 6892048e328SMark Yao { 69063ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 69192915da6SJohn Keeping struct drm_crtc_state *crtc_state; 69263ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 6932048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 6942048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6952048e328SMark Yao int ret; 6964c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 6974c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6984c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 6994c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7002048e328SMark Yao 70163ebb9faSMark Yao if (!crtc || !fb) 702d47a7246STomasz Figa return 0; 70392915da6SJohn Keeping 70492915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 70592915da6SJohn Keeping if (WARN_ON(!crtc_state)) 70692915da6SJohn Keeping return -EINVAL; 70792915da6SJohn Keeping 70881af63a4SVille Syrjälä ret = drm_atomic_helper_check_plane_state(state, crtc_state, 709f9b96be0SVille Syrjälä min_scale, max_scale, 710f9b96be0SVille Syrjälä true, true); 7112048e328SMark Yao if (ret) 7122048e328SMark Yao return ret; 7132048e328SMark Yao 714f9b96be0SVille Syrjälä if (!state->visible) 715d47a7246STomasz Figa return 0; 7162048e328SMark Yao 717438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 718d47a7246STomasz Figa if (ret < 0) 719d47a7246STomasz Figa return ret; 72084c7f8caSMark Yao 72184c7f8caSMark Yao /* 72284c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 72384c7f8caSMark Yao * need align with 2 pixel. 72484c7f8caSMark Yao */ 725d8bd23d9SAyan Kumar Halder if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 726d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 72763ebb9faSMark Yao return -EINVAL; 728d415fb87SMark yao } 72963ebb9faSMark Yao 730677e8bbcSDaniele Castagna if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 731677e8bbcSDaniele Castagna DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 732677e8bbcSDaniele Castagna return -EINVAL; 733677e8bbcSDaniele Castagna } 734677e8bbcSDaniele Castagna 73563ebb9faSMark Yao return 0; 73684c7f8caSMark Yao } 73784c7f8caSMark Yao 73863ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 73963ebb9faSMark Yao struct drm_plane_state *old_state) 74063ebb9faSMark Yao { 74163ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 74263ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 74363ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 7442048e328SMark Yao 74563ebb9faSMark Yao if (!old_state->crtc) 74663ebb9faSMark Yao return; 7472048e328SMark Yao 74863ebb9faSMark Yao spin_lock(&vop->reg_lock); 7492048e328SMark Yao 750e9abc611SJonas Karlman vop_win_disable(vop, win); 7512048e328SMark Yao 75263ebb9faSMark Yao spin_unlock(&vop->reg_lock); 75363ebb9faSMark Yao } 75463ebb9faSMark Yao 75563ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 75663ebb9faSMark Yao struct drm_plane_state *old_state) 75763ebb9faSMark Yao { 75863ebb9faSMark Yao struct drm_plane_state *state = plane->state; 75963ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 76063ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 76163ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 7621c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 76363ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 76463ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 76563ebb9faSMark Yao unsigned int actual_w, actual_h; 76663ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 76763ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 768ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 769ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 77063ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 77163ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 77263ebb9faSMark Yao unsigned long offset; 77363ebb9faSMark Yao dma_addr_t dma_addr; 77463ebb9faSMark Yao uint32_t val; 77563ebb9faSMark Yao bool rb_swap; 77658badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 777d47a7246STomasz Figa int format; 7781c21aa8fSDaniele Castagna int is_yuv = fb->format->is_yuv; 7791c21aa8fSDaniele Castagna int i; 78063ebb9faSMark Yao 78163ebb9faSMark Yao /* 78263ebb9faSMark Yao * can't update plane when vop is disabled. 78363ebb9faSMark Yao */ 7844f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 78563ebb9faSMark Yao return; 78663ebb9faSMark Yao 78763ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 78863ebb9faSMark Yao return; 78963ebb9faSMark Yao 790d47a7246STomasz Figa if (!state->visible) { 79163ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 79263ebb9faSMark Yao return; 79363ebb9faSMark Yao } 79463ebb9faSMark Yao 795957428f9SDaniel Stone obj = fb->obj[0]; 79663ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 79763ebb9faSMark Yao 79863ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 79963ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 80063ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 80163ebb9faSMark Yao 80263ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 80363ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 80463ebb9faSMark Yao 80563ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 80663ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 80763ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 80863ebb9faSMark Yao 809353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 81063ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 811d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 812d47a7246STomasz Figa 813677e8bbcSDaniele Castagna /* 814677e8bbcSDaniele Castagna * For y-mirroring we need to move address 815677e8bbcSDaniele Castagna * to the beginning of the last line. 816677e8bbcSDaniele Castagna */ 817677e8bbcSDaniele Castagna if (state->rotation & DRM_MODE_REFLECT_Y) 818677e8bbcSDaniele Castagna dma_addr += (actual_h - 1) * fb->pitches[0]; 819677e8bbcSDaniele Castagna 820438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 82163ebb9faSMark Yao 82263ebb9faSMark Yao spin_lock(&vop->reg_lock); 82363ebb9faSMark Yao 824d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 825da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 826d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 8271c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 828677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, y_mir_en, 829677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 830677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, x_mir_en, 831677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 8321c21aa8fSDaniele Castagna 8331c21aa8fSDaniele Castagna if (is_yuv) { 834438b74a5SVille Syrjälä int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 835438b74a5SVille Syrjälä int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 836353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 83784c7f8caSMark Yao 838957428f9SDaniel Stone uv_obj = fb->obj[1]; 83984c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 84084c7f8caSMark Yao 84163ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 84263ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 84384c7f8caSMark Yao 84463ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 845da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 84663ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 8471c21aa8fSDaniele Castagna 8481c21aa8fSDaniele Castagna for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 8491c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 8501c21aa8fSDaniele Castagna win_yuv2yuv, 8511c21aa8fSDaniele Castagna y2r_coefficients[i], 8521c21aa8fSDaniele Castagna bt601_yuv2rgb[i]); 8531c21aa8fSDaniele Castagna } 85484c7f8caSMark Yao } 8554c156c21SMark Yao 8564c156c21SMark Yao if (win->phy->scl) 8574c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 85863ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 859438b74a5SVille Syrjälä fb->format->format); 8604c156c21SMark Yao 86163ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 86263ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 86363ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 8644c156c21SMark Yao 865438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 86685a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 8672048e328SMark Yao 86858badaa7SKristian H. Kristensen /* 86958badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 87058badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 87158badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 87258badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 87358badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 87458badaa7SKristian H. Kristensen */ 87558badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 8762048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 8772048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 8782048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 8792048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 8802048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 8812048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 8822048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 8832048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 8842048e328SMark Yao } else { 8852048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 8862048e328SMark Yao } 8872048e328SMark Yao 8882048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 8892048e328SMark Yao spin_unlock(&vop->reg_lock); 8902048e328SMark Yao } 8912048e328SMark Yao 89215609559SEnric Balletbo i Serra static int vop_plane_atomic_async_check(struct drm_plane *plane, 89315609559SEnric Balletbo i Serra struct drm_plane_state *state) 89415609559SEnric Balletbo i Serra { 89515609559SEnric Balletbo i Serra struct vop_win *vop_win = to_vop_win(plane); 89615609559SEnric Balletbo i Serra const struct vop_win_data *win = vop_win->data; 89715609559SEnric Balletbo i Serra int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 89815609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 89915609559SEnric Balletbo i Serra int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 90015609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 90115609559SEnric Balletbo i Serra struct drm_crtc_state *crtc_state; 90215609559SEnric Balletbo i Serra 90315609559SEnric Balletbo i Serra if (plane != state->crtc->cursor) 90415609559SEnric Balletbo i Serra return -EINVAL; 90515609559SEnric Balletbo i Serra 90615609559SEnric Balletbo i Serra if (!plane->state) 90715609559SEnric Balletbo i Serra return -EINVAL; 90815609559SEnric Balletbo i Serra 90915609559SEnric Balletbo i Serra if (!plane->state->fb) 91015609559SEnric Balletbo i Serra return -EINVAL; 91115609559SEnric Balletbo i Serra 91215609559SEnric Balletbo i Serra if (state->state) 91315609559SEnric Balletbo i Serra crtc_state = drm_atomic_get_existing_crtc_state(state->state, 91415609559SEnric Balletbo i Serra state->crtc); 91515609559SEnric Balletbo i Serra else /* Special case for asynchronous cursor updates. */ 91615609559SEnric Balletbo i Serra crtc_state = plane->crtc->state; 91715609559SEnric Balletbo i Serra 91815609559SEnric Balletbo i Serra return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 91915609559SEnric Balletbo i Serra min_scale, max_scale, 92015609559SEnric Balletbo i Serra true, true); 92115609559SEnric Balletbo i Serra } 92215609559SEnric Balletbo i Serra 92315609559SEnric Balletbo i Serra static void vop_plane_atomic_async_update(struct drm_plane *plane, 92415609559SEnric Balletbo i Serra struct drm_plane_state *new_state) 92515609559SEnric Balletbo i Serra { 92615609559SEnric Balletbo i Serra struct vop *vop = to_vop(plane->state->crtc); 92715609559SEnric Balletbo i Serra struct drm_plane_state *plane_state; 92815609559SEnric Balletbo i Serra 92915609559SEnric Balletbo i Serra plane_state = plane->funcs->atomic_duplicate_state(plane); 93015609559SEnric Balletbo i Serra plane_state->crtc_x = new_state->crtc_x; 93115609559SEnric Balletbo i Serra plane_state->crtc_y = new_state->crtc_y; 93215609559SEnric Balletbo i Serra plane_state->crtc_h = new_state->crtc_h; 93315609559SEnric Balletbo i Serra plane_state->crtc_w = new_state->crtc_w; 93415609559SEnric Balletbo i Serra plane_state->src_x = new_state->src_x; 93515609559SEnric Balletbo i Serra plane_state->src_y = new_state->src_y; 93615609559SEnric Balletbo i Serra plane_state->src_h = new_state->src_h; 93715609559SEnric Balletbo i Serra plane_state->src_w = new_state->src_w; 93815609559SEnric Balletbo i Serra 93915609559SEnric Balletbo i Serra if (plane_state->fb != new_state->fb) 94015609559SEnric Balletbo i Serra drm_atomic_set_fb_for_plane(plane_state, new_state->fb); 94115609559SEnric Balletbo i Serra 94215609559SEnric Balletbo i Serra swap(plane_state, plane->state); 94315609559SEnric Balletbo i Serra 94415609559SEnric Balletbo i Serra if (plane->state->fb && plane->state->fb != new_state->fb) { 94515609559SEnric Balletbo i Serra drm_framebuffer_get(plane->state->fb); 94615609559SEnric Balletbo i Serra WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 94715609559SEnric Balletbo i Serra drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb); 94815609559SEnric Balletbo i Serra set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 94915609559SEnric Balletbo i Serra } 95015609559SEnric Balletbo i Serra 95115609559SEnric Balletbo i Serra if (vop->is_enabled) { 95215609559SEnric Balletbo i Serra rockchip_drm_psr_inhibit_get_state(new_state->state); 95315609559SEnric Balletbo i Serra vop_plane_atomic_update(plane, plane->state); 95415609559SEnric Balletbo i Serra spin_lock(&vop->reg_lock); 95515609559SEnric Balletbo i Serra vop_cfg_done(vop); 95615609559SEnric Balletbo i Serra spin_unlock(&vop->reg_lock); 95715609559SEnric Balletbo i Serra rockchip_drm_psr_inhibit_put_state(new_state->state); 95815609559SEnric Balletbo i Serra } 95915609559SEnric Balletbo i Serra 96015609559SEnric Balletbo i Serra plane->funcs->atomic_destroy_state(plane, plane_state); 96115609559SEnric Balletbo i Serra } 96215609559SEnric Balletbo i Serra 96363ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 96463ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 96563ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 96663ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 96715609559SEnric Balletbo i Serra .atomic_async_check = vop_plane_atomic_async_check, 96815609559SEnric Balletbo i Serra .atomic_async_update = vop_plane_atomic_async_update, 96963d5e06aSHeiko Stuebner .prepare_fb = drm_gem_fb_prepare_fb, 97063ebb9faSMark Yao }; 97163ebb9faSMark Yao 9722048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 97363ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 97463ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 9752048e328SMark Yao .destroy = vop_plane_destroy, 976d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 977d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 978d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 9792048e328SMark Yao }; 9802048e328SMark Yao 9812048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 9822048e328SMark Yao { 9832048e328SMark Yao struct vop *vop = to_vop(crtc); 9842048e328SMark Yao unsigned long flags; 9852048e328SMark Yao 98663ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 9872048e328SMark Yao return -EPERM; 9882048e328SMark Yao 9892048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 9902048e328SMark Yao 991fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 992dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 9932048e328SMark Yao 9942048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 9952048e328SMark Yao 9962048e328SMark Yao return 0; 9972048e328SMark Yao } 9982048e328SMark Yao 9992048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 10002048e328SMark Yao { 10012048e328SMark Yao struct vop *vop = to_vop(crtc); 10022048e328SMark Yao unsigned long flags; 10032048e328SMark Yao 100463ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10052048e328SMark Yao return; 100631e980c5SMark Yao 10072048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1008dbb3d944SMark Yao 1009dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1010dbb3d944SMark Yao 10112048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10122048e328SMark Yao } 10132048e328SMark Yao 10142048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 10152048e328SMark Yao const struct drm_display_mode *mode, 10162048e328SMark Yao struct drm_display_mode *adjusted_mode) 10172048e328SMark Yao { 1018b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 1019b59b8de3SChris Zhong 1020b59b8de3SChris Zhong adjusted_mode->clock = 1021b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 1022b59b8de3SChris Zhong 10232048e328SMark Yao return true; 10242048e328SMark Yao } 10252048e328SMark Yao 10260b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 10270b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 10282048e328SMark Yao { 10292048e328SMark Yao struct vop *vop = to_vop(crtc); 1030efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 10314e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 103263ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 10332048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 10342048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 10352048e328SMark Yao u16 htotal = adjusted_mode->htotal; 10362048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 10372048e328SMark Yao u16 hact_end = hact_st + hdisplay; 10382048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 10392048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 10402048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 10412048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 10422048e328SMark Yao u16 vact_end = vact_st + vdisplay; 10430a63bfd0SMark Yao uint32_t pin_pol, val; 104439a9ad8fSSean Paul int ret; 10452048e328SMark Yao 1046e334d48bSzain wang mutex_lock(&vop->vop_lock); 1047e334d48bSzain wang 1048893b6cadSDaniel Vetter WARN_ON(vop->event); 1049893b6cadSDaniel Vetter 105039a9ad8fSSean Paul ret = vop_enable(crtc); 105139a9ad8fSSean Paul if (ret) { 1052e334d48bSzain wang mutex_unlock(&vop->vop_lock); 105339a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 105439a9ad8fSSean Paul return; 105539a9ad8fSSean Paul } 105639a9ad8fSSean Paul 10571a0f7ed3SChris Zhong pin_pol = BIT(DCLK_INVERT); 1058d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1059d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 1060d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1061d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 10629a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 1063cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 10640a63bfd0SMark Yao 10654e257d9eSMark Yao switch (s->output_type) { 10664e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 10679a61c54bSMark yao VOP_REG_SET(vop, output, rgb_en, 1); 10689a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 10694e257d9eSMark Yao break; 10704e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 10719a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 10729a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 10734e257d9eSMark Yao break; 10744e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 10759a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 10769a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 10774e257d9eSMark Yao break; 10784e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 10799a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 10809a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 1081cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 1082cf6d100dSHeiko Stuebner !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 10834e257d9eSMark Yao break; 10841a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 10851a0f7ed3SChris Zhong pin_pol &= ~BIT(DCLK_INVERT); 10869a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 10879a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 10881a0f7ed3SChris Zhong break; 10894e257d9eSMark Yao default: 1090ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1091ee4d7899SSean Paul s->output_type); 10924e257d9eSMark Yao } 1093efd11cc8SMark yao 1094efd11cc8SMark yao /* 1095efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 1096efd11cc8SMark yao */ 1097efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1098efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1099efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 11006bda8112SMark Yao 11016bda8112SMark Yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8) 11026bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 11036bda8112SMark Yao else 11046bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 11056bda8112SMark Yao 11069a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 11072048e328SMark Yao 11089a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 11092048e328SMark Yao val = hact_st << 16; 11102048e328SMark Yao val |= hact_end; 11119a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 11129a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 11132048e328SMark Yao 11149a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 11152048e328SMark Yao val = vact_st << 16; 11162048e328SMark Yao val |= vact_end; 11179a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 11189a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 11192048e328SMark Yao 11209a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1121459b086dSJeffy Chen 11222048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1123ce3887edSMark Yao 11249a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 1125e334d48bSzain wang mutex_unlock(&vop->vop_lock); 11262048e328SMark Yao } 11272048e328SMark Yao 11287caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 11297caecdbeSTomasz Figa { 11307caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 11317caecdbeSTomasz Figa } 11327caecdbeSTomasz Figa 11337caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 11347caecdbeSTomasz Figa { 11357caecdbeSTomasz Figa bool pending; 11367caecdbeSTomasz Figa int ret; 11377caecdbeSTomasz Figa 11387caecdbeSTomasz Figa /* 11397caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 11407caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 11417caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 11427caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 11437caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 11447caecdbeSTomasz Figa * shouldn't exceed microseconds range. 11457caecdbeSTomasz Figa */ 11467caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 11477caecdbeSTomasz Figa !pending, 0, 10 * 1000); 11487caecdbeSTomasz Figa if (ret) 11497caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 11507caecdbeSTomasz Figa 11517caecdbeSTomasz Figa synchronize_irq(vop->irq); 11527caecdbeSTomasz Figa } 11537caecdbeSTomasz Figa 115463ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 115563ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 115663ebb9faSMark Yao { 115747a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1158e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 115963ebb9faSMark Yao struct vop *vop = to_vop(crtc); 116047a7eb45STomasz Figa struct drm_plane *plane; 116147a7eb45STomasz Figa int i; 116263ebb9faSMark Yao 116363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 116463ebb9faSMark Yao return; 116563ebb9faSMark Yao 116663ebb9faSMark Yao spin_lock(&vop->reg_lock); 116763ebb9faSMark Yao 116863ebb9faSMark Yao vop_cfg_done(vop); 116963ebb9faSMark Yao 117063ebb9faSMark Yao spin_unlock(&vop->reg_lock); 11717caecdbeSTomasz Figa 11727caecdbeSTomasz Figa /* 11737caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 11747caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 11757caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 11767caecdbeSTomasz Figa */ 11777caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 117847a7eb45STomasz Figa 117941ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 118041ee4367STomasz Figa if (crtc->state->event) { 118141ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 118241ee4367STomasz Figa WARN_ON(vop->event); 118341ee4367STomasz Figa 118441ee4367STomasz Figa vop->event = crtc->state->event; 118541ee4367STomasz Figa crtc->state->event = NULL; 118641ee4367STomasz Figa } 118741ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 118841ee4367STomasz Figa 1189e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1190e741f2b1SMaarten Lankhorst new_plane_state, i) { 119147a7eb45STomasz Figa if (!old_plane_state->fb) 119247a7eb45STomasz Figa continue; 119347a7eb45STomasz Figa 1194e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 119547a7eb45STomasz Figa continue; 119647a7eb45STomasz Figa 1197adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 11982d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 119947a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 120047a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 120147a7eb45STomasz Figa } 120263ebb9faSMark Yao } 120363ebb9faSMark Yao 12042048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 12052048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 120663ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 12070b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 120864581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 12092048e328SMark Yao }; 12102048e328SMark Yao 12112048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 12122048e328SMark Yao { 12132048e328SMark Yao drm_crtc_cleanup(crtc); 12142048e328SMark Yao } 12152048e328SMark Yao 1216dc0b408fSJohn Keeping static void vop_crtc_reset(struct drm_crtc *crtc) 1217dc0b408fSJohn Keeping { 1218dc0b408fSJohn Keeping if (crtc->state) 1219dc0b408fSJohn Keeping __drm_atomic_helper_crtc_destroy_state(crtc->state); 1220dc0b408fSJohn Keeping kfree(crtc->state); 1221dc0b408fSJohn Keeping 1222dc0b408fSJohn Keeping crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1223dc0b408fSJohn Keeping if (crtc->state) 1224dc0b408fSJohn Keeping crtc->state->crtc = crtc; 1225dc0b408fSJohn Keeping } 1226dc0b408fSJohn Keeping 12274e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 12284e257d9eSMark Yao { 12294e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 12304e257d9eSMark Yao 12314e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 12324e257d9eSMark Yao if (!rockchip_state) 12334e257d9eSMark Yao return NULL; 12344e257d9eSMark Yao 12354e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 12364e257d9eSMark Yao return &rockchip_state->base; 12374e257d9eSMark Yao } 12384e257d9eSMark Yao 12394e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 12404e257d9eSMark Yao struct drm_crtc_state *state) 12414e257d9eSMark Yao { 12424e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 12434e257d9eSMark Yao 1244ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 12454e257d9eSMark Yao kfree(s); 12464e257d9eSMark Yao } 12474e257d9eSMark Yao 12486cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 12493190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 12503190e58dSTomeu Vizoso { 12513190e58dSTomeu Vizoso struct drm_connector *connector; 12522cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 12533190e58dSTomeu Vizoso 12542cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 12552cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 12563190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 12572cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 12583190e58dSTomeu Vizoso return connector; 12593190e58dSTomeu Vizoso } 12602cbeb64fSGustavo Padovan } 12612cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 12623190e58dSTomeu Vizoso 12633190e58dSTomeu Vizoso return NULL; 12643190e58dSTomeu Vizoso } 12653190e58dSTomeu Vizoso 12663190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1267c0811a7dSMahesh Kumar const char *source_name) 12683190e58dSTomeu Vizoso { 12693190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 12703190e58dSTomeu Vizoso struct drm_connector *connector; 12713190e58dSTomeu Vizoso int ret; 12723190e58dSTomeu Vizoso 12733190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 12743190e58dSTomeu Vizoso if (!connector) 12753190e58dSTomeu Vizoso return -EINVAL; 12763190e58dSTomeu Vizoso 12773190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 12783190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 12793190e58dSTomeu Vizoso else if (!source_name) 12803190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 12813190e58dSTomeu Vizoso else 12823190e58dSTomeu Vizoso ret = -EINVAL; 12833190e58dSTomeu Vizoso 12843190e58dSTomeu Vizoso return ret; 12853190e58dSTomeu Vizoso } 1286b8d913c0SMahesh Kumar 1287b8d913c0SMahesh Kumar static int 1288b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1289b8d913c0SMahesh Kumar size_t *values_cnt) 1290b8d913c0SMahesh Kumar { 1291b8d913c0SMahesh Kumar if (source_name && strcmp(source_name, "auto") != 0) 1292b8d913c0SMahesh Kumar return -EINVAL; 1293b8d913c0SMahesh Kumar 1294b8d913c0SMahesh Kumar *values_cnt = 3; 1295b8d913c0SMahesh Kumar return 0; 1296b8d913c0SMahesh Kumar } 1297b8d913c0SMahesh Kumar 12986cca3869SSean Paul #else 12996cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1300c0811a7dSMahesh Kumar const char *source_name) 13016cca3869SSean Paul { 13026cca3869SSean Paul return -ENODEV; 13036cca3869SSean Paul } 1304b8d913c0SMahesh Kumar 1305b8d913c0SMahesh Kumar static int 1306b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1307b8d913c0SMahesh Kumar size_t *values_cnt) 1308b8d913c0SMahesh Kumar { 1309b8d913c0SMahesh Kumar return -ENODEV; 1310b8d913c0SMahesh Kumar } 13116cca3869SSean Paul #endif 13123190e58dSTomeu Vizoso 13132048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 131463ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 131563ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 13162048e328SMark Yao .destroy = vop_crtc_destroy, 1317dc0b408fSJohn Keeping .reset = vop_crtc_reset, 13184e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 13194e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1320c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1321c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 13223190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 1323b8d913c0SMahesh Kumar .verify_crc_source = vop_crtc_verify_crc_source, 13242048e328SMark Yao }; 13252048e328SMark Yao 132647a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 132747a7eb45STomasz Figa { 132847a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 132947a7eb45STomasz Figa struct drm_framebuffer *fb = val; 133047a7eb45STomasz Figa 133147a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1332adedbf03SCihangir Akturk drm_framebuffer_put(fb); 133347a7eb45STomasz Figa } 133447a7eb45STomasz Figa 133563ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 13362048e328SMark Yao { 133763ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 133863ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 13392048e328SMark Yao 13401c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1341893b6cadSDaniel Vetter if (vop->event) { 134263ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 13435b680403SSean Paul drm_crtc_vblank_put(crtc); 1344646ec687STomasz Figa vop->event = NULL; 13455b680403SSean Paul } 13461c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1347893b6cadSDaniel Vetter 134847a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 134947a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 13502048e328SMark Yao } 13512048e328SMark Yao 13522048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 13532048e328SMark Yao { 13542048e328SMark Yao struct vop *vop = data; 1355b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1356dbb3d944SMark Yao uint32_t active_irqs; 13571067219bSMark Yao int ret = IRQ_NONE; 13582048e328SMark Yao 13592048e328SMark Yao /* 13606456314fSSandy Huang * The irq is shared with the iommu. If the runtime-pm state of the 13616456314fSSandy Huang * vop-device is disabled the irq has to be targeted at the iommu. 13626456314fSSandy Huang */ 13636456314fSSandy Huang if (!pm_runtime_get_if_in_use(vop->dev)) 13646456314fSSandy Huang return IRQ_NONE; 13656456314fSSandy Huang 13666456314fSSandy Huang if (vop_core_clks_enable(vop)) { 13676456314fSSandy Huang DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 13686456314fSSandy Huang goto out; 13696456314fSSandy Huang } 13706456314fSSandy Huang 13716456314fSSandy Huang /* 1372dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 13732048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 13742048e328SMark Yao */ 13751c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1376dbb3d944SMark Yao 1377dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 13782048e328SMark Yao /* Clear all active interrupt sources */ 13792048e328SMark Yao if (active_irqs) 1380dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1381dbb3d944SMark Yao 13821c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 13832048e328SMark Yao 13842048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 13852048e328SMark Yao if (!active_irqs) 13866456314fSSandy Huang goto out_disable; 13872048e328SMark Yao 13881067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 13891067219bSMark Yao complete(&vop->dsp_hold_completion); 13901067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 13911067219bSMark Yao ret = IRQ_HANDLED; 13922048e328SMark Yao } 13932048e328SMark Yao 139469c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 139569c34e41SYakir Yang complete(&vop->line_flag_completion); 139669c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 139769c34e41SYakir Yang ret = IRQ_HANDLED; 139869c34e41SYakir Yang } 139969c34e41SYakir Yang 14001067219bSMark Yao if (active_irqs & FS_INTR) { 1401b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 140263ebb9faSMark Yao vop_handle_vblank(vop); 14031067219bSMark Yao active_irqs &= ~FS_INTR; 140463ebb9faSMark Yao ret = IRQ_HANDLED; 14051067219bSMark Yao } 14062048e328SMark Yao 14071067219bSMark Yao /* Unhandled irqs are spurious. */ 14081067219bSMark Yao if (active_irqs) 1409ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1410ee4d7899SSean Paul active_irqs); 14111067219bSMark Yao 14126456314fSSandy Huang out_disable: 14136456314fSSandy Huang vop_core_clks_disable(vop); 14146456314fSSandy Huang out: 14156456314fSSandy Huang pm_runtime_put(vop->dev); 14161067219bSMark Yao return ret; 14172048e328SMark Yao } 14182048e328SMark Yao 1419677e8bbcSDaniele Castagna static void vop_plane_add_properties(struct drm_plane *plane, 1420677e8bbcSDaniele Castagna const struct vop_win_data *win_data) 1421677e8bbcSDaniele Castagna { 1422677e8bbcSDaniele Castagna unsigned int flags = 0; 1423677e8bbcSDaniele Castagna 1424677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1425677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1426677e8bbcSDaniele Castagna if (flags) 1427677e8bbcSDaniele Castagna drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1428677e8bbcSDaniele Castagna DRM_MODE_ROTATE_0 | flags); 1429677e8bbcSDaniele Castagna } 1430677e8bbcSDaniele Castagna 14312048e328SMark Yao static int vop_create_crtc(struct vop *vop) 14322048e328SMark Yao { 14332048e328SMark Yao const struct vop_data *vop_data = vop->data; 14342048e328SMark Yao struct device *dev = vop->dev; 14352048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1436328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 14372048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 14382048e328SMark Yao struct device_node *port; 14392048e328SMark Yao int ret; 14402048e328SMark Yao int i; 14412048e328SMark Yao 14422048e328SMark Yao /* 14432048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 14442048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 14452048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 14462048e328SMark Yao */ 14472048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14482048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14492048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 14502048e328SMark Yao 14512048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 14522048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 14532048e328SMark Yao continue; 14542048e328SMark Yao 14552048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 14562048e328SMark Yao 0, &vop_plane_funcs, 14572048e328SMark Yao win_data->phy->data_formats, 14582048e328SMark Yao win_data->phy->nformats, 1459e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 14602048e328SMark Yao if (ret) { 1461ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1462ee4d7899SSean Paul ret); 14632048e328SMark Yao goto err_cleanup_planes; 14642048e328SMark Yao } 14652048e328SMark Yao 14662048e328SMark Yao plane = &vop_win->base; 146763ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 1468677e8bbcSDaniele Castagna vop_plane_add_properties(plane, win_data); 14692048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 14702048e328SMark Yao primary = plane; 14712048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 14722048e328SMark Yao cursor = plane; 14732048e328SMark Yao } 14742048e328SMark Yao 14752048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1476f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 14772048e328SMark Yao if (ret) 1478328b51c0SDouglas Anderson goto err_cleanup_planes; 14792048e328SMark Yao 14802048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 14812048e328SMark Yao 14822048e328SMark Yao /* 14832048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 14842048e328SMark Yao * to the newly created crtc. 14852048e328SMark Yao */ 14862048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14872048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14882048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 1489a3e77e16SVille Syrjälä unsigned long possible_crtcs = drm_crtc_mask(crtc); 14902048e328SMark Yao 14912048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 14922048e328SMark Yao continue; 14932048e328SMark Yao 14942048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 14952048e328SMark Yao possible_crtcs, 14962048e328SMark Yao &vop_plane_funcs, 14972048e328SMark Yao win_data->phy->data_formats, 14982048e328SMark Yao win_data->phy->nformats, 1499e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 15002048e328SMark Yao if (ret) { 1501ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1502ee4d7899SSean Paul ret); 15032048e328SMark Yao goto err_cleanup_crtc; 15042048e328SMark Yao } 150563ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1506677e8bbcSDaniele Castagna vop_plane_add_properties(&vop_win->base, win_data); 15072048e328SMark Yao } 15082048e328SMark Yao 15092048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 15102048e328SMark Yao if (!port) { 15114bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 15124bf99144SRob Herring dev->of_node); 1513328b51c0SDouglas Anderson ret = -ENOENT; 15142048e328SMark Yao goto err_cleanup_crtc; 15152048e328SMark Yao } 15162048e328SMark Yao 151747a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 151847a7eb45STomasz Figa vop_fb_unref_worker); 151947a7eb45STomasz Figa 15201067219bSMark Yao init_completion(&vop->dsp_hold_completion); 152169c34e41SYakir Yang init_completion(&vop->line_flag_completion); 15222048e328SMark Yao crtc->port = port; 15232048e328SMark Yao 15242048e328SMark Yao return 0; 15252048e328SMark Yao 15262048e328SMark Yao err_cleanup_crtc: 15272048e328SMark Yao drm_crtc_cleanup(crtc); 15282048e328SMark Yao err_cleanup_planes: 1529328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1530328b51c0SDouglas Anderson head) 15312048e328SMark Yao drm_plane_cleanup(plane); 15322048e328SMark Yao return ret; 15332048e328SMark Yao } 15342048e328SMark Yao 15352048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 15362048e328SMark Yao { 15372048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1538328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1539328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 15402048e328SMark Yao 15412048e328SMark Yao of_node_put(crtc->port); 1542328b51c0SDouglas Anderson 1543328b51c0SDouglas Anderson /* 1544328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1545328b51c0SDouglas Anderson * 1546328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1547328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1548328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1549328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1550328b51c0SDouglas Anderson */ 1551328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1552328b51c0SDouglas Anderson head) 1553328b51c0SDouglas Anderson vop_plane_destroy(plane); 1554328b51c0SDouglas Anderson 1555328b51c0SDouglas Anderson /* 1556328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1557328b51c0SDouglas Anderson * references the CRTC. 1558328b51c0SDouglas Anderson */ 15592048e328SMark Yao drm_crtc_cleanup(crtc); 156047a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 15612048e328SMark Yao } 15622048e328SMark Yao 15632048e328SMark Yao static int vop_initial(struct vop *vop) 15642048e328SMark Yao { 15652048e328SMark Yao const struct vop_data *vop_data = vop->data; 15662048e328SMark Yao struct reset_control *ahb_rst; 15672048e328SMark Yao int i, ret; 15682048e328SMark Yao 15692048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 15702048e328SMark Yao if (IS_ERR(vop->hclk)) { 1571d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 15722048e328SMark Yao return PTR_ERR(vop->hclk); 15732048e328SMark Yao } 15742048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 15752048e328SMark Yao if (IS_ERR(vop->aclk)) { 1576d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 15772048e328SMark Yao return PTR_ERR(vop->aclk); 15782048e328SMark Yao } 15792048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 15802048e328SMark Yao if (IS_ERR(vop->dclk)) { 1581d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 15822048e328SMark Yao return PTR_ERR(vop->dclk); 15832048e328SMark Yao } 15842048e328SMark Yao 15855e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 15865e570373SJeffy Chen if (ret < 0) { 1587d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 15885e570373SJeffy Chen return ret; 15895e570373SJeffy Chen } 15905e570373SJeffy Chen 15912048e328SMark Yao ret = clk_prepare(vop->dclk); 15922048e328SMark Yao if (ret < 0) { 1593d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 15945e570373SJeffy Chen goto err_put_pm_runtime; 15952048e328SMark Yao } 15962048e328SMark Yao 1597d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1598d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 15992048e328SMark Yao if (ret < 0) { 1600d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 16012048e328SMark Yao goto err_unprepare_dclk; 16022048e328SMark Yao } 16032048e328SMark Yao 1604d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 16052048e328SMark Yao if (ret < 0) { 1606d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1607d7b53fd9SSjoerd Simons goto err_disable_hclk; 16082048e328SMark Yao } 1609d7b53fd9SSjoerd Simons 16102048e328SMark Yao /* 16112048e328SMark Yao * do hclk_reset, reset all vop registers. 16122048e328SMark Yao */ 16132048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 16142048e328SMark Yao if (IS_ERR(ahb_rst)) { 1615d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 16162048e328SMark Yao ret = PTR_ERR(ahb_rst); 1617d7b53fd9SSjoerd Simons goto err_disable_aclk; 16182048e328SMark Yao } 16192048e328SMark Yao reset_control_assert(ahb_rst); 16202048e328SMark Yao usleep_range(10, 20); 16212048e328SMark Yao reset_control_deassert(ahb_rst); 16222048e328SMark Yao 16235f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 16245f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 16255f9e93feSMarc Zyngier 162676f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 162776f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 16282048e328SMark Yao 16299a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 16309a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 16312048e328SMark Yao 16322048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16332048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 16349dd2aca4SMark yao int channel = i * 2 + 1; 16352048e328SMark Yao 16369dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1637e9abc611SJonas Karlman vop_win_disable(vop, win); 163860b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 16392048e328SMark Yao } 16402048e328SMark Yao 16412048e328SMark Yao vop_cfg_done(vop); 16422048e328SMark Yao 16432048e328SMark Yao /* 16442048e328SMark Yao * do dclk_reset, let all config take affect. 16452048e328SMark Yao */ 16462048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 16472048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1648d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 16492048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1650d7b53fd9SSjoerd Simons goto err_disable_aclk; 16512048e328SMark Yao } 16522048e328SMark Yao reset_control_assert(vop->dclk_rst); 16532048e328SMark Yao usleep_range(10, 20); 16542048e328SMark Yao reset_control_deassert(vop->dclk_rst); 16552048e328SMark Yao 16562048e328SMark Yao clk_disable(vop->hclk); 1657d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 16582048e328SMark Yao 165931e980c5SMark Yao vop->is_enabled = false; 16602048e328SMark Yao 16615e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 16625e570373SJeffy Chen 16632048e328SMark Yao return 0; 16642048e328SMark Yao 1665d7b53fd9SSjoerd Simons err_disable_aclk: 1666d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 16672048e328SMark Yao err_disable_hclk: 1668d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 16692048e328SMark Yao err_unprepare_dclk: 16702048e328SMark Yao clk_unprepare(vop->dclk); 16715e570373SJeffy Chen err_put_pm_runtime: 16725e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 16732048e328SMark Yao return ret; 16742048e328SMark Yao } 16752048e328SMark Yao 16762048e328SMark Yao /* 16772048e328SMark Yao * Initialize the vop->win array elements. 16782048e328SMark Yao */ 16792048e328SMark Yao static void vop_win_init(struct vop *vop) 16802048e328SMark Yao { 16812048e328SMark Yao const struct vop_data *vop_data = vop->data; 16822048e328SMark Yao unsigned int i; 16832048e328SMark Yao 16842048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16852048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 16862048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 16872048e328SMark Yao 16882048e328SMark Yao vop_win->data = win_data; 16892048e328SMark Yao vop_win->vop = vop; 1690ce6912b4SHeiko Stuebner 1691ce6912b4SHeiko Stuebner if (vop_data->win_yuv2yuv) 16921c21aa8fSDaniele Castagna vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 16932048e328SMark Yao } 16942048e328SMark Yao } 16952048e328SMark Yao 169669c34e41SYakir Yang /** 1697459b086dSJeffy Chen * rockchip_drm_wait_vact_end 169869c34e41SYakir Yang * @crtc: CRTC to enable line flag 169969c34e41SYakir Yang * @mstimeout: millisecond for timeout 170069c34e41SYakir Yang * 1701459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 170269c34e41SYakir Yang * 170369c34e41SYakir Yang * Returns: 170469c34e41SYakir Yang * Zero on success, negative errno on failure. 170569c34e41SYakir Yang */ 1706459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 170769c34e41SYakir Yang { 170869c34e41SYakir Yang struct vop *vop = to_vop(crtc); 170969c34e41SYakir Yang unsigned long jiffies_left; 1710e334d48bSzain wang int ret = 0; 171169c34e41SYakir Yang 171269c34e41SYakir Yang if (!crtc || !vop->is_enabled) 171369c34e41SYakir Yang return -ENODEV; 171469c34e41SYakir Yang 1715e334d48bSzain wang mutex_lock(&vop->vop_lock); 1716e334d48bSzain wang if (mstimeout <= 0) { 1717e334d48bSzain wang ret = -EINVAL; 1718e334d48bSzain wang goto out; 1719e334d48bSzain wang } 172069c34e41SYakir Yang 1721e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 1722e334d48bSzain wang ret = -EBUSY; 1723e334d48bSzain wang goto out; 1724e334d48bSzain wang } 172569c34e41SYakir Yang 172669c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1727459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 172869c34e41SYakir Yang 172969c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 173069c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 173169c34e41SYakir Yang vop_line_flag_irq_disable(vop); 173269c34e41SYakir Yang 173369c34e41SYakir Yang if (jiffies_left == 0) { 1734d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1735e334d48bSzain wang ret = -ETIMEDOUT; 1736e334d48bSzain wang goto out; 173769c34e41SYakir Yang } 173869c34e41SYakir Yang 1739e334d48bSzain wang out: 1740e334d48bSzain wang mutex_unlock(&vop->vop_lock); 1741e334d48bSzain wang return ret; 174269c34e41SYakir Yang } 1743459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 174469c34e41SYakir Yang 17452048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 17462048e328SMark Yao { 17472048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 17482048e328SMark Yao const struct vop_data *vop_data; 17492048e328SMark Yao struct drm_device *drm_dev = data; 17502048e328SMark Yao struct vop *vop; 17512048e328SMark Yao struct resource *res; 17523ea68922SHeiko Stuebner int ret, irq; 17532048e328SMark Yao 1754a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 17552048e328SMark Yao if (!vop_data) 17562048e328SMark Yao return -ENODEV; 17572048e328SMark Yao 17582048e328SMark Yao /* Allocate vop struct and its vop_win array */ 175929adeb4fSGustavo A. R. Silva vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 176029adeb4fSGustavo A. R. Silva GFP_KERNEL); 17612048e328SMark Yao if (!vop) 17622048e328SMark Yao return -ENOMEM; 17632048e328SMark Yao 17642048e328SMark Yao vop->dev = dev; 17652048e328SMark Yao vop->data = vop_data; 17662048e328SMark Yao vop->drm_dev = drm_dev; 17672048e328SMark Yao dev_set_drvdata(dev, vop); 17682048e328SMark Yao 17692048e328SMark Yao vop_win_init(vop); 17702048e328SMark Yao 17712048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 17722048e328SMark Yao vop->len = resource_size(res); 17732048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 17742048e328SMark Yao if (IS_ERR(vop->regs)) 17752048e328SMark Yao return PTR_ERR(vop->regs); 17762048e328SMark Yao 17772048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 17782048e328SMark Yao if (!vop->regsbak) 17792048e328SMark Yao return -ENOMEM; 17802048e328SMark Yao 17813ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 17823ea68922SHeiko Stuebner if (irq < 0) { 1783d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 17843ea68922SHeiko Stuebner return irq; 17852048e328SMark Yao } 17863ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 17872048e328SMark Yao 17882048e328SMark Yao spin_lock_init(&vop->reg_lock); 17892048e328SMark Yao spin_lock_init(&vop->irq_lock); 1790e334d48bSzain wang mutex_init(&vop->vop_lock); 17912048e328SMark Yao 17922048e328SMark Yao ret = vop_create_crtc(vop); 17932048e328SMark Yao if (ret) 17945f9e93feSMarc Zyngier return ret; 17952048e328SMark Yao 17962048e328SMark Yao pm_runtime_enable(&pdev->dev); 17975182c1a5SYakir Yang 17985e570373SJeffy Chen ret = vop_initial(vop); 17995e570373SJeffy Chen if (ret < 0) { 1800d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 1801d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 18025e570373SJeffy Chen goto err_disable_pm_runtime; 18035e570373SJeffy Chen } 18045e570373SJeffy Chen 18055f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 18065f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 18075f9e93feSMarc Zyngier if (ret) 18085f9e93feSMarc Zyngier goto err_disable_pm_runtime; 18095f9e93feSMarc Zyngier 18101f0f0151SSandy Huang if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 18111f0f0151SSandy Huang vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 18121f0f0151SSandy Huang if (IS_ERR(vop->rgb)) { 18131f0f0151SSandy Huang ret = PTR_ERR(vop->rgb); 18141f0f0151SSandy Huang goto err_disable_pm_runtime; 18151f0f0151SSandy Huang } 18161f0f0151SSandy Huang } 18171f0f0151SSandy Huang 18182048e328SMark Yao return 0; 18198c763c9bSSean Paul 18205e570373SJeffy Chen err_disable_pm_runtime: 18215e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 18225e570373SJeffy Chen vop_destroy_crtc(vop); 18238c763c9bSSean Paul return ret; 18242048e328SMark Yao } 18252048e328SMark Yao 18262048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 18272048e328SMark Yao { 18282048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 18292048e328SMark Yao 18301f0f0151SSandy Huang if (vop->rgb) 18311f0f0151SSandy Huang rockchip_rgb_fini(vop->rgb); 18321f0f0151SSandy Huang 18332048e328SMark Yao pm_runtime_disable(dev); 18342048e328SMark Yao vop_destroy_crtc(vop); 1835ec6e7767SJeffy Chen 1836ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 1837ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 1838ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 18392048e328SMark Yao } 18402048e328SMark Yao 1841a67719d1SMark Yao const struct component_ops vop_component_ops = { 18422048e328SMark Yao .bind = vop_bind, 18432048e328SMark Yao .unbind = vop_unbind, 18442048e328SMark Yao }; 184554255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1846