12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 2047a7eb45STomasz Figa #include <drm/drm_flip_work.h> 212048e328SMark Yao #include <drm/drm_plane_helper.h> 226cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 233190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 246cca3869SSean Paul #endif 252048e328SMark Yao 262048e328SMark Yao #include <linux/kernel.h> 2700fe6148SPaul Gortmaker #include <linux/module.h> 282048e328SMark Yao #include <linux/platform_device.h> 292048e328SMark Yao #include <linux/clk.h> 307caecdbeSTomasz Figa #include <linux/iopoll.h> 312048e328SMark Yao #include <linux/of.h> 322048e328SMark Yao #include <linux/of_device.h> 332048e328SMark Yao #include <linux/pm_runtime.h> 342048e328SMark Yao #include <linux/component.h> 352048e328SMark Yao 362048e328SMark Yao #include <linux/reset.h> 372048e328SMark Yao #include <linux/delay.h> 382048e328SMark Yao 392048e328SMark Yao #include "rockchip_drm_drv.h" 402048e328SMark Yao #include "rockchip_drm_gem.h" 412048e328SMark Yao #include "rockchip_drm_fb.h" 425182c1a5SYakir Yang #include "rockchip_drm_psr.h" 432048e328SMark Yao #include "rockchip_drm_vop.h" 442048e328SMark Yao 452048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 469a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 474c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 489a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 491194fffbSMark Yao #define VOP_SCL_SET_EXT(x, win, name, v) \ 509a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 519a61c54bSMark yao win->base, ~0, v, #name) 52ac6560dfSMark yao 53ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 549a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 559a61c54bSMark yao 569a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 579a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58ac6560dfSMark yao 59dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60dbb3d944SMark Yao do { \ 61c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 62dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 64dbb3d944SMark Yao reg |= (v) << i; \ 65c7647f86SJohn Keeping mask |= 1 << i; \ 66dbb3d944SMark Yao } \ 67c7647f86SJohn Keeping } \ 68ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69dbb3d944SMark Yao } while (0) 70dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 71dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 72dbb3d944SMark Yao 732048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 749a61c54bSMark yao vop_read_reg(x, win->offset, win->phy->name) 752048e328SMark Yao 762048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 772048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 782048e328SMark Yao 792048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 802048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 812048e328SMark Yao 8247a7eb45STomasz Figa enum vop_pending { 8347a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 8447a7eb45STomasz Figa }; 8547a7eb45STomasz Figa 862048e328SMark Yao struct vop_win { 872048e328SMark Yao struct drm_plane base; 882048e328SMark Yao const struct vop_win_data *data; 892048e328SMark Yao struct vop *vop; 902048e328SMark Yao }; 912048e328SMark Yao 922048e328SMark Yao struct vop { 932048e328SMark Yao struct drm_crtc crtc; 942048e328SMark Yao struct device *dev; 952048e328SMark Yao struct drm_device *drm_dev; 9631e980c5SMark Yao bool is_enabled; 972048e328SMark Yao 982048e328SMark Yao /* mutex vsync_ work */ 992048e328SMark Yao struct mutex vsync_mutex; 1002048e328SMark Yao bool vsync_work_pending; 1011067219bSMark Yao struct completion dsp_hold_completion; 1024f9d39a7SDaniel Vetter 1034f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 10463ebb9faSMark Yao struct drm_pending_vblank_event *event; 1052048e328SMark Yao 10647a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 10747a7eb45STomasz Figa unsigned long pending; 10847a7eb45STomasz Figa 10969c34e41SYakir Yang struct completion line_flag_completion; 11069c34e41SYakir Yang 1112048e328SMark Yao const struct vop_data *data; 1122048e328SMark Yao 1132048e328SMark Yao uint32_t *regsbak; 1142048e328SMark Yao void __iomem *regs; 1152048e328SMark Yao 1162048e328SMark Yao /* physical map length of vop register */ 1172048e328SMark Yao uint32_t len; 1182048e328SMark Yao 1192048e328SMark Yao /* one time only one process allowed to config the register */ 1202048e328SMark Yao spinlock_t reg_lock; 1212048e328SMark Yao /* lock vop irq reg */ 1222048e328SMark Yao spinlock_t irq_lock; 1232048e328SMark Yao 1242048e328SMark Yao unsigned int irq; 1252048e328SMark Yao 1262048e328SMark Yao /* vop AHP clk */ 1272048e328SMark Yao struct clk *hclk; 1282048e328SMark Yao /* vop dclk */ 1292048e328SMark Yao struct clk *dclk; 1302048e328SMark Yao /* vop share memory frequency */ 1312048e328SMark Yao struct clk *aclk; 1322048e328SMark Yao 1332048e328SMark Yao /* vop dclk reset */ 1342048e328SMark Yao struct reset_control *dclk_rst; 1352048e328SMark Yao 1362048e328SMark Yao struct vop_win win[]; 1372048e328SMark Yao }; 1382048e328SMark Yao 1392048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1402048e328SMark Yao { 1412048e328SMark Yao writel(v, vop->regs + offset); 1422048e328SMark Yao vop->regsbak[offset >> 2] = v; 1432048e328SMark Yao } 1442048e328SMark Yao 1452048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1462048e328SMark Yao { 1472048e328SMark Yao return readl(vop->regs + offset); 1482048e328SMark Yao } 1492048e328SMark Yao 1502048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1512048e328SMark Yao const struct vop_reg *reg) 1522048e328SMark Yao { 1532048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1542048e328SMark Yao } 1552048e328SMark Yao 1569a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 1579a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 1589a61c54bSMark yao const char *reg_name) 1592048e328SMark Yao { 1609a61c54bSMark yao int offset, mask, shift; 161d49463ecSMark Yao 1629a61c54bSMark yao if (!reg || !reg->mask) { 1639a61c54bSMark yao dev_dbg(vop->dev, "Warning: not support %s\n", reg_name); 1649a61c54bSMark yao return; 1659a61c54bSMark yao } 1669a61c54bSMark yao 1679a61c54bSMark yao offset = reg->offset + _offset; 1689a61c54bSMark yao mask = reg->mask & _mask; 1699a61c54bSMark yao shift = reg->shift; 1709a61c54bSMark yao 1719a61c54bSMark yao if (reg->write_mask) { 172d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 173d49463ecSMark Yao } else { 1742048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1752048e328SMark Yao 176d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 177d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 1782048e328SMark Yao } 1792048e328SMark Yao 1809a61c54bSMark yao if (reg->relaxed) 181d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 182d49463ecSMark Yao else 183d49463ecSMark Yao writel(v, vop->regs + offset); 1842048e328SMark Yao } 1852048e328SMark Yao 186dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 187dbb3d944SMark Yao const struct vop_reg *reg, int type) 188dbb3d944SMark Yao { 189dbb3d944SMark Yao uint32_t i, ret = 0; 190dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 191dbb3d944SMark Yao 192dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 193dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 194dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 195dbb3d944SMark Yao } 196dbb3d944SMark Yao 197dbb3d944SMark Yao return ret; 198dbb3d944SMark Yao } 199dbb3d944SMark Yao 2000cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2010cf33fe3SMark Yao { 2029a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2030cf33fe3SMark Yao } 2040cf33fe3SMark Yao 20585a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 20685a359f2STomasz Figa { 20785a359f2STomasz Figa switch (format) { 20885a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 20985a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 21085a359f2STomasz Figa case DRM_FORMAT_BGR888: 21185a359f2STomasz Figa case DRM_FORMAT_BGR565: 21285a359f2STomasz Figa return true; 21385a359f2STomasz Figa default: 21485a359f2STomasz Figa return false; 21585a359f2STomasz Figa } 21685a359f2STomasz Figa } 21785a359f2STomasz Figa 2182048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2192048e328SMark Yao { 2202048e328SMark Yao switch (format) { 2212048e328SMark Yao case DRM_FORMAT_XRGB8888: 2222048e328SMark Yao case DRM_FORMAT_ARGB8888: 22385a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 22485a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2252048e328SMark Yao return VOP_FMT_ARGB8888; 2262048e328SMark Yao case DRM_FORMAT_RGB888: 22785a359f2STomasz Figa case DRM_FORMAT_BGR888: 2282048e328SMark Yao return VOP_FMT_RGB888; 2292048e328SMark Yao case DRM_FORMAT_RGB565: 23085a359f2STomasz Figa case DRM_FORMAT_BGR565: 2312048e328SMark Yao return VOP_FMT_RGB565; 2322048e328SMark Yao case DRM_FORMAT_NV12: 2332048e328SMark Yao return VOP_FMT_YUV420SP; 2342048e328SMark Yao case DRM_FORMAT_NV16: 2352048e328SMark Yao return VOP_FMT_YUV422SP; 2362048e328SMark Yao case DRM_FORMAT_NV24: 2372048e328SMark Yao return VOP_FMT_YUV444SP; 2382048e328SMark Yao default: 239ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2402048e328SMark Yao return -EINVAL; 2412048e328SMark Yao } 2422048e328SMark Yao } 2432048e328SMark Yao 24484c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 24584c7f8caSMark Yao { 24684c7f8caSMark Yao switch (format) { 24784c7f8caSMark Yao case DRM_FORMAT_NV12: 24884c7f8caSMark Yao case DRM_FORMAT_NV16: 24984c7f8caSMark Yao case DRM_FORMAT_NV24: 25084c7f8caSMark Yao return true; 25184c7f8caSMark Yao default: 25284c7f8caSMark Yao return false; 25384c7f8caSMark Yao } 25484c7f8caSMark Yao } 25584c7f8caSMark Yao 2562048e328SMark Yao static bool is_alpha_support(uint32_t format) 2572048e328SMark Yao { 2582048e328SMark Yao switch (format) { 2592048e328SMark Yao case DRM_FORMAT_ARGB8888: 26085a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2612048e328SMark Yao return true; 2622048e328SMark Yao default: 2632048e328SMark Yao return false; 2642048e328SMark Yao } 2652048e328SMark Yao } 2662048e328SMark Yao 2674c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2684c156c21SMark Yao uint32_t dst, bool is_horizontal, 2694c156c21SMark Yao int vsu_mode, int *vskiplines) 2704c156c21SMark Yao { 2714c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2724c156c21SMark Yao 2734c156c21SMark Yao if (is_horizontal) { 2744c156c21SMark Yao if (mode == SCALE_UP) 2754c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2764c156c21SMark Yao else if (mode == SCALE_DOWN) 2774c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2784c156c21SMark Yao } else { 2794c156c21SMark Yao if (mode == SCALE_UP) { 2804c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2814c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2824c156c21SMark Yao else 2834c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2844c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2854c156c21SMark Yao if (vskiplines) { 2864c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 2874c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 2884c156c21SMark Yao *vskiplines); 2894c156c21SMark Yao } else { 2904c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2914c156c21SMark Yao } 2924c156c21SMark Yao } 2934c156c21SMark Yao } 2944c156c21SMark Yao 2954c156c21SMark Yao return val; 2964c156c21SMark Yao } 2974c156c21SMark Yao 2984c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 2994c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3004c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 3014c156c21SMark Yao { 3024c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3034c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3044c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 3054c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 3064c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 3074c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 3084c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 3094c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 3104c156c21SMark Yao uint16_t vsu_mode; 3114c156c21SMark Yao uint16_t lb_mode; 3124c156c21SMark Yao uint32_t val; 3132db00cf5SMark Yao int vskiplines = 0; 3144c156c21SMark Yao 3154c156c21SMark Yao if (dst_w > 3840) { 316ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3174c156c21SMark Yao return; 3184c156c21SMark Yao } 3194c156c21SMark Yao 3201194fffbSMark Yao if (!win->phy->scl->ext) { 3211194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3221194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3231194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3241194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3251194fffbSMark Yao if (is_yuv) { 3261194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 327ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3281194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 329ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3301194fffbSMark Yao } 3311194fffbSMark Yao return; 3321194fffbSMark Yao } 3331194fffbSMark Yao 3344c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3354c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3364c156c21SMark Yao 3374c156c21SMark Yao if (is_yuv) { 3384c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3394c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3404c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3414c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3424c156c21SMark Yao else 3434c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3444c156c21SMark Yao } else { 3454c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3464c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3474c156c21SMark Yao else 3484c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3494c156c21SMark Yao } 3504c156c21SMark Yao 3511194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3524c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3534c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 354ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3554c156c21SMark Yao return; 3564c156c21SMark Yao } 3574c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 358ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3594c156c21SMark Yao return; 3604c156c21SMark Yao } 3614c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3624c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3634c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3644c156c21SMark Yao } else { 3654c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3664c156c21SMark Yao } 3674c156c21SMark Yao 3684c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3694c156c21SMark Yao true, 0, NULL); 3704c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3714c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3724c156c21SMark Yao false, vsu_mode, &vskiplines); 3734c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3744c156c21SMark Yao 3751194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3761194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3774c156c21SMark Yao 3781194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3791194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3801194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3811194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3821194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3834c156c21SMark Yao if (is_yuv) { 3844c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3854c156c21SMark Yao dst_w, true, 0, NULL); 3864c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 3874c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 3884c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 3894c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 3904c156c21SMark Yao 3911194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 3921194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 3931194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 3941194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 3951194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 3961194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 3971194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 3984c156c21SMark Yao } 3994c156c21SMark Yao } 4004c156c21SMark Yao 4011067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4021067219bSMark Yao { 4031067219bSMark Yao unsigned long flags; 4041067219bSMark Yao 4051067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4061067219bSMark Yao return; 4071067219bSMark Yao 4081067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4091067219bSMark Yao 410fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 411dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4121067219bSMark Yao 4131067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4141067219bSMark Yao } 4151067219bSMark Yao 4161067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4171067219bSMark Yao { 4181067219bSMark Yao unsigned long flags; 4191067219bSMark Yao 4201067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4211067219bSMark Yao return; 4221067219bSMark Yao 4231067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4241067219bSMark Yao 425dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4261067219bSMark Yao 4271067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4281067219bSMark Yao } 4291067219bSMark Yao 43069c34e41SYakir Yang /* 43169c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 43269c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 43369c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 43469c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 43569c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 43669c34e41SYakir Yang * 43769c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 43869c34e41SYakir Yang * Interrupts 43969c34e41SYakir Yang * LINE_FLAG -------------------------------+ 44069c34e41SYakir Yang * FRAME_SYNC ----+ | 44169c34e41SYakir Yang * | | 44269c34e41SYakir Yang * v v 44369c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 44469c34e41SYakir Yang * ^ ^ ^ ^ 44569c34e41SYakir Yang * | | | | 44669c34e41SYakir Yang * | | | | 44769c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 44869c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 44969c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 45069c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 45169c34e41SYakir Yang */ 45269c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 45369c34e41SYakir Yang { 45469c34e41SYakir Yang uint32_t line_flag_irq; 45569c34e41SYakir Yang unsigned long flags; 45669c34e41SYakir Yang 45769c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 45869c34e41SYakir Yang 45969c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 46069c34e41SYakir Yang 46169c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 46269c34e41SYakir Yang 46369c34e41SYakir Yang return !!line_flag_irq; 46469c34e41SYakir Yang } 46569c34e41SYakir Yang 466459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 46769c34e41SYakir Yang { 46869c34e41SYakir Yang unsigned long flags; 46969c34e41SYakir Yang 47069c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 47169c34e41SYakir Yang return; 47269c34e41SYakir Yang 47369c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 47469c34e41SYakir Yang 475fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 47669c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 47769c34e41SYakir Yang 47869c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 47969c34e41SYakir Yang } 48069c34e41SYakir Yang 48169c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 48269c34e41SYakir Yang { 48369c34e41SYakir Yang unsigned long flags; 48469c34e41SYakir Yang 48569c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 48669c34e41SYakir Yang return; 48769c34e41SYakir Yang 48869c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 48969c34e41SYakir Yang 49069c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 49169c34e41SYakir Yang 49269c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 49369c34e41SYakir Yang } 49469c34e41SYakir Yang 49539a9ad8fSSean Paul static int vop_enable(struct drm_crtc *crtc) 4962048e328SMark Yao { 4972048e328SMark Yao struct vop *vop = to_vop(crtc); 4982048e328SMark Yao int ret; 4992048e328SMark Yao 5005d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5015d82d1a7SMark Yao if (ret < 0) { 5025d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 5035e570373SJeffy Chen return ret; 5045d82d1a7SMark Yao } 5055d82d1a7SMark Yao 5062048e328SMark Yao ret = clk_enable(vop->hclk); 50739a9ad8fSSean Paul if (WARN_ON(ret < 0)) 50839a9ad8fSSean Paul goto err_put_pm_runtime; 5092048e328SMark Yao 5102048e328SMark Yao ret = clk_enable(vop->dclk); 51139a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5122048e328SMark Yao goto err_disable_hclk; 5132048e328SMark Yao 5142048e328SMark Yao ret = clk_enable(vop->aclk); 51539a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5162048e328SMark Yao goto err_disable_dclk; 5172048e328SMark Yao 5182048e328SMark Yao /* 5192048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5202048e328SMark Yao * automatically with this master device via common driver code. 5212048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5222048e328SMark Yao * mapping. 5232048e328SMark Yao */ 5242048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5252048e328SMark Yao if (ret) { 5262048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 5272048e328SMark Yao goto err_disable_aclk; 5282048e328SMark Yao } 5292048e328SMark Yao 53077faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 53117a794d7SChris Zhong vop_cfg_done(vop); 53217a794d7SChris Zhong 53352ab7891SMark Yao /* 53452ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 53552ab7891SMark Yao */ 53652ab7891SMark Yao vop->is_enabled = true; 53752ab7891SMark Yao 5382048e328SMark Yao spin_lock(&vop->reg_lock); 5392048e328SMark Yao 5409a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 5412048e328SMark Yao 5422048e328SMark Yao spin_unlock(&vop->reg_lock); 5432048e328SMark Yao 5442048e328SMark Yao enable_irq(vop->irq); 5452048e328SMark Yao 546b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 5472048e328SMark Yao 54839a9ad8fSSean Paul return 0; 5492048e328SMark Yao 5502048e328SMark Yao err_disable_aclk: 5512048e328SMark Yao clk_disable(vop->aclk); 5522048e328SMark Yao err_disable_dclk: 5532048e328SMark Yao clk_disable(vop->dclk); 5542048e328SMark Yao err_disable_hclk: 5552048e328SMark Yao clk_disable(vop->hclk); 55639a9ad8fSSean Paul err_put_pm_runtime: 55739a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 55839a9ad8fSSean Paul return ret; 5592048e328SMark Yao } 5602048e328SMark Yao 56164581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 56264581714SLaurent Pinchart struct drm_crtc_state *old_state) 5632048e328SMark Yao { 5642048e328SMark Yao struct vop *vop = to_vop(crtc); 5653ed6c649STomeu Vizoso int i; 5662048e328SMark Yao 567893b6cadSDaniel Vetter WARN_ON(vop->event); 568893b6cadSDaniel Vetter 569b883c9baSSean Paul rockchip_drm_psr_deactivate(&vop->crtc); 570b883c9baSSean Paul 5713ed6c649STomeu Vizoso /* 5723ed6c649STomeu Vizoso * We need to make sure that all windows are disabled before we 5733ed6c649STomeu Vizoso * disable that crtc. Otherwise we might try to scan from a destroyed 5743ed6c649STomeu Vizoso * buffer later. 5753ed6c649STomeu Vizoso */ 5763ed6c649STomeu Vizoso for (i = 0; i < vop->data->win_size; i++) { 5773ed6c649STomeu Vizoso struct vop_win *vop_win = &vop->win[i]; 5783ed6c649STomeu Vizoso const struct vop_win_data *win = vop_win->data; 5793ed6c649STomeu Vizoso 5803ed6c649STomeu Vizoso spin_lock(&vop->reg_lock); 5813ed6c649STomeu Vizoso VOP_WIN_SET(vop, win, enable, 0); 5823ed6c649STomeu Vizoso spin_unlock(&vop->reg_lock); 5833ed6c649STomeu Vizoso } 5843ed6c649STomeu Vizoso 58517a794d7SChris Zhong vop_cfg_done(vop); 58617a794d7SChris Zhong 587b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 5882048e328SMark Yao 5892048e328SMark Yao /* 5901067219bSMark Yao * Vop standby will take effect at end of current frame, 5911067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5921067219bSMark Yao * 5931067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5941067219bSMark Yao * if not, memory bus maybe dead. 5952048e328SMark Yao */ 5961067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 5971067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 5981067219bSMark Yao 5992048e328SMark Yao spin_lock(&vop->reg_lock); 6002048e328SMark Yao 6019a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6022048e328SMark Yao 6032048e328SMark Yao spin_unlock(&vop->reg_lock); 60452ab7891SMark Yao 6051067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 6062048e328SMark Yao 6071067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6081067219bSMark Yao 6091067219bSMark Yao disable_irq(vop->irq); 6101067219bSMark Yao 6111067219bSMark Yao vop->is_enabled = false; 6121067219bSMark Yao 6131067219bSMark Yao /* 6141067219bSMark Yao * vop standby complete, so iommu detach is safe. 6151067219bSMark Yao */ 6162048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6172048e328SMark Yao 6181067219bSMark Yao clk_disable(vop->dclk); 6192048e328SMark Yao clk_disable(vop->aclk); 6202048e328SMark Yao clk_disable(vop->hclk); 6215d82d1a7SMark Yao pm_runtime_put(vop->dev); 622893b6cadSDaniel Vetter 623893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 624893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 625893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 626893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 627893b6cadSDaniel Vetter 628893b6cadSDaniel Vetter crtc->state->event = NULL; 629893b6cadSDaniel Vetter } 6302048e328SMark Yao } 6312048e328SMark Yao 63263ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 6332048e328SMark Yao { 63463ebb9faSMark Yao drm_plane_cleanup(plane); 6352048e328SMark Yao } 6362048e328SMark Yao 63763ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 63863ebb9faSMark Yao struct drm_plane_state *state) 6392048e328SMark Yao { 64063ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 64192915da6SJohn Keeping struct drm_crtc_state *crtc_state; 64263ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 6432048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 6442048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6452048e328SMark Yao int ret; 64663ebb9faSMark Yao struct drm_rect clip; 6474c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 6484c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6494c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 6504c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6512048e328SMark Yao 65263ebb9faSMark Yao if (!crtc || !fb) 653d47a7246STomasz Figa return 0; 65492915da6SJohn Keeping 65592915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 65692915da6SJohn Keeping if (WARN_ON(!crtc_state)) 65792915da6SJohn Keeping return -EINVAL; 65892915da6SJohn Keeping 65963ebb9faSMark Yao clip.x1 = 0; 66063ebb9faSMark Yao clip.y1 = 0; 66192915da6SJohn Keeping clip.x2 = crtc_state->adjusted_mode.hdisplay; 66292915da6SJohn Keeping clip.y2 = crtc_state->adjusted_mode.vdisplay; 66363ebb9faSMark Yao 664f9b96be0SVille Syrjälä ret = drm_plane_helper_check_state(state, &clip, 665f9b96be0SVille Syrjälä min_scale, max_scale, 666f9b96be0SVille Syrjälä true, true); 6672048e328SMark Yao if (ret) 6682048e328SMark Yao return ret; 6692048e328SMark Yao 670f9b96be0SVille Syrjälä if (!state->visible) 671d47a7246STomasz Figa return 0; 6722048e328SMark Yao 673438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 674d47a7246STomasz Figa if (ret < 0) 675d47a7246STomasz Figa return ret; 67684c7f8caSMark Yao 67784c7f8caSMark Yao /* 67884c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 67984c7f8caSMark Yao * need align with 2 pixel. 68084c7f8caSMark Yao */ 681438b74a5SVille Syrjälä if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) 68263ebb9faSMark Yao return -EINVAL; 68363ebb9faSMark Yao 68463ebb9faSMark Yao return 0; 68584c7f8caSMark Yao } 68684c7f8caSMark Yao 68763ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 68863ebb9faSMark Yao struct drm_plane_state *old_state) 68963ebb9faSMark Yao { 69063ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 69163ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 69263ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 6932048e328SMark Yao 69463ebb9faSMark Yao if (!old_state->crtc) 69563ebb9faSMark Yao return; 6962048e328SMark Yao 69763ebb9faSMark Yao spin_lock(&vop->reg_lock); 6982048e328SMark Yao 69963ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 7002048e328SMark Yao 70163ebb9faSMark Yao spin_unlock(&vop->reg_lock); 70263ebb9faSMark Yao } 70363ebb9faSMark Yao 70463ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 70563ebb9faSMark Yao struct drm_plane_state *old_state) 70663ebb9faSMark Yao { 70763ebb9faSMark Yao struct drm_plane_state *state = plane->state; 70863ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 70963ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 71063ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 71163ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 71263ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 71363ebb9faSMark Yao unsigned int actual_w, actual_h; 71463ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 71563ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 716ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 717ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 71863ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 71963ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 72063ebb9faSMark Yao unsigned long offset; 72163ebb9faSMark Yao dma_addr_t dma_addr; 72263ebb9faSMark Yao uint32_t val; 72363ebb9faSMark Yao bool rb_swap; 724d47a7246STomasz Figa int format; 72563ebb9faSMark Yao 72663ebb9faSMark Yao /* 72763ebb9faSMark Yao * can't update plane when vop is disabled. 72863ebb9faSMark Yao */ 7294f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 73063ebb9faSMark Yao return; 73163ebb9faSMark Yao 73263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 73363ebb9faSMark Yao return; 73463ebb9faSMark Yao 735d47a7246STomasz Figa if (!state->visible) { 73663ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 73763ebb9faSMark Yao return; 73863ebb9faSMark Yao } 73963ebb9faSMark Yao 74063ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 74163ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 74263ebb9faSMark Yao 74363ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 74463ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 74563ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 74663ebb9faSMark Yao 74763ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 74863ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 74963ebb9faSMark Yao 75063ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 75163ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 75263ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 75363ebb9faSMark Yao 754353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 75563ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 756d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 757d47a7246STomasz Figa 758438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 75963ebb9faSMark Yao 76063ebb9faSMark Yao spin_lock(&vop->reg_lock); 76163ebb9faSMark Yao 762d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 76363ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 764d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 765438b74a5SVille Syrjälä if (is_yuv_support(fb->format->format)) { 766438b74a5SVille Syrjälä int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 767438b74a5SVille Syrjälä int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 768353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 76984c7f8caSMark Yao 77084c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 77184c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 77284c7f8caSMark Yao 77363ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 77463ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 77584c7f8caSMark Yao 77663ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 77763ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 77863ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 77984c7f8caSMark Yao } 7804c156c21SMark Yao 7814c156c21SMark Yao if (win->phy->scl) 7824c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 78363ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 784438b74a5SVille Syrjälä fb->format->format); 7854c156c21SMark Yao 78663ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 78763ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 78863ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 7894c156c21SMark Yao 790438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 79185a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 7922048e328SMark Yao 793438b74a5SVille Syrjälä if (is_alpha_support(fb->format->format)) { 7942048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 7952048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 7962048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 7972048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 7982048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 7992048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 8002048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 8012048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 8022048e328SMark Yao } else { 8032048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 8042048e328SMark Yao } 8052048e328SMark Yao 8062048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 8072048e328SMark Yao spin_unlock(&vop->reg_lock); 8082048e328SMark Yao } 8092048e328SMark Yao 81063ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 81163ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 81263ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 81363ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 81463ebb9faSMark Yao }; 81563ebb9faSMark Yao 8162048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 81763ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 81863ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 8192048e328SMark Yao .destroy = vop_plane_destroy, 820d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 821d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 822d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 8232048e328SMark Yao }; 8242048e328SMark Yao 8252048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 8262048e328SMark Yao { 8272048e328SMark Yao struct vop *vop = to_vop(crtc); 8282048e328SMark Yao unsigned long flags; 8292048e328SMark Yao 83063ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8312048e328SMark Yao return -EPERM; 8322048e328SMark Yao 8332048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 8342048e328SMark Yao 835fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 836dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 8372048e328SMark Yao 8382048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8392048e328SMark Yao 8402048e328SMark Yao return 0; 8412048e328SMark Yao } 8422048e328SMark Yao 8432048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 8442048e328SMark Yao { 8452048e328SMark Yao struct vop *vop = to_vop(crtc); 8462048e328SMark Yao unsigned long flags; 8472048e328SMark Yao 84863ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8492048e328SMark Yao return; 85031e980c5SMark Yao 8512048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 852dbb3d944SMark Yao 853dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 854dbb3d944SMark Yao 8552048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8562048e328SMark Yao } 8572048e328SMark Yao 8582048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 8592048e328SMark Yao const struct drm_display_mode *mode, 8602048e328SMark Yao struct drm_display_mode *adjusted_mode) 8612048e328SMark Yao { 862b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 863b59b8de3SChris Zhong 864b59b8de3SChris Zhong adjusted_mode->clock = 865b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 866b59b8de3SChris Zhong 8672048e328SMark Yao return true; 8682048e328SMark Yao } 8692048e328SMark Yao 8700b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 8710b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 8722048e328SMark Yao { 8732048e328SMark Yao struct vop *vop = to_vop(crtc); 874efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 8754e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 87663ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 8772048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 8782048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 8792048e328SMark Yao u16 htotal = adjusted_mode->htotal; 8802048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 8812048e328SMark Yao u16 hact_end = hact_st + hdisplay; 8822048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 8832048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 8842048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 8852048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 8862048e328SMark Yao u16 vact_end = vact_st + vdisplay; 8870a63bfd0SMark Yao uint32_t pin_pol, val; 88839a9ad8fSSean Paul int ret; 8892048e328SMark Yao 890893b6cadSDaniel Vetter WARN_ON(vop->event); 891893b6cadSDaniel Vetter 89239a9ad8fSSean Paul ret = vop_enable(crtc); 89339a9ad8fSSean Paul if (ret) { 89439a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 89539a9ad8fSSean Paul return; 89639a9ad8fSSean Paul } 89739a9ad8fSSean Paul 8982048e328SMark Yao /* 899ce3887edSMark Yao * If dclk rate is zero, mean that scanout is stop, 900ce3887edSMark Yao * we don't need wait any more. 9012048e328SMark Yao */ 902ce3887edSMark Yao if (clk_get_rate(vop->dclk)) { 903ce3887edSMark Yao /* 904ce3887edSMark Yao * Rk3288 vop timing register is immediately, when configure 905ce3887edSMark Yao * display timing on display time, may cause tearing. 906ce3887edSMark Yao * 907ce3887edSMark Yao * Vop standby will take effect at end of current frame, 908ce3887edSMark Yao * if dsp hold valid irq happen, it means standby complete. 909ce3887edSMark Yao * 910ce3887edSMark Yao * mode set: 911ce3887edSMark Yao * standby and wait complete --> |---- 912ce3887edSMark Yao * | display time 913ce3887edSMark Yao * |---- 914ce3887edSMark Yao * |---> dsp hold irq 915ce3887edSMark Yao * configure display timing --> | 916ce3887edSMark Yao * standby exit | 917ce3887edSMark Yao * | new frame start. 918ce3887edSMark Yao */ 919ce3887edSMark Yao 920ce3887edSMark Yao reinit_completion(&vop->dsp_hold_completion); 921ce3887edSMark Yao vop_dsp_hold_valid_irq_enable(vop); 922ce3887edSMark Yao 923ce3887edSMark Yao spin_lock(&vop->reg_lock); 924ce3887edSMark Yao 9259a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 926ce3887edSMark Yao 927ce3887edSMark Yao spin_unlock(&vop->reg_lock); 928ce3887edSMark Yao 929ce3887edSMark Yao wait_for_completion(&vop->dsp_hold_completion); 930ce3887edSMark Yao 931ce3887edSMark Yao vop_dsp_hold_valid_irq_disable(vop); 932ce3887edSMark Yao } 9332048e328SMark Yao 9341a0f7ed3SChris Zhong pin_pol = BIT(DCLK_INVERT); 935d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 936d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 937d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 938d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 9399a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 9400a63bfd0SMark Yao 9414e257d9eSMark Yao switch (s->output_type) { 9424e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 9439a61c54bSMark yao VOP_REG_SET(vop, output, rgb_en, 1); 9449a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 9454e257d9eSMark Yao break; 9464e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 9479a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 9489a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 9494e257d9eSMark Yao break; 9504e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 9519a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 9529a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 9534e257d9eSMark Yao break; 9544e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 9559a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 9569a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 9574e257d9eSMark Yao break; 9581a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 9591a0f7ed3SChris Zhong pin_pol &= ~BIT(DCLK_INVERT); 9609a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 9619a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 9621a0f7ed3SChris Zhong break; 9634e257d9eSMark Yao default: 964ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 965ee4d7899SSean Paul s->output_type); 9664e257d9eSMark Yao } 967efd11cc8SMark yao 968efd11cc8SMark yao /* 969efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 970efd11cc8SMark yao */ 971efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 972efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 973efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 9749a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 9752048e328SMark Yao 9769a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 9772048e328SMark Yao val = hact_st << 16; 9782048e328SMark Yao val |= hact_end; 9799a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 9809a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 9812048e328SMark Yao 9829a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 9832048e328SMark Yao val = vact_st << 16; 9842048e328SMark Yao val |= vact_end; 9859a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 9869a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 9872048e328SMark Yao 9889a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 989459b086dSJeffy Chen 9902048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 991ce3887edSMark Yao 9929a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 993b883c9baSSean Paul 994b883c9baSSean Paul rockchip_drm_psr_activate(&vop->crtc); 9952048e328SMark Yao } 9962048e328SMark Yao 9977caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 9987caecdbeSTomasz Figa { 9997caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 10007caecdbeSTomasz Figa } 10017caecdbeSTomasz Figa 10027caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 10037caecdbeSTomasz Figa { 10047caecdbeSTomasz Figa bool pending; 10057caecdbeSTomasz Figa int ret; 10067caecdbeSTomasz Figa 10077caecdbeSTomasz Figa /* 10087caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 10097caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 10107caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 10117caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 10127caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 10137caecdbeSTomasz Figa * shouldn't exceed microseconds range. 10147caecdbeSTomasz Figa */ 10157caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 10167caecdbeSTomasz Figa !pending, 0, 10 * 1000); 10177caecdbeSTomasz Figa if (ret) 10187caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 10197caecdbeSTomasz Figa 10207caecdbeSTomasz Figa synchronize_irq(vop->irq); 10217caecdbeSTomasz Figa } 10227caecdbeSTomasz Figa 102363ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 102463ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 102563ebb9faSMark Yao { 102647a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1027e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 102863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 102947a7eb45STomasz Figa struct drm_plane *plane; 103047a7eb45STomasz Figa int i; 103163ebb9faSMark Yao 103263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 103363ebb9faSMark Yao return; 103463ebb9faSMark Yao 103563ebb9faSMark Yao spin_lock(&vop->reg_lock); 103663ebb9faSMark Yao 103763ebb9faSMark Yao vop_cfg_done(vop); 103863ebb9faSMark Yao 103963ebb9faSMark Yao spin_unlock(&vop->reg_lock); 10407caecdbeSTomasz Figa 10417caecdbeSTomasz Figa /* 10427caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 10437caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 10447caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 10457caecdbeSTomasz Figa */ 10467caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 104747a7eb45STomasz Figa 104841ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 104941ee4367STomasz Figa if (crtc->state->event) { 105041ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 105141ee4367STomasz Figa WARN_ON(vop->event); 105241ee4367STomasz Figa 105341ee4367STomasz Figa vop->event = crtc->state->event; 105441ee4367STomasz Figa crtc->state->event = NULL; 105541ee4367STomasz Figa } 105641ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 105741ee4367STomasz Figa 1058e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1059e741f2b1SMaarten Lankhorst new_plane_state, i) { 106047a7eb45STomasz Figa if (!old_plane_state->fb) 106147a7eb45STomasz Figa continue; 106247a7eb45STomasz Figa 1063e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 106447a7eb45STomasz Figa continue; 106547a7eb45STomasz Figa 106647a7eb45STomasz Figa drm_framebuffer_reference(old_plane_state->fb); 106747a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 106847a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 106947a7eb45STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 107047a7eb45STomasz Figa } 107163ebb9faSMark Yao } 107263ebb9faSMark Yao 107363ebb9faSMark Yao static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 107463ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 107563ebb9faSMark Yao { 1076b883c9baSSean Paul rockchip_drm_psr_flush(crtc); 10772048e328SMark Yao } 10782048e328SMark Yao 10792048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 10802048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 108163ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 108263ebb9faSMark Yao .atomic_begin = vop_crtc_atomic_begin, 10830b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 108464581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 10852048e328SMark Yao }; 10862048e328SMark Yao 10872048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 10882048e328SMark Yao { 10892048e328SMark Yao drm_crtc_cleanup(crtc); 10902048e328SMark Yao } 10912048e328SMark Yao 1092dc0b408fSJohn Keeping static void vop_crtc_reset(struct drm_crtc *crtc) 1093dc0b408fSJohn Keeping { 1094dc0b408fSJohn Keeping if (crtc->state) 1095dc0b408fSJohn Keeping __drm_atomic_helper_crtc_destroy_state(crtc->state); 1096dc0b408fSJohn Keeping kfree(crtc->state); 1097dc0b408fSJohn Keeping 1098dc0b408fSJohn Keeping crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1099dc0b408fSJohn Keeping if (crtc->state) 1100dc0b408fSJohn Keeping crtc->state->crtc = crtc; 1101dc0b408fSJohn Keeping } 1102dc0b408fSJohn Keeping 11034e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 11044e257d9eSMark Yao { 11054e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 11064e257d9eSMark Yao 11074e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 11084e257d9eSMark Yao if (!rockchip_state) 11094e257d9eSMark Yao return NULL; 11104e257d9eSMark Yao 11114e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 11124e257d9eSMark Yao return &rockchip_state->base; 11134e257d9eSMark Yao } 11144e257d9eSMark Yao 11154e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 11164e257d9eSMark Yao struct drm_crtc_state *state) 11174e257d9eSMark Yao { 11184e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 11194e257d9eSMark Yao 1120ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 11214e257d9eSMark Yao kfree(s); 11224e257d9eSMark Yao } 11234e257d9eSMark Yao 11246cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 11253190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 11263190e58dSTomeu Vizoso { 11273190e58dSTomeu Vizoso struct drm_connector *connector; 11282cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 11293190e58dSTomeu Vizoso 11302cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 11312cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 11323190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 11332cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 11343190e58dSTomeu Vizoso return connector; 11353190e58dSTomeu Vizoso } 11362cbeb64fSGustavo Padovan } 11372cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 11383190e58dSTomeu Vizoso 11393190e58dSTomeu Vizoso return NULL; 11403190e58dSTomeu Vizoso } 11413190e58dSTomeu Vizoso 11423190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 11433190e58dSTomeu Vizoso const char *source_name, size_t *values_cnt) 11443190e58dSTomeu Vizoso { 11453190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 11463190e58dSTomeu Vizoso struct drm_connector *connector; 11473190e58dSTomeu Vizoso int ret; 11483190e58dSTomeu Vizoso 11493190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 11503190e58dSTomeu Vizoso if (!connector) 11513190e58dSTomeu Vizoso return -EINVAL; 11523190e58dSTomeu Vizoso 11533190e58dSTomeu Vizoso *values_cnt = 3; 11543190e58dSTomeu Vizoso 11553190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 11563190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 11573190e58dSTomeu Vizoso else if (!source_name) 11583190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 11593190e58dSTomeu Vizoso else 11603190e58dSTomeu Vizoso ret = -EINVAL; 11613190e58dSTomeu Vizoso 11623190e58dSTomeu Vizoso return ret; 11633190e58dSTomeu Vizoso } 11646cca3869SSean Paul #else 11656cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 11666cca3869SSean Paul const char *source_name, size_t *values_cnt) 11676cca3869SSean Paul { 11686cca3869SSean Paul return -ENODEV; 11696cca3869SSean Paul } 11706cca3869SSean Paul #endif 11713190e58dSTomeu Vizoso 11722048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 117363ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 117463ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 11752048e328SMark Yao .destroy = vop_crtc_destroy, 1176dc0b408fSJohn Keeping .reset = vop_crtc_reset, 11774e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 11784e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1179c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1180c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 11813190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 11822048e328SMark Yao }; 11832048e328SMark Yao 118447a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 118547a7eb45STomasz Figa { 118647a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 118747a7eb45STomasz Figa struct drm_framebuffer *fb = val; 118847a7eb45STomasz Figa 118947a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 119047a7eb45STomasz Figa drm_framebuffer_unreference(fb); 119147a7eb45STomasz Figa } 119247a7eb45STomasz Figa 119363ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 11942048e328SMark Yao { 119563ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 119663ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 119763ebb9faSMark Yao unsigned long flags; 11982048e328SMark Yao 119963ebb9faSMark Yao spin_lock_irqsave(&drm->event_lock, flags); 1200893b6cadSDaniel Vetter if (vop->event) { 120163ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 12025b680403SSean Paul drm_crtc_vblank_put(crtc); 1203646ec687STomasz Figa vop->event = NULL; 12045b680403SSean Paul } 1205893b6cadSDaniel Vetter spin_unlock_irqrestore(&drm->event_lock, flags); 1206893b6cadSDaniel Vetter 120747a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 120847a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 12092048e328SMark Yao } 12102048e328SMark Yao 12112048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 12122048e328SMark Yao { 12132048e328SMark Yao struct vop *vop = data; 1214b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1215dbb3d944SMark Yao uint32_t active_irqs; 12162048e328SMark Yao unsigned long flags; 12171067219bSMark Yao int ret = IRQ_NONE; 12182048e328SMark Yao 12192048e328SMark Yao /* 1220dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 12212048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 12222048e328SMark Yao */ 12232048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1224dbb3d944SMark Yao 1225dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 12262048e328SMark Yao /* Clear all active interrupt sources */ 12272048e328SMark Yao if (active_irqs) 1228dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1229dbb3d944SMark Yao 12302048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 12312048e328SMark Yao 12322048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 12332048e328SMark Yao if (!active_irqs) 12342048e328SMark Yao return IRQ_NONE; 12352048e328SMark Yao 12361067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 12371067219bSMark Yao complete(&vop->dsp_hold_completion); 12381067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 12391067219bSMark Yao ret = IRQ_HANDLED; 12402048e328SMark Yao } 12412048e328SMark Yao 124269c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 124369c34e41SYakir Yang complete(&vop->line_flag_completion); 124469c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 124569c34e41SYakir Yang ret = IRQ_HANDLED; 124669c34e41SYakir Yang } 124769c34e41SYakir Yang 12481067219bSMark Yao if (active_irqs & FS_INTR) { 1249b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 125063ebb9faSMark Yao vop_handle_vblank(vop); 12511067219bSMark Yao active_irqs &= ~FS_INTR; 125263ebb9faSMark Yao ret = IRQ_HANDLED; 12531067219bSMark Yao } 12542048e328SMark Yao 12551067219bSMark Yao /* Unhandled irqs are spurious. */ 12561067219bSMark Yao if (active_irqs) 1257ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1258ee4d7899SSean Paul active_irqs); 12591067219bSMark Yao 12601067219bSMark Yao return ret; 12612048e328SMark Yao } 12622048e328SMark Yao 12632048e328SMark Yao static int vop_create_crtc(struct vop *vop) 12642048e328SMark Yao { 12652048e328SMark Yao const struct vop_data *vop_data = vop->data; 12662048e328SMark Yao struct device *dev = vop->dev; 12672048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1268328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 12692048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12702048e328SMark Yao struct device_node *port; 12712048e328SMark Yao int ret; 12722048e328SMark Yao int i; 12732048e328SMark Yao 12742048e328SMark Yao /* 12752048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 12762048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 12772048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 12782048e328SMark Yao */ 12792048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12802048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12812048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12822048e328SMark Yao 12832048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 12842048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 12852048e328SMark Yao continue; 12862048e328SMark Yao 12872048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12882048e328SMark Yao 0, &vop_plane_funcs, 12892048e328SMark Yao win_data->phy->data_formats, 12902048e328SMark Yao win_data->phy->nformats, 1291e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 12922048e328SMark Yao if (ret) { 1293ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1294ee4d7899SSean Paul ret); 12952048e328SMark Yao goto err_cleanup_planes; 12962048e328SMark Yao } 12972048e328SMark Yao 12982048e328SMark Yao plane = &vop_win->base; 129963ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 13002048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 13012048e328SMark Yao primary = plane; 13022048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 13032048e328SMark Yao cursor = plane; 13042048e328SMark Yao } 13052048e328SMark Yao 13062048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1307f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 13082048e328SMark Yao if (ret) 1309328b51c0SDouglas Anderson goto err_cleanup_planes; 13102048e328SMark Yao 13112048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 13122048e328SMark Yao 13132048e328SMark Yao /* 13142048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 13152048e328SMark Yao * to the newly created crtc. 13162048e328SMark Yao */ 13172048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13182048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13192048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 13202048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 13212048e328SMark Yao 13222048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 13232048e328SMark Yao continue; 13242048e328SMark Yao 13252048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 13262048e328SMark Yao possible_crtcs, 13272048e328SMark Yao &vop_plane_funcs, 13282048e328SMark Yao win_data->phy->data_formats, 13292048e328SMark Yao win_data->phy->nformats, 1330e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 13312048e328SMark Yao if (ret) { 1332ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1333ee4d7899SSean Paul ret); 13342048e328SMark Yao goto err_cleanup_crtc; 13352048e328SMark Yao } 133663ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 13372048e328SMark Yao } 13382048e328SMark Yao 13392048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 13402048e328SMark Yao if (!port) { 13414bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 13424bf99144SRob Herring dev->of_node); 1343328b51c0SDouglas Anderson ret = -ENOENT; 13442048e328SMark Yao goto err_cleanup_crtc; 13452048e328SMark Yao } 13462048e328SMark Yao 134747a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 134847a7eb45STomasz Figa vop_fb_unref_worker); 134947a7eb45STomasz Figa 13501067219bSMark Yao init_completion(&vop->dsp_hold_completion); 135169c34e41SYakir Yang init_completion(&vop->line_flag_completion); 13522048e328SMark Yao crtc->port = port; 13532048e328SMark Yao 13542048e328SMark Yao return 0; 13552048e328SMark Yao 13562048e328SMark Yao err_cleanup_crtc: 13572048e328SMark Yao drm_crtc_cleanup(crtc); 13582048e328SMark Yao err_cleanup_planes: 1359328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1360328b51c0SDouglas Anderson head) 13612048e328SMark Yao drm_plane_cleanup(plane); 13622048e328SMark Yao return ret; 13632048e328SMark Yao } 13642048e328SMark Yao 13652048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 13662048e328SMark Yao { 13672048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1368328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1369328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 13702048e328SMark Yao 13712048e328SMark Yao of_node_put(crtc->port); 1372328b51c0SDouglas Anderson 1373328b51c0SDouglas Anderson /* 1374328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1375328b51c0SDouglas Anderson * 1376328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1377328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1378328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1379328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1380328b51c0SDouglas Anderson */ 1381328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1382328b51c0SDouglas Anderson head) 1383328b51c0SDouglas Anderson vop_plane_destroy(plane); 1384328b51c0SDouglas Anderson 1385328b51c0SDouglas Anderson /* 1386328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1387328b51c0SDouglas Anderson * references the CRTC. 1388328b51c0SDouglas Anderson */ 13892048e328SMark Yao drm_crtc_cleanup(crtc); 139047a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 13912048e328SMark Yao } 13922048e328SMark Yao 13932048e328SMark Yao static int vop_initial(struct vop *vop) 13942048e328SMark Yao { 13952048e328SMark Yao const struct vop_data *vop_data = vop->data; 13962048e328SMark Yao struct reset_control *ahb_rst; 13972048e328SMark Yao int i, ret; 13982048e328SMark Yao 13992048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 14002048e328SMark Yao if (IS_ERR(vop->hclk)) { 14012048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 14022048e328SMark Yao return PTR_ERR(vop->hclk); 14032048e328SMark Yao } 14042048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 14052048e328SMark Yao if (IS_ERR(vop->aclk)) { 14062048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 14072048e328SMark Yao return PTR_ERR(vop->aclk); 14082048e328SMark Yao } 14092048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 14102048e328SMark Yao if (IS_ERR(vop->dclk)) { 14112048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 14122048e328SMark Yao return PTR_ERR(vop->dclk); 14132048e328SMark Yao } 14142048e328SMark Yao 14155e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 14165e570373SJeffy Chen if (ret < 0) { 14175e570373SJeffy Chen dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 14185e570373SJeffy Chen return ret; 14195e570373SJeffy Chen } 14205e570373SJeffy Chen 14212048e328SMark Yao ret = clk_prepare(vop->dclk); 14222048e328SMark Yao if (ret < 0) { 14232048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 14245e570373SJeffy Chen goto err_put_pm_runtime; 14252048e328SMark Yao } 14262048e328SMark Yao 1427d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1428d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 14292048e328SMark Yao if (ret < 0) { 1430d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable hclk\n"); 14312048e328SMark Yao goto err_unprepare_dclk; 14322048e328SMark Yao } 14332048e328SMark Yao 1434d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 14352048e328SMark Yao if (ret < 0) { 1436d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1437d7b53fd9SSjoerd Simons goto err_disable_hclk; 14382048e328SMark Yao } 1439d7b53fd9SSjoerd Simons 14402048e328SMark Yao /* 14412048e328SMark Yao * do hclk_reset, reset all vop registers. 14422048e328SMark Yao */ 14432048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 14442048e328SMark Yao if (IS_ERR(ahb_rst)) { 14452048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 14462048e328SMark Yao ret = PTR_ERR(ahb_rst); 1447d7b53fd9SSjoerd Simons goto err_disable_aclk; 14482048e328SMark Yao } 14492048e328SMark Yao reset_control_assert(ahb_rst); 14502048e328SMark Yao usleep_range(10, 20); 14512048e328SMark Yao reset_control_deassert(ahb_rst); 14522048e328SMark Yao 14532048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 14542048e328SMark Yao 14559a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 14569a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 14572048e328SMark Yao 14582048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14592048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 14609dd2aca4SMark yao int channel = i * 2 + 1; 14612048e328SMark Yao 14629dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 14632048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 146460b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 14652048e328SMark Yao } 14662048e328SMark Yao 14672048e328SMark Yao vop_cfg_done(vop); 14682048e328SMark Yao 14692048e328SMark Yao /* 14702048e328SMark Yao * do dclk_reset, let all config take affect. 14712048e328SMark Yao */ 14722048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 14732048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 14742048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 14752048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1476d7b53fd9SSjoerd Simons goto err_disable_aclk; 14772048e328SMark Yao } 14782048e328SMark Yao reset_control_assert(vop->dclk_rst); 14792048e328SMark Yao usleep_range(10, 20); 14802048e328SMark Yao reset_control_deassert(vop->dclk_rst); 14812048e328SMark Yao 14822048e328SMark Yao clk_disable(vop->hclk); 1483d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 14842048e328SMark Yao 148531e980c5SMark Yao vop->is_enabled = false; 14862048e328SMark Yao 14875e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14885e570373SJeffy Chen 14892048e328SMark Yao return 0; 14902048e328SMark Yao 1491d7b53fd9SSjoerd Simons err_disable_aclk: 1492d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 14932048e328SMark Yao err_disable_hclk: 1494d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 14952048e328SMark Yao err_unprepare_dclk: 14962048e328SMark Yao clk_unprepare(vop->dclk); 14975e570373SJeffy Chen err_put_pm_runtime: 14985e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14992048e328SMark Yao return ret; 15002048e328SMark Yao } 15012048e328SMark Yao 15022048e328SMark Yao /* 15032048e328SMark Yao * Initialize the vop->win array elements. 15042048e328SMark Yao */ 15052048e328SMark Yao static void vop_win_init(struct vop *vop) 15062048e328SMark Yao { 15072048e328SMark Yao const struct vop_data *vop_data = vop->data; 15082048e328SMark Yao unsigned int i; 15092048e328SMark Yao 15102048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 15112048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 15122048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 15132048e328SMark Yao 15142048e328SMark Yao vop_win->data = win_data; 15152048e328SMark Yao vop_win->vop = vop; 15162048e328SMark Yao } 15172048e328SMark Yao } 15182048e328SMark Yao 151969c34e41SYakir Yang /** 1520459b086dSJeffy Chen * rockchip_drm_wait_vact_end 152169c34e41SYakir Yang * @crtc: CRTC to enable line flag 152269c34e41SYakir Yang * @mstimeout: millisecond for timeout 152369c34e41SYakir Yang * 1524459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 152569c34e41SYakir Yang * 152669c34e41SYakir Yang * Returns: 152769c34e41SYakir Yang * Zero on success, negative errno on failure. 152869c34e41SYakir Yang */ 1529459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 153069c34e41SYakir Yang { 153169c34e41SYakir Yang struct vop *vop = to_vop(crtc); 153269c34e41SYakir Yang unsigned long jiffies_left; 153369c34e41SYakir Yang 153469c34e41SYakir Yang if (!crtc || !vop->is_enabled) 153569c34e41SYakir Yang return -ENODEV; 153669c34e41SYakir Yang 1537459b086dSJeffy Chen if (mstimeout <= 0) 153869c34e41SYakir Yang return -EINVAL; 153969c34e41SYakir Yang 154069c34e41SYakir Yang if (vop_line_flag_irq_is_enabled(vop)) 154169c34e41SYakir Yang return -EBUSY; 154269c34e41SYakir Yang 154369c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1544459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 154569c34e41SYakir Yang 154669c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 154769c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 154869c34e41SYakir Yang vop_line_flag_irq_disable(vop); 154969c34e41SYakir Yang 155069c34e41SYakir Yang if (jiffies_left == 0) { 155169c34e41SYakir Yang dev_err(vop->dev, "Timeout waiting for IRQ\n"); 155269c34e41SYakir Yang return -ETIMEDOUT; 155369c34e41SYakir Yang } 155469c34e41SYakir Yang 155569c34e41SYakir Yang return 0; 155669c34e41SYakir Yang } 1557459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 155869c34e41SYakir Yang 15592048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 15602048e328SMark Yao { 15612048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 15622048e328SMark Yao const struct vop_data *vop_data; 15632048e328SMark Yao struct drm_device *drm_dev = data; 15642048e328SMark Yao struct vop *vop; 15652048e328SMark Yao struct resource *res; 15662048e328SMark Yao size_t alloc_size; 15673ea68922SHeiko Stuebner int ret, irq; 15682048e328SMark Yao 1569a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 15702048e328SMark Yao if (!vop_data) 15712048e328SMark Yao return -ENODEV; 15722048e328SMark Yao 15732048e328SMark Yao /* Allocate vop struct and its vop_win array */ 15742048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 15752048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 15762048e328SMark Yao if (!vop) 15772048e328SMark Yao return -ENOMEM; 15782048e328SMark Yao 15792048e328SMark Yao vop->dev = dev; 15802048e328SMark Yao vop->data = vop_data; 15812048e328SMark Yao vop->drm_dev = drm_dev; 15822048e328SMark Yao dev_set_drvdata(dev, vop); 15832048e328SMark Yao 15842048e328SMark Yao vop_win_init(vop); 15852048e328SMark Yao 15862048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15872048e328SMark Yao vop->len = resource_size(res); 15882048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 15892048e328SMark Yao if (IS_ERR(vop->regs)) 15902048e328SMark Yao return PTR_ERR(vop->regs); 15912048e328SMark Yao 15922048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 15932048e328SMark Yao if (!vop->regsbak) 15942048e328SMark Yao return -ENOMEM; 15952048e328SMark Yao 15963ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 15973ea68922SHeiko Stuebner if (irq < 0) { 15982048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 15993ea68922SHeiko Stuebner return irq; 16002048e328SMark Yao } 16013ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 16022048e328SMark Yao 16032048e328SMark Yao spin_lock_init(&vop->reg_lock); 16042048e328SMark Yao spin_lock_init(&vop->irq_lock); 16052048e328SMark Yao 16062048e328SMark Yao mutex_init(&vop->vsync_mutex); 16072048e328SMark Yao 160863ebb9faSMark Yao ret = devm_request_irq(dev, vop->irq, vop_isr, 16092048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 16102048e328SMark Yao if (ret) 16112048e328SMark Yao return ret; 16122048e328SMark Yao 16132048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 16142048e328SMark Yao disable_irq(vop->irq); 16152048e328SMark Yao 16162048e328SMark Yao ret = vop_create_crtc(vop); 16172048e328SMark Yao if (ret) 16188c763c9bSSean Paul goto err_enable_irq; 16192048e328SMark Yao 16202048e328SMark Yao pm_runtime_enable(&pdev->dev); 16215182c1a5SYakir Yang 16225e570373SJeffy Chen ret = vop_initial(vop); 16235e570373SJeffy Chen if (ret < 0) { 16245e570373SJeffy Chen dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 16255e570373SJeffy Chen goto err_disable_pm_runtime; 16265e570373SJeffy Chen } 16275e570373SJeffy Chen 16282048e328SMark Yao return 0; 16298c763c9bSSean Paul 16305e570373SJeffy Chen err_disable_pm_runtime: 16315e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 16325e570373SJeffy Chen vop_destroy_crtc(vop); 16338c763c9bSSean Paul err_enable_irq: 16348c763c9bSSean Paul enable_irq(vop->irq); /* To balance out the disable_irq above */ 16358c763c9bSSean Paul return ret; 16362048e328SMark Yao } 16372048e328SMark Yao 16382048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 16392048e328SMark Yao { 16402048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 16412048e328SMark Yao 16422048e328SMark Yao pm_runtime_disable(dev); 16432048e328SMark Yao vop_destroy_crtc(vop); 1644ec6e7767SJeffy Chen 1645ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 1646ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 1647ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 16482048e328SMark Yao } 16492048e328SMark Yao 1650a67719d1SMark Yao const struct component_ops vop_component_ops = { 16512048e328SMark Yao .bind = vop_bind, 16522048e328SMark Yao .unbind = vop_unbind, 16532048e328SMark Yao }; 165454255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1655