12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 202048e328SMark Yao #include <drm/drm_plane_helper.h> 212048e328SMark Yao 222048e328SMark Yao #include <linux/kernel.h> 2300fe6148SPaul Gortmaker #include <linux/module.h> 242048e328SMark Yao #include <linux/platform_device.h> 252048e328SMark Yao #include <linux/clk.h> 262048e328SMark Yao #include <linux/of.h> 272048e328SMark Yao #include <linux/of_device.h> 282048e328SMark Yao #include <linux/pm_runtime.h> 292048e328SMark Yao #include <linux/component.h> 302048e328SMark Yao 312048e328SMark Yao #include <linux/reset.h> 322048e328SMark Yao #include <linux/delay.h> 332048e328SMark Yao 342048e328SMark Yao #include "rockchip_drm_drv.h" 352048e328SMark Yao #include "rockchip_drm_gem.h" 362048e328SMark Yao #include "rockchip_drm_fb.h" 372048e328SMark Yao #include "rockchip_drm_vop.h" 382048e328SMark Yao 392048e328SMark Yao #define VOP_REG(off, _mask, s) \ 402048e328SMark Yao {.offset = off, \ 412048e328SMark Yao .mask = _mask, \ 422048e328SMark Yao .shift = s,} 432048e328SMark Yao 442048e328SMark Yao #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 452048e328SMark Yao vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 462048e328SMark Yao #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 472048e328SMark Yao vop_mask_write(x, off, (mask) << shift, (v) << shift) 482048e328SMark Yao 492048e328SMark Yao #define REG_SET(x, base, reg, v, mode) \ 502048e328SMark Yao __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 512048e328SMark Yao 522048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 532048e328SMark Yao REG_SET(x, win->base, win->phy->name, v, RELAXED) 544c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 554c156c21SMark Yao REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 562048e328SMark Yao #define VOP_CTRL_SET(x, name, v) \ 572048e328SMark Yao REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 582048e328SMark Yao 592048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 602048e328SMark Yao vop_read_reg(x, win->base, &win->phy->name) 612048e328SMark Yao 622048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 632048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 642048e328SMark Yao 652048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 662048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 6763ebb9faSMark Yao #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) 682048e328SMark Yao 6963ebb9faSMark Yao struct vop_plane_state { 7063ebb9faSMark Yao struct drm_plane_state base; 7163ebb9faSMark Yao int format; 7263ebb9faSMark Yao struct drm_rect src; 7363ebb9faSMark Yao struct drm_rect dest; 742048e328SMark Yao dma_addr_t yrgb_mst; 7563ebb9faSMark Yao bool enable; 762048e328SMark Yao }; 772048e328SMark Yao 782048e328SMark Yao struct vop_win { 792048e328SMark Yao struct drm_plane base; 802048e328SMark Yao const struct vop_win_data *data; 812048e328SMark Yao struct vop *vop; 822048e328SMark Yao 8363ebb9faSMark Yao struct vop_plane_state state; 842048e328SMark Yao }; 852048e328SMark Yao 862048e328SMark Yao struct vop { 872048e328SMark Yao struct drm_crtc crtc; 882048e328SMark Yao struct device *dev; 892048e328SMark Yao struct drm_device *drm_dev; 9031e980c5SMark Yao bool is_enabled; 912048e328SMark Yao 922048e328SMark Yao /* mutex vsync_ work */ 932048e328SMark Yao struct mutex vsync_mutex; 942048e328SMark Yao bool vsync_work_pending; 951067219bSMark Yao struct completion dsp_hold_completion; 9663ebb9faSMark Yao struct completion wait_update_complete; 9763ebb9faSMark Yao struct drm_pending_vblank_event *event; 982048e328SMark Yao 992048e328SMark Yao const struct vop_data *data; 1002048e328SMark Yao 1012048e328SMark Yao uint32_t *regsbak; 1022048e328SMark Yao void __iomem *regs; 1032048e328SMark Yao 1042048e328SMark Yao /* physical map length of vop register */ 1052048e328SMark Yao uint32_t len; 1062048e328SMark Yao 1072048e328SMark Yao /* one time only one process allowed to config the register */ 1082048e328SMark Yao spinlock_t reg_lock; 1092048e328SMark Yao /* lock vop irq reg */ 1102048e328SMark Yao spinlock_t irq_lock; 1112048e328SMark Yao 1122048e328SMark Yao unsigned int irq; 1132048e328SMark Yao 1142048e328SMark Yao /* vop AHP clk */ 1152048e328SMark Yao struct clk *hclk; 1162048e328SMark Yao /* vop dclk */ 1172048e328SMark Yao struct clk *dclk; 1182048e328SMark Yao /* vop share memory frequency */ 1192048e328SMark Yao struct clk *aclk; 1202048e328SMark Yao 1212048e328SMark Yao /* vop dclk reset */ 1222048e328SMark Yao struct reset_control *dclk_rst; 1232048e328SMark Yao 1242048e328SMark Yao struct vop_win win[]; 1252048e328SMark Yao }; 1262048e328SMark Yao 1272048e328SMark Yao enum vop_data_format { 1282048e328SMark Yao VOP_FMT_ARGB8888 = 0, 1292048e328SMark Yao VOP_FMT_RGB888, 1302048e328SMark Yao VOP_FMT_RGB565, 1312048e328SMark Yao VOP_FMT_YUV420SP = 4, 1322048e328SMark Yao VOP_FMT_YUV422SP, 1332048e328SMark Yao VOP_FMT_YUV444SP, 1342048e328SMark Yao }; 1352048e328SMark Yao 1362048e328SMark Yao struct vop_reg_data { 1372048e328SMark Yao uint32_t offset; 1382048e328SMark Yao uint32_t value; 1392048e328SMark Yao }; 1402048e328SMark Yao 1412048e328SMark Yao struct vop_reg { 1422048e328SMark Yao uint32_t offset; 1432048e328SMark Yao uint32_t shift; 1442048e328SMark Yao uint32_t mask; 1452048e328SMark Yao }; 1462048e328SMark Yao 1472048e328SMark Yao struct vop_ctrl { 1482048e328SMark Yao struct vop_reg standby; 1492048e328SMark Yao struct vop_reg data_blank; 1502048e328SMark Yao struct vop_reg gate_en; 1512048e328SMark Yao struct vop_reg mmu_en; 1522048e328SMark Yao struct vop_reg rgb_en; 1532048e328SMark Yao struct vop_reg edp_en; 1542048e328SMark Yao struct vop_reg hdmi_en; 1552048e328SMark Yao struct vop_reg mipi_en; 1562048e328SMark Yao struct vop_reg out_mode; 1572048e328SMark Yao struct vop_reg dither_down; 1582048e328SMark Yao struct vop_reg dither_up; 1592048e328SMark Yao struct vop_reg pin_pol; 1602048e328SMark Yao 1612048e328SMark Yao struct vop_reg htotal_pw; 1622048e328SMark Yao struct vop_reg hact_st_end; 1632048e328SMark Yao struct vop_reg vtotal_pw; 1642048e328SMark Yao struct vop_reg vact_st_end; 1652048e328SMark Yao struct vop_reg hpost_st_end; 1662048e328SMark Yao struct vop_reg vpost_st_end; 1672048e328SMark Yao }; 1682048e328SMark Yao 1694c156c21SMark Yao struct vop_scl_regs { 1704c156c21SMark Yao struct vop_reg cbcr_vsd_mode; 1714c156c21SMark Yao struct vop_reg cbcr_vsu_mode; 1724c156c21SMark Yao struct vop_reg cbcr_hsd_mode; 1734c156c21SMark Yao struct vop_reg cbcr_ver_scl_mode; 1744c156c21SMark Yao struct vop_reg cbcr_hor_scl_mode; 1754c156c21SMark Yao struct vop_reg yrgb_vsd_mode; 1764c156c21SMark Yao struct vop_reg yrgb_vsu_mode; 1774c156c21SMark Yao struct vop_reg yrgb_hsd_mode; 1784c156c21SMark Yao struct vop_reg yrgb_ver_scl_mode; 1794c156c21SMark Yao struct vop_reg yrgb_hor_scl_mode; 1804c156c21SMark Yao struct vop_reg line_load_mode; 1814c156c21SMark Yao struct vop_reg cbcr_axi_gather_num; 1824c156c21SMark Yao struct vop_reg yrgb_axi_gather_num; 1834c156c21SMark Yao struct vop_reg vsd_cbcr_gt2; 1844c156c21SMark Yao struct vop_reg vsd_cbcr_gt4; 1854c156c21SMark Yao struct vop_reg vsd_yrgb_gt2; 1864c156c21SMark Yao struct vop_reg vsd_yrgb_gt4; 1874c156c21SMark Yao struct vop_reg bic_coe_sel; 1884c156c21SMark Yao struct vop_reg cbcr_axi_gather_en; 1894c156c21SMark Yao struct vop_reg yrgb_axi_gather_en; 1904c156c21SMark Yao 1914c156c21SMark Yao struct vop_reg lb_mode; 1924c156c21SMark Yao struct vop_reg scale_yrgb_x; 1934c156c21SMark Yao struct vop_reg scale_yrgb_y; 1944c156c21SMark Yao struct vop_reg scale_cbcr_x; 1954c156c21SMark Yao struct vop_reg scale_cbcr_y; 1964c156c21SMark Yao }; 1974c156c21SMark Yao 1982048e328SMark Yao struct vop_win_phy { 1994c156c21SMark Yao const struct vop_scl_regs *scl; 2002048e328SMark Yao const uint32_t *data_formats; 2012048e328SMark Yao uint32_t nformats; 2022048e328SMark Yao 2032048e328SMark Yao struct vop_reg enable; 2042048e328SMark Yao struct vop_reg format; 20585a359f2STomasz Figa struct vop_reg rb_swap; 2062048e328SMark Yao struct vop_reg act_info; 2072048e328SMark Yao struct vop_reg dsp_info; 2082048e328SMark Yao struct vop_reg dsp_st; 2092048e328SMark Yao struct vop_reg yrgb_mst; 2102048e328SMark Yao struct vop_reg uv_mst; 2112048e328SMark Yao struct vop_reg yrgb_vir; 2122048e328SMark Yao struct vop_reg uv_vir; 2132048e328SMark Yao 2142048e328SMark Yao struct vop_reg dst_alpha_ctl; 2152048e328SMark Yao struct vop_reg src_alpha_ctl; 2162048e328SMark Yao }; 2172048e328SMark Yao 2182048e328SMark Yao struct vop_win_data { 2192048e328SMark Yao uint32_t base; 2202048e328SMark Yao const struct vop_win_phy *phy; 2212048e328SMark Yao enum drm_plane_type type; 2222048e328SMark Yao }; 2232048e328SMark Yao 2242048e328SMark Yao struct vop_data { 2252048e328SMark Yao const struct vop_reg_data *init_table; 2262048e328SMark Yao unsigned int table_size; 2272048e328SMark Yao const struct vop_ctrl *ctrl; 2282048e328SMark Yao const struct vop_win_data *win; 2292048e328SMark Yao unsigned int win_size; 2302048e328SMark Yao }; 2312048e328SMark Yao 2322048e328SMark Yao static const uint32_t formats_01[] = { 2332048e328SMark Yao DRM_FORMAT_XRGB8888, 2342048e328SMark Yao DRM_FORMAT_ARGB8888, 23585a359f2STomasz Figa DRM_FORMAT_XBGR8888, 23685a359f2STomasz Figa DRM_FORMAT_ABGR8888, 2372048e328SMark Yao DRM_FORMAT_RGB888, 23885a359f2STomasz Figa DRM_FORMAT_BGR888, 2392048e328SMark Yao DRM_FORMAT_RGB565, 24085a359f2STomasz Figa DRM_FORMAT_BGR565, 2412048e328SMark Yao DRM_FORMAT_NV12, 2422048e328SMark Yao DRM_FORMAT_NV16, 2432048e328SMark Yao DRM_FORMAT_NV24, 2442048e328SMark Yao }; 2452048e328SMark Yao 2462048e328SMark Yao static const uint32_t formats_234[] = { 2472048e328SMark Yao DRM_FORMAT_XRGB8888, 2482048e328SMark Yao DRM_FORMAT_ARGB8888, 24985a359f2STomasz Figa DRM_FORMAT_XBGR8888, 25085a359f2STomasz Figa DRM_FORMAT_ABGR8888, 2512048e328SMark Yao DRM_FORMAT_RGB888, 25285a359f2STomasz Figa DRM_FORMAT_BGR888, 2532048e328SMark Yao DRM_FORMAT_RGB565, 25485a359f2STomasz Figa DRM_FORMAT_BGR565, 2552048e328SMark Yao }; 2562048e328SMark Yao 2574c156c21SMark Yao static const struct vop_scl_regs win_full_scl = { 2584c156c21SMark Yao .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31), 2594c156c21SMark Yao .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30), 2604c156c21SMark Yao .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28), 2614c156c21SMark Yao .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26), 2624c156c21SMark Yao .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24), 2634c156c21SMark Yao .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23), 2644c156c21SMark Yao .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22), 2654c156c21SMark Yao .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20), 2664c156c21SMark Yao .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18), 2674c156c21SMark Yao .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16), 2684c156c21SMark Yao .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15), 2694c156c21SMark Yao .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12), 2704c156c21SMark Yao .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8), 2714c156c21SMark Yao .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7), 2724c156c21SMark Yao .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6), 2734c156c21SMark Yao .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5), 2744c156c21SMark Yao .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4), 2754c156c21SMark Yao .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2), 2764c156c21SMark Yao .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1), 2774c156c21SMark Yao .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0), 2784c156c21SMark Yao .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5), 2794c156c21SMark Yao .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 2804c156c21SMark Yao .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 2814c156c21SMark Yao .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 2824c156c21SMark Yao .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16), 2834c156c21SMark Yao }; 2844c156c21SMark Yao 2852048e328SMark Yao static const struct vop_win_phy win01_data = { 2864c156c21SMark Yao .scl = &win_full_scl, 2872048e328SMark Yao .data_formats = formats_01, 2882048e328SMark Yao .nformats = ARRAY_SIZE(formats_01), 2892048e328SMark Yao .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), 2902048e328SMark Yao .format = VOP_REG(WIN0_CTRL0, 0x7, 1), 29185a359f2STomasz Figa .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12), 2922048e328SMark Yao .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0), 2932048e328SMark Yao .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0), 2942048e328SMark Yao .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0), 2952048e328SMark Yao .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0), 2962048e328SMark Yao .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0), 2972048e328SMark Yao .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0), 2982048e328SMark Yao .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16), 2992048e328SMark Yao .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0), 3002048e328SMark Yao .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0), 3012048e328SMark Yao }; 3022048e328SMark Yao 3032048e328SMark Yao static const struct vop_win_phy win23_data = { 3042048e328SMark Yao .data_formats = formats_234, 3052048e328SMark Yao .nformats = ARRAY_SIZE(formats_234), 3062048e328SMark Yao .enable = VOP_REG(WIN2_CTRL0, 0x1, 0), 3072048e328SMark Yao .format = VOP_REG(WIN2_CTRL0, 0x7, 1), 30885a359f2STomasz Figa .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12), 3092048e328SMark Yao .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0), 3102048e328SMark Yao .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0), 3112048e328SMark Yao .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0), 3122048e328SMark Yao .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0), 3132048e328SMark Yao .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0), 3142048e328SMark Yao .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0), 3152048e328SMark Yao }; 3162048e328SMark Yao 3172048e328SMark Yao static const struct vop_ctrl ctrl_data = { 3182048e328SMark Yao .standby = VOP_REG(SYS_CTRL, 0x1, 22), 3192048e328SMark Yao .gate_en = VOP_REG(SYS_CTRL, 0x1, 23), 3202048e328SMark Yao .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20), 3212048e328SMark Yao .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12), 3222048e328SMark Yao .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13), 3232048e328SMark Yao .edp_en = VOP_REG(SYS_CTRL, 0x1, 14), 3242048e328SMark Yao .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15), 3252048e328SMark Yao .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1), 3262048e328SMark Yao .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6), 3272048e328SMark Yao .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19), 3282048e328SMark Yao .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0), 3292048e328SMark Yao .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4), 3302048e328SMark Yao .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 3312048e328SMark Yao .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0), 3322048e328SMark Yao .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 3332048e328SMark Yao .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0), 3342048e328SMark Yao .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0), 3352048e328SMark Yao .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0), 3362048e328SMark Yao }; 3372048e328SMark Yao 3382048e328SMark Yao static const struct vop_reg_data vop_init_reg_table[] = { 3392048e328SMark Yao {SYS_CTRL, 0x00c00000}, 3402048e328SMark Yao {DSP_CTRL0, 0x00000000}, 3412048e328SMark Yao {WIN0_CTRL0, 0x00000080}, 3422048e328SMark Yao {WIN1_CTRL0, 0x00000080}, 343c1998f08SMark Yao /* TODO: Win2/3 support multiple area function, but we haven't found 344c1998f08SMark Yao * a suitable way to use it yet, so let's just use them as other windows 345c1998f08SMark Yao * with only area 0 enabled. 346c1998f08SMark Yao */ 347c1998f08SMark Yao {WIN2_CTRL0, 0x00000010}, 348c1998f08SMark Yao {WIN3_CTRL0, 0x00000010}, 3492048e328SMark Yao }; 3502048e328SMark Yao 3512048e328SMark Yao /* 3522048e328SMark Yao * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 3532048e328SMark Yao * special support to get alpha blending working. For now, just use overlay 354d3cae7dfSyao mark * window 3 for the drm cursor. 355d3cae7dfSyao mark * 3562048e328SMark Yao */ 3572048e328SMark Yao static const struct vop_win_data rk3288_vop_win_data[] = { 3582048e328SMark Yao { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, 359d3cae7dfSyao mark { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY }, 3602048e328SMark Yao { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, 361d3cae7dfSyao mark { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR }, 3622048e328SMark Yao }; 3632048e328SMark Yao 3642048e328SMark Yao static const struct vop_data rk3288_vop = { 3652048e328SMark Yao .init_table = vop_init_reg_table, 3662048e328SMark Yao .table_size = ARRAY_SIZE(vop_init_reg_table), 3672048e328SMark Yao .ctrl = &ctrl_data, 3682048e328SMark Yao .win = rk3288_vop_win_data, 3692048e328SMark Yao .win_size = ARRAY_SIZE(rk3288_vop_win_data), 3702048e328SMark Yao }; 3712048e328SMark Yao 3722048e328SMark Yao static const struct of_device_id vop_driver_dt_match[] = { 3732048e328SMark Yao { .compatible = "rockchip,rk3288-vop", 3742048e328SMark Yao .data = &rk3288_vop }, 3752048e328SMark Yao {}, 3762048e328SMark Yao }; 3773b134cedSLuis de Bethencourt MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 3782048e328SMark Yao 3792048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 3802048e328SMark Yao { 3812048e328SMark Yao writel(v, vop->regs + offset); 3822048e328SMark Yao vop->regsbak[offset >> 2] = v; 3832048e328SMark Yao } 3842048e328SMark Yao 3852048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 3862048e328SMark Yao { 3872048e328SMark Yao return readl(vop->regs + offset); 3882048e328SMark Yao } 3892048e328SMark Yao 3902048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 3912048e328SMark Yao const struct vop_reg *reg) 3922048e328SMark Yao { 3932048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 3942048e328SMark Yao } 3952048e328SMark Yao 3962048e328SMark Yao static inline void vop_cfg_done(struct vop *vop) 3972048e328SMark Yao { 3982048e328SMark Yao writel(0x01, vop->regs + REG_CFG_DONE); 3992048e328SMark Yao } 4002048e328SMark Yao 4012048e328SMark Yao static inline void vop_mask_write(struct vop *vop, uint32_t offset, 4022048e328SMark Yao uint32_t mask, uint32_t v) 4032048e328SMark Yao { 4042048e328SMark Yao if (mask) { 4052048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 4062048e328SMark Yao 4072048e328SMark Yao cached_val = (cached_val & ~mask) | v; 4082048e328SMark Yao writel(cached_val, vop->regs + offset); 4092048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 4102048e328SMark Yao } 4112048e328SMark Yao } 4122048e328SMark Yao 4132048e328SMark Yao static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 4142048e328SMark Yao uint32_t mask, uint32_t v) 4152048e328SMark Yao { 4162048e328SMark Yao if (mask) { 4172048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 4182048e328SMark Yao 4192048e328SMark Yao cached_val = (cached_val & ~mask) | v; 4202048e328SMark Yao writel_relaxed(cached_val, vop->regs + offset); 4212048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 4222048e328SMark Yao } 4232048e328SMark Yao } 4242048e328SMark Yao 42585a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 42685a359f2STomasz Figa { 42785a359f2STomasz Figa switch (format) { 42885a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 42985a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 43085a359f2STomasz Figa case DRM_FORMAT_BGR888: 43185a359f2STomasz Figa case DRM_FORMAT_BGR565: 43285a359f2STomasz Figa return true; 43385a359f2STomasz Figa default: 43485a359f2STomasz Figa return false; 43585a359f2STomasz Figa } 43685a359f2STomasz Figa } 43785a359f2STomasz Figa 4382048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 4392048e328SMark Yao { 4402048e328SMark Yao switch (format) { 4412048e328SMark Yao case DRM_FORMAT_XRGB8888: 4422048e328SMark Yao case DRM_FORMAT_ARGB8888: 44385a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 44485a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 4452048e328SMark Yao return VOP_FMT_ARGB8888; 4462048e328SMark Yao case DRM_FORMAT_RGB888: 44785a359f2STomasz Figa case DRM_FORMAT_BGR888: 4482048e328SMark Yao return VOP_FMT_RGB888; 4492048e328SMark Yao case DRM_FORMAT_RGB565: 45085a359f2STomasz Figa case DRM_FORMAT_BGR565: 4512048e328SMark Yao return VOP_FMT_RGB565; 4522048e328SMark Yao case DRM_FORMAT_NV12: 4532048e328SMark Yao return VOP_FMT_YUV420SP; 4542048e328SMark Yao case DRM_FORMAT_NV16: 4552048e328SMark Yao return VOP_FMT_YUV422SP; 4562048e328SMark Yao case DRM_FORMAT_NV24: 4572048e328SMark Yao return VOP_FMT_YUV444SP; 4582048e328SMark Yao default: 4592048e328SMark Yao DRM_ERROR("unsupport format[%08x]\n", format); 4602048e328SMark Yao return -EINVAL; 4612048e328SMark Yao } 4622048e328SMark Yao } 4632048e328SMark Yao 46484c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 46584c7f8caSMark Yao { 46684c7f8caSMark Yao switch (format) { 46784c7f8caSMark Yao case DRM_FORMAT_NV12: 46884c7f8caSMark Yao case DRM_FORMAT_NV16: 46984c7f8caSMark Yao case DRM_FORMAT_NV24: 47084c7f8caSMark Yao return true; 47184c7f8caSMark Yao default: 47284c7f8caSMark Yao return false; 47384c7f8caSMark Yao } 47484c7f8caSMark Yao } 47584c7f8caSMark Yao 4762048e328SMark Yao static bool is_alpha_support(uint32_t format) 4772048e328SMark Yao { 4782048e328SMark Yao switch (format) { 4792048e328SMark Yao case DRM_FORMAT_ARGB8888: 48085a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 4812048e328SMark Yao return true; 4822048e328SMark Yao default: 4832048e328SMark Yao return false; 4842048e328SMark Yao } 4852048e328SMark Yao } 4862048e328SMark Yao 4874c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 4884c156c21SMark Yao uint32_t dst, bool is_horizontal, 4894c156c21SMark Yao int vsu_mode, int *vskiplines) 4904c156c21SMark Yao { 4914c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 4924c156c21SMark Yao 4934c156c21SMark Yao if (is_horizontal) { 4944c156c21SMark Yao if (mode == SCALE_UP) 4954c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 4964c156c21SMark Yao else if (mode == SCALE_DOWN) 4974c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 4984c156c21SMark Yao } else { 4994c156c21SMark Yao if (mode == SCALE_UP) { 5004c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 5014c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 5024c156c21SMark Yao else 5034c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 5044c156c21SMark Yao } else if (mode == SCALE_DOWN) { 5054c156c21SMark Yao if (vskiplines) { 5064c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 5074c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 5084c156c21SMark Yao *vskiplines); 5094c156c21SMark Yao } else { 5104c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 5114c156c21SMark Yao } 5124c156c21SMark Yao } 5134c156c21SMark Yao } 5144c156c21SMark Yao 5154c156c21SMark Yao return val; 5164c156c21SMark Yao } 5174c156c21SMark Yao 5184c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 5194c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 5204c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 5214c156c21SMark Yao { 5224c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 5234c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 5244c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 5254c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 5264c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 5274c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 5284c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 5294c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 5304c156c21SMark Yao uint16_t vsu_mode; 5314c156c21SMark Yao uint16_t lb_mode; 5324c156c21SMark Yao uint32_t val; 5334c156c21SMark Yao int vskiplines; 5344c156c21SMark Yao 5354c156c21SMark Yao if (dst_w > 3840) { 5364c156c21SMark Yao DRM_ERROR("Maximum destination width (3840) exceeded\n"); 5374c156c21SMark Yao return; 5384c156c21SMark Yao } 5394c156c21SMark Yao 5404c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 5414c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 5424c156c21SMark Yao 5434c156c21SMark Yao if (is_yuv) { 5444c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 5454c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 5464c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 5474c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 5484c156c21SMark Yao else 5494c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 5504c156c21SMark Yao } else { 5514c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 5524c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 5534c156c21SMark Yao else 5544c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 5554c156c21SMark Yao } 5564c156c21SMark Yao 5574c156c21SMark Yao VOP_SCL_SET(vop, win, lb_mode, lb_mode); 5584c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 5594c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 5604c156c21SMark Yao DRM_ERROR("ERROR : not allow yrgb ver scale\n"); 5614c156c21SMark Yao return; 5624c156c21SMark Yao } 5634c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 5644c156c21SMark Yao DRM_ERROR("ERROR : not allow cbcr ver scale\n"); 5654c156c21SMark Yao return; 5664c156c21SMark Yao } 5674c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 5684c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 5694c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 5704c156c21SMark Yao } else { 5714c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 5724c156c21SMark Yao } 5734c156c21SMark Yao 5744c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 5754c156c21SMark Yao true, 0, NULL); 5764c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 5774c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 5784c156c21SMark Yao false, vsu_mode, &vskiplines); 5794c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 5804c156c21SMark Yao 5814c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4); 5824c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2); 5834c156c21SMark Yao 5844c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 5854c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 5864c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 5874c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 5884c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode); 5894c156c21SMark Yao if (is_yuv) { 5904c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 5914c156c21SMark Yao dst_w, true, 0, NULL); 5924c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 5934c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 5944c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 5954c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 5964c156c21SMark Yao 5974c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4); 5984c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2); 5994c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 6004c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 6014c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 6024c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 6034c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode); 6044c156c21SMark Yao } 6054c156c21SMark Yao } 6064c156c21SMark Yao 6071067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 6081067219bSMark Yao { 6091067219bSMark Yao unsigned long flags; 6101067219bSMark Yao 6111067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 6121067219bSMark Yao return; 6131067219bSMark Yao 6141067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 6151067219bSMark Yao 6161067219bSMark Yao vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 6171067219bSMark Yao DSP_HOLD_VALID_INTR_EN(1)); 6181067219bSMark Yao 6191067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 6201067219bSMark Yao } 6211067219bSMark Yao 6221067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 6231067219bSMark Yao { 6241067219bSMark Yao unsigned long flags; 6251067219bSMark Yao 6261067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 6271067219bSMark Yao return; 6281067219bSMark Yao 6291067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 6301067219bSMark Yao 6311067219bSMark Yao vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 6321067219bSMark Yao DSP_HOLD_VALID_INTR_EN(0)); 6331067219bSMark Yao 6341067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 6351067219bSMark Yao } 6361067219bSMark Yao 63763ebb9faSMark Yao static void vop_enable(struct drm_crtc *crtc) 6382048e328SMark Yao { 6392048e328SMark Yao struct vop *vop = to_vop(crtc); 6402048e328SMark Yao int ret; 6412048e328SMark Yao 64231e980c5SMark Yao if (vop->is_enabled) 64331e980c5SMark Yao return; 64431e980c5SMark Yao 6455d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 6465d82d1a7SMark Yao if (ret < 0) { 6475d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 6485d82d1a7SMark Yao return; 6495d82d1a7SMark Yao } 6505d82d1a7SMark Yao 6512048e328SMark Yao ret = clk_enable(vop->hclk); 6522048e328SMark Yao if (ret < 0) { 6532048e328SMark Yao dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 6542048e328SMark Yao return; 6552048e328SMark Yao } 6562048e328SMark Yao 6572048e328SMark Yao ret = clk_enable(vop->dclk); 6582048e328SMark Yao if (ret < 0) { 6592048e328SMark Yao dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 6602048e328SMark Yao goto err_disable_hclk; 6612048e328SMark Yao } 6622048e328SMark Yao 6632048e328SMark Yao ret = clk_enable(vop->aclk); 6642048e328SMark Yao if (ret < 0) { 6652048e328SMark Yao dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 6662048e328SMark Yao goto err_disable_dclk; 6672048e328SMark Yao } 6682048e328SMark Yao 6692048e328SMark Yao /* 6702048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 6712048e328SMark Yao * automatically with this master device via common driver code. 6722048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 6732048e328SMark Yao * mapping. 6742048e328SMark Yao */ 6752048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 6762048e328SMark Yao if (ret) { 6772048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 6782048e328SMark Yao goto err_disable_aclk; 6792048e328SMark Yao } 6802048e328SMark Yao 68177faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 68252ab7891SMark Yao /* 68352ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 68452ab7891SMark Yao */ 68552ab7891SMark Yao vop->is_enabled = true; 68652ab7891SMark Yao 6872048e328SMark Yao spin_lock(&vop->reg_lock); 6882048e328SMark Yao 6892048e328SMark Yao VOP_CTRL_SET(vop, standby, 0); 6902048e328SMark Yao 6912048e328SMark Yao spin_unlock(&vop->reg_lock); 6922048e328SMark Yao 6932048e328SMark Yao enable_irq(vop->irq); 6942048e328SMark Yao 695b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6962048e328SMark Yao 6972048e328SMark Yao return; 6982048e328SMark Yao 6992048e328SMark Yao err_disable_aclk: 7002048e328SMark Yao clk_disable(vop->aclk); 7012048e328SMark Yao err_disable_dclk: 7022048e328SMark Yao clk_disable(vop->dclk); 7032048e328SMark Yao err_disable_hclk: 7042048e328SMark Yao clk_disable(vop->hclk); 7052048e328SMark Yao } 7062048e328SMark Yao 7070ad3675dSMark Yao static void vop_crtc_disable(struct drm_crtc *crtc) 7082048e328SMark Yao { 7092048e328SMark Yao struct vop *vop = to_vop(crtc); 7102048e328SMark Yao 71131e980c5SMark Yao if (!vop->is_enabled) 71231e980c5SMark Yao return; 71331e980c5SMark Yao 714b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 7152048e328SMark Yao 7162048e328SMark Yao /* 7171067219bSMark Yao * Vop standby will take effect at end of current frame, 7181067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 7191067219bSMark Yao * 7201067219bSMark Yao * we must wait standby complete when we want to disable aclk, 7211067219bSMark Yao * if not, memory bus maybe dead. 7222048e328SMark Yao */ 7231067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 7241067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 7251067219bSMark Yao 7262048e328SMark Yao spin_lock(&vop->reg_lock); 7272048e328SMark Yao 7282048e328SMark Yao VOP_CTRL_SET(vop, standby, 1); 7292048e328SMark Yao 7302048e328SMark Yao spin_unlock(&vop->reg_lock); 73152ab7891SMark Yao 7321067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 7332048e328SMark Yao 7341067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 7351067219bSMark Yao 7361067219bSMark Yao disable_irq(vop->irq); 7371067219bSMark Yao 7381067219bSMark Yao vop->is_enabled = false; 7391067219bSMark Yao 7401067219bSMark Yao /* 7411067219bSMark Yao * vop standby complete, so iommu detach is safe. 7421067219bSMark Yao */ 7432048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 7442048e328SMark Yao 7451067219bSMark Yao clk_disable(vop->dclk); 7462048e328SMark Yao clk_disable(vop->aclk); 7472048e328SMark Yao clk_disable(vop->hclk); 7485d82d1a7SMark Yao pm_runtime_put(vop->dev); 7492048e328SMark Yao } 7502048e328SMark Yao 75163ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 7522048e328SMark Yao { 75363ebb9faSMark Yao drm_plane_cleanup(plane); 7542048e328SMark Yao } 7552048e328SMark Yao 75663ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 75763ebb9faSMark Yao struct drm_plane_state *state) 7582048e328SMark Yao { 75963ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 76063ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 7612048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 76263ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 7632048e328SMark Yao const struct vop_win_data *win = vop_win->data; 7642048e328SMark Yao bool visible; 7652048e328SMark Yao int ret; 76663ebb9faSMark Yao struct drm_rect *dest = &vop_plane_state->dest; 76763ebb9faSMark Yao struct drm_rect *src = &vop_plane_state->src; 76863ebb9faSMark Yao struct drm_rect clip; 7694c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 7704c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7714c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 7724c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7732048e328SMark Yao 77463ebb9faSMark Yao crtc = crtc ? crtc : plane->state->crtc; 77563ebb9faSMark Yao /* 77663ebb9faSMark Yao * Both crtc or plane->state->crtc can be null. 77763ebb9faSMark Yao */ 77863ebb9faSMark Yao if (!crtc || !fb) 77963ebb9faSMark Yao goto out_disable; 78063ebb9faSMark Yao src->x1 = state->src_x; 78163ebb9faSMark Yao src->y1 = state->src_y; 78263ebb9faSMark Yao src->x2 = state->src_x + state->src_w; 78363ebb9faSMark Yao src->y2 = state->src_y + state->src_h; 78463ebb9faSMark Yao dest->x1 = state->crtc_x; 78563ebb9faSMark Yao dest->y1 = state->crtc_y; 78663ebb9faSMark Yao dest->x2 = state->crtc_x + state->crtc_w; 78763ebb9faSMark Yao dest->y2 = state->crtc_y + state->crtc_h; 78863ebb9faSMark Yao 78963ebb9faSMark Yao clip.x1 = 0; 79063ebb9faSMark Yao clip.y1 = 0; 79163ebb9faSMark Yao clip.x2 = crtc->mode.hdisplay; 79263ebb9faSMark Yao clip.y2 = crtc->mode.vdisplay; 79363ebb9faSMark Yao 79463ebb9faSMark Yao ret = drm_plane_helper_check_update(plane, crtc, state->fb, 79563ebb9faSMark Yao src, dest, &clip, 7964c156c21SMark Yao min_scale, 7974c156c21SMark Yao max_scale, 79863ebb9faSMark Yao true, true, &visible); 7992048e328SMark Yao if (ret) 8002048e328SMark Yao return ret; 8012048e328SMark Yao 8022048e328SMark Yao if (!visible) 80363ebb9faSMark Yao goto out_disable; 8042048e328SMark Yao 80563ebb9faSMark Yao vop_plane_state->format = vop_convert_format(fb->pixel_format); 80663ebb9faSMark Yao if (vop_plane_state->format < 0) 80763ebb9faSMark Yao return vop_plane_state->format; 80884c7f8caSMark Yao 80984c7f8caSMark Yao /* 81084c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 81184c7f8caSMark Yao * need align with 2 pixel. 81284c7f8caSMark Yao */ 81363ebb9faSMark Yao if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) 81463ebb9faSMark Yao return -EINVAL; 81563ebb9faSMark Yao 81663ebb9faSMark Yao vop_plane_state->enable = true; 81763ebb9faSMark Yao 81863ebb9faSMark Yao return 0; 81963ebb9faSMark Yao 82063ebb9faSMark Yao out_disable: 82163ebb9faSMark Yao vop_plane_state->enable = false; 82263ebb9faSMark Yao return 0; 82384c7f8caSMark Yao } 82484c7f8caSMark Yao 82563ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 82663ebb9faSMark Yao struct drm_plane_state *old_state) 82763ebb9faSMark Yao { 82863ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); 82963ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 83063ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 83163ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 8322048e328SMark Yao 83363ebb9faSMark Yao if (!old_state->crtc) 83463ebb9faSMark Yao return; 8352048e328SMark Yao 83663ebb9faSMark Yao spin_lock(&vop->reg_lock); 8372048e328SMark Yao 83863ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 8392048e328SMark Yao 84063ebb9faSMark Yao spin_unlock(&vop->reg_lock); 84163ebb9faSMark Yao 84263ebb9faSMark Yao vop_plane_state->enable = false; 84363ebb9faSMark Yao } 84463ebb9faSMark Yao 84563ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 84663ebb9faSMark Yao struct drm_plane_state *old_state) 84763ebb9faSMark Yao { 84863ebb9faSMark Yao struct drm_plane_state *state = plane->state; 84963ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 85063ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 85163ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 85263ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 85363ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 85463ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 85563ebb9faSMark Yao unsigned int actual_w, actual_h; 85663ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 85763ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 85863ebb9faSMark Yao struct drm_rect *src = &vop_plane_state->src; 85963ebb9faSMark Yao struct drm_rect *dest = &vop_plane_state->dest; 86063ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 86163ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 86263ebb9faSMark Yao unsigned long offset; 86363ebb9faSMark Yao dma_addr_t dma_addr; 86463ebb9faSMark Yao uint32_t val; 86563ebb9faSMark Yao bool rb_swap; 86663ebb9faSMark Yao 86763ebb9faSMark Yao /* 86863ebb9faSMark Yao * can't update plane when vop is disabled. 86963ebb9faSMark Yao */ 87063ebb9faSMark Yao if (!crtc) 87163ebb9faSMark Yao return; 87263ebb9faSMark Yao 87363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 87463ebb9faSMark Yao return; 87563ebb9faSMark Yao 87663ebb9faSMark Yao if (!vop_plane_state->enable) { 87763ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 87863ebb9faSMark Yao return; 87963ebb9faSMark Yao } 88063ebb9faSMark Yao 88163ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 88263ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 88363ebb9faSMark Yao 88463ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 88563ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 88663ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 88763ebb9faSMark Yao 88863ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 88963ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 89063ebb9faSMark Yao 89163ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 89263ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 89363ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 89463ebb9faSMark Yao 89563ebb9faSMark Yao offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 89663ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 89763ebb9faSMark Yao vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 89863ebb9faSMark Yao 89963ebb9faSMark Yao spin_lock(&vop->reg_lock); 90063ebb9faSMark Yao 90163ebb9faSMark Yao VOP_WIN_SET(vop, win, format, vop_plane_state->format); 90263ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 90363ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); 90463ebb9faSMark Yao if (is_yuv_support(fb->pixel_format)) { 90584c7f8caSMark Yao int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 90684c7f8caSMark Yao int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 90784c7f8caSMark Yao int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 90884c7f8caSMark Yao 90984c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 91084c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 91184c7f8caSMark Yao 91263ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 91363ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 91484c7f8caSMark Yao 91563ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 91663ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 91763ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 91884c7f8caSMark Yao } 9194c156c21SMark Yao 9204c156c21SMark Yao if (win->phy->scl) 9214c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 92263ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 9234c156c21SMark Yao fb->pixel_format); 9244c156c21SMark Yao 92563ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 92663ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 92763ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 9284c156c21SMark Yao 92963ebb9faSMark Yao rb_swap = has_rb_swapped(fb->pixel_format); 93085a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 9312048e328SMark Yao 93263ebb9faSMark Yao if (is_alpha_support(fb->pixel_format)) { 9332048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 9342048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 9352048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 9362048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 9372048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 9382048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 9392048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 9402048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 9412048e328SMark Yao } else { 9422048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 9432048e328SMark Yao } 9442048e328SMark Yao 9452048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 9462048e328SMark Yao spin_unlock(&vop->reg_lock); 9472048e328SMark Yao } 9482048e328SMark Yao 94963ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 95063ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 95163ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 95263ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 95363ebb9faSMark Yao }; 95463ebb9faSMark Yao 95563ebb9faSMark Yao void vop_atomic_plane_reset(struct drm_plane *plane) 9562048e328SMark Yao { 95763ebb9faSMark Yao struct vop_plane_state *vop_plane_state = 95863ebb9faSMark Yao to_vop_plane_state(plane->state); 95963ebb9faSMark Yao 96063ebb9faSMark Yao if (plane->state && plane->state->fb) 96163ebb9faSMark Yao drm_framebuffer_unreference(plane->state->fb); 96263ebb9faSMark Yao 96363ebb9faSMark Yao kfree(vop_plane_state); 96463ebb9faSMark Yao vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); 96563ebb9faSMark Yao if (!vop_plane_state) 96663ebb9faSMark Yao return; 96763ebb9faSMark Yao 96863ebb9faSMark Yao plane->state = &vop_plane_state->base; 96963ebb9faSMark Yao plane->state->plane = plane; 9702048e328SMark Yao } 9712048e328SMark Yao 97263ebb9faSMark Yao struct drm_plane_state * 97363ebb9faSMark Yao vop_atomic_plane_duplicate_state(struct drm_plane *plane) 9742048e328SMark Yao { 97563ebb9faSMark Yao struct vop_plane_state *old_vop_plane_state; 97663ebb9faSMark Yao struct vop_plane_state *vop_plane_state; 9772048e328SMark Yao 97863ebb9faSMark Yao if (WARN_ON(!plane->state)) 97963ebb9faSMark Yao return NULL; 9802048e328SMark Yao 98163ebb9faSMark Yao old_vop_plane_state = to_vop_plane_state(plane->state); 98263ebb9faSMark Yao vop_plane_state = kmemdup(old_vop_plane_state, 98363ebb9faSMark Yao sizeof(*vop_plane_state), GFP_KERNEL); 98463ebb9faSMark Yao if (!vop_plane_state) 98563ebb9faSMark Yao return NULL; 98663ebb9faSMark Yao 98763ebb9faSMark Yao __drm_atomic_helper_plane_duplicate_state(plane, 98863ebb9faSMark Yao &vop_plane_state->base); 98963ebb9faSMark Yao 99063ebb9faSMark Yao return &vop_plane_state->base; 9912048e328SMark Yao } 9922048e328SMark Yao 99363ebb9faSMark Yao static void vop_atomic_plane_destroy_state(struct drm_plane *plane, 99463ebb9faSMark Yao struct drm_plane_state *state) 9952048e328SMark Yao { 99663ebb9faSMark Yao struct vop_plane_state *vop_state = to_vop_plane_state(state); 9972048e328SMark Yao 99863ebb9faSMark Yao __drm_atomic_helper_plane_destroy_state(plane, state); 9992048e328SMark Yao 100063ebb9faSMark Yao kfree(vop_state); 10012048e328SMark Yao } 10022048e328SMark Yao 10032048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 100463ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 100563ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 10062048e328SMark Yao .destroy = vop_plane_destroy, 100763ebb9faSMark Yao .reset = vop_atomic_plane_reset, 100863ebb9faSMark Yao .atomic_duplicate_state = vop_atomic_plane_duplicate_state, 100963ebb9faSMark Yao .atomic_destroy_state = vop_atomic_plane_destroy_state, 10102048e328SMark Yao }; 10112048e328SMark Yao 10122048e328SMark Yao int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, 10132048e328SMark Yao int connector_type, 10142048e328SMark Yao int out_mode) 10152048e328SMark Yao { 10162048e328SMark Yao struct vop *vop = to_vop(crtc); 10172048e328SMark Yao 1018d0e20d0eSMark Yao if (WARN_ON(!vop->is_enabled)) 1019d0e20d0eSMark Yao return -EINVAL; 1020d0e20d0eSMark Yao 1021d0e20d0eSMark Yao switch (connector_type) { 1022d0e20d0eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 1023d0e20d0eSMark Yao VOP_CTRL_SET(vop, rgb_en, 1); 1024d0e20d0eSMark Yao break; 1025d0e20d0eSMark Yao case DRM_MODE_CONNECTOR_eDP: 1026d0e20d0eSMark Yao VOP_CTRL_SET(vop, edp_en, 1); 1027d0e20d0eSMark Yao break; 1028d0e20d0eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 1029d0e20d0eSMark Yao VOP_CTRL_SET(vop, hdmi_en, 1); 1030d0e20d0eSMark Yao break; 1031d0e20d0eSMark Yao default: 1032d0e20d0eSMark Yao DRM_ERROR("unsupport connector_type[%d]\n", connector_type); 1033d0e20d0eSMark Yao return -EINVAL; 1034d0e20d0eSMark Yao }; 1035d0e20d0eSMark Yao VOP_CTRL_SET(vop, out_mode, out_mode); 10362048e328SMark Yao 10372048e328SMark Yao return 0; 10382048e328SMark Yao } 1039f66a1627SPhilipp Zabel EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); 10402048e328SMark Yao 10412048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 10422048e328SMark Yao { 10432048e328SMark Yao struct vop *vop = to_vop(crtc); 10442048e328SMark Yao unsigned long flags; 10452048e328SMark Yao 104663ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10472048e328SMark Yao return -EPERM; 10482048e328SMark Yao 10492048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 10502048e328SMark Yao 10512048e328SMark Yao vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1)); 10522048e328SMark Yao 10532048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10542048e328SMark Yao 10552048e328SMark Yao return 0; 10562048e328SMark Yao } 10572048e328SMark Yao 10582048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 10592048e328SMark Yao { 10602048e328SMark Yao struct vop *vop = to_vop(crtc); 10612048e328SMark Yao unsigned long flags; 10622048e328SMark Yao 106363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10642048e328SMark Yao return; 106531e980c5SMark Yao 10662048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 10672048e328SMark Yao vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0)); 10682048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10692048e328SMark Yao } 10702048e328SMark Yao 107163ebb9faSMark Yao static void vop_crtc_wait_for_update(struct drm_crtc *crtc) 107263ebb9faSMark Yao { 107363ebb9faSMark Yao struct vop *vop = to_vop(crtc); 107463ebb9faSMark Yao 107563ebb9faSMark Yao reinit_completion(&vop->wait_update_complete); 107663ebb9faSMark Yao WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); 107763ebb9faSMark Yao } 107863ebb9faSMark Yao 10792048e328SMark Yao static const struct rockchip_crtc_funcs private_crtc_funcs = { 10802048e328SMark Yao .enable_vblank = vop_crtc_enable_vblank, 10812048e328SMark Yao .disable_vblank = vop_crtc_disable_vblank, 108263ebb9faSMark Yao .wait_for_update = vop_crtc_wait_for_update, 10832048e328SMark Yao }; 10842048e328SMark Yao 10852048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 10862048e328SMark Yao const struct drm_display_mode *mode, 10872048e328SMark Yao struct drm_display_mode *adjusted_mode) 10882048e328SMark Yao { 10892048e328SMark Yao if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) 10902048e328SMark Yao return false; 10912048e328SMark Yao 10922048e328SMark Yao return true; 10932048e328SMark Yao } 10942048e328SMark Yao 109563ebb9faSMark Yao static void vop_crtc_enable(struct drm_crtc *crtc) 10962048e328SMark Yao { 10972048e328SMark Yao struct vop *vop = to_vop(crtc); 109863ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 10992048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 11002048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 11012048e328SMark Yao u16 htotal = adjusted_mode->htotal; 11022048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 11032048e328SMark Yao u16 hact_end = hact_st + hdisplay; 11042048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 11052048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 11062048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 11072048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 11082048e328SMark Yao u16 vact_end = vact_st + vdisplay; 11092048e328SMark Yao uint32_t val; 11102048e328SMark Yao 111163ebb9faSMark Yao vop_enable(crtc); 11122048e328SMark Yao /* 1113ce3887edSMark Yao * If dclk rate is zero, mean that scanout is stop, 1114ce3887edSMark Yao * we don't need wait any more. 11152048e328SMark Yao */ 1116ce3887edSMark Yao if (clk_get_rate(vop->dclk)) { 1117ce3887edSMark Yao /* 1118ce3887edSMark Yao * Rk3288 vop timing register is immediately, when configure 1119ce3887edSMark Yao * display timing on display time, may cause tearing. 1120ce3887edSMark Yao * 1121ce3887edSMark Yao * Vop standby will take effect at end of current frame, 1122ce3887edSMark Yao * if dsp hold valid irq happen, it means standby complete. 1123ce3887edSMark Yao * 1124ce3887edSMark Yao * mode set: 1125ce3887edSMark Yao * standby and wait complete --> |---- 1126ce3887edSMark Yao * | display time 1127ce3887edSMark Yao * |---- 1128ce3887edSMark Yao * |---> dsp hold irq 1129ce3887edSMark Yao * configure display timing --> | 1130ce3887edSMark Yao * standby exit | 1131ce3887edSMark Yao * | new frame start. 1132ce3887edSMark Yao */ 1133ce3887edSMark Yao 1134ce3887edSMark Yao reinit_completion(&vop->dsp_hold_completion); 1135ce3887edSMark Yao vop_dsp_hold_valid_irq_enable(vop); 1136ce3887edSMark Yao 1137ce3887edSMark Yao spin_lock(&vop->reg_lock); 1138ce3887edSMark Yao 1139ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 1); 1140ce3887edSMark Yao 1141ce3887edSMark Yao spin_unlock(&vop->reg_lock); 1142ce3887edSMark Yao 1143ce3887edSMark Yao wait_for_completion(&vop->dsp_hold_completion); 1144ce3887edSMark Yao 1145ce3887edSMark Yao vop_dsp_hold_valid_irq_disable(vop); 1146ce3887edSMark Yao } 11472048e328SMark Yao 11482048e328SMark Yao val = 0x8; 114944ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 115044ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 11512048e328SMark Yao VOP_CTRL_SET(vop, pin_pol, val); 11522048e328SMark Yao 11532048e328SMark Yao VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 11542048e328SMark Yao val = hact_st << 16; 11552048e328SMark Yao val |= hact_end; 11562048e328SMark Yao VOP_CTRL_SET(vop, hact_st_end, val); 11572048e328SMark Yao VOP_CTRL_SET(vop, hpost_st_end, val); 11582048e328SMark Yao 11592048e328SMark Yao VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 11602048e328SMark Yao val = vact_st << 16; 11612048e328SMark Yao val |= vact_end; 11622048e328SMark Yao VOP_CTRL_SET(vop, vact_st_end, val); 11632048e328SMark Yao VOP_CTRL_SET(vop, vpost_st_end, val); 11642048e328SMark Yao 11652048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1166ce3887edSMark Yao 1167ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 0); 11682048e328SMark Yao } 11692048e328SMark Yao 117063ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 117163ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 117263ebb9faSMark Yao { 117363ebb9faSMark Yao struct vop *vop = to_vop(crtc); 117463ebb9faSMark Yao 117563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 117663ebb9faSMark Yao return; 117763ebb9faSMark Yao 117863ebb9faSMark Yao spin_lock(&vop->reg_lock); 117963ebb9faSMark Yao 118063ebb9faSMark Yao vop_cfg_done(vop); 118163ebb9faSMark Yao 118263ebb9faSMark Yao spin_unlock(&vop->reg_lock); 118363ebb9faSMark Yao } 118463ebb9faSMark Yao 118563ebb9faSMark Yao static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 118663ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 118763ebb9faSMark Yao { 118863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 118963ebb9faSMark Yao 119063ebb9faSMark Yao if (crtc->state->event) { 119163ebb9faSMark Yao WARN_ON(drm_crtc_vblank_get(crtc) != 0); 119263ebb9faSMark Yao 119363ebb9faSMark Yao vop->event = crtc->state->event; 119463ebb9faSMark Yao crtc->state->event = NULL; 119563ebb9faSMark Yao } 11962048e328SMark Yao } 11972048e328SMark Yao 11982048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 11990ad3675dSMark Yao .enable = vop_crtc_enable, 12000ad3675dSMark Yao .disable = vop_crtc_disable, 12012048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 120263ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 120363ebb9faSMark Yao .atomic_begin = vop_crtc_atomic_begin, 12042048e328SMark Yao }; 12052048e328SMark Yao 12062048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 12072048e328SMark Yao { 12082048e328SMark Yao drm_crtc_cleanup(crtc); 12092048e328SMark Yao } 12102048e328SMark Yao 12112048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 121263ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 121363ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 12142048e328SMark Yao .destroy = vop_crtc_destroy, 121563ebb9faSMark Yao .reset = drm_atomic_helper_crtc_reset, 121663ebb9faSMark Yao .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 121763ebb9faSMark Yao .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 12182048e328SMark Yao }; 12192048e328SMark Yao 122063ebb9faSMark Yao static bool vop_win_pending_is_complete(struct vop_win *vop_win) 12212048e328SMark Yao { 122263ebb9faSMark Yao struct drm_plane *plane = &vop_win->base; 122363ebb9faSMark Yao struct vop_plane_state *state = to_vop_plane_state(plane->state); 12242048e328SMark Yao dma_addr_t yrgb_mst; 12252048e328SMark Yao 122663ebb9faSMark Yao if (!state->enable) 122763ebb9faSMark Yao return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; 122863ebb9faSMark Yao 12292048e328SMark Yao yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 12302048e328SMark Yao 123163ebb9faSMark Yao return yrgb_mst == state->yrgb_mst; 12322048e328SMark Yao } 12332048e328SMark Yao 123463ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 12352048e328SMark Yao { 123663ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 123763ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 123863ebb9faSMark Yao unsigned long flags; 123963ebb9faSMark Yao int i; 12402048e328SMark Yao 124163ebb9faSMark Yao for (i = 0; i < vop->data->win_size; i++) { 124263ebb9faSMark Yao if (!vop_win_pending_is_complete(&vop->win[i])) 12432048e328SMark Yao return; 12442048e328SMark Yao } 12452048e328SMark Yao 124663ebb9faSMark Yao if (vop->event) { 124763ebb9faSMark Yao spin_lock_irqsave(&drm->event_lock, flags); 12482048e328SMark Yao 124963ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 125063ebb9faSMark Yao drm_crtc_vblank_put(crtc); 125163ebb9faSMark Yao vop->event = NULL; 125263ebb9faSMark Yao 125363ebb9faSMark Yao spin_unlock_irqrestore(&drm->event_lock, flags); 12542048e328SMark Yao } 125563ebb9faSMark Yao if (!completion_done(&vop->wait_update_complete)) 125663ebb9faSMark Yao complete(&vop->wait_update_complete); 12572048e328SMark Yao } 12582048e328SMark Yao 12592048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 12602048e328SMark Yao { 12612048e328SMark Yao struct vop *vop = data; 1262b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 12632048e328SMark Yao uint32_t intr0_reg, active_irqs; 12642048e328SMark Yao unsigned long flags; 12651067219bSMark Yao int ret = IRQ_NONE; 12662048e328SMark Yao 12672048e328SMark Yao /* 12682048e328SMark Yao * INTR_CTRL0 register has interrupt status, enable and clear bits, we 12692048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 12702048e328SMark Yao */ 12712048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 12722048e328SMark Yao intr0_reg = vop_readl(vop, INTR_CTRL0); 12732048e328SMark Yao active_irqs = intr0_reg & INTR_MASK; 12742048e328SMark Yao /* Clear all active interrupt sources */ 12752048e328SMark Yao if (active_irqs) 12762048e328SMark Yao vop_writel(vop, INTR_CTRL0, 12772048e328SMark Yao intr0_reg | (active_irqs << INTR_CLR_SHIFT)); 12782048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 12792048e328SMark Yao 12802048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 12812048e328SMark Yao if (!active_irqs) 12822048e328SMark Yao return IRQ_NONE; 12832048e328SMark Yao 12841067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 12851067219bSMark Yao complete(&vop->dsp_hold_completion); 12861067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 12871067219bSMark Yao ret = IRQ_HANDLED; 12882048e328SMark Yao } 12892048e328SMark Yao 12901067219bSMark Yao if (active_irqs & FS_INTR) { 1291b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 129263ebb9faSMark Yao vop_handle_vblank(vop); 12931067219bSMark Yao active_irqs &= ~FS_INTR; 129463ebb9faSMark Yao ret = IRQ_HANDLED; 12951067219bSMark Yao } 12962048e328SMark Yao 12971067219bSMark Yao /* Unhandled irqs are spurious. */ 12981067219bSMark Yao if (active_irqs) 12991067219bSMark Yao DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 13001067219bSMark Yao 13011067219bSMark Yao return ret; 13022048e328SMark Yao } 13032048e328SMark Yao 13042048e328SMark Yao static int vop_create_crtc(struct vop *vop) 13052048e328SMark Yao { 13062048e328SMark Yao const struct vop_data *vop_data = vop->data; 13072048e328SMark Yao struct device *dev = vop->dev; 13082048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 13092048e328SMark Yao struct drm_plane *primary = NULL, *cursor = NULL, *plane; 13102048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 13112048e328SMark Yao struct device_node *port; 13122048e328SMark Yao int ret; 13132048e328SMark Yao int i; 13142048e328SMark Yao 13152048e328SMark Yao /* 13162048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 13172048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 13182048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 13192048e328SMark Yao */ 13202048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13212048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13222048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 13232048e328SMark Yao 13242048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 13252048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 13262048e328SMark Yao continue; 13272048e328SMark Yao 13282048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 13292048e328SMark Yao 0, &vop_plane_funcs, 13302048e328SMark Yao win_data->phy->data_formats, 13312048e328SMark Yao win_data->phy->nformats, 1332b0b3b795SVille Syrjälä win_data->type, NULL); 13332048e328SMark Yao if (ret) { 13342048e328SMark Yao DRM_ERROR("failed to initialize plane\n"); 13352048e328SMark Yao goto err_cleanup_planes; 13362048e328SMark Yao } 13372048e328SMark Yao 13382048e328SMark Yao plane = &vop_win->base; 133963ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 13402048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 13412048e328SMark Yao primary = plane; 13422048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 13432048e328SMark Yao cursor = plane; 13442048e328SMark Yao } 13452048e328SMark Yao 13462048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1347f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 13482048e328SMark Yao if (ret) 13492048e328SMark Yao return ret; 13502048e328SMark Yao 13512048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 13522048e328SMark Yao 13532048e328SMark Yao /* 13542048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 13552048e328SMark Yao * to the newly created crtc. 13562048e328SMark Yao */ 13572048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13582048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13592048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 13602048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 13612048e328SMark Yao 13622048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 13632048e328SMark Yao continue; 13642048e328SMark Yao 13652048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 13662048e328SMark Yao possible_crtcs, 13672048e328SMark Yao &vop_plane_funcs, 13682048e328SMark Yao win_data->phy->data_formats, 13692048e328SMark Yao win_data->phy->nformats, 1370b0b3b795SVille Syrjälä win_data->type, NULL); 13712048e328SMark Yao if (ret) { 13722048e328SMark Yao DRM_ERROR("failed to initialize overlay plane\n"); 13732048e328SMark Yao goto err_cleanup_crtc; 13742048e328SMark Yao } 137563ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 13762048e328SMark Yao } 13772048e328SMark Yao 13782048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 13792048e328SMark Yao if (!port) { 13802048e328SMark Yao DRM_ERROR("no port node found in %s\n", 13812048e328SMark Yao dev->of_node->full_name); 13822048e328SMark Yao goto err_cleanup_crtc; 13832048e328SMark Yao } 13842048e328SMark Yao 13851067219bSMark Yao init_completion(&vop->dsp_hold_completion); 138663ebb9faSMark Yao init_completion(&vop->wait_update_complete); 13872048e328SMark Yao crtc->port = port; 1388b5f7b755SMark Yao rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); 13892048e328SMark Yao 13902048e328SMark Yao return 0; 13912048e328SMark Yao 13922048e328SMark Yao err_cleanup_crtc: 13932048e328SMark Yao drm_crtc_cleanup(crtc); 13942048e328SMark Yao err_cleanup_planes: 13952048e328SMark Yao list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) 13962048e328SMark Yao drm_plane_cleanup(plane); 13972048e328SMark Yao return ret; 13982048e328SMark Yao } 13992048e328SMark Yao 14002048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 14012048e328SMark Yao { 14022048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 14032048e328SMark Yao 1404b5f7b755SMark Yao rockchip_unregister_crtc_funcs(crtc); 14052048e328SMark Yao of_node_put(crtc->port); 14062048e328SMark Yao drm_crtc_cleanup(crtc); 14072048e328SMark Yao } 14082048e328SMark Yao 14092048e328SMark Yao static int vop_initial(struct vop *vop) 14102048e328SMark Yao { 14112048e328SMark Yao const struct vop_data *vop_data = vop->data; 14122048e328SMark Yao const struct vop_reg_data *init_table = vop_data->init_table; 14132048e328SMark Yao struct reset_control *ahb_rst; 14142048e328SMark Yao int i, ret; 14152048e328SMark Yao 14162048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 14172048e328SMark Yao if (IS_ERR(vop->hclk)) { 14182048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 14192048e328SMark Yao return PTR_ERR(vop->hclk); 14202048e328SMark Yao } 14212048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 14222048e328SMark Yao if (IS_ERR(vop->aclk)) { 14232048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 14242048e328SMark Yao return PTR_ERR(vop->aclk); 14252048e328SMark Yao } 14262048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 14272048e328SMark Yao if (IS_ERR(vop->dclk)) { 14282048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 14292048e328SMark Yao return PTR_ERR(vop->dclk); 14302048e328SMark Yao } 14312048e328SMark Yao 14322048e328SMark Yao ret = clk_prepare(vop->dclk); 14332048e328SMark Yao if (ret < 0) { 14342048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 1435d7b53fd9SSjoerd Simons return ret; 14362048e328SMark Yao } 14372048e328SMark Yao 1438d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1439d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 14402048e328SMark Yao if (ret < 0) { 1441d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable hclk\n"); 14422048e328SMark Yao goto err_unprepare_dclk; 14432048e328SMark Yao } 14442048e328SMark Yao 1445d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 14462048e328SMark Yao if (ret < 0) { 1447d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1448d7b53fd9SSjoerd Simons goto err_disable_hclk; 14492048e328SMark Yao } 1450d7b53fd9SSjoerd Simons 14512048e328SMark Yao /* 14522048e328SMark Yao * do hclk_reset, reset all vop registers. 14532048e328SMark Yao */ 14542048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 14552048e328SMark Yao if (IS_ERR(ahb_rst)) { 14562048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 14572048e328SMark Yao ret = PTR_ERR(ahb_rst); 1458d7b53fd9SSjoerd Simons goto err_disable_aclk; 14592048e328SMark Yao } 14602048e328SMark Yao reset_control_assert(ahb_rst); 14612048e328SMark Yao usleep_range(10, 20); 14622048e328SMark Yao reset_control_deassert(ahb_rst); 14632048e328SMark Yao 14642048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 14652048e328SMark Yao 14662048e328SMark Yao for (i = 0; i < vop_data->table_size; i++) 14672048e328SMark Yao vop_writel(vop, init_table[i].offset, init_table[i].value); 14682048e328SMark Yao 14692048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14702048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 14712048e328SMark Yao 14722048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 14732048e328SMark Yao } 14742048e328SMark Yao 14752048e328SMark Yao vop_cfg_done(vop); 14762048e328SMark Yao 14772048e328SMark Yao /* 14782048e328SMark Yao * do dclk_reset, let all config take affect. 14792048e328SMark Yao */ 14802048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 14812048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 14822048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 14832048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1484d7b53fd9SSjoerd Simons goto err_disable_aclk; 14852048e328SMark Yao } 14862048e328SMark Yao reset_control_assert(vop->dclk_rst); 14872048e328SMark Yao usleep_range(10, 20); 14882048e328SMark Yao reset_control_deassert(vop->dclk_rst); 14892048e328SMark Yao 14902048e328SMark Yao clk_disable(vop->hclk); 1491d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 14922048e328SMark Yao 149331e980c5SMark Yao vop->is_enabled = false; 14942048e328SMark Yao 14952048e328SMark Yao return 0; 14962048e328SMark Yao 1497d7b53fd9SSjoerd Simons err_disable_aclk: 1498d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 14992048e328SMark Yao err_disable_hclk: 1500d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 15012048e328SMark Yao err_unprepare_dclk: 15022048e328SMark Yao clk_unprepare(vop->dclk); 15032048e328SMark Yao return ret; 15042048e328SMark Yao } 15052048e328SMark Yao 15062048e328SMark Yao /* 15072048e328SMark Yao * Initialize the vop->win array elements. 15082048e328SMark Yao */ 15092048e328SMark Yao static void vop_win_init(struct vop *vop) 15102048e328SMark Yao { 15112048e328SMark Yao const struct vop_data *vop_data = vop->data; 15122048e328SMark Yao unsigned int i; 15132048e328SMark Yao 15142048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 15152048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 15162048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 15172048e328SMark Yao 15182048e328SMark Yao vop_win->data = win_data; 15192048e328SMark Yao vop_win->vop = vop; 15202048e328SMark Yao } 15212048e328SMark Yao } 15222048e328SMark Yao 15232048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 15242048e328SMark Yao { 15252048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 15262048e328SMark Yao const struct of_device_id *of_id; 15272048e328SMark Yao const struct vop_data *vop_data; 15282048e328SMark Yao struct drm_device *drm_dev = data; 15292048e328SMark Yao struct vop *vop; 15302048e328SMark Yao struct resource *res; 15312048e328SMark Yao size_t alloc_size; 15323ea68922SHeiko Stuebner int ret, irq; 15332048e328SMark Yao 15342048e328SMark Yao of_id = of_match_device(vop_driver_dt_match, dev); 15352048e328SMark Yao vop_data = of_id->data; 15362048e328SMark Yao if (!vop_data) 15372048e328SMark Yao return -ENODEV; 15382048e328SMark Yao 15392048e328SMark Yao /* Allocate vop struct and its vop_win array */ 15402048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 15412048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 15422048e328SMark Yao if (!vop) 15432048e328SMark Yao return -ENOMEM; 15442048e328SMark Yao 15452048e328SMark Yao vop->dev = dev; 15462048e328SMark Yao vop->data = vop_data; 15472048e328SMark Yao vop->drm_dev = drm_dev; 15482048e328SMark Yao dev_set_drvdata(dev, vop); 15492048e328SMark Yao 15502048e328SMark Yao vop_win_init(vop); 15512048e328SMark Yao 15522048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15532048e328SMark Yao vop->len = resource_size(res); 15542048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 15552048e328SMark Yao if (IS_ERR(vop->regs)) 15562048e328SMark Yao return PTR_ERR(vop->regs); 15572048e328SMark Yao 15582048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 15592048e328SMark Yao if (!vop->regsbak) 15602048e328SMark Yao return -ENOMEM; 15612048e328SMark Yao 15622048e328SMark Yao ret = vop_initial(vop); 15632048e328SMark Yao if (ret < 0) { 15642048e328SMark Yao dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 15652048e328SMark Yao return ret; 15662048e328SMark Yao } 15672048e328SMark Yao 15683ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 15693ea68922SHeiko Stuebner if (irq < 0) { 15702048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 15713ea68922SHeiko Stuebner return irq; 15722048e328SMark Yao } 15733ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 15742048e328SMark Yao 15752048e328SMark Yao spin_lock_init(&vop->reg_lock); 15762048e328SMark Yao spin_lock_init(&vop->irq_lock); 15772048e328SMark Yao 15782048e328SMark Yao mutex_init(&vop->vsync_mutex); 15792048e328SMark Yao 158063ebb9faSMark Yao ret = devm_request_irq(dev, vop->irq, vop_isr, 15812048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 15822048e328SMark Yao if (ret) 15832048e328SMark Yao return ret; 15842048e328SMark Yao 15852048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 15862048e328SMark Yao disable_irq(vop->irq); 15872048e328SMark Yao 15882048e328SMark Yao ret = vop_create_crtc(vop); 15892048e328SMark Yao if (ret) 15902048e328SMark Yao return ret; 15912048e328SMark Yao 15922048e328SMark Yao pm_runtime_enable(&pdev->dev); 15932048e328SMark Yao return 0; 15942048e328SMark Yao } 15952048e328SMark Yao 15962048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 15972048e328SMark Yao { 15982048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 15992048e328SMark Yao 16002048e328SMark Yao pm_runtime_disable(dev); 16012048e328SMark Yao vop_destroy_crtc(vop); 16022048e328SMark Yao } 16032048e328SMark Yao 16042048e328SMark Yao static const struct component_ops vop_component_ops = { 16052048e328SMark Yao .bind = vop_bind, 16062048e328SMark Yao .unbind = vop_unbind, 16072048e328SMark Yao }; 16082048e328SMark Yao 16092048e328SMark Yao static int vop_probe(struct platform_device *pdev) 16102048e328SMark Yao { 16112048e328SMark Yao struct device *dev = &pdev->dev; 16122048e328SMark Yao 16132048e328SMark Yao if (!dev->of_node) { 16142048e328SMark Yao dev_err(dev, "can't find vop devices\n"); 16152048e328SMark Yao return -ENODEV; 16162048e328SMark Yao } 16172048e328SMark Yao 16182048e328SMark Yao return component_add(dev, &vop_component_ops); 16192048e328SMark Yao } 16202048e328SMark Yao 16212048e328SMark Yao static int vop_remove(struct platform_device *pdev) 16222048e328SMark Yao { 16232048e328SMark Yao component_del(&pdev->dev, &vop_component_ops); 16242048e328SMark Yao 16252048e328SMark Yao return 0; 16262048e328SMark Yao } 16272048e328SMark Yao 16282048e328SMark Yao struct platform_driver vop_platform_driver = { 16292048e328SMark Yao .probe = vop_probe, 16302048e328SMark Yao .remove = vop_remove, 16312048e328SMark Yao .driver = { 16322048e328SMark Yao .name = "rockchip-vop", 16332048e328SMark Yao .owner = THIS_MODULE, 16342048e328SMark Yao .of_match_table = of_match_ptr(vop_driver_dt_match), 16352048e328SMark Yao }, 16362048e328SMark Yao }; 16372048e328SMark Yao 16382048e328SMark Yao module_platform_driver(vop_platform_driver); 16392048e328SMark Yao 16402048e328SMark Yao MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>"); 16412048e328SMark Yao MODULE_DESCRIPTION("ROCKCHIP VOP Driver"); 16422048e328SMark Yao MODULE_LICENSE("GPL v2"); 1643