19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22048e328SMark Yao /* 32048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 42048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 52048e328SMark Yao */ 62048e328SMark Yao 7c2156ccdSSam Ravnborg #include <linux/clk.h> 8c2156ccdSSam Ravnborg #include <linux/component.h> 9c2156ccdSSam Ravnborg #include <linux/delay.h> 10c2156ccdSSam Ravnborg #include <linux/iopoll.h> 11c2156ccdSSam Ravnborg #include <linux/kernel.h> 12c2156ccdSSam Ravnborg #include <linux/module.h> 13c2156ccdSSam Ravnborg #include <linux/of.h> 14c2156ccdSSam Ravnborg #include <linux/of_device.h> 15c2156ccdSSam Ravnborg #include <linux/overflow.h> 16c2156ccdSSam Ravnborg #include <linux/platform_device.h> 17c2156ccdSSam Ravnborg #include <linux/pm_runtime.h> 18c2156ccdSSam Ravnborg #include <linux/reset.h> 19c2156ccdSSam Ravnborg 202048e328SMark Yao #include <drm/drm.h> 2163ebb9faSMark Yao #include <drm/drm_atomic.h> 2215609559SEnric Balletbo i Serra #include <drm/drm_atomic_uapi.h> 232048e328SMark Yao #include <drm/drm_crtc.h> 2447a7eb45STomasz Figa #include <drm/drm_flip_work.h> 25c2156ccdSSam Ravnborg #include <drm/drm_fourcc.h> 2663d5e06aSHeiko Stuebner #include <drm/drm_gem_framebuffer_helper.h> 272048e328SMark Yao #include <drm/drm_plane_helper.h> 28fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 296c836d96SSean Paul #include <drm/drm_self_refresh_helper.h> 30c2156ccdSSam Ravnborg #include <drm/drm_vblank.h> 31c2156ccdSSam Ravnborg 326cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 333190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 346cca3869SSean Paul #endif 352048e328SMark Yao 362048e328SMark Yao #include "rockchip_drm_drv.h" 372048e328SMark Yao #include "rockchip_drm_gem.h" 382048e328SMark Yao #include "rockchip_drm_fb.h" 392048e328SMark Yao #include "rockchip_drm_vop.h" 401f0f0151SSandy Huang #include "rockchip_rgb.h" 412048e328SMark Yao 426c836d96SSean Paul #define VOP_SELF_REFRESH_ENTRY_DELAY_MS 100 436c836d96SSean Paul 442996fb75SEzequiel Garcia #define VOP_WIN_SET(vop, win, name, v) \ 459a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 462996fb75SEzequiel Garcia #define VOP_SCL_SET(vop, win, name, v) \ 479a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 482996fb75SEzequiel Garcia #define VOP_SCL_SET_EXT(vop, win, name, v) \ 499a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 509a61c54bSMark yao win->base, ~0, v, #name) 51ac6560dfSMark yao 522996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 531c21aa8fSDaniele Castagna do { \ 541c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 551c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 561c21aa8fSDaniele Castagna } while (0) 571c21aa8fSDaniele Castagna 582996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 591c21aa8fSDaniele Castagna do { \ 601c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 611c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 621c21aa8fSDaniele Castagna } while (0) 631c21aa8fSDaniele Castagna 64ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 659a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 669a61c54bSMark yao 679a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 689a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 69ac6560dfSMark yao 70dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 71dbb3d944SMark Yao do { \ 72c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 73dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 74c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 75dbb3d944SMark Yao reg |= (v) << i; \ 76c7647f86SJohn Keeping mask |= 1 << i; \ 77dbb3d944SMark Yao } \ 78c7647f86SJohn Keeping } \ 79ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 80dbb3d944SMark Yao } while (0) 81dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 82dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 83dbb3d944SMark Yao 842996fb75SEzequiel Garcia #define VOP_WIN_GET(vop, win, name) \ 852996fb75SEzequiel Garcia vop_read_reg(vop, win->offset, win->phy->name) 862048e328SMark Yao 87677e8bbcSDaniele Castagna #define VOP_WIN_HAS_REG(win, name) \ 88677e8bbcSDaniele Castagna (!!(win->phy->name.mask)) 89677e8bbcSDaniele Castagna 902048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 912048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 922048e328SMark Yao 9358badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 9458badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 9558badaa7SKristian H. Kristensen 962048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 972048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 982048e328SMark Yao 991c21aa8fSDaniele Castagna /* 1001c21aa8fSDaniele Castagna * The coefficients of the following matrix are all fixed points. 1011c21aa8fSDaniele Castagna * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 1021c21aa8fSDaniele Castagna * They are all represented in two's complement. 1031c21aa8fSDaniele Castagna */ 1041c21aa8fSDaniele Castagna static const uint32_t bt601_yuv2rgb[] = { 1051c21aa8fSDaniele Castagna 0x4A8, 0x0, 0x662, 1061c21aa8fSDaniele Castagna 0x4A8, 0x1E6F, 0x1CBF, 1071c21aa8fSDaniele Castagna 0x4A8, 0x812, 0x0, 1081c21aa8fSDaniele Castagna 0x321168, 0x0877CF, 0x2EB127 1091c21aa8fSDaniele Castagna }; 1101c21aa8fSDaniele Castagna 11147a7eb45STomasz Figa enum vop_pending { 11247a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 11347a7eb45STomasz Figa }; 11447a7eb45STomasz Figa 1152048e328SMark Yao struct vop_win { 1162048e328SMark Yao struct drm_plane base; 1172048e328SMark Yao const struct vop_win_data *data; 1181c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *yuv2yuv_data; 1192048e328SMark Yao struct vop *vop; 1202048e328SMark Yao }; 1212048e328SMark Yao 1221f0f0151SSandy Huang struct rockchip_rgb; 1232048e328SMark Yao struct vop { 1242048e328SMark Yao struct drm_crtc crtc; 1252048e328SMark Yao struct device *dev; 1262048e328SMark Yao struct drm_device *drm_dev; 12731e980c5SMark Yao bool is_enabled; 1282048e328SMark Yao 1291067219bSMark Yao struct completion dsp_hold_completion; 130bed030a4SSean Paul unsigned int win_enabled; 1314f9d39a7SDaniel Vetter 1324f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 13363ebb9faSMark Yao struct drm_pending_vblank_event *event; 1342048e328SMark Yao 13547a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 13647a7eb45STomasz Figa unsigned long pending; 13747a7eb45STomasz Figa 13869c34e41SYakir Yang struct completion line_flag_completion; 13969c34e41SYakir Yang 1402048e328SMark Yao const struct vop_data *data; 1412048e328SMark Yao 1422048e328SMark Yao uint32_t *regsbak; 1432048e328SMark Yao void __iomem *regs; 1442048e328SMark Yao 1452048e328SMark Yao /* physical map length of vop register */ 1462048e328SMark Yao uint32_t len; 1472048e328SMark Yao 1482048e328SMark Yao /* one time only one process allowed to config the register */ 1492048e328SMark Yao spinlock_t reg_lock; 1502048e328SMark Yao /* lock vop irq reg */ 1512048e328SMark Yao spinlock_t irq_lock; 152e334d48bSzain wang /* protects crtc enable/disable */ 153e334d48bSzain wang struct mutex vop_lock; 1542048e328SMark Yao 1552048e328SMark Yao unsigned int irq; 1562048e328SMark Yao 1572048e328SMark Yao /* vop AHP clk */ 1582048e328SMark Yao struct clk *hclk; 1592048e328SMark Yao /* vop dclk */ 1602048e328SMark Yao struct clk *dclk; 1612048e328SMark Yao /* vop share memory frequency */ 1622048e328SMark Yao struct clk *aclk; 1632048e328SMark Yao 1642048e328SMark Yao /* vop dclk reset */ 1652048e328SMark Yao struct reset_control *dclk_rst; 1662048e328SMark Yao 1671f0f0151SSandy Huang /* optional internal rgb encoder */ 1681f0f0151SSandy Huang struct rockchip_rgb *rgb; 1691f0f0151SSandy Huang 1702048e328SMark Yao struct vop_win win[]; 1712048e328SMark Yao }; 1722048e328SMark Yao 1732048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1742048e328SMark Yao { 1752048e328SMark Yao writel(v, vop->regs + offset); 1762048e328SMark Yao vop->regsbak[offset >> 2] = v; 1772048e328SMark Yao } 1782048e328SMark Yao 1792048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1802048e328SMark Yao { 1812048e328SMark Yao return readl(vop->regs + offset); 1822048e328SMark Yao } 1832048e328SMark Yao 1842048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1852048e328SMark Yao const struct vop_reg *reg) 1862048e328SMark Yao { 1872048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1882048e328SMark Yao } 1892048e328SMark Yao 1909a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 1919a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 1929a61c54bSMark yao const char *reg_name) 1932048e328SMark Yao { 1949a61c54bSMark yao int offset, mask, shift; 195d49463ecSMark Yao 1969a61c54bSMark yao if (!reg || !reg->mask) { 197d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 1989a61c54bSMark yao return; 1999a61c54bSMark yao } 2009a61c54bSMark yao 2019a61c54bSMark yao offset = reg->offset + _offset; 2029a61c54bSMark yao mask = reg->mask & _mask; 2039a61c54bSMark yao shift = reg->shift; 2049a61c54bSMark yao 2059a61c54bSMark yao if (reg->write_mask) { 206d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 207d49463ecSMark Yao } else { 2082048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 2092048e328SMark Yao 210d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 211d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 2122048e328SMark Yao } 2132048e328SMark Yao 2149a61c54bSMark yao if (reg->relaxed) 215d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 216d49463ecSMark Yao else 217d49463ecSMark Yao writel(v, vop->regs + offset); 2182048e328SMark Yao } 2192048e328SMark Yao 220dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 221dbb3d944SMark Yao const struct vop_reg *reg, int type) 222dbb3d944SMark Yao { 223dbb3d944SMark Yao uint32_t i, ret = 0; 224dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 225dbb3d944SMark Yao 226dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 227dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 228dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 229dbb3d944SMark Yao } 230dbb3d944SMark Yao 231dbb3d944SMark Yao return ret; 232dbb3d944SMark Yao } 233dbb3d944SMark Yao 2340cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2350cf33fe3SMark Yao { 2369a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2370cf33fe3SMark Yao } 2380cf33fe3SMark Yao 23985a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 24085a359f2STomasz Figa { 24185a359f2STomasz Figa switch (format) { 24285a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 24385a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 24485a359f2STomasz Figa case DRM_FORMAT_BGR888: 24585a359f2STomasz Figa case DRM_FORMAT_BGR565: 24685a359f2STomasz Figa return true; 24785a359f2STomasz Figa default: 24885a359f2STomasz Figa return false; 24985a359f2STomasz Figa } 25085a359f2STomasz Figa } 25185a359f2STomasz Figa 2522048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2532048e328SMark Yao { 2542048e328SMark Yao switch (format) { 2552048e328SMark Yao case DRM_FORMAT_XRGB8888: 2562048e328SMark Yao case DRM_FORMAT_ARGB8888: 25785a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 25885a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2592048e328SMark Yao return VOP_FMT_ARGB8888; 2602048e328SMark Yao case DRM_FORMAT_RGB888: 26185a359f2STomasz Figa case DRM_FORMAT_BGR888: 2622048e328SMark Yao return VOP_FMT_RGB888; 2632048e328SMark Yao case DRM_FORMAT_RGB565: 26485a359f2STomasz Figa case DRM_FORMAT_BGR565: 2652048e328SMark Yao return VOP_FMT_RGB565; 2662048e328SMark Yao case DRM_FORMAT_NV12: 2672048e328SMark Yao return VOP_FMT_YUV420SP; 2682048e328SMark Yao case DRM_FORMAT_NV16: 2692048e328SMark Yao return VOP_FMT_YUV422SP; 2702048e328SMark Yao case DRM_FORMAT_NV24: 2712048e328SMark Yao return VOP_FMT_YUV444SP; 2722048e328SMark Yao default: 273ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2742048e328SMark Yao return -EINVAL; 2752048e328SMark Yao } 2762048e328SMark Yao } 2772048e328SMark Yao 2784c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2794c156c21SMark Yao uint32_t dst, bool is_horizontal, 2804c156c21SMark Yao int vsu_mode, int *vskiplines) 2814c156c21SMark Yao { 2824c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2834c156c21SMark Yao 284ce91d373SJeffy Chen if (vskiplines) 285ce91d373SJeffy Chen *vskiplines = 0; 286ce91d373SJeffy Chen 2874c156c21SMark Yao if (is_horizontal) { 2884c156c21SMark Yao if (mode == SCALE_UP) 2894c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2904c156c21SMark Yao else if (mode == SCALE_DOWN) 2914c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2924c156c21SMark Yao } else { 2934c156c21SMark Yao if (mode == SCALE_UP) { 2944c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2954c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2964c156c21SMark Yao else 2974c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2984c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2994c156c21SMark Yao if (vskiplines) { 3004c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 3014c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 3024c156c21SMark Yao *vskiplines); 3034c156c21SMark Yao } else { 3044c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3054c156c21SMark Yao } 3064c156c21SMark Yao } 3074c156c21SMark Yao } 3084c156c21SMark Yao 3094c156c21SMark Yao return val; 3104c156c21SMark Yao } 3114c156c21SMark Yao 3124c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3134c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 31445babef0SMaxime Ripard uint32_t dst_h, const struct drm_format_info *info) 3154c156c21SMark Yao { 3164c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3174c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3184c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 319d8bd23d9SAyan Kumar Halder bool is_yuv = false; 320f3e9632cSMaxime Ripard uint16_t cbcr_src_w = src_w / info->hsub; 321f3e9632cSMaxime Ripard uint16_t cbcr_src_h = src_h / info->vsub; 3224c156c21SMark Yao uint16_t vsu_mode; 3234c156c21SMark Yao uint16_t lb_mode; 3244c156c21SMark Yao uint32_t val; 325ce91d373SJeffy Chen int vskiplines; 3264c156c21SMark Yao 327d8bd23d9SAyan Kumar Halder if (info->is_yuv) 328d8bd23d9SAyan Kumar Halder is_yuv = true; 329d8bd23d9SAyan Kumar Halder 3304c156c21SMark Yao if (dst_w > 3840) { 331ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3324c156c21SMark Yao return; 3334c156c21SMark Yao } 3344c156c21SMark Yao 3351194fffbSMark Yao if (!win->phy->scl->ext) { 3361194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3371194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3381194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3391194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3401194fffbSMark Yao if (is_yuv) { 3411194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 342ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3431194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 344ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3451194fffbSMark Yao } 3461194fffbSMark Yao return; 3471194fffbSMark Yao } 3481194fffbSMark Yao 3494c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3504c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3514c156c21SMark Yao 3524c156c21SMark Yao if (is_yuv) { 3534c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3544c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3554c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3564c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3574c156c21SMark Yao else 3584c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3594c156c21SMark Yao } else { 3604c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3614c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3624c156c21SMark Yao else 3634c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3644c156c21SMark Yao } 3654c156c21SMark Yao 3661194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3674c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3684c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 369ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3704c156c21SMark Yao return; 3714c156c21SMark Yao } 3724c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 373ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3744c156c21SMark Yao return; 3754c156c21SMark Yao } 3764c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3774c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3784c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3794c156c21SMark Yao } else { 3804c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3814c156c21SMark Yao } 3824c156c21SMark Yao 3834c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3844c156c21SMark Yao true, 0, NULL); 3854c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3864c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3874c156c21SMark Yao false, vsu_mode, &vskiplines); 3884c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3894c156c21SMark Yao 3901194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3911194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3924c156c21SMark Yao 3931194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3941194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3951194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3961194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3971194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3984c156c21SMark Yao if (is_yuv) { 3994c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 4004c156c21SMark Yao dst_w, true, 0, NULL); 4014c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 4024c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 4034c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 4044c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 4054c156c21SMark Yao 4061194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 4071194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4081194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4091194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4101194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4111194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4121194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4134c156c21SMark Yao } 4144c156c21SMark Yao } 4154c156c21SMark Yao 4161067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4171067219bSMark Yao { 4181067219bSMark Yao unsigned long flags; 4191067219bSMark Yao 4201067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4211067219bSMark Yao return; 4221067219bSMark Yao 4231067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4241067219bSMark Yao 425fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 426dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4271067219bSMark Yao 4281067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4291067219bSMark Yao } 4301067219bSMark Yao 4311067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4321067219bSMark Yao { 4331067219bSMark Yao unsigned long flags; 4341067219bSMark Yao 4351067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4361067219bSMark Yao return; 4371067219bSMark Yao 4381067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4391067219bSMark Yao 440dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4411067219bSMark Yao 4421067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4431067219bSMark Yao } 4441067219bSMark Yao 44569c34e41SYakir Yang /* 44669c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 44769c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 44869c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 44969c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 45069c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 45169c34e41SYakir Yang * 45269c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 45369c34e41SYakir Yang * Interrupts 45469c34e41SYakir Yang * LINE_FLAG -------------------------------+ 45569c34e41SYakir Yang * FRAME_SYNC ----+ | 45669c34e41SYakir Yang * | | 45769c34e41SYakir Yang * v v 45869c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 45969c34e41SYakir Yang * ^ ^ ^ ^ 46069c34e41SYakir Yang * | | | | 46169c34e41SYakir Yang * | | | | 46269c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 46369c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 46469c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 46569c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 46669c34e41SYakir Yang */ 46769c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 46869c34e41SYakir Yang { 46969c34e41SYakir Yang uint32_t line_flag_irq; 47069c34e41SYakir Yang unsigned long flags; 47169c34e41SYakir Yang 47269c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 47369c34e41SYakir Yang 47469c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 47569c34e41SYakir Yang 47669c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 47769c34e41SYakir Yang 47869c34e41SYakir Yang return !!line_flag_irq; 47969c34e41SYakir Yang } 48069c34e41SYakir Yang 481459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 48269c34e41SYakir Yang { 48369c34e41SYakir Yang unsigned long flags; 48469c34e41SYakir Yang 48569c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 48669c34e41SYakir Yang return; 48769c34e41SYakir Yang 48869c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 48969c34e41SYakir Yang 490fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 49169c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 49269c34e41SYakir Yang 49369c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 49469c34e41SYakir Yang } 49569c34e41SYakir Yang 49669c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 49769c34e41SYakir Yang { 49869c34e41SYakir Yang unsigned long flags; 49969c34e41SYakir Yang 50069c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 50169c34e41SYakir Yang return; 50269c34e41SYakir Yang 50369c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 50469c34e41SYakir Yang 50569c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 50669c34e41SYakir Yang 50769c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 50869c34e41SYakir Yang } 50969c34e41SYakir Yang 510e2810a71SHeiko Stuebner static int vop_core_clks_enable(struct vop *vop) 511e2810a71SHeiko Stuebner { 512e2810a71SHeiko Stuebner int ret; 513e2810a71SHeiko Stuebner 514e2810a71SHeiko Stuebner ret = clk_enable(vop->hclk); 515e2810a71SHeiko Stuebner if (ret < 0) 516e2810a71SHeiko Stuebner return ret; 517e2810a71SHeiko Stuebner 518e2810a71SHeiko Stuebner ret = clk_enable(vop->aclk); 519e2810a71SHeiko Stuebner if (ret < 0) 520e2810a71SHeiko Stuebner goto err_disable_hclk; 521e2810a71SHeiko Stuebner 522e2810a71SHeiko Stuebner return 0; 523e2810a71SHeiko Stuebner 524e2810a71SHeiko Stuebner err_disable_hclk: 525e2810a71SHeiko Stuebner clk_disable(vop->hclk); 526e2810a71SHeiko Stuebner return ret; 527e2810a71SHeiko Stuebner } 528e2810a71SHeiko Stuebner 529e2810a71SHeiko Stuebner static void vop_core_clks_disable(struct vop *vop) 530e2810a71SHeiko Stuebner { 531e2810a71SHeiko Stuebner clk_disable(vop->aclk); 532e2810a71SHeiko Stuebner clk_disable(vop->hclk); 533e2810a71SHeiko Stuebner } 534e2810a71SHeiko Stuebner 5352b60e11dSSean Paul static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 536e9abc611SJonas Karlman { 5372b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 5382b60e11dSSean Paul 539e9abc611SJonas Karlman if (win->phy->scl && win->phy->scl->ext) { 540e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 541e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 542e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 543e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 544e9abc611SJonas Karlman } 545e9abc611SJonas Karlman 546e9abc611SJonas Karlman VOP_WIN_SET(vop, win, enable, 0); 547bed030a4SSean Paul vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 548e9abc611SJonas Karlman } 549e9abc611SJonas Karlman 5506c836d96SSean Paul static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 5512048e328SMark Yao { 5522048e328SMark Yao struct vop *vop = to_vop(crtc); 55364d77564SMark yao int ret, i; 5542048e328SMark Yao 5555d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5565d82d1a7SMark Yao if (ret < 0) { 557d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 5585e570373SJeffy Chen return ret; 5595d82d1a7SMark Yao } 5605d82d1a7SMark Yao 561e2810a71SHeiko Stuebner ret = vop_core_clks_enable(vop); 56239a9ad8fSSean Paul if (WARN_ON(ret < 0)) 56339a9ad8fSSean Paul goto err_put_pm_runtime; 5642048e328SMark Yao 5652048e328SMark Yao ret = clk_enable(vop->dclk); 56639a9ad8fSSean Paul if (WARN_ON(ret < 0)) 567e2810a71SHeiko Stuebner goto err_disable_core; 5682048e328SMark Yao 5692048e328SMark Yao /* 5702048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5712048e328SMark Yao * automatically with this master device via common driver code. 5722048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5732048e328SMark Yao * mapping. 5742048e328SMark Yao */ 5752048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5762048e328SMark Yao if (ret) { 577d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 578d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 579e2810a71SHeiko Stuebner goto err_disable_dclk; 5802048e328SMark Yao } 5812048e328SMark Yao 58276f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 58376f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 58476f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 58576f1416eSMarc Zyngier 58664d77564SMark yao /* 58764d77564SMark yao * We need to make sure that all windows are disabled before we 58864d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 58964d77564SMark yao * buffer later. 5906c836d96SSean Paul * 5916c836d96SSean Paul * In the case of enable-after-PSR, we don't need to worry about this 5926c836d96SSean Paul * case since the buffer is guaranteed to be valid and disabling the 5936c836d96SSean Paul * window will result in screen glitches on PSR exit. 59464d77564SMark yao */ 5956c836d96SSean Paul if (!old_state || !old_state->self_refresh_active) { 59664d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 59764d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 59864d77564SMark yao 5992b60e11dSSean Paul vop_win_disable(vop, vop_win); 60064d77564SMark yao } 6016c836d96SSean Paul } 60276f1416eSMarc Zyngier spin_unlock(&vop->reg_lock); 60364d77564SMark yao 60417a794d7SChris Zhong vop_cfg_done(vop); 60517a794d7SChris Zhong 60652ab7891SMark Yao /* 60752ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 60852ab7891SMark Yao */ 60952ab7891SMark Yao vop->is_enabled = true; 61052ab7891SMark Yao 6112048e328SMark Yao spin_lock(&vop->reg_lock); 6122048e328SMark Yao 6139a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6142048e328SMark Yao 6152048e328SMark Yao spin_unlock(&vop->reg_lock); 6162048e328SMark Yao 617b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6182048e328SMark Yao 61939a9ad8fSSean Paul return 0; 6202048e328SMark Yao 6212048e328SMark Yao err_disable_dclk: 6222048e328SMark Yao clk_disable(vop->dclk); 623e2810a71SHeiko Stuebner err_disable_core: 624e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 62539a9ad8fSSean Paul err_put_pm_runtime: 62639a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 62739a9ad8fSSean Paul return ret; 6282048e328SMark Yao } 6292048e328SMark Yao 630bed030a4SSean Paul static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 631bed030a4SSean Paul { 632bed030a4SSean Paul struct vop *vop = to_vop(crtc); 633bed030a4SSean Paul int i; 634bed030a4SSean Paul 635bed030a4SSean Paul spin_lock(&vop->reg_lock); 636bed030a4SSean Paul 637bed030a4SSean Paul for (i = 0; i < vop->data->win_size; i++) { 638bed030a4SSean Paul struct vop_win *vop_win = &vop->win[i]; 639bed030a4SSean Paul const struct vop_win_data *win = vop_win->data; 640bed030a4SSean Paul 641bed030a4SSean Paul VOP_WIN_SET(vop, win, enable, 642bed030a4SSean Paul enabled && (vop->win_enabled & BIT(i))); 643bed030a4SSean Paul } 644bed030a4SSean Paul vop_cfg_done(vop); 645bed030a4SSean Paul 646bed030a4SSean Paul spin_unlock(&vop->reg_lock); 647bed030a4SSean Paul } 648bed030a4SSean Paul 64964581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 65064581714SLaurent Pinchart struct drm_crtc_state *old_state) 6512048e328SMark Yao { 6522048e328SMark Yao struct vop *vop = to_vop(crtc); 6532048e328SMark Yao 654893b6cadSDaniel Vetter WARN_ON(vop->event); 655893b6cadSDaniel Vetter 656bed030a4SSean Paul if (crtc->state->self_refresh_active) 657bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, false); 658bed030a4SSean Paul 659e334d48bSzain wang mutex_lock(&vop->vop_lock); 6606c836d96SSean Paul 661b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 6622048e328SMark Yao 663bed030a4SSean Paul if (crtc->state->self_refresh_active) 664bed030a4SSean Paul goto out; 665bed030a4SSean Paul 6662048e328SMark Yao /* 6671067219bSMark Yao * Vop standby will take effect at end of current frame, 6681067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 6691067219bSMark Yao * 6701067219bSMark Yao * we must wait standby complete when we want to disable aclk, 6711067219bSMark Yao * if not, memory bus maybe dead. 6722048e328SMark Yao */ 6731067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 6741067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 6751067219bSMark Yao 6762048e328SMark Yao spin_lock(&vop->reg_lock); 6772048e328SMark Yao 6789a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6792048e328SMark Yao 6802048e328SMark Yao spin_unlock(&vop->reg_lock); 68152ab7891SMark Yao 6821067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 6832048e328SMark Yao 6841067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6851067219bSMark Yao 6861067219bSMark Yao vop->is_enabled = false; 6871067219bSMark Yao 6881067219bSMark Yao /* 6891067219bSMark Yao * vop standby complete, so iommu detach is safe. 6901067219bSMark Yao */ 6912048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6922048e328SMark Yao 6931067219bSMark Yao clk_disable(vop->dclk); 694e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 6955d82d1a7SMark Yao pm_runtime_put(vop->dev); 696bed030a4SSean Paul 697bed030a4SSean Paul out: 698e334d48bSzain wang mutex_unlock(&vop->vop_lock); 699893b6cadSDaniel Vetter 700893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 701893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 702893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 703893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 704893b6cadSDaniel Vetter 705893b6cadSDaniel Vetter crtc->state->event = NULL; 706893b6cadSDaniel Vetter } 7072048e328SMark Yao } 7082048e328SMark Yao 70963ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 7102048e328SMark Yao { 71163ebb9faSMark Yao drm_plane_cleanup(plane); 7122048e328SMark Yao } 7132048e328SMark Yao 71463ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 71563ebb9faSMark Yao struct drm_plane_state *state) 7162048e328SMark Yao { 71763ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 71892915da6SJohn Keeping struct drm_crtc_state *crtc_state; 71963ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 7202048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 7212048e328SMark Yao const struct vop_win_data *win = vop_win->data; 7222048e328SMark Yao int ret; 7234c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 7244c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7254c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 7264c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7272048e328SMark Yao 72863ebb9faSMark Yao if (!crtc || !fb) 729d47a7246STomasz Figa return 0; 73092915da6SJohn Keeping 73192915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 73292915da6SJohn Keeping if (WARN_ON(!crtc_state)) 73392915da6SJohn Keeping return -EINVAL; 73492915da6SJohn Keeping 73581af63a4SVille Syrjälä ret = drm_atomic_helper_check_plane_state(state, crtc_state, 736f9b96be0SVille Syrjälä min_scale, max_scale, 737f9b96be0SVille Syrjälä true, true); 7382048e328SMark Yao if (ret) 7392048e328SMark Yao return ret; 7402048e328SMark Yao 741f9b96be0SVille Syrjälä if (!state->visible) 742d47a7246STomasz Figa return 0; 7432048e328SMark Yao 744438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 745d47a7246STomasz Figa if (ret < 0) 746d47a7246STomasz Figa return ret; 74784c7f8caSMark Yao 74884c7f8caSMark Yao /* 74984c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 75084c7f8caSMark Yao * need align with 2 pixel. 75184c7f8caSMark Yao */ 752d8bd23d9SAyan Kumar Halder if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 753d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 75463ebb9faSMark Yao return -EINVAL; 755d415fb87SMark yao } 75663ebb9faSMark Yao 757677e8bbcSDaniele Castagna if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 758677e8bbcSDaniele Castagna DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 759677e8bbcSDaniele Castagna return -EINVAL; 760677e8bbcSDaniele Castagna } 761677e8bbcSDaniele Castagna 76263ebb9faSMark Yao return 0; 76384c7f8caSMark Yao } 76484c7f8caSMark Yao 76563ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 76663ebb9faSMark Yao struct drm_plane_state *old_state) 76763ebb9faSMark Yao { 76863ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 76963ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 7702048e328SMark Yao 77163ebb9faSMark Yao if (!old_state->crtc) 77263ebb9faSMark Yao return; 7732048e328SMark Yao 77463ebb9faSMark Yao spin_lock(&vop->reg_lock); 7752048e328SMark Yao 7762b60e11dSSean Paul vop_win_disable(vop, vop_win); 7772048e328SMark Yao 77863ebb9faSMark Yao spin_unlock(&vop->reg_lock); 77963ebb9faSMark Yao } 78063ebb9faSMark Yao 78163ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 78263ebb9faSMark Yao struct drm_plane_state *old_state) 78363ebb9faSMark Yao { 78463ebb9faSMark Yao struct drm_plane_state *state = plane->state; 78563ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 78663ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 78763ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 7881c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 78963ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 79063ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 79163ebb9faSMark Yao unsigned int actual_w, actual_h; 79263ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 79363ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 794ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 795ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 79663ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 79763ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 79863ebb9faSMark Yao unsigned long offset; 79963ebb9faSMark Yao dma_addr_t dma_addr; 80063ebb9faSMark Yao uint32_t val; 80163ebb9faSMark Yao bool rb_swap; 80258badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 803d47a7246STomasz Figa int format; 8041c21aa8fSDaniele Castagna int is_yuv = fb->format->is_yuv; 8051c21aa8fSDaniele Castagna int i; 80663ebb9faSMark Yao 80763ebb9faSMark Yao /* 80863ebb9faSMark Yao * can't update plane when vop is disabled. 80963ebb9faSMark Yao */ 8104f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 81163ebb9faSMark Yao return; 81263ebb9faSMark Yao 81363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 81463ebb9faSMark Yao return; 81563ebb9faSMark Yao 816d47a7246STomasz Figa if (!state->visible) { 81763ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 81863ebb9faSMark Yao return; 81963ebb9faSMark Yao } 82063ebb9faSMark Yao 821957428f9SDaniel Stone obj = fb->obj[0]; 82263ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 82363ebb9faSMark Yao 82463ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 82563ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 82663ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 82763ebb9faSMark Yao 82863ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 82963ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 83063ebb9faSMark Yao 83163ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 83263ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 83363ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 83463ebb9faSMark Yao 835353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 83663ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 837d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 838d47a7246STomasz Figa 839677e8bbcSDaniele Castagna /* 840677e8bbcSDaniele Castagna * For y-mirroring we need to move address 841677e8bbcSDaniele Castagna * to the beginning of the last line. 842677e8bbcSDaniele Castagna */ 843677e8bbcSDaniele Castagna if (state->rotation & DRM_MODE_REFLECT_Y) 844677e8bbcSDaniele Castagna dma_addr += (actual_h - 1) * fb->pitches[0]; 845677e8bbcSDaniele Castagna 846438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 84763ebb9faSMark Yao 84863ebb9faSMark Yao spin_lock(&vop->reg_lock); 84963ebb9faSMark Yao 850d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 851da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 852d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 8531c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 854677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, y_mir_en, 855677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 856677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, x_mir_en, 857677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 8581c21aa8fSDaniele Castagna 8591c21aa8fSDaniele Castagna if (is_yuv) { 860f3e9632cSMaxime Ripard int hsub = fb->format->hsub; 861f3e9632cSMaxime Ripard int vsub = fb->format->vsub; 862353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 86384c7f8caSMark Yao 864957428f9SDaniel Stone uv_obj = fb->obj[1]; 86584c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 86684c7f8caSMark Yao 86763ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 86863ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 86984c7f8caSMark Yao 87063ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 871da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 87263ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 8731c21aa8fSDaniele Castagna 8741c21aa8fSDaniele Castagna for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 8751c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 8761c21aa8fSDaniele Castagna win_yuv2yuv, 8771c21aa8fSDaniele Castagna y2r_coefficients[i], 8781c21aa8fSDaniele Castagna bt601_yuv2rgb[i]); 8791c21aa8fSDaniele Castagna } 88084c7f8caSMark Yao } 8814c156c21SMark Yao 8824c156c21SMark Yao if (win->phy->scl) 8834c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 88463ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 88545babef0SMaxime Ripard fb->format); 8864c156c21SMark Yao 88763ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 88863ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 88963ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 8904c156c21SMark Yao 891438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 89285a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 8932048e328SMark Yao 89458badaa7SKristian H. Kristensen /* 89558badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 89658badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 89758badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 89858badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 89958badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 90058badaa7SKristian H. Kristensen */ 90158badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 9022048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 9032048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 9042048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 9052048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 9062048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 9072048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 9082048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 9092048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 9102048e328SMark Yao } else { 9112048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 9122048e328SMark Yao } 9132048e328SMark Yao 9142048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 915bed030a4SSean Paul vop->win_enabled |= BIT(win_index); 9162048e328SMark Yao spin_unlock(&vop->reg_lock); 9172048e328SMark Yao } 9182048e328SMark Yao 91915609559SEnric Balletbo i Serra static int vop_plane_atomic_async_check(struct drm_plane *plane, 92015609559SEnric Balletbo i Serra struct drm_plane_state *state) 92115609559SEnric Balletbo i Serra { 92215609559SEnric Balletbo i Serra struct vop_win *vop_win = to_vop_win(plane); 92315609559SEnric Balletbo i Serra const struct vop_win_data *win = vop_win->data; 92415609559SEnric Balletbo i Serra int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 92515609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 92615609559SEnric Balletbo i Serra int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 92715609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 92815609559SEnric Balletbo i Serra struct drm_crtc_state *crtc_state; 92915609559SEnric Balletbo i Serra 93015609559SEnric Balletbo i Serra if (plane != state->crtc->cursor) 93115609559SEnric Balletbo i Serra return -EINVAL; 93215609559SEnric Balletbo i Serra 93315609559SEnric Balletbo i Serra if (!plane->state) 93415609559SEnric Balletbo i Serra return -EINVAL; 93515609559SEnric Balletbo i Serra 93615609559SEnric Balletbo i Serra if (!plane->state->fb) 93715609559SEnric Balletbo i Serra return -EINVAL; 93815609559SEnric Balletbo i Serra 93915609559SEnric Balletbo i Serra if (state->state) 94015609559SEnric Balletbo i Serra crtc_state = drm_atomic_get_existing_crtc_state(state->state, 94115609559SEnric Balletbo i Serra state->crtc); 94215609559SEnric Balletbo i Serra else /* Special case for asynchronous cursor updates. */ 94315609559SEnric Balletbo i Serra crtc_state = plane->crtc->state; 94415609559SEnric Balletbo i Serra 94515609559SEnric Balletbo i Serra return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 94615609559SEnric Balletbo i Serra min_scale, max_scale, 94715609559SEnric Balletbo i Serra true, true); 94815609559SEnric Balletbo i Serra } 94915609559SEnric Balletbo i Serra 95015609559SEnric Balletbo i Serra static void vop_plane_atomic_async_update(struct drm_plane *plane, 95115609559SEnric Balletbo i Serra struct drm_plane_state *new_state) 95215609559SEnric Balletbo i Serra { 95315609559SEnric Balletbo i Serra struct vop *vop = to_vop(plane->state->crtc); 954d985a353SHelen Koike struct drm_framebuffer *old_fb = plane->state->fb; 95515609559SEnric Balletbo i Serra 956d985a353SHelen Koike plane->state->crtc_x = new_state->crtc_x; 957d985a353SHelen Koike plane->state->crtc_y = new_state->crtc_y; 958d985a353SHelen Koike plane->state->crtc_h = new_state->crtc_h; 959d985a353SHelen Koike plane->state->crtc_w = new_state->crtc_w; 960d985a353SHelen Koike plane->state->src_x = new_state->src_x; 961d985a353SHelen Koike plane->state->src_y = new_state->src_y; 962d985a353SHelen Koike plane->state->src_h = new_state->src_h; 963d985a353SHelen Koike plane->state->src_w = new_state->src_w; 964d985a353SHelen Koike swap(plane->state->fb, new_state->fb); 96515609559SEnric Balletbo i Serra 96615609559SEnric Balletbo i Serra if (vop->is_enabled) { 96715609559SEnric Balletbo i Serra vop_plane_atomic_update(plane, plane->state); 96815609559SEnric Balletbo i Serra spin_lock(&vop->reg_lock); 96915609559SEnric Balletbo i Serra vop_cfg_done(vop); 97015609559SEnric Balletbo i Serra spin_unlock(&vop->reg_lock); 97115609559SEnric Balletbo i Serra 972d985a353SHelen Koike /* 973d985a353SHelen Koike * A scanout can still be occurring, so we can't drop the 974d985a353SHelen Koike * reference to the old framebuffer. To solve this we get a 975d985a353SHelen Koike * reference to old_fb and set a worker to release it later. 976d985a353SHelen Koike * FIXME: if we perform 500 async_update calls before the 977d985a353SHelen Koike * vblank, then we can have 500 different framebuffers waiting 978d985a353SHelen Koike * to be released. 979d985a353SHelen Koike */ 980d985a353SHelen Koike if (old_fb && plane->state->fb != old_fb) { 981d985a353SHelen Koike drm_framebuffer_get(old_fb); 982d985a353SHelen Koike WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 983d985a353SHelen Koike drm_flip_work_queue(&vop->fb_unref_work, old_fb); 984d985a353SHelen Koike set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 985d985a353SHelen Koike } 986d985a353SHelen Koike } 98715609559SEnric Balletbo i Serra } 98815609559SEnric Balletbo i Serra 98963ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 99063ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 99163ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 99263ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 99315609559SEnric Balletbo i Serra .atomic_async_check = vop_plane_atomic_async_check, 99415609559SEnric Balletbo i Serra .atomic_async_update = vop_plane_atomic_async_update, 99563d5e06aSHeiko Stuebner .prepare_fb = drm_gem_fb_prepare_fb, 99663ebb9faSMark Yao }; 99763ebb9faSMark Yao 9982048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 99963ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 100063ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 10012048e328SMark Yao .destroy = vop_plane_destroy, 1002d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 1003d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1004d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 10052048e328SMark Yao }; 10062048e328SMark Yao 10072048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 10082048e328SMark Yao { 10092048e328SMark Yao struct vop *vop = to_vop(crtc); 10102048e328SMark Yao unsigned long flags; 10112048e328SMark Yao 101263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10132048e328SMark Yao return -EPERM; 10142048e328SMark Yao 10152048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 10162048e328SMark Yao 1017fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1018dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 10192048e328SMark Yao 10202048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10212048e328SMark Yao 10222048e328SMark Yao return 0; 10232048e328SMark Yao } 10242048e328SMark Yao 10252048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 10262048e328SMark Yao { 10272048e328SMark Yao struct vop *vop = to_vop(crtc); 10282048e328SMark Yao unsigned long flags; 10292048e328SMark Yao 103063ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10312048e328SMark Yao return; 103231e980c5SMark Yao 10332048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1034dbb3d944SMark Yao 1035dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1036dbb3d944SMark Yao 10372048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10382048e328SMark Yao } 10392048e328SMark Yao 10402048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 10412048e328SMark Yao const struct drm_display_mode *mode, 10422048e328SMark Yao struct drm_display_mode *adjusted_mode) 10432048e328SMark Yao { 1044b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 1045b59b8de3SChris Zhong 1046b59b8de3SChris Zhong adjusted_mode->clock = 1047527e4ca3SDouglas Anderson DIV_ROUND_UP(clk_round_rate(vop->dclk, 1048527e4ca3SDouglas Anderson adjusted_mode->clock * 1000), 1000); 1049b59b8de3SChris Zhong 10502048e328SMark Yao return true; 10512048e328SMark Yao } 10522048e328SMark Yao 10530b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 10540b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 10552048e328SMark Yao { 10562048e328SMark Yao struct vop *vop = to_vop(crtc); 1057efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 10584e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 105963ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 10602048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 10612048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 10622048e328SMark Yao u16 htotal = adjusted_mode->htotal; 10632048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 10642048e328SMark Yao u16 hact_end = hact_st + hdisplay; 10652048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 10662048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 10672048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 10682048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 10692048e328SMark Yao u16 vact_end = vact_st + vdisplay; 10700a63bfd0SMark Yao uint32_t pin_pol, val; 1071a5c0fa44SUrja Rannikko int dither_bpc = s->output_bpc ? s->output_bpc : 10; 107239a9ad8fSSean Paul int ret; 10732048e328SMark Yao 1074bed030a4SSean Paul if (old_state && old_state->self_refresh_active) { 1075bed030a4SSean Paul drm_crtc_vblank_on(crtc); 1076bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, true); 1077bed030a4SSean Paul return; 1078bed030a4SSean Paul } 1079bed030a4SSean Paul 1080e334d48bSzain wang mutex_lock(&vop->vop_lock); 1081e334d48bSzain wang 1082893b6cadSDaniel Vetter WARN_ON(vop->event); 1083893b6cadSDaniel Vetter 10846c836d96SSean Paul ret = vop_enable(crtc, old_state); 108539a9ad8fSSean Paul if (ret) { 1086e334d48bSzain wang mutex_unlock(&vop->vop_lock); 108739a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 108839a9ad8fSSean Paul return; 108939a9ad8fSSean Paul } 109039a9ad8fSSean Paul 10911a0f7ed3SChris Zhong pin_pol = BIT(DCLK_INVERT); 1092d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1093d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 1094d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1095d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 10969a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 1097cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 10980a63bfd0SMark Yao 10994e257d9eSMark Yao switch (s->output_type) { 11004e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 11019a61c54bSMark yao VOP_REG_SET(vop, output, rgb_en, 1); 11029a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 11034e257d9eSMark Yao break; 11044e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 11059a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 11069a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 11074e257d9eSMark Yao break; 11084e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 11099a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 11109a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 11114e257d9eSMark Yao break; 11124e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 11139a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 11149a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 1115cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 1116cf6d100dSHeiko Stuebner !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 11174e257d9eSMark Yao break; 11181a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 11191a0f7ed3SChris Zhong pin_pol &= ~BIT(DCLK_INVERT); 11209a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 11219a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 11221a0f7ed3SChris Zhong break; 11234e257d9eSMark Yao default: 1124ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1125ee4d7899SSean Paul s->output_type); 11264e257d9eSMark Yao } 1127efd11cc8SMark yao 1128efd11cc8SMark yao /* 1129efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 1130efd11cc8SMark yao */ 1131efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1132efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1133efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 11346bda8112SMark Yao 1135a5c0fa44SUrja Rannikko if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 11366bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 11376bda8112SMark Yao else 11386bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 11396bda8112SMark Yao 1140a5c0fa44SUrja Rannikko if (dither_bpc == 6) { 1141a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1142a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1143a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 1); 1144a5c0fa44SUrja Rannikko } else { 1145a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 0); 1146a5c0fa44SUrja Rannikko } 1147a5c0fa44SUrja Rannikko 11489a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 11492048e328SMark Yao 11509a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 11512048e328SMark Yao val = hact_st << 16; 11522048e328SMark Yao val |= hact_end; 11539a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 11549a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 11552048e328SMark Yao 11569a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 11572048e328SMark Yao val = vact_st << 16; 11582048e328SMark Yao val |= vact_end; 11599a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 11609a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 11612048e328SMark Yao 11629a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1163459b086dSJeffy Chen 11642048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1165ce3887edSMark Yao 11669a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 1167e334d48bSzain wang mutex_unlock(&vop->vop_lock); 11682048e328SMark Yao } 11692048e328SMark Yao 11707caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 11717caecdbeSTomasz Figa { 11727caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 11737caecdbeSTomasz Figa } 11747caecdbeSTomasz Figa 11757caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 11767caecdbeSTomasz Figa { 11777caecdbeSTomasz Figa bool pending; 11787caecdbeSTomasz Figa int ret; 11797caecdbeSTomasz Figa 11807caecdbeSTomasz Figa /* 11817caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 11827caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 11837caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 11847caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 11857caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 11867caecdbeSTomasz Figa * shouldn't exceed microseconds range. 11877caecdbeSTomasz Figa */ 11887caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 11897caecdbeSTomasz Figa !pending, 0, 10 * 1000); 11907caecdbeSTomasz Figa if (ret) 11917caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 11927caecdbeSTomasz Figa 11937caecdbeSTomasz Figa synchronize_irq(vop->irq); 11947caecdbeSTomasz Figa } 11957caecdbeSTomasz Figa 119663ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 119763ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 119863ebb9faSMark Yao { 119947a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1200e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 120163ebb9faSMark Yao struct vop *vop = to_vop(crtc); 120247a7eb45STomasz Figa struct drm_plane *plane; 120347a7eb45STomasz Figa int i; 120463ebb9faSMark Yao 120563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 120663ebb9faSMark Yao return; 120763ebb9faSMark Yao 120863ebb9faSMark Yao spin_lock(&vop->reg_lock); 120963ebb9faSMark Yao 121063ebb9faSMark Yao vop_cfg_done(vop); 121163ebb9faSMark Yao 121263ebb9faSMark Yao spin_unlock(&vop->reg_lock); 12137caecdbeSTomasz Figa 12147caecdbeSTomasz Figa /* 12157caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 12167caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 12177caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 12187caecdbeSTomasz Figa */ 12197caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 122047a7eb45STomasz Figa 122141ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 122241ee4367STomasz Figa if (crtc->state->event) { 122341ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 122441ee4367STomasz Figa WARN_ON(vop->event); 122541ee4367STomasz Figa 122641ee4367STomasz Figa vop->event = crtc->state->event; 122741ee4367STomasz Figa crtc->state->event = NULL; 122841ee4367STomasz Figa } 122941ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 123041ee4367STomasz Figa 1231e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1232e741f2b1SMaarten Lankhorst new_plane_state, i) { 123347a7eb45STomasz Figa if (!old_plane_state->fb) 123447a7eb45STomasz Figa continue; 123547a7eb45STomasz Figa 1236e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 123747a7eb45STomasz Figa continue; 123847a7eb45STomasz Figa 1239adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 12402d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 124147a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 124247a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 124347a7eb45STomasz Figa } 124463ebb9faSMark Yao } 124563ebb9faSMark Yao 12462048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 12472048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 124863ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 12490b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 125064581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 12512048e328SMark Yao }; 12522048e328SMark Yao 12532048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 12542048e328SMark Yao { 12552048e328SMark Yao drm_crtc_cleanup(crtc); 12562048e328SMark Yao } 12572048e328SMark Yao 12584e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 12594e257d9eSMark Yao { 12604e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 12614e257d9eSMark Yao 12624e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 12634e257d9eSMark Yao if (!rockchip_state) 12644e257d9eSMark Yao return NULL; 12654e257d9eSMark Yao 12664e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 12674e257d9eSMark Yao return &rockchip_state->base; 12684e257d9eSMark Yao } 12694e257d9eSMark Yao 12704e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 12714e257d9eSMark Yao struct drm_crtc_state *state) 12724e257d9eSMark Yao { 12734e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 12744e257d9eSMark Yao 1275ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 12764e257d9eSMark Yao kfree(s); 12774e257d9eSMark Yao } 12784e257d9eSMark Yao 127901e2eaf4SMaarten Lankhorst static void vop_crtc_reset(struct drm_crtc *crtc) 128001e2eaf4SMaarten Lankhorst { 128101e2eaf4SMaarten Lankhorst struct rockchip_crtc_state *crtc_state = 128201e2eaf4SMaarten Lankhorst kzalloc(sizeof(*crtc_state), GFP_KERNEL); 128301e2eaf4SMaarten Lankhorst 128401e2eaf4SMaarten Lankhorst if (crtc->state) 128501e2eaf4SMaarten Lankhorst vop_crtc_destroy_state(crtc, crtc->state); 128601e2eaf4SMaarten Lankhorst 128701e2eaf4SMaarten Lankhorst __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 128801e2eaf4SMaarten Lankhorst } 128901e2eaf4SMaarten Lankhorst 12906cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 12913190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 12923190e58dSTomeu Vizoso { 12933190e58dSTomeu Vizoso struct drm_connector *connector; 12942cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 12953190e58dSTomeu Vizoso 12962cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 12972cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 12983190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 12992cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 13003190e58dSTomeu Vizoso return connector; 13013190e58dSTomeu Vizoso } 13022cbeb64fSGustavo Padovan } 13032cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 13043190e58dSTomeu Vizoso 13053190e58dSTomeu Vizoso return NULL; 13063190e58dSTomeu Vizoso } 13073190e58dSTomeu Vizoso 13083190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1309c0811a7dSMahesh Kumar const char *source_name) 13103190e58dSTomeu Vizoso { 13113190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 13123190e58dSTomeu Vizoso struct drm_connector *connector; 13133190e58dSTomeu Vizoso int ret; 13143190e58dSTomeu Vizoso 13153190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 13163190e58dSTomeu Vizoso if (!connector) 13173190e58dSTomeu Vizoso return -EINVAL; 13183190e58dSTomeu Vizoso 13193190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 13203190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 13213190e58dSTomeu Vizoso else if (!source_name) 13223190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 13233190e58dSTomeu Vizoso else 13243190e58dSTomeu Vizoso ret = -EINVAL; 13253190e58dSTomeu Vizoso 13263190e58dSTomeu Vizoso return ret; 13273190e58dSTomeu Vizoso } 1328b8d913c0SMahesh Kumar 1329b8d913c0SMahesh Kumar static int 1330b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1331b8d913c0SMahesh Kumar size_t *values_cnt) 1332b8d913c0SMahesh Kumar { 1333b8d913c0SMahesh Kumar if (source_name && strcmp(source_name, "auto") != 0) 1334b8d913c0SMahesh Kumar return -EINVAL; 1335b8d913c0SMahesh Kumar 1336b8d913c0SMahesh Kumar *values_cnt = 3; 1337b8d913c0SMahesh Kumar return 0; 1338b8d913c0SMahesh Kumar } 1339b8d913c0SMahesh Kumar 13406cca3869SSean Paul #else 13416cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1342c0811a7dSMahesh Kumar const char *source_name) 13436cca3869SSean Paul { 13446cca3869SSean Paul return -ENODEV; 13456cca3869SSean Paul } 1346b8d913c0SMahesh Kumar 1347b8d913c0SMahesh Kumar static int 1348b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1349b8d913c0SMahesh Kumar size_t *values_cnt) 1350b8d913c0SMahesh Kumar { 1351b8d913c0SMahesh Kumar return -ENODEV; 1352b8d913c0SMahesh Kumar } 13536cca3869SSean Paul #endif 13543190e58dSTomeu Vizoso 13552048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 135663ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 135763ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 13582048e328SMark Yao .destroy = vop_crtc_destroy, 1359dc0b408fSJohn Keeping .reset = vop_crtc_reset, 13604e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 13614e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1362c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1363c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 13643190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 1365b8d913c0SMahesh Kumar .verify_crc_source = vop_crtc_verify_crc_source, 13662048e328SMark Yao }; 13672048e328SMark Yao 136847a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 136947a7eb45STomasz Figa { 137047a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 137147a7eb45STomasz Figa struct drm_framebuffer *fb = val; 137247a7eb45STomasz Figa 137347a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1374adedbf03SCihangir Akturk drm_framebuffer_put(fb); 137547a7eb45STomasz Figa } 137647a7eb45STomasz Figa 137763ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 13782048e328SMark Yao { 137963ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 138063ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 13812048e328SMark Yao 13821c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1383893b6cadSDaniel Vetter if (vop->event) { 138463ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 13855b680403SSean Paul drm_crtc_vblank_put(crtc); 1386646ec687STomasz Figa vop->event = NULL; 13875b680403SSean Paul } 13881c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1389893b6cadSDaniel Vetter 139047a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 139147a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 13922048e328SMark Yao } 13932048e328SMark Yao 13942048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 13952048e328SMark Yao { 13962048e328SMark Yao struct vop *vop = data; 1397b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1398dbb3d944SMark Yao uint32_t active_irqs; 13991067219bSMark Yao int ret = IRQ_NONE; 14002048e328SMark Yao 14012048e328SMark Yao /* 14026456314fSSandy Huang * The irq is shared with the iommu. If the runtime-pm state of the 14036456314fSSandy Huang * vop-device is disabled the irq has to be targeted at the iommu. 14046456314fSSandy Huang */ 14056456314fSSandy Huang if (!pm_runtime_get_if_in_use(vop->dev)) 14066456314fSSandy Huang return IRQ_NONE; 14076456314fSSandy Huang 14086456314fSSandy Huang if (vop_core_clks_enable(vop)) { 14096456314fSSandy Huang DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 14106456314fSSandy Huang goto out; 14116456314fSSandy Huang } 14126456314fSSandy Huang 14136456314fSSandy Huang /* 1414dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 14152048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 14162048e328SMark Yao */ 14171c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1418dbb3d944SMark Yao 1419dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 14202048e328SMark Yao /* Clear all active interrupt sources */ 14212048e328SMark Yao if (active_irqs) 1422dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1423dbb3d944SMark Yao 14241c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 14252048e328SMark Yao 14262048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 14272048e328SMark Yao if (!active_irqs) 14286456314fSSandy Huang goto out_disable; 14292048e328SMark Yao 14301067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 14311067219bSMark Yao complete(&vop->dsp_hold_completion); 14321067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 14331067219bSMark Yao ret = IRQ_HANDLED; 14342048e328SMark Yao } 14352048e328SMark Yao 143669c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 143769c34e41SYakir Yang complete(&vop->line_flag_completion); 143869c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 143969c34e41SYakir Yang ret = IRQ_HANDLED; 144069c34e41SYakir Yang } 144169c34e41SYakir Yang 14421067219bSMark Yao if (active_irqs & FS_INTR) { 1443b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 144463ebb9faSMark Yao vop_handle_vblank(vop); 14451067219bSMark Yao active_irqs &= ~FS_INTR; 144663ebb9faSMark Yao ret = IRQ_HANDLED; 14471067219bSMark Yao } 14482048e328SMark Yao 14491067219bSMark Yao /* Unhandled irqs are spurious. */ 14501067219bSMark Yao if (active_irqs) 1451ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1452ee4d7899SSean Paul active_irqs); 14531067219bSMark Yao 14546456314fSSandy Huang out_disable: 14556456314fSSandy Huang vop_core_clks_disable(vop); 14566456314fSSandy Huang out: 14576456314fSSandy Huang pm_runtime_put(vop->dev); 14581067219bSMark Yao return ret; 14592048e328SMark Yao } 14602048e328SMark Yao 1461677e8bbcSDaniele Castagna static void vop_plane_add_properties(struct drm_plane *plane, 1462677e8bbcSDaniele Castagna const struct vop_win_data *win_data) 1463677e8bbcSDaniele Castagna { 1464677e8bbcSDaniele Castagna unsigned int flags = 0; 1465677e8bbcSDaniele Castagna 1466677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1467677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1468677e8bbcSDaniele Castagna if (flags) 1469677e8bbcSDaniele Castagna drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1470677e8bbcSDaniele Castagna DRM_MODE_ROTATE_0 | flags); 1471677e8bbcSDaniele Castagna } 1472677e8bbcSDaniele Castagna 14732048e328SMark Yao static int vop_create_crtc(struct vop *vop) 14742048e328SMark Yao { 14752048e328SMark Yao const struct vop_data *vop_data = vop->data; 14762048e328SMark Yao struct device *dev = vop->dev; 14772048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1478328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 14792048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 14802048e328SMark Yao struct device_node *port; 14812048e328SMark Yao int ret; 14822048e328SMark Yao int i; 14832048e328SMark Yao 14842048e328SMark Yao /* 14852048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 14862048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 14872048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 14882048e328SMark Yao */ 14892048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14902048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14912048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 14922048e328SMark Yao 14932048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 14942048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 14952048e328SMark Yao continue; 14962048e328SMark Yao 14972048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 14982048e328SMark Yao 0, &vop_plane_funcs, 14992048e328SMark Yao win_data->phy->data_formats, 15002048e328SMark Yao win_data->phy->nformats, 1501e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 15022048e328SMark Yao if (ret) { 1503ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1504ee4d7899SSean Paul ret); 15052048e328SMark Yao goto err_cleanup_planes; 15062048e328SMark Yao } 15072048e328SMark Yao 15082048e328SMark Yao plane = &vop_win->base; 150963ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 1510677e8bbcSDaniele Castagna vop_plane_add_properties(plane, win_data); 15112048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 15122048e328SMark Yao primary = plane; 15132048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 15142048e328SMark Yao cursor = plane; 15152048e328SMark Yao } 15162048e328SMark Yao 15172048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1518f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 15192048e328SMark Yao if (ret) 1520328b51c0SDouglas Anderson goto err_cleanup_planes; 15212048e328SMark Yao 15222048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 15232048e328SMark Yao 15242048e328SMark Yao /* 15252048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 15262048e328SMark Yao * to the newly created crtc. 15272048e328SMark Yao */ 15282048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 15292048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 15302048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 1531a3e77e16SVille Syrjälä unsigned long possible_crtcs = drm_crtc_mask(crtc); 15322048e328SMark Yao 15332048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 15342048e328SMark Yao continue; 15352048e328SMark Yao 15362048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 15372048e328SMark Yao possible_crtcs, 15382048e328SMark Yao &vop_plane_funcs, 15392048e328SMark Yao win_data->phy->data_formats, 15402048e328SMark Yao win_data->phy->nformats, 1541e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 15422048e328SMark Yao if (ret) { 1543ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1544ee4d7899SSean Paul ret); 15452048e328SMark Yao goto err_cleanup_crtc; 15462048e328SMark Yao } 154763ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1548677e8bbcSDaniele Castagna vop_plane_add_properties(&vop_win->base, win_data); 15492048e328SMark Yao } 15502048e328SMark Yao 15512048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 15522048e328SMark Yao if (!port) { 15534bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 15544bf99144SRob Herring dev->of_node); 1555328b51c0SDouglas Anderson ret = -ENOENT; 15562048e328SMark Yao goto err_cleanup_crtc; 15572048e328SMark Yao } 15582048e328SMark Yao 155947a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 156047a7eb45STomasz Figa vop_fb_unref_worker); 156147a7eb45STomasz Figa 15621067219bSMark Yao init_completion(&vop->dsp_hold_completion); 156369c34e41SYakir Yang init_completion(&vop->line_flag_completion); 15642048e328SMark Yao crtc->port = port; 15652048e328SMark Yao 15666c836d96SSean Paul ret = drm_self_refresh_helper_init(crtc, 15676c836d96SSean Paul VOP_SELF_REFRESH_ENTRY_DELAY_MS); 15686c836d96SSean Paul if (ret) 15696c836d96SSean Paul DRM_DEV_DEBUG_KMS(vop->dev, 15706c836d96SSean Paul "Failed to init %s with SR helpers %d, ignoring\n", 15716c836d96SSean Paul crtc->name, ret); 15726c836d96SSean Paul 15732048e328SMark Yao return 0; 15742048e328SMark Yao 15752048e328SMark Yao err_cleanup_crtc: 15762048e328SMark Yao drm_crtc_cleanup(crtc); 15772048e328SMark Yao err_cleanup_planes: 1578328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1579328b51c0SDouglas Anderson head) 15802048e328SMark Yao drm_plane_cleanup(plane); 15812048e328SMark Yao return ret; 15822048e328SMark Yao } 15832048e328SMark Yao 15842048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 15852048e328SMark Yao { 15862048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1587328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1588328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 15892048e328SMark Yao 15906c836d96SSean Paul drm_self_refresh_helper_cleanup(crtc); 15916c836d96SSean Paul 15922048e328SMark Yao of_node_put(crtc->port); 1593328b51c0SDouglas Anderson 1594328b51c0SDouglas Anderson /* 1595328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1596328b51c0SDouglas Anderson * 1597328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1598328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1599328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1600328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1601328b51c0SDouglas Anderson */ 1602328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1603328b51c0SDouglas Anderson head) 1604328b51c0SDouglas Anderson vop_plane_destroy(plane); 1605328b51c0SDouglas Anderson 1606328b51c0SDouglas Anderson /* 1607328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1608328b51c0SDouglas Anderson * references the CRTC. 1609328b51c0SDouglas Anderson */ 16102048e328SMark Yao drm_crtc_cleanup(crtc); 161147a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 16122048e328SMark Yao } 16132048e328SMark Yao 16142048e328SMark Yao static int vop_initial(struct vop *vop) 16152048e328SMark Yao { 16162048e328SMark Yao struct reset_control *ahb_rst; 16172048e328SMark Yao int i, ret; 16182048e328SMark Yao 16192048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 16202048e328SMark Yao if (IS_ERR(vop->hclk)) { 1621d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 16222048e328SMark Yao return PTR_ERR(vop->hclk); 16232048e328SMark Yao } 16242048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 16252048e328SMark Yao if (IS_ERR(vop->aclk)) { 1626d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 16272048e328SMark Yao return PTR_ERR(vop->aclk); 16282048e328SMark Yao } 16292048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 16302048e328SMark Yao if (IS_ERR(vop->dclk)) { 1631d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 16322048e328SMark Yao return PTR_ERR(vop->dclk); 16332048e328SMark Yao } 16342048e328SMark Yao 16355e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 16365e570373SJeffy Chen if (ret < 0) { 1637d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 16385e570373SJeffy Chen return ret; 16395e570373SJeffy Chen } 16405e570373SJeffy Chen 16412048e328SMark Yao ret = clk_prepare(vop->dclk); 16422048e328SMark Yao if (ret < 0) { 1643d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 16445e570373SJeffy Chen goto err_put_pm_runtime; 16452048e328SMark Yao } 16462048e328SMark Yao 1647d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1648d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 16492048e328SMark Yao if (ret < 0) { 1650d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 16512048e328SMark Yao goto err_unprepare_dclk; 16522048e328SMark Yao } 16532048e328SMark Yao 1654d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 16552048e328SMark Yao if (ret < 0) { 1656d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1657d7b53fd9SSjoerd Simons goto err_disable_hclk; 16582048e328SMark Yao } 1659d7b53fd9SSjoerd Simons 16602048e328SMark Yao /* 16612048e328SMark Yao * do hclk_reset, reset all vop registers. 16622048e328SMark Yao */ 16632048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 16642048e328SMark Yao if (IS_ERR(ahb_rst)) { 1665d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 16662048e328SMark Yao ret = PTR_ERR(ahb_rst); 1667d7b53fd9SSjoerd Simons goto err_disable_aclk; 16682048e328SMark Yao } 16692048e328SMark Yao reset_control_assert(ahb_rst); 16702048e328SMark Yao usleep_range(10, 20); 16712048e328SMark Yao reset_control_deassert(ahb_rst); 16722048e328SMark Yao 16735f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 16745f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 16755f9e93feSMarc Zyngier 167676f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 167776f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 16782048e328SMark Yao 16799a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 16809a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 16812048e328SMark Yao 16822b60e11dSSean Paul for (i = 0; i < vop->data->win_size; i++) { 16832b60e11dSSean Paul struct vop_win *vop_win = &vop->win[i]; 16842b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 16859dd2aca4SMark yao int channel = i * 2 + 1; 16862048e328SMark Yao 16879dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 16882b60e11dSSean Paul vop_win_disable(vop, vop_win); 168960b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 16902048e328SMark Yao } 16912048e328SMark Yao 16922048e328SMark Yao vop_cfg_done(vop); 16932048e328SMark Yao 16942048e328SMark Yao /* 16952048e328SMark Yao * do dclk_reset, let all config take affect. 16962048e328SMark Yao */ 16972048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 16982048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1699d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 17002048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1701d7b53fd9SSjoerd Simons goto err_disable_aclk; 17022048e328SMark Yao } 17032048e328SMark Yao reset_control_assert(vop->dclk_rst); 17042048e328SMark Yao usleep_range(10, 20); 17052048e328SMark Yao reset_control_deassert(vop->dclk_rst); 17062048e328SMark Yao 17072048e328SMark Yao clk_disable(vop->hclk); 1708d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 17092048e328SMark Yao 171031e980c5SMark Yao vop->is_enabled = false; 17112048e328SMark Yao 17125e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 17135e570373SJeffy Chen 17142048e328SMark Yao return 0; 17152048e328SMark Yao 1716d7b53fd9SSjoerd Simons err_disable_aclk: 1717d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 17182048e328SMark Yao err_disable_hclk: 1719d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 17202048e328SMark Yao err_unprepare_dclk: 17212048e328SMark Yao clk_unprepare(vop->dclk); 17225e570373SJeffy Chen err_put_pm_runtime: 17235e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 17242048e328SMark Yao return ret; 17252048e328SMark Yao } 17262048e328SMark Yao 17272048e328SMark Yao /* 17282048e328SMark Yao * Initialize the vop->win array elements. 17292048e328SMark Yao */ 17302048e328SMark Yao static void vop_win_init(struct vop *vop) 17312048e328SMark Yao { 17322048e328SMark Yao const struct vop_data *vop_data = vop->data; 17332048e328SMark Yao unsigned int i; 17342048e328SMark Yao 17352048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 17362048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 17372048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 17382048e328SMark Yao 17392048e328SMark Yao vop_win->data = win_data; 17402048e328SMark Yao vop_win->vop = vop; 1741ce6912b4SHeiko Stuebner 1742ce6912b4SHeiko Stuebner if (vop_data->win_yuv2yuv) 17431c21aa8fSDaniele Castagna vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 17442048e328SMark Yao } 17452048e328SMark Yao } 17462048e328SMark Yao 174769c34e41SYakir Yang /** 1748459b086dSJeffy Chen * rockchip_drm_wait_vact_end 174969c34e41SYakir Yang * @crtc: CRTC to enable line flag 175069c34e41SYakir Yang * @mstimeout: millisecond for timeout 175169c34e41SYakir Yang * 1752459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 175369c34e41SYakir Yang * 175469c34e41SYakir Yang * Returns: 175569c34e41SYakir Yang * Zero on success, negative errno on failure. 175669c34e41SYakir Yang */ 1757459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 175869c34e41SYakir Yang { 175969c34e41SYakir Yang struct vop *vop = to_vop(crtc); 176069c34e41SYakir Yang unsigned long jiffies_left; 1761e334d48bSzain wang int ret = 0; 176269c34e41SYakir Yang 176369c34e41SYakir Yang if (!crtc || !vop->is_enabled) 176469c34e41SYakir Yang return -ENODEV; 176569c34e41SYakir Yang 1766e334d48bSzain wang mutex_lock(&vop->vop_lock); 1767e334d48bSzain wang if (mstimeout <= 0) { 1768e334d48bSzain wang ret = -EINVAL; 1769e334d48bSzain wang goto out; 1770e334d48bSzain wang } 177169c34e41SYakir Yang 1772e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 1773e334d48bSzain wang ret = -EBUSY; 1774e334d48bSzain wang goto out; 1775e334d48bSzain wang } 177669c34e41SYakir Yang 177769c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1778459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 177969c34e41SYakir Yang 178069c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 178169c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 178269c34e41SYakir Yang vop_line_flag_irq_disable(vop); 178369c34e41SYakir Yang 178469c34e41SYakir Yang if (jiffies_left == 0) { 1785d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1786e334d48bSzain wang ret = -ETIMEDOUT; 1787e334d48bSzain wang goto out; 178869c34e41SYakir Yang } 178969c34e41SYakir Yang 1790e334d48bSzain wang out: 1791e334d48bSzain wang mutex_unlock(&vop->vop_lock); 1792e334d48bSzain wang return ret; 179369c34e41SYakir Yang } 1794459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 179569c34e41SYakir Yang 17962048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 17972048e328SMark Yao { 17982048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 17992048e328SMark Yao const struct vop_data *vop_data; 18002048e328SMark Yao struct drm_device *drm_dev = data; 18012048e328SMark Yao struct vop *vop; 18022048e328SMark Yao struct resource *res; 18033ea68922SHeiko Stuebner int ret, irq; 18042048e328SMark Yao 1805a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 18062048e328SMark Yao if (!vop_data) 18072048e328SMark Yao return -ENODEV; 18082048e328SMark Yao 18092048e328SMark Yao /* Allocate vop struct and its vop_win array */ 181029adeb4fSGustavo A. R. Silva vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 181129adeb4fSGustavo A. R. Silva GFP_KERNEL); 18122048e328SMark Yao if (!vop) 18132048e328SMark Yao return -ENOMEM; 18142048e328SMark Yao 18152048e328SMark Yao vop->dev = dev; 18162048e328SMark Yao vop->data = vop_data; 18172048e328SMark Yao vop->drm_dev = drm_dev; 18182048e328SMark Yao dev_set_drvdata(dev, vop); 18192048e328SMark Yao 18202048e328SMark Yao vop_win_init(vop); 18212048e328SMark Yao 18222048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 18232048e328SMark Yao vop->len = resource_size(res); 18242048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 18252048e328SMark Yao if (IS_ERR(vop->regs)) 18262048e328SMark Yao return PTR_ERR(vop->regs); 18272048e328SMark Yao 18282048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 18292048e328SMark Yao if (!vop->regsbak) 18302048e328SMark Yao return -ENOMEM; 18312048e328SMark Yao 18323ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 18333ea68922SHeiko Stuebner if (irq < 0) { 1834d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 18353ea68922SHeiko Stuebner return irq; 18362048e328SMark Yao } 18373ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 18382048e328SMark Yao 18392048e328SMark Yao spin_lock_init(&vop->reg_lock); 18402048e328SMark Yao spin_lock_init(&vop->irq_lock); 1841e334d48bSzain wang mutex_init(&vop->vop_lock); 18422048e328SMark Yao 18432048e328SMark Yao ret = vop_create_crtc(vop); 18442048e328SMark Yao if (ret) 18455f9e93feSMarc Zyngier return ret; 18462048e328SMark Yao 18472048e328SMark Yao pm_runtime_enable(&pdev->dev); 18485182c1a5SYakir Yang 18495e570373SJeffy Chen ret = vop_initial(vop); 18505e570373SJeffy Chen if (ret < 0) { 1851d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 1852d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 18535e570373SJeffy Chen goto err_disable_pm_runtime; 18545e570373SJeffy Chen } 18555e570373SJeffy Chen 18565f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 18575f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 18585f9e93feSMarc Zyngier if (ret) 18595f9e93feSMarc Zyngier goto err_disable_pm_runtime; 18605f9e93feSMarc Zyngier 18611f0f0151SSandy Huang if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 18621f0f0151SSandy Huang vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 18631f0f0151SSandy Huang if (IS_ERR(vop->rgb)) { 18641f0f0151SSandy Huang ret = PTR_ERR(vop->rgb); 18651f0f0151SSandy Huang goto err_disable_pm_runtime; 18661f0f0151SSandy Huang } 18671f0f0151SSandy Huang } 18681f0f0151SSandy Huang 18692048e328SMark Yao return 0; 18708c763c9bSSean Paul 18715e570373SJeffy Chen err_disable_pm_runtime: 18725e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 18735e570373SJeffy Chen vop_destroy_crtc(vop); 18748c763c9bSSean Paul return ret; 18752048e328SMark Yao } 18762048e328SMark Yao 18772048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 18782048e328SMark Yao { 18792048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 18802048e328SMark Yao 18811f0f0151SSandy Huang if (vop->rgb) 18821f0f0151SSandy Huang rockchip_rgb_fini(vop->rgb); 18831f0f0151SSandy Huang 18842048e328SMark Yao pm_runtime_disable(dev); 18852048e328SMark Yao vop_destroy_crtc(vop); 1886ec6e7767SJeffy Chen 1887ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 1888ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 1889ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 18902048e328SMark Yao } 18912048e328SMark Yao 1892a67719d1SMark Yao const struct component_ops vop_component_ops = { 18932048e328SMark Yao .bind = vop_bind, 18942048e328SMark Yao .unbind = vop_unbind, 18952048e328SMark Yao }; 189654255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1897