12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 172048e328SMark Yao #include <drm/drm_crtc.h> 182048e328SMark Yao #include <drm/drm_crtc_helper.h> 192048e328SMark Yao #include <drm/drm_plane_helper.h> 202048e328SMark Yao 212048e328SMark Yao #include <linux/kernel.h> 2200fe6148SPaul Gortmaker #include <linux/module.h> 232048e328SMark Yao #include <linux/platform_device.h> 242048e328SMark Yao #include <linux/clk.h> 252048e328SMark Yao #include <linux/of.h> 262048e328SMark Yao #include <linux/of_device.h> 272048e328SMark Yao #include <linux/pm_runtime.h> 282048e328SMark Yao #include <linux/component.h> 292048e328SMark Yao 302048e328SMark Yao #include <linux/reset.h> 312048e328SMark Yao #include <linux/delay.h> 322048e328SMark Yao 332048e328SMark Yao #include "rockchip_drm_drv.h" 342048e328SMark Yao #include "rockchip_drm_gem.h" 352048e328SMark Yao #include "rockchip_drm_fb.h" 362048e328SMark Yao #include "rockchip_drm_vop.h" 372048e328SMark Yao 382048e328SMark Yao #define VOP_REG(off, _mask, s) \ 392048e328SMark Yao {.offset = off, \ 402048e328SMark Yao .mask = _mask, \ 412048e328SMark Yao .shift = s,} 422048e328SMark Yao 432048e328SMark Yao #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 442048e328SMark Yao vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 452048e328SMark Yao #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 462048e328SMark Yao vop_mask_write(x, off, (mask) << shift, (v) << shift) 472048e328SMark Yao 482048e328SMark Yao #define REG_SET(x, base, reg, v, mode) \ 492048e328SMark Yao __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 502048e328SMark Yao 512048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 522048e328SMark Yao REG_SET(x, win->base, win->phy->name, v, RELAXED) 534c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 544c156c21SMark Yao REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 552048e328SMark Yao #define VOP_CTRL_SET(x, name, v) \ 562048e328SMark Yao REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 572048e328SMark Yao 582048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 592048e328SMark Yao vop_read_reg(x, win->base, &win->phy->name) 602048e328SMark Yao 612048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 622048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 632048e328SMark Yao 642048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 652048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 662048e328SMark Yao 672048e328SMark Yao struct vop_win_state { 682048e328SMark Yao struct list_head head; 692048e328SMark Yao struct drm_framebuffer *fb; 702048e328SMark Yao dma_addr_t yrgb_mst; 712048e328SMark Yao struct drm_pending_vblank_event *event; 722048e328SMark Yao }; 732048e328SMark Yao 742048e328SMark Yao struct vop_win { 752048e328SMark Yao struct drm_plane base; 762048e328SMark Yao const struct vop_win_data *data; 772048e328SMark Yao struct vop *vop; 782048e328SMark Yao 792048e328SMark Yao struct list_head pending; 802048e328SMark Yao struct vop_win_state *active; 812048e328SMark Yao }; 822048e328SMark Yao 832048e328SMark Yao struct vop { 842048e328SMark Yao struct drm_crtc crtc; 852048e328SMark Yao struct device *dev; 862048e328SMark Yao struct drm_device *drm_dev; 8731e980c5SMark Yao bool is_enabled; 882048e328SMark Yao 892048e328SMark Yao int connector_type; 902048e328SMark Yao int connector_out_mode; 912048e328SMark Yao 922048e328SMark Yao /* mutex vsync_ work */ 932048e328SMark Yao struct mutex vsync_mutex; 942048e328SMark Yao bool vsync_work_pending; 951067219bSMark Yao struct completion dsp_hold_completion; 962048e328SMark Yao 972048e328SMark Yao const struct vop_data *data; 982048e328SMark Yao 992048e328SMark Yao uint32_t *regsbak; 1002048e328SMark Yao void __iomem *regs; 1012048e328SMark Yao 1022048e328SMark Yao /* physical map length of vop register */ 1032048e328SMark Yao uint32_t len; 1042048e328SMark Yao 1052048e328SMark Yao /* one time only one process allowed to config the register */ 1062048e328SMark Yao spinlock_t reg_lock; 1072048e328SMark Yao /* lock vop irq reg */ 1082048e328SMark Yao spinlock_t irq_lock; 1092048e328SMark Yao 1102048e328SMark Yao unsigned int irq; 1112048e328SMark Yao 1122048e328SMark Yao /* vop AHP clk */ 1132048e328SMark Yao struct clk *hclk; 1142048e328SMark Yao /* vop dclk */ 1152048e328SMark Yao struct clk *dclk; 1162048e328SMark Yao /* vop share memory frequency */ 1172048e328SMark Yao struct clk *aclk; 1182048e328SMark Yao 1192048e328SMark Yao /* vop dclk reset */ 1202048e328SMark Yao struct reset_control *dclk_rst; 1212048e328SMark Yao 1222048e328SMark Yao int pipe; 1232048e328SMark Yao 1242048e328SMark Yao struct vop_win win[]; 1252048e328SMark Yao }; 1262048e328SMark Yao 1272048e328SMark Yao enum vop_data_format { 1282048e328SMark Yao VOP_FMT_ARGB8888 = 0, 1292048e328SMark Yao VOP_FMT_RGB888, 1302048e328SMark Yao VOP_FMT_RGB565, 1312048e328SMark Yao VOP_FMT_YUV420SP = 4, 1322048e328SMark Yao VOP_FMT_YUV422SP, 1332048e328SMark Yao VOP_FMT_YUV444SP, 1342048e328SMark Yao }; 1352048e328SMark Yao 1362048e328SMark Yao struct vop_reg_data { 1372048e328SMark Yao uint32_t offset; 1382048e328SMark Yao uint32_t value; 1392048e328SMark Yao }; 1402048e328SMark Yao 1412048e328SMark Yao struct vop_reg { 1422048e328SMark Yao uint32_t offset; 1432048e328SMark Yao uint32_t shift; 1442048e328SMark Yao uint32_t mask; 1452048e328SMark Yao }; 1462048e328SMark Yao 1472048e328SMark Yao struct vop_ctrl { 1482048e328SMark Yao struct vop_reg standby; 1492048e328SMark Yao struct vop_reg data_blank; 1502048e328SMark Yao struct vop_reg gate_en; 1512048e328SMark Yao struct vop_reg mmu_en; 1522048e328SMark Yao struct vop_reg rgb_en; 1532048e328SMark Yao struct vop_reg edp_en; 1542048e328SMark Yao struct vop_reg hdmi_en; 1552048e328SMark Yao struct vop_reg mipi_en; 1562048e328SMark Yao struct vop_reg out_mode; 1572048e328SMark Yao struct vop_reg dither_down; 1582048e328SMark Yao struct vop_reg dither_up; 1592048e328SMark Yao struct vop_reg pin_pol; 1602048e328SMark Yao 1612048e328SMark Yao struct vop_reg htotal_pw; 1622048e328SMark Yao struct vop_reg hact_st_end; 1632048e328SMark Yao struct vop_reg vtotal_pw; 1642048e328SMark Yao struct vop_reg vact_st_end; 1652048e328SMark Yao struct vop_reg hpost_st_end; 1662048e328SMark Yao struct vop_reg vpost_st_end; 1672048e328SMark Yao }; 1682048e328SMark Yao 1694c156c21SMark Yao struct vop_scl_regs { 1704c156c21SMark Yao struct vop_reg cbcr_vsd_mode; 1714c156c21SMark Yao struct vop_reg cbcr_vsu_mode; 1724c156c21SMark Yao struct vop_reg cbcr_hsd_mode; 1734c156c21SMark Yao struct vop_reg cbcr_ver_scl_mode; 1744c156c21SMark Yao struct vop_reg cbcr_hor_scl_mode; 1754c156c21SMark Yao struct vop_reg yrgb_vsd_mode; 1764c156c21SMark Yao struct vop_reg yrgb_vsu_mode; 1774c156c21SMark Yao struct vop_reg yrgb_hsd_mode; 1784c156c21SMark Yao struct vop_reg yrgb_ver_scl_mode; 1794c156c21SMark Yao struct vop_reg yrgb_hor_scl_mode; 1804c156c21SMark Yao struct vop_reg line_load_mode; 1814c156c21SMark Yao struct vop_reg cbcr_axi_gather_num; 1824c156c21SMark Yao struct vop_reg yrgb_axi_gather_num; 1834c156c21SMark Yao struct vop_reg vsd_cbcr_gt2; 1844c156c21SMark Yao struct vop_reg vsd_cbcr_gt4; 1854c156c21SMark Yao struct vop_reg vsd_yrgb_gt2; 1864c156c21SMark Yao struct vop_reg vsd_yrgb_gt4; 1874c156c21SMark Yao struct vop_reg bic_coe_sel; 1884c156c21SMark Yao struct vop_reg cbcr_axi_gather_en; 1894c156c21SMark Yao struct vop_reg yrgb_axi_gather_en; 1904c156c21SMark Yao 1914c156c21SMark Yao struct vop_reg lb_mode; 1924c156c21SMark Yao struct vop_reg scale_yrgb_x; 1934c156c21SMark Yao struct vop_reg scale_yrgb_y; 1944c156c21SMark Yao struct vop_reg scale_cbcr_x; 1954c156c21SMark Yao struct vop_reg scale_cbcr_y; 1964c156c21SMark Yao }; 1974c156c21SMark Yao 1982048e328SMark Yao struct vop_win_phy { 1994c156c21SMark Yao const struct vop_scl_regs *scl; 2002048e328SMark Yao const uint32_t *data_formats; 2012048e328SMark Yao uint32_t nformats; 2022048e328SMark Yao 2032048e328SMark Yao struct vop_reg enable; 2042048e328SMark Yao struct vop_reg format; 20585a359f2STomasz Figa struct vop_reg rb_swap; 2062048e328SMark Yao struct vop_reg act_info; 2072048e328SMark Yao struct vop_reg dsp_info; 2082048e328SMark Yao struct vop_reg dsp_st; 2092048e328SMark Yao struct vop_reg yrgb_mst; 2102048e328SMark Yao struct vop_reg uv_mst; 2112048e328SMark Yao struct vop_reg yrgb_vir; 2122048e328SMark Yao struct vop_reg uv_vir; 2132048e328SMark Yao 2142048e328SMark Yao struct vop_reg dst_alpha_ctl; 2152048e328SMark Yao struct vop_reg src_alpha_ctl; 2162048e328SMark Yao }; 2172048e328SMark Yao 2182048e328SMark Yao struct vop_win_data { 2192048e328SMark Yao uint32_t base; 2202048e328SMark Yao const struct vop_win_phy *phy; 2212048e328SMark Yao enum drm_plane_type type; 2222048e328SMark Yao }; 2232048e328SMark Yao 2242048e328SMark Yao struct vop_data { 2252048e328SMark Yao const struct vop_reg_data *init_table; 2262048e328SMark Yao unsigned int table_size; 2272048e328SMark Yao const struct vop_ctrl *ctrl; 2282048e328SMark Yao const struct vop_win_data *win; 2292048e328SMark Yao unsigned int win_size; 2302048e328SMark Yao }; 2312048e328SMark Yao 2322048e328SMark Yao static const uint32_t formats_01[] = { 2332048e328SMark Yao DRM_FORMAT_XRGB8888, 2342048e328SMark Yao DRM_FORMAT_ARGB8888, 23585a359f2STomasz Figa DRM_FORMAT_XBGR8888, 23685a359f2STomasz Figa DRM_FORMAT_ABGR8888, 2372048e328SMark Yao DRM_FORMAT_RGB888, 23885a359f2STomasz Figa DRM_FORMAT_BGR888, 2392048e328SMark Yao DRM_FORMAT_RGB565, 24085a359f2STomasz Figa DRM_FORMAT_BGR565, 2412048e328SMark Yao DRM_FORMAT_NV12, 2422048e328SMark Yao DRM_FORMAT_NV16, 2432048e328SMark Yao DRM_FORMAT_NV24, 2442048e328SMark Yao }; 2452048e328SMark Yao 2462048e328SMark Yao static const uint32_t formats_234[] = { 2472048e328SMark Yao DRM_FORMAT_XRGB8888, 2482048e328SMark Yao DRM_FORMAT_ARGB8888, 24985a359f2STomasz Figa DRM_FORMAT_XBGR8888, 25085a359f2STomasz Figa DRM_FORMAT_ABGR8888, 2512048e328SMark Yao DRM_FORMAT_RGB888, 25285a359f2STomasz Figa DRM_FORMAT_BGR888, 2532048e328SMark Yao DRM_FORMAT_RGB565, 25485a359f2STomasz Figa DRM_FORMAT_BGR565, 2552048e328SMark Yao }; 2562048e328SMark Yao 2574c156c21SMark Yao static const struct vop_scl_regs win_full_scl = { 2584c156c21SMark Yao .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31), 2594c156c21SMark Yao .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30), 2604c156c21SMark Yao .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28), 2614c156c21SMark Yao .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26), 2624c156c21SMark Yao .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24), 2634c156c21SMark Yao .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23), 2644c156c21SMark Yao .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22), 2654c156c21SMark Yao .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20), 2664c156c21SMark Yao .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18), 2674c156c21SMark Yao .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16), 2684c156c21SMark Yao .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15), 2694c156c21SMark Yao .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12), 2704c156c21SMark Yao .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8), 2714c156c21SMark Yao .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7), 2724c156c21SMark Yao .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6), 2734c156c21SMark Yao .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5), 2744c156c21SMark Yao .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4), 2754c156c21SMark Yao .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2), 2764c156c21SMark Yao .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1), 2774c156c21SMark Yao .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0), 2784c156c21SMark Yao .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5), 2794c156c21SMark Yao .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 2804c156c21SMark Yao .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 2814c156c21SMark Yao .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 2824c156c21SMark Yao .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16), 2834c156c21SMark Yao }; 2844c156c21SMark Yao 2852048e328SMark Yao static const struct vop_win_phy win01_data = { 2864c156c21SMark Yao .scl = &win_full_scl, 2872048e328SMark Yao .data_formats = formats_01, 2882048e328SMark Yao .nformats = ARRAY_SIZE(formats_01), 2892048e328SMark Yao .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), 2902048e328SMark Yao .format = VOP_REG(WIN0_CTRL0, 0x7, 1), 29185a359f2STomasz Figa .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12), 2922048e328SMark Yao .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0), 2932048e328SMark Yao .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0), 2942048e328SMark Yao .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0), 2952048e328SMark Yao .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0), 2962048e328SMark Yao .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0), 2972048e328SMark Yao .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0), 2982048e328SMark Yao .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16), 2992048e328SMark Yao .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0), 3002048e328SMark Yao .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0), 3012048e328SMark Yao }; 3022048e328SMark Yao 3032048e328SMark Yao static const struct vop_win_phy win23_data = { 3042048e328SMark Yao .data_formats = formats_234, 3052048e328SMark Yao .nformats = ARRAY_SIZE(formats_234), 3062048e328SMark Yao .enable = VOP_REG(WIN2_CTRL0, 0x1, 0), 3072048e328SMark Yao .format = VOP_REG(WIN2_CTRL0, 0x7, 1), 30885a359f2STomasz Figa .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12), 3092048e328SMark Yao .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0), 3102048e328SMark Yao .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0), 3112048e328SMark Yao .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0), 3122048e328SMark Yao .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0), 3132048e328SMark Yao .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0), 3142048e328SMark Yao .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0), 3152048e328SMark Yao }; 3162048e328SMark Yao 3172048e328SMark Yao static const struct vop_ctrl ctrl_data = { 3182048e328SMark Yao .standby = VOP_REG(SYS_CTRL, 0x1, 22), 3192048e328SMark Yao .gate_en = VOP_REG(SYS_CTRL, 0x1, 23), 3202048e328SMark Yao .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20), 3212048e328SMark Yao .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12), 3222048e328SMark Yao .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13), 3232048e328SMark Yao .edp_en = VOP_REG(SYS_CTRL, 0x1, 14), 3242048e328SMark Yao .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15), 3252048e328SMark Yao .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1), 3262048e328SMark Yao .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6), 3272048e328SMark Yao .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19), 3282048e328SMark Yao .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0), 3292048e328SMark Yao .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4), 3302048e328SMark Yao .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 3312048e328SMark Yao .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0), 3322048e328SMark Yao .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 3332048e328SMark Yao .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0), 3342048e328SMark Yao .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0), 3352048e328SMark Yao .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0), 3362048e328SMark Yao }; 3372048e328SMark Yao 3382048e328SMark Yao static const struct vop_reg_data vop_init_reg_table[] = { 3392048e328SMark Yao {SYS_CTRL, 0x00c00000}, 3402048e328SMark Yao {DSP_CTRL0, 0x00000000}, 3412048e328SMark Yao {WIN0_CTRL0, 0x00000080}, 3422048e328SMark Yao {WIN1_CTRL0, 0x00000080}, 343c1998f08SMark Yao /* TODO: Win2/3 support multiple area function, but we haven't found 344c1998f08SMark Yao * a suitable way to use it yet, so let's just use them as other windows 345c1998f08SMark Yao * with only area 0 enabled. 346c1998f08SMark Yao */ 347c1998f08SMark Yao {WIN2_CTRL0, 0x00000010}, 348c1998f08SMark Yao {WIN3_CTRL0, 0x00000010}, 3492048e328SMark Yao }; 3502048e328SMark Yao 3512048e328SMark Yao /* 3522048e328SMark Yao * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 3532048e328SMark Yao * special support to get alpha blending working. For now, just use overlay 354d3cae7dfSyao mark * window 3 for the drm cursor. 355d3cae7dfSyao mark * 3562048e328SMark Yao */ 3572048e328SMark Yao static const struct vop_win_data rk3288_vop_win_data[] = { 3582048e328SMark Yao { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, 359d3cae7dfSyao mark { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY }, 3602048e328SMark Yao { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, 361d3cae7dfSyao mark { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR }, 3622048e328SMark Yao }; 3632048e328SMark Yao 3642048e328SMark Yao static const struct vop_data rk3288_vop = { 3652048e328SMark Yao .init_table = vop_init_reg_table, 3662048e328SMark Yao .table_size = ARRAY_SIZE(vop_init_reg_table), 3672048e328SMark Yao .ctrl = &ctrl_data, 3682048e328SMark Yao .win = rk3288_vop_win_data, 3692048e328SMark Yao .win_size = ARRAY_SIZE(rk3288_vop_win_data), 3702048e328SMark Yao }; 3712048e328SMark Yao 3722048e328SMark Yao static const struct of_device_id vop_driver_dt_match[] = { 3732048e328SMark Yao { .compatible = "rockchip,rk3288-vop", 3742048e328SMark Yao .data = &rk3288_vop }, 3752048e328SMark Yao {}, 3762048e328SMark Yao }; 3773b134cedSLuis de Bethencourt MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 3782048e328SMark Yao 3792048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 3802048e328SMark Yao { 3812048e328SMark Yao writel(v, vop->regs + offset); 3822048e328SMark Yao vop->regsbak[offset >> 2] = v; 3832048e328SMark Yao } 3842048e328SMark Yao 3852048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 3862048e328SMark Yao { 3872048e328SMark Yao return readl(vop->regs + offset); 3882048e328SMark Yao } 3892048e328SMark Yao 3902048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 3912048e328SMark Yao const struct vop_reg *reg) 3922048e328SMark Yao { 3932048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 3942048e328SMark Yao } 3952048e328SMark Yao 3962048e328SMark Yao static inline void vop_cfg_done(struct vop *vop) 3972048e328SMark Yao { 3982048e328SMark Yao writel(0x01, vop->regs + REG_CFG_DONE); 3992048e328SMark Yao } 4002048e328SMark Yao 4012048e328SMark Yao static inline void vop_mask_write(struct vop *vop, uint32_t offset, 4022048e328SMark Yao uint32_t mask, uint32_t v) 4032048e328SMark Yao { 4042048e328SMark Yao if (mask) { 4052048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 4062048e328SMark Yao 4072048e328SMark Yao cached_val = (cached_val & ~mask) | v; 4082048e328SMark Yao writel(cached_val, vop->regs + offset); 4092048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 4102048e328SMark Yao } 4112048e328SMark Yao } 4122048e328SMark Yao 4132048e328SMark Yao static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 4142048e328SMark Yao uint32_t mask, uint32_t v) 4152048e328SMark Yao { 4162048e328SMark Yao if (mask) { 4172048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 4182048e328SMark Yao 4192048e328SMark Yao cached_val = (cached_val & ~mask) | v; 4202048e328SMark Yao writel_relaxed(cached_val, vop->regs + offset); 4212048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 4222048e328SMark Yao } 4232048e328SMark Yao } 4242048e328SMark Yao 42585a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 42685a359f2STomasz Figa { 42785a359f2STomasz Figa switch (format) { 42885a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 42985a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 43085a359f2STomasz Figa case DRM_FORMAT_BGR888: 43185a359f2STomasz Figa case DRM_FORMAT_BGR565: 43285a359f2STomasz Figa return true; 43385a359f2STomasz Figa default: 43485a359f2STomasz Figa return false; 43585a359f2STomasz Figa } 43685a359f2STomasz Figa } 43785a359f2STomasz Figa 4382048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 4392048e328SMark Yao { 4402048e328SMark Yao switch (format) { 4412048e328SMark Yao case DRM_FORMAT_XRGB8888: 4422048e328SMark Yao case DRM_FORMAT_ARGB8888: 44385a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 44485a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 4452048e328SMark Yao return VOP_FMT_ARGB8888; 4462048e328SMark Yao case DRM_FORMAT_RGB888: 44785a359f2STomasz Figa case DRM_FORMAT_BGR888: 4482048e328SMark Yao return VOP_FMT_RGB888; 4492048e328SMark Yao case DRM_FORMAT_RGB565: 45085a359f2STomasz Figa case DRM_FORMAT_BGR565: 4512048e328SMark Yao return VOP_FMT_RGB565; 4522048e328SMark Yao case DRM_FORMAT_NV12: 4532048e328SMark Yao return VOP_FMT_YUV420SP; 4542048e328SMark Yao case DRM_FORMAT_NV16: 4552048e328SMark Yao return VOP_FMT_YUV422SP; 4562048e328SMark Yao case DRM_FORMAT_NV24: 4572048e328SMark Yao return VOP_FMT_YUV444SP; 4582048e328SMark Yao default: 4592048e328SMark Yao DRM_ERROR("unsupport format[%08x]\n", format); 4602048e328SMark Yao return -EINVAL; 4612048e328SMark Yao } 4622048e328SMark Yao } 4632048e328SMark Yao 46484c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 46584c7f8caSMark Yao { 46684c7f8caSMark Yao switch (format) { 46784c7f8caSMark Yao case DRM_FORMAT_NV12: 46884c7f8caSMark Yao case DRM_FORMAT_NV16: 46984c7f8caSMark Yao case DRM_FORMAT_NV24: 47084c7f8caSMark Yao return true; 47184c7f8caSMark Yao default: 47284c7f8caSMark Yao return false; 47384c7f8caSMark Yao } 47484c7f8caSMark Yao } 47584c7f8caSMark Yao 4762048e328SMark Yao static bool is_alpha_support(uint32_t format) 4772048e328SMark Yao { 4782048e328SMark Yao switch (format) { 4792048e328SMark Yao case DRM_FORMAT_ARGB8888: 48085a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 4812048e328SMark Yao return true; 4822048e328SMark Yao default: 4832048e328SMark Yao return false; 4842048e328SMark Yao } 4852048e328SMark Yao } 4862048e328SMark Yao 4874c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 4884c156c21SMark Yao uint32_t dst, bool is_horizontal, 4894c156c21SMark Yao int vsu_mode, int *vskiplines) 4904c156c21SMark Yao { 4914c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 4924c156c21SMark Yao 4934c156c21SMark Yao if (is_horizontal) { 4944c156c21SMark Yao if (mode == SCALE_UP) 4954c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 4964c156c21SMark Yao else if (mode == SCALE_DOWN) 4974c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 4984c156c21SMark Yao } else { 4994c156c21SMark Yao if (mode == SCALE_UP) { 5004c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 5014c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 5024c156c21SMark Yao else 5034c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 5044c156c21SMark Yao } else if (mode == SCALE_DOWN) { 5054c156c21SMark Yao if (vskiplines) { 5064c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 5074c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 5084c156c21SMark Yao *vskiplines); 5094c156c21SMark Yao } else { 5104c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 5114c156c21SMark Yao } 5124c156c21SMark Yao } 5134c156c21SMark Yao } 5144c156c21SMark Yao 5154c156c21SMark Yao return val; 5164c156c21SMark Yao } 5174c156c21SMark Yao 5184c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 5194c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 5204c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 5214c156c21SMark Yao { 5224c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 5234c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 5244c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 5254c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 5264c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 5274c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 5284c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 5294c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 5304c156c21SMark Yao uint16_t vsu_mode; 5314c156c21SMark Yao uint16_t lb_mode; 5324c156c21SMark Yao uint32_t val; 5334c156c21SMark Yao int vskiplines; 5344c156c21SMark Yao 5354c156c21SMark Yao if (dst_w > 3840) { 5364c156c21SMark Yao DRM_ERROR("Maximum destination width (3840) exceeded\n"); 5374c156c21SMark Yao return; 5384c156c21SMark Yao } 5394c156c21SMark Yao 5404c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 5414c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 5424c156c21SMark Yao 5434c156c21SMark Yao if (is_yuv) { 5444c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 5454c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 5464c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 5474c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 5484c156c21SMark Yao else 5494c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 5504c156c21SMark Yao } else { 5514c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 5524c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 5534c156c21SMark Yao else 5544c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 5554c156c21SMark Yao } 5564c156c21SMark Yao 5574c156c21SMark Yao VOP_SCL_SET(vop, win, lb_mode, lb_mode); 5584c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 5594c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 5604c156c21SMark Yao DRM_ERROR("ERROR : not allow yrgb ver scale\n"); 5614c156c21SMark Yao return; 5624c156c21SMark Yao } 5634c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 5644c156c21SMark Yao DRM_ERROR("ERROR : not allow cbcr ver scale\n"); 5654c156c21SMark Yao return; 5664c156c21SMark Yao } 5674c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 5684c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 5694c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 5704c156c21SMark Yao } else { 5714c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 5724c156c21SMark Yao } 5734c156c21SMark Yao 5744c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 5754c156c21SMark Yao true, 0, NULL); 5764c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 5774c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 5784c156c21SMark Yao false, vsu_mode, &vskiplines); 5794c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 5804c156c21SMark Yao 5814c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4); 5824c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2); 5834c156c21SMark Yao 5844c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 5854c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 5864c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 5874c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 5884c156c21SMark Yao VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode); 5894c156c21SMark Yao if (is_yuv) { 5904c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 5914c156c21SMark Yao dst_w, true, 0, NULL); 5924c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 5934c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 5944c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 5954c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 5964c156c21SMark Yao 5974c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4); 5984c156c21SMark Yao VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2); 5994c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 6004c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 6014c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 6024c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 6034c156c21SMark Yao VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode); 6044c156c21SMark Yao } 6054c156c21SMark Yao } 6064c156c21SMark Yao 6071067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 6081067219bSMark Yao { 6091067219bSMark Yao unsigned long flags; 6101067219bSMark Yao 6111067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 6121067219bSMark Yao return; 6131067219bSMark Yao 6141067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 6151067219bSMark Yao 6161067219bSMark Yao vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 6171067219bSMark Yao DSP_HOLD_VALID_INTR_EN(1)); 6181067219bSMark Yao 6191067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 6201067219bSMark Yao } 6211067219bSMark Yao 6221067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 6231067219bSMark Yao { 6241067219bSMark Yao unsigned long flags; 6251067219bSMark Yao 6261067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 6271067219bSMark Yao return; 6281067219bSMark Yao 6291067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 6301067219bSMark Yao 6311067219bSMark Yao vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 6321067219bSMark Yao DSP_HOLD_VALID_INTR_EN(0)); 6331067219bSMark Yao 6341067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 6351067219bSMark Yao } 6361067219bSMark Yao 6372048e328SMark Yao static void vop_enable(struct drm_crtc *crtc) 6382048e328SMark Yao { 6392048e328SMark Yao struct vop *vop = to_vop(crtc); 6402048e328SMark Yao int ret; 6412048e328SMark Yao 64231e980c5SMark Yao if (vop->is_enabled) 64331e980c5SMark Yao return; 64431e980c5SMark Yao 6455d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 6465d82d1a7SMark Yao if (ret < 0) { 6475d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 6485d82d1a7SMark Yao return; 6495d82d1a7SMark Yao } 6505d82d1a7SMark Yao 6512048e328SMark Yao ret = clk_enable(vop->hclk); 6522048e328SMark Yao if (ret < 0) { 6532048e328SMark Yao dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 6542048e328SMark Yao return; 6552048e328SMark Yao } 6562048e328SMark Yao 6572048e328SMark Yao ret = clk_enable(vop->dclk); 6582048e328SMark Yao if (ret < 0) { 6592048e328SMark Yao dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 6602048e328SMark Yao goto err_disable_hclk; 6612048e328SMark Yao } 6622048e328SMark Yao 6632048e328SMark Yao ret = clk_enable(vop->aclk); 6642048e328SMark Yao if (ret < 0) { 6652048e328SMark Yao dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 6662048e328SMark Yao goto err_disable_dclk; 6672048e328SMark Yao } 6682048e328SMark Yao 6692048e328SMark Yao /* 6702048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 6712048e328SMark Yao * automatically with this master device via common driver code. 6722048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 6732048e328SMark Yao * mapping. 6742048e328SMark Yao */ 6752048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 6762048e328SMark Yao if (ret) { 6772048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 6782048e328SMark Yao goto err_disable_aclk; 6792048e328SMark Yao } 6802048e328SMark Yao 68177faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 68252ab7891SMark Yao /* 68352ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 68452ab7891SMark Yao */ 68552ab7891SMark Yao vop->is_enabled = true; 68652ab7891SMark Yao 6872048e328SMark Yao spin_lock(&vop->reg_lock); 6882048e328SMark Yao 6892048e328SMark Yao VOP_CTRL_SET(vop, standby, 0); 6902048e328SMark Yao 6912048e328SMark Yao spin_unlock(&vop->reg_lock); 6922048e328SMark Yao 6932048e328SMark Yao enable_irq(vop->irq); 6942048e328SMark Yao 6952048e328SMark Yao drm_vblank_on(vop->drm_dev, vop->pipe); 6962048e328SMark Yao 6972048e328SMark Yao return; 6982048e328SMark Yao 6992048e328SMark Yao err_disable_aclk: 7002048e328SMark Yao clk_disable(vop->aclk); 7012048e328SMark Yao err_disable_dclk: 7022048e328SMark Yao clk_disable(vop->dclk); 7032048e328SMark Yao err_disable_hclk: 7042048e328SMark Yao clk_disable(vop->hclk); 7052048e328SMark Yao } 7062048e328SMark Yao 7072048e328SMark Yao static void vop_disable(struct drm_crtc *crtc) 7082048e328SMark Yao { 7092048e328SMark Yao struct vop *vop = to_vop(crtc); 7102048e328SMark Yao 71131e980c5SMark Yao if (!vop->is_enabled) 71231e980c5SMark Yao return; 71331e980c5SMark Yao 7142048e328SMark Yao drm_vblank_off(crtc->dev, vop->pipe); 7152048e328SMark Yao 7162048e328SMark Yao /* 7171067219bSMark Yao * Vop standby will take effect at end of current frame, 7181067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 7191067219bSMark Yao * 7201067219bSMark Yao * we must wait standby complete when we want to disable aclk, 7211067219bSMark Yao * if not, memory bus maybe dead. 7222048e328SMark Yao */ 7231067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 7241067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 7251067219bSMark Yao 7262048e328SMark Yao spin_lock(&vop->reg_lock); 7272048e328SMark Yao 7282048e328SMark Yao VOP_CTRL_SET(vop, standby, 1); 7292048e328SMark Yao 7302048e328SMark Yao spin_unlock(&vop->reg_lock); 73152ab7891SMark Yao 7321067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 7332048e328SMark Yao 7341067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 7351067219bSMark Yao 7361067219bSMark Yao disable_irq(vop->irq); 7371067219bSMark Yao 7381067219bSMark Yao vop->is_enabled = false; 7391067219bSMark Yao 7401067219bSMark Yao /* 7411067219bSMark Yao * vop standby complete, so iommu detach is safe. 7421067219bSMark Yao */ 7432048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 7442048e328SMark Yao 7451067219bSMark Yao clk_disable(vop->dclk); 7462048e328SMark Yao clk_disable(vop->aclk); 7472048e328SMark Yao clk_disable(vop->hclk); 7485d82d1a7SMark Yao pm_runtime_put(vop->dev); 7492048e328SMark Yao } 7502048e328SMark Yao 7512048e328SMark Yao /* 7522048e328SMark Yao * Caller must hold vsync_mutex. 7532048e328SMark Yao */ 7542048e328SMark Yao static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win) 7552048e328SMark Yao { 7562048e328SMark Yao struct vop_win_state *last; 7572048e328SMark Yao struct vop_win_state *active = vop_win->active; 7582048e328SMark Yao 7592048e328SMark Yao if (list_empty(&vop_win->pending)) 7602048e328SMark Yao return active ? active->fb : NULL; 7612048e328SMark Yao 7622048e328SMark Yao last = list_last_entry(&vop_win->pending, struct vop_win_state, head); 7632048e328SMark Yao return last ? last->fb : NULL; 7642048e328SMark Yao } 7652048e328SMark Yao 7662048e328SMark Yao /* 7672048e328SMark Yao * Caller must hold vsync_mutex. 7682048e328SMark Yao */ 7692048e328SMark Yao static int vop_win_queue_fb(struct vop_win *vop_win, 7702048e328SMark Yao struct drm_framebuffer *fb, dma_addr_t yrgb_mst, 7712048e328SMark Yao struct drm_pending_vblank_event *event) 7722048e328SMark Yao { 7732048e328SMark Yao struct vop_win_state *state; 7742048e328SMark Yao 7752048e328SMark Yao state = kzalloc(sizeof(*state), GFP_KERNEL); 7762048e328SMark Yao if (!state) 7772048e328SMark Yao return -ENOMEM; 7782048e328SMark Yao 7792048e328SMark Yao state->fb = fb; 7802048e328SMark Yao state->yrgb_mst = yrgb_mst; 7812048e328SMark Yao state->event = event; 7822048e328SMark Yao 7832048e328SMark Yao list_add_tail(&state->head, &vop_win->pending); 7842048e328SMark Yao 7852048e328SMark Yao return 0; 7862048e328SMark Yao } 7872048e328SMark Yao 7882048e328SMark Yao static int vop_update_plane_event(struct drm_plane *plane, 7892048e328SMark Yao struct drm_crtc *crtc, 7902048e328SMark Yao struct drm_framebuffer *fb, int crtc_x, 7912048e328SMark Yao int crtc_y, unsigned int crtc_w, 7922048e328SMark Yao unsigned int crtc_h, uint32_t src_x, 7932048e328SMark Yao uint32_t src_y, uint32_t src_w, 7942048e328SMark Yao uint32_t src_h, 7952048e328SMark Yao struct drm_pending_vblank_event *event) 7962048e328SMark Yao { 7972048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 7982048e328SMark Yao const struct vop_win_data *win = vop_win->data; 7992048e328SMark Yao struct vop *vop = to_vop(crtc); 8002048e328SMark Yao struct drm_gem_object *obj; 8012048e328SMark Yao struct rockchip_gem_object *rk_obj; 80284c7f8caSMark Yao struct drm_gem_object *uv_obj; 80384c7f8caSMark Yao struct rockchip_gem_object *rk_uv_obj; 8042048e328SMark Yao unsigned long offset; 8052048e328SMark Yao unsigned int actual_w; 8062048e328SMark Yao unsigned int actual_h; 8072048e328SMark Yao unsigned int dsp_stx; 8082048e328SMark Yao unsigned int dsp_sty; 8092048e328SMark Yao unsigned int y_vir_stride; 81084c7f8caSMark Yao unsigned int uv_vir_stride = 0; 8112048e328SMark Yao dma_addr_t yrgb_mst; 81284c7f8caSMark Yao dma_addr_t uv_mst = 0; 8132048e328SMark Yao enum vop_data_format format; 8142048e328SMark Yao uint32_t val; 8152048e328SMark Yao bool is_alpha; 81685a359f2STomasz Figa bool rb_swap; 81784c7f8caSMark Yao bool is_yuv; 8182048e328SMark Yao bool visible; 8192048e328SMark Yao int ret; 8202048e328SMark Yao struct drm_rect dest = { 8212048e328SMark Yao .x1 = crtc_x, 8222048e328SMark Yao .y1 = crtc_y, 8232048e328SMark Yao .x2 = crtc_x + crtc_w, 8242048e328SMark Yao .y2 = crtc_y + crtc_h, 8252048e328SMark Yao }; 8262048e328SMark Yao struct drm_rect src = { 8272048e328SMark Yao /* 16.16 fixed point */ 8282048e328SMark Yao .x1 = src_x, 8292048e328SMark Yao .y1 = src_y, 8302048e328SMark Yao .x2 = src_x + src_w, 8312048e328SMark Yao .y2 = src_y + src_h, 8322048e328SMark Yao }; 8332048e328SMark Yao const struct drm_rect clip = { 8342048e328SMark Yao .x2 = crtc->mode.hdisplay, 8352048e328SMark Yao .y2 = crtc->mode.vdisplay, 8362048e328SMark Yao }; 8372048e328SMark Yao bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY; 8384c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 8394c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 8404c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 8414c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 8422048e328SMark Yao 8432048e328SMark Yao ret = drm_plane_helper_check_update(plane, crtc, fb, 8442048e328SMark Yao &src, &dest, &clip, 8454c156c21SMark Yao min_scale, 8464c156c21SMark Yao max_scale, 8472048e328SMark Yao can_position, false, &visible); 8482048e328SMark Yao if (ret) 8492048e328SMark Yao return ret; 8502048e328SMark Yao 8512048e328SMark Yao if (!visible) 8522048e328SMark Yao return 0; 8532048e328SMark Yao 8542048e328SMark Yao is_alpha = is_alpha_support(fb->pixel_format); 85585a359f2STomasz Figa rb_swap = has_rb_swapped(fb->pixel_format); 85684c7f8caSMark Yao is_yuv = is_yuv_support(fb->pixel_format); 85784c7f8caSMark Yao 8582048e328SMark Yao format = vop_convert_format(fb->pixel_format); 8592048e328SMark Yao if (format < 0) 8602048e328SMark Yao return format; 8612048e328SMark Yao 8622048e328SMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 8632048e328SMark Yao if (!obj) { 8642048e328SMark Yao DRM_ERROR("fail to get rockchip gem object from framebuffer\n"); 8652048e328SMark Yao return -EINVAL; 8662048e328SMark Yao } 8672048e328SMark Yao 8682048e328SMark Yao rk_obj = to_rockchip_obj(obj); 8692048e328SMark Yao 87084c7f8caSMark Yao if (is_yuv) { 87184c7f8caSMark Yao /* 87284c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 87384c7f8caSMark Yao * need align with 2 pixel. 87484c7f8caSMark Yao */ 87584c7f8caSMark Yao val = (src.x1 >> 16) % 2; 87684c7f8caSMark Yao src.x1 += val << 16; 87784c7f8caSMark Yao src.x2 += val << 16; 87884c7f8caSMark Yao } 87984c7f8caSMark Yao 8802048e328SMark Yao actual_w = (src.x2 - src.x1) >> 16; 8812048e328SMark Yao actual_h = (src.y2 - src.y1) >> 16; 8822048e328SMark Yao 883acf8c3e0SMark Yao dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start; 884acf8c3e0SMark Yao dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 8852048e328SMark Yao 88684c7f8caSMark Yao offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 8872048e328SMark Yao offset += (src.y1 >> 16) * fb->pitches[0]; 8882048e328SMark Yao 88984c7f8caSMark Yao yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 890f1c79abeSMark Yao y_vir_stride = fb->pitches[0] >> 2; 8912048e328SMark Yao 89284c7f8caSMark Yao if (is_yuv) { 89384c7f8caSMark Yao int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 89484c7f8caSMark Yao int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 89584c7f8caSMark Yao int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 89684c7f8caSMark Yao 89784c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 89884c7f8caSMark Yao if (!uv_obj) { 89984c7f8caSMark Yao DRM_ERROR("fail to get uv object from framebuffer\n"); 90084c7f8caSMark Yao return -EINVAL; 90184c7f8caSMark Yao } 90284c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 90384c7f8caSMark Yao uv_vir_stride = fb->pitches[1] >> 2; 90484c7f8caSMark Yao 90584c7f8caSMark Yao offset = (src.x1 >> 16) * bpp / hsub; 90684c7f8caSMark Yao offset += (src.y1 >> 16) * fb->pitches[1] / vsub; 90784c7f8caSMark Yao 90884c7f8caSMark Yao uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 90984c7f8caSMark Yao } 91084c7f8caSMark Yao 9112048e328SMark Yao /* 9122048e328SMark Yao * If this plane update changes the plane's framebuffer, (or more 9132048e328SMark Yao * precisely, if this update has a different framebuffer than the last 9142048e328SMark Yao * update), enqueue it so we can track when it completes. 9152048e328SMark Yao * 9162048e328SMark Yao * Only when we discover that this update has completed, can we 9172048e328SMark Yao * unreference any previous framebuffers. 9182048e328SMark Yao */ 9192048e328SMark Yao mutex_lock(&vop->vsync_mutex); 9202048e328SMark Yao if (fb != vop_win_last_pending_fb(vop_win)) { 9212048e328SMark Yao ret = drm_vblank_get(plane->dev, vop->pipe); 9222048e328SMark Yao if (ret) { 9232048e328SMark Yao DRM_ERROR("failed to get vblank, %d\n", ret); 9242048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 9252048e328SMark Yao return ret; 9262048e328SMark Yao } 9272048e328SMark Yao 9282048e328SMark Yao drm_framebuffer_reference(fb); 9292048e328SMark Yao 9302048e328SMark Yao ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event); 9312048e328SMark Yao if (ret) { 9322048e328SMark Yao drm_vblank_put(plane->dev, vop->pipe); 9332048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 9342048e328SMark Yao return ret; 9352048e328SMark Yao } 9362048e328SMark Yao 9372048e328SMark Yao vop->vsync_work_pending = true; 9382048e328SMark Yao } 9392048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 9402048e328SMark Yao 9412048e328SMark Yao spin_lock(&vop->reg_lock); 9422048e328SMark Yao 9432048e328SMark Yao VOP_WIN_SET(vop, win, format, format); 9442048e328SMark Yao VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride); 9452048e328SMark Yao VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst); 94684c7f8caSMark Yao if (is_yuv) { 94784c7f8caSMark Yao VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride); 94884c7f8caSMark Yao VOP_WIN_SET(vop, win, uv_mst, uv_mst); 94984c7f8caSMark Yao } 9504c156c21SMark Yao 9514c156c21SMark Yao if (win->phy->scl) 9524c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 9534c156c21SMark Yao dest.x2 - dest.x1, dest.y2 - dest.y1, 9544c156c21SMark Yao fb->pixel_format); 9554c156c21SMark Yao 9562048e328SMark Yao val = (actual_h - 1) << 16; 9572048e328SMark Yao val |= (actual_w - 1) & 0xffff; 9582048e328SMark Yao VOP_WIN_SET(vop, win, act_info, val); 9594c156c21SMark Yao 9604c156c21SMark Yao val = (dest.y2 - dest.y1 - 1) << 16; 9614c156c21SMark Yao val |= (dest.x2 - dest.x1 - 1) & 0xffff; 9622048e328SMark Yao VOP_WIN_SET(vop, win, dsp_info, val); 96372906ce0SDominik Behr val = dsp_sty << 16; 96472906ce0SDominik Behr val |= dsp_stx & 0xffff; 9652048e328SMark Yao VOP_WIN_SET(vop, win, dsp_st, val); 96685a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 9672048e328SMark Yao 9682048e328SMark Yao if (is_alpha) { 9692048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 9702048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 9712048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 9722048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 9732048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 9742048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 9752048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 9762048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 9772048e328SMark Yao } else { 9782048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 9792048e328SMark Yao } 9802048e328SMark Yao 9812048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 9822048e328SMark Yao 9832048e328SMark Yao vop_cfg_done(vop); 9842048e328SMark Yao spin_unlock(&vop->reg_lock); 9852048e328SMark Yao 9862048e328SMark Yao return 0; 9872048e328SMark Yao } 9882048e328SMark Yao 9892048e328SMark Yao static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 9902048e328SMark Yao struct drm_framebuffer *fb, int crtc_x, int crtc_y, 9912048e328SMark Yao unsigned int crtc_w, unsigned int crtc_h, 9922048e328SMark Yao uint32_t src_x, uint32_t src_y, uint32_t src_w, 9932048e328SMark Yao uint32_t src_h) 9942048e328SMark Yao { 9952048e328SMark Yao return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w, 9962048e328SMark Yao crtc_h, src_x, src_y, src_w, src_h, 9972048e328SMark Yao NULL); 9982048e328SMark Yao } 9992048e328SMark Yao 10002048e328SMark Yao static int vop_update_primary_plane(struct drm_crtc *crtc, 10012048e328SMark Yao struct drm_pending_vblank_event *event) 10022048e328SMark Yao { 10032048e328SMark Yao unsigned int crtc_w, crtc_h; 10042048e328SMark Yao 10052048e328SMark Yao crtc_w = crtc->primary->fb->width - crtc->x; 10062048e328SMark Yao crtc_h = crtc->primary->fb->height - crtc->y; 10072048e328SMark Yao 10082048e328SMark Yao return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb, 10092048e328SMark Yao 0, 0, crtc_w, crtc_h, crtc->x << 16, 10102048e328SMark Yao crtc->y << 16, crtc_w << 16, 10112048e328SMark Yao crtc_h << 16, event); 10122048e328SMark Yao } 10132048e328SMark Yao 10142048e328SMark Yao static int vop_disable_plane(struct drm_plane *plane) 10152048e328SMark Yao { 10162048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 10172048e328SMark Yao const struct vop_win_data *win = vop_win->data; 10182048e328SMark Yao struct vop *vop; 10192048e328SMark Yao int ret; 10202048e328SMark Yao 10212048e328SMark Yao if (!plane->crtc) 10222048e328SMark Yao return 0; 10232048e328SMark Yao 10242048e328SMark Yao vop = to_vop(plane->crtc); 10252048e328SMark Yao 10262048e328SMark Yao ret = drm_vblank_get(plane->dev, vop->pipe); 10272048e328SMark Yao if (ret) { 10282048e328SMark Yao DRM_ERROR("failed to get vblank, %d\n", ret); 10292048e328SMark Yao return ret; 10302048e328SMark Yao } 10312048e328SMark Yao 10322048e328SMark Yao mutex_lock(&vop->vsync_mutex); 10332048e328SMark Yao 10342048e328SMark Yao ret = vop_win_queue_fb(vop_win, NULL, 0, NULL); 10352048e328SMark Yao if (ret) { 10362048e328SMark Yao drm_vblank_put(plane->dev, vop->pipe); 10372048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 10382048e328SMark Yao return ret; 10392048e328SMark Yao } 10402048e328SMark Yao 10412048e328SMark Yao vop->vsync_work_pending = true; 10422048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 10432048e328SMark Yao 10442048e328SMark Yao spin_lock(&vop->reg_lock); 10452048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 10462048e328SMark Yao vop_cfg_done(vop); 10472048e328SMark Yao spin_unlock(&vop->reg_lock); 10482048e328SMark Yao 10492048e328SMark Yao return 0; 10502048e328SMark Yao } 10512048e328SMark Yao 10522048e328SMark Yao static void vop_plane_destroy(struct drm_plane *plane) 10532048e328SMark Yao { 10542048e328SMark Yao vop_disable_plane(plane); 10552048e328SMark Yao drm_plane_cleanup(plane); 10562048e328SMark Yao } 10572048e328SMark Yao 10582048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 10592048e328SMark Yao .update_plane = vop_update_plane, 10602048e328SMark Yao .disable_plane = vop_disable_plane, 10612048e328SMark Yao .destroy = vop_plane_destroy, 10622048e328SMark Yao }; 10632048e328SMark Yao 10642048e328SMark Yao int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, 10652048e328SMark Yao int connector_type, 10662048e328SMark Yao int out_mode) 10672048e328SMark Yao { 10682048e328SMark Yao struct vop *vop = to_vop(crtc); 10692048e328SMark Yao 10702048e328SMark Yao vop->connector_type = connector_type; 10712048e328SMark Yao vop->connector_out_mode = out_mode; 10722048e328SMark Yao 10732048e328SMark Yao return 0; 10742048e328SMark Yao } 1075f66a1627SPhilipp Zabel EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); 10762048e328SMark Yao 10772048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 10782048e328SMark Yao { 10792048e328SMark Yao struct vop *vop = to_vop(crtc); 10802048e328SMark Yao unsigned long flags; 10812048e328SMark Yao 108231e980c5SMark Yao if (!vop->is_enabled) 10832048e328SMark Yao return -EPERM; 10842048e328SMark Yao 10852048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 10862048e328SMark Yao 10872048e328SMark Yao vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1)); 10882048e328SMark Yao 10892048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10902048e328SMark Yao 10912048e328SMark Yao return 0; 10922048e328SMark Yao } 10932048e328SMark Yao 10942048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 10952048e328SMark Yao { 10962048e328SMark Yao struct vop *vop = to_vop(crtc); 10972048e328SMark Yao unsigned long flags; 10982048e328SMark Yao 109931e980c5SMark Yao if (!vop->is_enabled) 11002048e328SMark Yao return; 110131e980c5SMark Yao 11022048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 11032048e328SMark Yao vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0)); 11042048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11052048e328SMark Yao } 11062048e328SMark Yao 11072048e328SMark Yao static const struct rockchip_crtc_funcs private_crtc_funcs = { 11082048e328SMark Yao .enable_vblank = vop_crtc_enable_vblank, 11092048e328SMark Yao .disable_vblank = vop_crtc_disable_vblank, 11102048e328SMark Yao }; 11112048e328SMark Yao 11122048e328SMark Yao static void vop_crtc_dpms(struct drm_crtc *crtc, int mode) 11132048e328SMark Yao { 11142048e328SMark Yao DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode); 11152048e328SMark Yao 11162048e328SMark Yao switch (mode) { 11172048e328SMark Yao case DRM_MODE_DPMS_ON: 11182048e328SMark Yao vop_enable(crtc); 11192048e328SMark Yao break; 11202048e328SMark Yao case DRM_MODE_DPMS_STANDBY: 11212048e328SMark Yao case DRM_MODE_DPMS_SUSPEND: 11222048e328SMark Yao case DRM_MODE_DPMS_OFF: 11232048e328SMark Yao vop_disable(crtc); 11242048e328SMark Yao break; 11252048e328SMark Yao default: 11262048e328SMark Yao DRM_DEBUG_KMS("unspecified mode %d\n", mode); 11272048e328SMark Yao break; 11282048e328SMark Yao } 11292048e328SMark Yao } 11302048e328SMark Yao 11312048e328SMark Yao static void vop_crtc_prepare(struct drm_crtc *crtc) 11322048e328SMark Yao { 11332048e328SMark Yao vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 11342048e328SMark Yao } 11352048e328SMark Yao 11362048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 11372048e328SMark Yao const struct drm_display_mode *mode, 11382048e328SMark Yao struct drm_display_mode *adjusted_mode) 11392048e328SMark Yao { 11402048e328SMark Yao if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) 11412048e328SMark Yao return false; 11422048e328SMark Yao 11432048e328SMark Yao return true; 11442048e328SMark Yao } 11452048e328SMark Yao 11462048e328SMark Yao static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 11472048e328SMark Yao struct drm_framebuffer *old_fb) 11482048e328SMark Yao { 11492048e328SMark Yao int ret; 11502048e328SMark Yao 11512048e328SMark Yao crtc->x = x; 11522048e328SMark Yao crtc->y = y; 11532048e328SMark Yao 11542048e328SMark Yao ret = vop_update_primary_plane(crtc, NULL); 11552048e328SMark Yao if (ret < 0) { 11562048e328SMark Yao DRM_ERROR("fail to update plane\n"); 11572048e328SMark Yao return ret; 11582048e328SMark Yao } 11592048e328SMark Yao 11602048e328SMark Yao return 0; 11612048e328SMark Yao } 11622048e328SMark Yao 11632048e328SMark Yao static int vop_crtc_mode_set(struct drm_crtc *crtc, 11642048e328SMark Yao struct drm_display_mode *mode, 11652048e328SMark Yao struct drm_display_mode *adjusted_mode, 11662048e328SMark Yao int x, int y, struct drm_framebuffer *fb) 11672048e328SMark Yao { 11682048e328SMark Yao struct vop *vop = to_vop(crtc); 11692048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 11702048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 11712048e328SMark Yao u16 htotal = adjusted_mode->htotal; 11722048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 11732048e328SMark Yao u16 hact_end = hact_st + hdisplay; 11742048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 11752048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 11762048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 11772048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 11782048e328SMark Yao u16 vact_end = vact_st + vdisplay; 11797f53fbbaSHeiko Stuebner int ret, ret_clk; 11802048e328SMark Yao uint32_t val; 11812048e328SMark Yao 11822048e328SMark Yao /* 11832048e328SMark Yao * disable dclk to stop frame scan, so that we can safe config mode and 11842048e328SMark Yao * enable iommu. 11852048e328SMark Yao */ 11862048e328SMark Yao clk_disable(vop->dclk); 11872048e328SMark Yao 11882048e328SMark Yao switch (vop->connector_type) { 11892048e328SMark Yao case DRM_MODE_CONNECTOR_LVDS: 11902048e328SMark Yao VOP_CTRL_SET(vop, rgb_en, 1); 11912048e328SMark Yao break; 11922048e328SMark Yao case DRM_MODE_CONNECTOR_eDP: 11932048e328SMark Yao VOP_CTRL_SET(vop, edp_en, 1); 11942048e328SMark Yao break; 11952048e328SMark Yao case DRM_MODE_CONNECTOR_HDMIA: 11962048e328SMark Yao VOP_CTRL_SET(vop, hdmi_en, 1); 11972048e328SMark Yao break; 11982048e328SMark Yao default: 11992048e328SMark Yao DRM_ERROR("unsupport connector_type[%d]\n", 12002048e328SMark Yao vop->connector_type); 12017f53fbbaSHeiko Stuebner ret = -EINVAL; 12027f53fbbaSHeiko Stuebner goto out; 12032048e328SMark Yao }; 12042048e328SMark Yao VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode); 12052048e328SMark Yao 12062048e328SMark Yao val = 0x8; 120744ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 120844ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 12092048e328SMark Yao VOP_CTRL_SET(vop, pin_pol, val); 12102048e328SMark Yao 12112048e328SMark Yao VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 12122048e328SMark Yao val = hact_st << 16; 12132048e328SMark Yao val |= hact_end; 12142048e328SMark Yao VOP_CTRL_SET(vop, hact_st_end, val); 12152048e328SMark Yao VOP_CTRL_SET(vop, hpost_st_end, val); 12162048e328SMark Yao 12172048e328SMark Yao VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 12182048e328SMark Yao val = vact_st << 16; 12192048e328SMark Yao val |= vact_end; 12202048e328SMark Yao VOP_CTRL_SET(vop, vact_st_end, val); 12212048e328SMark Yao VOP_CTRL_SET(vop, vpost_st_end, val); 12222048e328SMark Yao 12232048e328SMark Yao ret = vop_crtc_mode_set_base(crtc, x, y, fb); 12242048e328SMark Yao if (ret) 12257f53fbbaSHeiko Stuebner goto out; 12262048e328SMark Yao 12272048e328SMark Yao /* 12282048e328SMark Yao * reset dclk, take all mode config affect, so the clk would run in 12292048e328SMark Yao * correct frame. 12302048e328SMark Yao */ 12312048e328SMark Yao reset_control_assert(vop->dclk_rst); 12322048e328SMark Yao usleep_range(10, 20); 12332048e328SMark Yao reset_control_deassert(vop->dclk_rst); 12342048e328SMark Yao 12352048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 12367f53fbbaSHeiko Stuebner out: 12377f53fbbaSHeiko Stuebner ret_clk = clk_enable(vop->dclk); 12387f53fbbaSHeiko Stuebner if (ret_clk < 0) { 12397f53fbbaSHeiko Stuebner dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk); 12407f53fbbaSHeiko Stuebner return ret_clk; 12412048e328SMark Yao } 12422048e328SMark Yao 12437f53fbbaSHeiko Stuebner return ret; 12442048e328SMark Yao } 12452048e328SMark Yao 12462048e328SMark Yao static void vop_crtc_commit(struct drm_crtc *crtc) 12472048e328SMark Yao { 12482048e328SMark Yao } 12492048e328SMark Yao 12502048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 12512048e328SMark Yao .dpms = vop_crtc_dpms, 12522048e328SMark Yao .prepare = vop_crtc_prepare, 12532048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 12542048e328SMark Yao .mode_set = vop_crtc_mode_set, 12552048e328SMark Yao .mode_set_base = vop_crtc_mode_set_base, 12562048e328SMark Yao .commit = vop_crtc_commit, 12572048e328SMark Yao }; 12582048e328SMark Yao 12592048e328SMark Yao static int vop_crtc_page_flip(struct drm_crtc *crtc, 12602048e328SMark Yao struct drm_framebuffer *fb, 12612048e328SMark Yao struct drm_pending_vblank_event *event, 12622048e328SMark Yao uint32_t page_flip_flags) 12632048e328SMark Yao { 12642048e328SMark Yao struct vop *vop = to_vop(crtc); 12652048e328SMark Yao struct drm_framebuffer *old_fb = crtc->primary->fb; 12662048e328SMark Yao int ret; 12672048e328SMark Yao 126831e980c5SMark Yao /* when the page flip is requested, crtc should be on */ 126931e980c5SMark Yao if (!vop->is_enabled) { 127031e980c5SMark Yao DRM_DEBUG("page flip request rejected because crtc is off.\n"); 12712048e328SMark Yao return 0; 12722048e328SMark Yao } 12732048e328SMark Yao 12742048e328SMark Yao crtc->primary->fb = fb; 12752048e328SMark Yao 12762048e328SMark Yao ret = vop_update_primary_plane(crtc, event); 12772048e328SMark Yao if (ret) 12782048e328SMark Yao crtc->primary->fb = old_fb; 12792048e328SMark Yao 12802048e328SMark Yao return ret; 12812048e328SMark Yao } 12822048e328SMark Yao 12832048e328SMark Yao static void vop_win_state_complete(struct vop_win *vop_win, 12842048e328SMark Yao struct vop_win_state *state) 12852048e328SMark Yao { 12862048e328SMark Yao struct vop *vop = vop_win->vop; 12872048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12882048e328SMark Yao struct drm_device *drm = crtc->dev; 12892048e328SMark Yao unsigned long flags; 12902048e328SMark Yao 12912048e328SMark Yao if (state->event) { 12922048e328SMark Yao spin_lock_irqsave(&drm->event_lock, flags); 1293c9fbb7f7SDaniel Stone drm_crtc_send_vblank_event(crtc, state->event); 12942048e328SMark Yao spin_unlock_irqrestore(&drm->event_lock, flags); 12952048e328SMark Yao } 12962048e328SMark Yao 12972048e328SMark Yao list_del(&state->head); 12982048e328SMark Yao drm_vblank_put(crtc->dev, vop->pipe); 12992048e328SMark Yao } 13002048e328SMark Yao 13012048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 13022048e328SMark Yao { 13032048e328SMark Yao drm_crtc_cleanup(crtc); 13042048e328SMark Yao } 13052048e328SMark Yao 13062048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 13072048e328SMark Yao .set_config = drm_crtc_helper_set_config, 13082048e328SMark Yao .page_flip = vop_crtc_page_flip, 13092048e328SMark Yao .destroy = vop_crtc_destroy, 13102048e328SMark Yao }; 13112048e328SMark Yao 13122048e328SMark Yao static bool vop_win_state_is_active(struct vop_win *vop_win, 13132048e328SMark Yao struct vop_win_state *state) 13142048e328SMark Yao { 13152048e328SMark Yao bool active = false; 13162048e328SMark Yao 13172048e328SMark Yao if (state->fb) { 13182048e328SMark Yao dma_addr_t yrgb_mst; 13192048e328SMark Yao 13202048e328SMark Yao /* check yrgb_mst to tell if pending_fb is now front */ 13212048e328SMark Yao yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 13222048e328SMark Yao 13232048e328SMark Yao active = (yrgb_mst == state->yrgb_mst); 13242048e328SMark Yao } else { 13252048e328SMark Yao bool enabled; 13262048e328SMark Yao 13272048e328SMark Yao /* if enable bit is clear, plane is now disabled */ 13282048e328SMark Yao enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable); 13292048e328SMark Yao 13302048e328SMark Yao active = (enabled == 0); 13312048e328SMark Yao } 13322048e328SMark Yao 13332048e328SMark Yao return active; 13342048e328SMark Yao } 13352048e328SMark Yao 13362048e328SMark Yao static void vop_win_state_destroy(struct vop_win_state *state) 13372048e328SMark Yao { 13382048e328SMark Yao struct drm_framebuffer *fb = state->fb; 13392048e328SMark Yao 13402048e328SMark Yao if (fb) 13412048e328SMark Yao drm_framebuffer_unreference(fb); 13422048e328SMark Yao 13432048e328SMark Yao kfree(state); 13442048e328SMark Yao } 13452048e328SMark Yao 13462048e328SMark Yao static void vop_win_update_state(struct vop_win *vop_win) 13472048e328SMark Yao { 13482048e328SMark Yao struct vop_win_state *state, *n, *new_active = NULL; 13492048e328SMark Yao 13502048e328SMark Yao /* Check if any pending states are now active */ 13512048e328SMark Yao list_for_each_entry(state, &vop_win->pending, head) 13522048e328SMark Yao if (vop_win_state_is_active(vop_win, state)) { 13532048e328SMark Yao new_active = state; 13542048e328SMark Yao break; 13552048e328SMark Yao } 13562048e328SMark Yao 13572048e328SMark Yao if (!new_active) 13582048e328SMark Yao return; 13592048e328SMark Yao 13602048e328SMark Yao /* 13612048e328SMark Yao * Destroy any 'skipped' pending states - states that were queued 13622048e328SMark Yao * before the newly active state. 13632048e328SMark Yao */ 13642048e328SMark Yao list_for_each_entry_safe(state, n, &vop_win->pending, head) { 13652048e328SMark Yao if (state == new_active) 13662048e328SMark Yao break; 13672048e328SMark Yao vop_win_state_complete(vop_win, state); 13682048e328SMark Yao vop_win_state_destroy(state); 13692048e328SMark Yao } 13702048e328SMark Yao 13712048e328SMark Yao vop_win_state_complete(vop_win, new_active); 13722048e328SMark Yao 13732048e328SMark Yao if (vop_win->active) 13742048e328SMark Yao vop_win_state_destroy(vop_win->active); 13752048e328SMark Yao vop_win->active = new_active; 13762048e328SMark Yao } 13772048e328SMark Yao 13782048e328SMark Yao static bool vop_win_has_pending_state(struct vop_win *vop_win) 13792048e328SMark Yao { 13802048e328SMark Yao return !list_empty(&vop_win->pending); 13812048e328SMark Yao } 13822048e328SMark Yao 13832048e328SMark Yao static irqreturn_t vop_isr_thread(int irq, void *data) 13842048e328SMark Yao { 13852048e328SMark Yao struct vop *vop = data; 13862048e328SMark Yao const struct vop_data *vop_data = vop->data; 13872048e328SMark Yao unsigned int i; 13882048e328SMark Yao 13892048e328SMark Yao mutex_lock(&vop->vsync_mutex); 13902048e328SMark Yao 13912048e328SMark Yao if (!vop->vsync_work_pending) 13922048e328SMark Yao goto done; 13932048e328SMark Yao 13942048e328SMark Yao vop->vsync_work_pending = false; 13952048e328SMark Yao 13962048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13972048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13982048e328SMark Yao 13992048e328SMark Yao vop_win_update_state(vop_win); 14002048e328SMark Yao if (vop_win_has_pending_state(vop_win)) 14012048e328SMark Yao vop->vsync_work_pending = true; 14022048e328SMark Yao } 14032048e328SMark Yao 14042048e328SMark Yao done: 14052048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 14062048e328SMark Yao 14072048e328SMark Yao return IRQ_HANDLED; 14082048e328SMark Yao } 14092048e328SMark Yao 14102048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 14112048e328SMark Yao { 14122048e328SMark Yao struct vop *vop = data; 14132048e328SMark Yao uint32_t intr0_reg, active_irqs; 14142048e328SMark Yao unsigned long flags; 14151067219bSMark Yao int ret = IRQ_NONE; 14162048e328SMark Yao 14172048e328SMark Yao /* 14182048e328SMark Yao * INTR_CTRL0 register has interrupt status, enable and clear bits, we 14192048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 14202048e328SMark Yao */ 14212048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 14222048e328SMark Yao intr0_reg = vop_readl(vop, INTR_CTRL0); 14232048e328SMark Yao active_irqs = intr0_reg & INTR_MASK; 14242048e328SMark Yao /* Clear all active interrupt sources */ 14252048e328SMark Yao if (active_irqs) 14262048e328SMark Yao vop_writel(vop, INTR_CTRL0, 14272048e328SMark Yao intr0_reg | (active_irqs << INTR_CLR_SHIFT)); 14282048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 14292048e328SMark Yao 14302048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 14312048e328SMark Yao if (!active_irqs) 14322048e328SMark Yao return IRQ_NONE; 14332048e328SMark Yao 14341067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 14351067219bSMark Yao complete(&vop->dsp_hold_completion); 14361067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 14371067219bSMark Yao ret = IRQ_HANDLED; 14382048e328SMark Yao } 14392048e328SMark Yao 14401067219bSMark Yao if (active_irqs & FS_INTR) { 14412048e328SMark Yao drm_handle_vblank(vop->drm_dev, vop->pipe); 14421067219bSMark Yao active_irqs &= ~FS_INTR; 14431067219bSMark Yao ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 14441067219bSMark Yao } 14452048e328SMark Yao 14461067219bSMark Yao /* Unhandled irqs are spurious. */ 14471067219bSMark Yao if (active_irqs) 14481067219bSMark Yao DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 14491067219bSMark Yao 14501067219bSMark Yao return ret; 14512048e328SMark Yao } 14522048e328SMark Yao 14532048e328SMark Yao static int vop_create_crtc(struct vop *vop) 14542048e328SMark Yao { 14552048e328SMark Yao const struct vop_data *vop_data = vop->data; 14562048e328SMark Yao struct device *dev = vop->dev; 14572048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 14582048e328SMark Yao struct drm_plane *primary = NULL, *cursor = NULL, *plane; 14592048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 14602048e328SMark Yao struct device_node *port; 14612048e328SMark Yao int ret; 14622048e328SMark Yao int i; 14632048e328SMark Yao 14642048e328SMark Yao /* 14652048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 14662048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 14672048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 14682048e328SMark Yao */ 14692048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14702048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14712048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 14722048e328SMark Yao 14732048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 14742048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 14752048e328SMark Yao continue; 14762048e328SMark Yao 14772048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 14782048e328SMark Yao 0, &vop_plane_funcs, 14792048e328SMark Yao win_data->phy->data_formats, 14802048e328SMark Yao win_data->phy->nformats, 1481b0b3b795SVille Syrjälä win_data->type, NULL); 14822048e328SMark Yao if (ret) { 14832048e328SMark Yao DRM_ERROR("failed to initialize plane\n"); 14842048e328SMark Yao goto err_cleanup_planes; 14852048e328SMark Yao } 14862048e328SMark Yao 14872048e328SMark Yao plane = &vop_win->base; 14882048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 14892048e328SMark Yao primary = plane; 14902048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 14912048e328SMark Yao cursor = plane; 14922048e328SMark Yao } 14932048e328SMark Yao 14942048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1495f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 14962048e328SMark Yao if (ret) 14972048e328SMark Yao return ret; 14982048e328SMark Yao 14992048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 15002048e328SMark Yao 15012048e328SMark Yao /* 15022048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 15032048e328SMark Yao * to the newly created crtc. 15042048e328SMark Yao */ 15052048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 15062048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 15072048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 15082048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 15092048e328SMark Yao 15102048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 15112048e328SMark Yao continue; 15122048e328SMark Yao 15132048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 15142048e328SMark Yao possible_crtcs, 15152048e328SMark Yao &vop_plane_funcs, 15162048e328SMark Yao win_data->phy->data_formats, 15172048e328SMark Yao win_data->phy->nformats, 1518b0b3b795SVille Syrjälä win_data->type, NULL); 15192048e328SMark Yao if (ret) { 15202048e328SMark Yao DRM_ERROR("failed to initialize overlay plane\n"); 15212048e328SMark Yao goto err_cleanup_crtc; 15222048e328SMark Yao } 15232048e328SMark Yao } 15242048e328SMark Yao 15252048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 15262048e328SMark Yao if (!port) { 15272048e328SMark Yao DRM_ERROR("no port node found in %s\n", 15282048e328SMark Yao dev->of_node->full_name); 15292048e328SMark Yao goto err_cleanup_crtc; 15302048e328SMark Yao } 15312048e328SMark Yao 15321067219bSMark Yao init_completion(&vop->dsp_hold_completion); 15332048e328SMark Yao crtc->port = port; 15342048e328SMark Yao vop->pipe = drm_crtc_index(crtc); 15352048e328SMark Yao rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe); 15362048e328SMark Yao 15372048e328SMark Yao return 0; 15382048e328SMark Yao 15392048e328SMark Yao err_cleanup_crtc: 15402048e328SMark Yao drm_crtc_cleanup(crtc); 15412048e328SMark Yao err_cleanup_planes: 15422048e328SMark Yao list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) 15432048e328SMark Yao drm_plane_cleanup(plane); 15442048e328SMark Yao return ret; 15452048e328SMark Yao } 15462048e328SMark Yao 15472048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 15482048e328SMark Yao { 15492048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 15502048e328SMark Yao 15512048e328SMark Yao rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe); 15522048e328SMark Yao of_node_put(crtc->port); 15532048e328SMark Yao drm_crtc_cleanup(crtc); 15542048e328SMark Yao } 15552048e328SMark Yao 15562048e328SMark Yao static int vop_initial(struct vop *vop) 15572048e328SMark Yao { 15582048e328SMark Yao const struct vop_data *vop_data = vop->data; 15592048e328SMark Yao const struct vop_reg_data *init_table = vop_data->init_table; 15602048e328SMark Yao struct reset_control *ahb_rst; 15612048e328SMark Yao int i, ret; 15622048e328SMark Yao 15632048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 15642048e328SMark Yao if (IS_ERR(vop->hclk)) { 15652048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 15662048e328SMark Yao return PTR_ERR(vop->hclk); 15672048e328SMark Yao } 15682048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 15692048e328SMark Yao if (IS_ERR(vop->aclk)) { 15702048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 15712048e328SMark Yao return PTR_ERR(vop->aclk); 15722048e328SMark Yao } 15732048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 15742048e328SMark Yao if (IS_ERR(vop->dclk)) { 15752048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 15762048e328SMark Yao return PTR_ERR(vop->dclk); 15772048e328SMark Yao } 15782048e328SMark Yao 15792048e328SMark Yao ret = clk_prepare(vop->dclk); 15802048e328SMark Yao if (ret < 0) { 15812048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 1582d7b53fd9SSjoerd Simons return ret; 15832048e328SMark Yao } 15842048e328SMark Yao 1585d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1586d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 15872048e328SMark Yao if (ret < 0) { 1588d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable hclk\n"); 15892048e328SMark Yao goto err_unprepare_dclk; 15902048e328SMark Yao } 15912048e328SMark Yao 1592d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 15932048e328SMark Yao if (ret < 0) { 1594d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1595d7b53fd9SSjoerd Simons goto err_disable_hclk; 15962048e328SMark Yao } 1597d7b53fd9SSjoerd Simons 15982048e328SMark Yao /* 15992048e328SMark Yao * do hclk_reset, reset all vop registers. 16002048e328SMark Yao */ 16012048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 16022048e328SMark Yao if (IS_ERR(ahb_rst)) { 16032048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 16042048e328SMark Yao ret = PTR_ERR(ahb_rst); 1605d7b53fd9SSjoerd Simons goto err_disable_aclk; 16062048e328SMark Yao } 16072048e328SMark Yao reset_control_assert(ahb_rst); 16082048e328SMark Yao usleep_range(10, 20); 16092048e328SMark Yao reset_control_deassert(ahb_rst); 16102048e328SMark Yao 16112048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 16122048e328SMark Yao 16132048e328SMark Yao for (i = 0; i < vop_data->table_size; i++) 16142048e328SMark Yao vop_writel(vop, init_table[i].offset, init_table[i].value); 16152048e328SMark Yao 16162048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16172048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 16182048e328SMark Yao 16192048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 16202048e328SMark Yao } 16212048e328SMark Yao 16222048e328SMark Yao vop_cfg_done(vop); 16232048e328SMark Yao 16242048e328SMark Yao /* 16252048e328SMark Yao * do dclk_reset, let all config take affect. 16262048e328SMark Yao */ 16272048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 16282048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 16292048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 16302048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1631d7b53fd9SSjoerd Simons goto err_disable_aclk; 16322048e328SMark Yao } 16332048e328SMark Yao reset_control_assert(vop->dclk_rst); 16342048e328SMark Yao usleep_range(10, 20); 16352048e328SMark Yao reset_control_deassert(vop->dclk_rst); 16362048e328SMark Yao 16372048e328SMark Yao clk_disable(vop->hclk); 1638d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 16392048e328SMark Yao 164031e980c5SMark Yao vop->is_enabled = false; 16412048e328SMark Yao 16422048e328SMark Yao return 0; 16432048e328SMark Yao 1644d7b53fd9SSjoerd Simons err_disable_aclk: 1645d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 16462048e328SMark Yao err_disable_hclk: 1647d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 16482048e328SMark Yao err_unprepare_dclk: 16492048e328SMark Yao clk_unprepare(vop->dclk); 16502048e328SMark Yao return ret; 16512048e328SMark Yao } 16522048e328SMark Yao 16532048e328SMark Yao /* 16542048e328SMark Yao * Initialize the vop->win array elements. 16552048e328SMark Yao */ 16562048e328SMark Yao static void vop_win_init(struct vop *vop) 16572048e328SMark Yao { 16582048e328SMark Yao const struct vop_data *vop_data = vop->data; 16592048e328SMark Yao unsigned int i; 16602048e328SMark Yao 16612048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16622048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 16632048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 16642048e328SMark Yao 16652048e328SMark Yao vop_win->data = win_data; 16662048e328SMark Yao vop_win->vop = vop; 16672048e328SMark Yao INIT_LIST_HEAD(&vop_win->pending); 16682048e328SMark Yao } 16692048e328SMark Yao } 16702048e328SMark Yao 16712048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 16722048e328SMark Yao { 16732048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 16742048e328SMark Yao const struct of_device_id *of_id; 16752048e328SMark Yao const struct vop_data *vop_data; 16762048e328SMark Yao struct drm_device *drm_dev = data; 16772048e328SMark Yao struct vop *vop; 16782048e328SMark Yao struct resource *res; 16792048e328SMark Yao size_t alloc_size; 16803ea68922SHeiko Stuebner int ret, irq; 16812048e328SMark Yao 16822048e328SMark Yao of_id = of_match_device(vop_driver_dt_match, dev); 16832048e328SMark Yao vop_data = of_id->data; 16842048e328SMark Yao if (!vop_data) 16852048e328SMark Yao return -ENODEV; 16862048e328SMark Yao 16872048e328SMark Yao /* Allocate vop struct and its vop_win array */ 16882048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 16892048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 16902048e328SMark Yao if (!vop) 16912048e328SMark Yao return -ENOMEM; 16922048e328SMark Yao 16932048e328SMark Yao vop->dev = dev; 16942048e328SMark Yao vop->data = vop_data; 16952048e328SMark Yao vop->drm_dev = drm_dev; 16962048e328SMark Yao dev_set_drvdata(dev, vop); 16972048e328SMark Yao 16982048e328SMark Yao vop_win_init(vop); 16992048e328SMark Yao 17002048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 17012048e328SMark Yao vop->len = resource_size(res); 17022048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 17032048e328SMark Yao if (IS_ERR(vop->regs)) 17042048e328SMark Yao return PTR_ERR(vop->regs); 17052048e328SMark Yao 17062048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 17072048e328SMark Yao if (!vop->regsbak) 17082048e328SMark Yao return -ENOMEM; 17092048e328SMark Yao 17102048e328SMark Yao ret = vop_initial(vop); 17112048e328SMark Yao if (ret < 0) { 17122048e328SMark Yao dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 17132048e328SMark Yao return ret; 17142048e328SMark Yao } 17152048e328SMark Yao 17163ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 17173ea68922SHeiko Stuebner if (irq < 0) { 17182048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 17193ea68922SHeiko Stuebner return irq; 17202048e328SMark Yao } 17213ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 17222048e328SMark Yao 17232048e328SMark Yao spin_lock_init(&vop->reg_lock); 17242048e328SMark Yao spin_lock_init(&vop->irq_lock); 17252048e328SMark Yao 17262048e328SMark Yao mutex_init(&vop->vsync_mutex); 17272048e328SMark Yao 17282048e328SMark Yao ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread, 17292048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 17302048e328SMark Yao if (ret) 17312048e328SMark Yao return ret; 17322048e328SMark Yao 17332048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 17342048e328SMark Yao disable_irq(vop->irq); 17352048e328SMark Yao 17362048e328SMark Yao ret = vop_create_crtc(vop); 17372048e328SMark Yao if (ret) 17382048e328SMark Yao return ret; 17392048e328SMark Yao 17402048e328SMark Yao pm_runtime_enable(&pdev->dev); 17412048e328SMark Yao return 0; 17422048e328SMark Yao } 17432048e328SMark Yao 17442048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 17452048e328SMark Yao { 17462048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 17472048e328SMark Yao 17482048e328SMark Yao pm_runtime_disable(dev); 17492048e328SMark Yao vop_destroy_crtc(vop); 17502048e328SMark Yao } 17512048e328SMark Yao 17522048e328SMark Yao static const struct component_ops vop_component_ops = { 17532048e328SMark Yao .bind = vop_bind, 17542048e328SMark Yao .unbind = vop_unbind, 17552048e328SMark Yao }; 17562048e328SMark Yao 17572048e328SMark Yao static int vop_probe(struct platform_device *pdev) 17582048e328SMark Yao { 17592048e328SMark Yao struct device *dev = &pdev->dev; 17602048e328SMark Yao 17612048e328SMark Yao if (!dev->of_node) { 17622048e328SMark Yao dev_err(dev, "can't find vop devices\n"); 17632048e328SMark Yao return -ENODEV; 17642048e328SMark Yao } 17652048e328SMark Yao 17662048e328SMark Yao return component_add(dev, &vop_component_ops); 17672048e328SMark Yao } 17682048e328SMark Yao 17692048e328SMark Yao static int vop_remove(struct platform_device *pdev) 17702048e328SMark Yao { 17712048e328SMark Yao component_del(&pdev->dev, &vop_component_ops); 17722048e328SMark Yao 17732048e328SMark Yao return 0; 17742048e328SMark Yao } 17752048e328SMark Yao 17762048e328SMark Yao struct platform_driver vop_platform_driver = { 17772048e328SMark Yao .probe = vop_probe, 17782048e328SMark Yao .remove = vop_remove, 17792048e328SMark Yao .driver = { 17802048e328SMark Yao .name = "rockchip-vop", 17812048e328SMark Yao .owner = THIS_MODULE, 17822048e328SMark Yao .of_match_table = of_match_ptr(vop_driver_dt_match), 17832048e328SMark Yao }, 17842048e328SMark Yao }; 17852048e328SMark Yao 17862048e328SMark Yao module_platform_driver(vop_platform_driver); 17872048e328SMark Yao 17882048e328SMark Yao MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>"); 17892048e328SMark Yao MODULE_DESCRIPTION("ROCKCHIP VOP Driver"); 17902048e328SMark Yao MODULE_LICENSE("GPL v2"); 1791