19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22048e328SMark Yao /* 32048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 42048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 52048e328SMark Yao */ 62048e328SMark Yao 7c2156ccdSSam Ravnborg #include <linux/clk.h> 8c2156ccdSSam Ravnborg #include <linux/component.h> 9c2156ccdSSam Ravnborg #include <linux/delay.h> 10c2156ccdSSam Ravnborg #include <linux/iopoll.h> 11c2156ccdSSam Ravnborg #include <linux/kernel.h> 12c2156ccdSSam Ravnborg #include <linux/module.h> 13c2156ccdSSam Ravnborg #include <linux/of.h> 14c2156ccdSSam Ravnborg #include <linux/of_device.h> 15c2156ccdSSam Ravnborg #include <linux/overflow.h> 16c2156ccdSSam Ravnborg #include <linux/platform_device.h> 17c2156ccdSSam Ravnborg #include <linux/pm_runtime.h> 18c2156ccdSSam Ravnborg #include <linux/reset.h> 19c2156ccdSSam Ravnborg 202048e328SMark Yao #include <drm/drm.h> 2163ebb9faSMark Yao #include <drm/drm_atomic.h> 2215609559SEnric Balletbo i Serra #include <drm/drm_atomic_uapi.h> 23*90bb087fSVille Syrjälä #include <drm/drm_blend.h> 242048e328SMark Yao #include <drm/drm_crtc.h> 2547a7eb45STomasz Figa #include <drm/drm_flip_work.h> 26c2156ccdSSam Ravnborg #include <drm/drm_fourcc.h> 27720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h> 28820c1707SThomas Zimmermann #include <drm/drm_gem_atomic_helper.h> 2963d5e06aSHeiko Stuebner #include <drm/drm_gem_framebuffer_helper.h> 302048e328SMark Yao #include <drm/drm_plane_helper.h> 31fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 326c836d96SSean Paul #include <drm/drm_self_refresh_helper.h> 33c2156ccdSSam Ravnborg #include <drm/drm_vblank.h> 34c2156ccdSSam Ravnborg 356cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 363190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 376cca3869SSean Paul #endif 382048e328SMark Yao 392048e328SMark Yao #include "rockchip_drm_drv.h" 402048e328SMark Yao #include "rockchip_drm_gem.h" 412048e328SMark Yao #include "rockchip_drm_fb.h" 422048e328SMark Yao #include "rockchip_drm_vop.h" 431f0f0151SSandy Huang #include "rockchip_rgb.h" 442048e328SMark Yao 452996fb75SEzequiel Garcia #define VOP_WIN_SET(vop, win, name, v) \ 469a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 472996fb75SEzequiel Garcia #define VOP_SCL_SET(vop, win, name, v) \ 489a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 492996fb75SEzequiel Garcia #define VOP_SCL_SET_EXT(vop, win, name, v) \ 509a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 519a61c54bSMark yao win->base, ~0, v, #name) 52ac6560dfSMark yao 532996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 541c21aa8fSDaniele Castagna do { \ 551c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 561c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 571c21aa8fSDaniele Castagna } while (0) 581c21aa8fSDaniele Castagna 592996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 601c21aa8fSDaniele Castagna do { \ 611c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 621c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 631c21aa8fSDaniele Castagna } while (0) 641c21aa8fSDaniele Castagna 65ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 669a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 679a61c54bSMark yao 689a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 699a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 70ac6560dfSMark yao 71dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 72dbb3d944SMark Yao do { \ 73c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 74dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 75c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 76dbb3d944SMark Yao reg |= (v) << i; \ 77c7647f86SJohn Keeping mask |= 1 << i; \ 78dbb3d944SMark Yao } \ 79c7647f86SJohn Keeping } \ 80ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 81dbb3d944SMark Yao } while (0) 82dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 83dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 84dbb3d944SMark Yao 852996fb75SEzequiel Garcia #define VOP_WIN_GET(vop, win, name) \ 86cc8f1299SJohn Keeping vop_read_reg(vop, win->base, &win->phy->name) 872048e328SMark Yao 88677e8bbcSDaniele Castagna #define VOP_WIN_HAS_REG(win, name) \ 89677e8bbcSDaniele Castagna (!!(win->phy->name.mask)) 90677e8bbcSDaniele Castagna 912048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 922048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 932048e328SMark Yao 9458badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 9558badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 9658badaa7SKristian H. Kristensen 977707f722SAndrzej Pietrasiewicz #define VOP_AFBC_SET(vop, name, v) \ 987707f722SAndrzej Pietrasiewicz do { \ 997707f722SAndrzej Pietrasiewicz if ((vop)->data->afbc) \ 1007707f722SAndrzej Pietrasiewicz vop_reg_set((vop), &(vop)->data->afbc->name, \ 1017707f722SAndrzej Pietrasiewicz 0, ~0, v, #name); \ 1027707f722SAndrzej Pietrasiewicz } while (0) 1037707f722SAndrzej Pietrasiewicz 1042048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 1052048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 1062048e328SMark Yao 1077707f722SAndrzej Pietrasiewicz #define AFBC_FMT_RGB565 0x0 1087707f722SAndrzej Pietrasiewicz #define AFBC_FMT_U8U8U8U8 0x5 1097707f722SAndrzej Pietrasiewicz #define AFBC_FMT_U8U8U8 0x4 1107707f722SAndrzej Pietrasiewicz 1117707f722SAndrzej Pietrasiewicz #define AFBC_TILE_16x16 BIT(4) 1127707f722SAndrzej Pietrasiewicz 1131c21aa8fSDaniele Castagna /* 1141c21aa8fSDaniele Castagna * The coefficients of the following matrix are all fixed points. 1151c21aa8fSDaniele Castagna * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 1161c21aa8fSDaniele Castagna * They are all represented in two's complement. 1171c21aa8fSDaniele Castagna */ 1181c21aa8fSDaniele Castagna static const uint32_t bt601_yuv2rgb[] = { 1191c21aa8fSDaniele Castagna 0x4A8, 0x0, 0x662, 1201c21aa8fSDaniele Castagna 0x4A8, 0x1E6F, 0x1CBF, 1211c21aa8fSDaniele Castagna 0x4A8, 0x812, 0x0, 1221c21aa8fSDaniele Castagna 0x321168, 0x0877CF, 0x2EB127 1231c21aa8fSDaniele Castagna }; 1241c21aa8fSDaniele Castagna 12547a7eb45STomasz Figa enum vop_pending { 12647a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 12747a7eb45STomasz Figa }; 12847a7eb45STomasz Figa 1292048e328SMark Yao struct vop_win { 1302048e328SMark Yao struct drm_plane base; 1312048e328SMark Yao const struct vop_win_data *data; 1321c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *yuv2yuv_data; 1332048e328SMark Yao struct vop *vop; 1342048e328SMark Yao }; 1352048e328SMark Yao 1361f0f0151SSandy Huang struct rockchip_rgb; 1372048e328SMark Yao struct vop { 1382048e328SMark Yao struct drm_crtc crtc; 1392048e328SMark Yao struct device *dev; 1402048e328SMark Yao struct drm_device *drm_dev; 14131e980c5SMark Yao bool is_enabled; 1422048e328SMark Yao 1431067219bSMark Yao struct completion dsp_hold_completion; 144bed030a4SSean Paul unsigned int win_enabled; 1454f9d39a7SDaniel Vetter 1464f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 14763ebb9faSMark Yao struct drm_pending_vblank_event *event; 1482048e328SMark Yao 14947a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 15047a7eb45STomasz Figa unsigned long pending; 15147a7eb45STomasz Figa 15269c34e41SYakir Yang struct completion line_flag_completion; 15369c34e41SYakir Yang 1542048e328SMark Yao const struct vop_data *data; 1552048e328SMark Yao 1562048e328SMark Yao uint32_t *regsbak; 1572048e328SMark Yao void __iomem *regs; 158b23ab6acSEzequiel Garcia void __iomem *lut_regs; 1592048e328SMark Yao 1602048e328SMark Yao /* physical map length of vop register */ 1612048e328SMark Yao uint32_t len; 1622048e328SMark Yao 1632048e328SMark Yao /* one time only one process allowed to config the register */ 1642048e328SMark Yao spinlock_t reg_lock; 1652048e328SMark Yao /* lock vop irq reg */ 1662048e328SMark Yao spinlock_t irq_lock; 167e334d48bSzain wang /* protects crtc enable/disable */ 168e334d48bSzain wang struct mutex vop_lock; 1692048e328SMark Yao 1702048e328SMark Yao unsigned int irq; 1712048e328SMark Yao 1722048e328SMark Yao /* vop AHP clk */ 1732048e328SMark Yao struct clk *hclk; 1742048e328SMark Yao /* vop dclk */ 1752048e328SMark Yao struct clk *dclk; 1762048e328SMark Yao /* vop share memory frequency */ 1772048e328SMark Yao struct clk *aclk; 1782048e328SMark Yao 1792048e328SMark Yao /* vop dclk reset */ 1802048e328SMark Yao struct reset_control *dclk_rst; 1812048e328SMark Yao 1821f0f0151SSandy Huang /* optional internal rgb encoder */ 1831f0f0151SSandy Huang struct rockchip_rgb *rgb; 1841f0f0151SSandy Huang 1852048e328SMark Yao struct vop_win win[]; 1862048e328SMark Yao }; 1872048e328SMark Yao 1882048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1892048e328SMark Yao { 1902048e328SMark Yao writel(v, vop->regs + offset); 1912048e328SMark Yao vop->regsbak[offset >> 2] = v; 1922048e328SMark Yao } 1932048e328SMark Yao 1942048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1952048e328SMark Yao { 1962048e328SMark Yao return readl(vop->regs + offset); 1972048e328SMark Yao } 1982048e328SMark Yao 1992048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 2002048e328SMark Yao const struct vop_reg *reg) 2012048e328SMark Yao { 2022048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 2032048e328SMark Yao } 2042048e328SMark Yao 2059a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 2069a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 2079a61c54bSMark yao const char *reg_name) 2082048e328SMark Yao { 2099a61c54bSMark yao int offset, mask, shift; 210d49463ecSMark Yao 2119a61c54bSMark yao if (!reg || !reg->mask) { 212d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 2139a61c54bSMark yao return; 2149a61c54bSMark yao } 2159a61c54bSMark yao 2169a61c54bSMark yao offset = reg->offset + _offset; 2179a61c54bSMark yao mask = reg->mask & _mask; 2189a61c54bSMark yao shift = reg->shift; 2199a61c54bSMark yao 2209a61c54bSMark yao if (reg->write_mask) { 221d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 222d49463ecSMark Yao } else { 2232048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 2242048e328SMark Yao 225d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 226d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 2272048e328SMark Yao } 2282048e328SMark Yao 2299a61c54bSMark yao if (reg->relaxed) 230d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 231d49463ecSMark Yao else 232d49463ecSMark Yao writel(v, vop->regs + offset); 2332048e328SMark Yao } 2342048e328SMark Yao 235dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 236dbb3d944SMark Yao const struct vop_reg *reg, int type) 237dbb3d944SMark Yao { 238dbb3d944SMark Yao uint32_t i, ret = 0; 239dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 240dbb3d944SMark Yao 241dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 242dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 243dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 244dbb3d944SMark Yao } 245dbb3d944SMark Yao 246dbb3d944SMark Yao return ret; 247dbb3d944SMark Yao } 248dbb3d944SMark Yao 2490cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2500cf33fe3SMark Yao { 2519a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2520cf33fe3SMark Yao } 2530cf33fe3SMark Yao 25485a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 25585a359f2STomasz Figa { 25685a359f2STomasz Figa switch (format) { 25785a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 25885a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 25985a359f2STomasz Figa case DRM_FORMAT_BGR888: 26085a359f2STomasz Figa case DRM_FORMAT_BGR565: 26185a359f2STomasz Figa return true; 26285a359f2STomasz Figa default: 26385a359f2STomasz Figa return false; 26485a359f2STomasz Figa } 26585a359f2STomasz Figa } 26685a359f2STomasz Figa 2673fa50896SChen-Yu Tsai static bool has_uv_swapped(uint32_t format) 2683fa50896SChen-Yu Tsai { 2693fa50896SChen-Yu Tsai switch (format) { 2703fa50896SChen-Yu Tsai case DRM_FORMAT_NV21: 2713fa50896SChen-Yu Tsai case DRM_FORMAT_NV61: 2723fa50896SChen-Yu Tsai case DRM_FORMAT_NV42: 2733fa50896SChen-Yu Tsai return true; 2743fa50896SChen-Yu Tsai default: 2753fa50896SChen-Yu Tsai return false; 2763fa50896SChen-Yu Tsai } 2773fa50896SChen-Yu Tsai } 2783fa50896SChen-Yu Tsai 2792048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2802048e328SMark Yao { 2812048e328SMark Yao switch (format) { 2822048e328SMark Yao case DRM_FORMAT_XRGB8888: 2832048e328SMark Yao case DRM_FORMAT_ARGB8888: 28485a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 28585a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2862048e328SMark Yao return VOP_FMT_ARGB8888; 2872048e328SMark Yao case DRM_FORMAT_RGB888: 28885a359f2STomasz Figa case DRM_FORMAT_BGR888: 2892048e328SMark Yao return VOP_FMT_RGB888; 2902048e328SMark Yao case DRM_FORMAT_RGB565: 29185a359f2STomasz Figa case DRM_FORMAT_BGR565: 2922048e328SMark Yao return VOP_FMT_RGB565; 2932048e328SMark Yao case DRM_FORMAT_NV12: 2943fa50896SChen-Yu Tsai case DRM_FORMAT_NV21: 2952048e328SMark Yao return VOP_FMT_YUV420SP; 2962048e328SMark Yao case DRM_FORMAT_NV16: 2973fa50896SChen-Yu Tsai case DRM_FORMAT_NV61: 2982048e328SMark Yao return VOP_FMT_YUV422SP; 2992048e328SMark Yao case DRM_FORMAT_NV24: 3003fa50896SChen-Yu Tsai case DRM_FORMAT_NV42: 3012048e328SMark Yao return VOP_FMT_YUV444SP; 3022048e328SMark Yao default: 303ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 3042048e328SMark Yao return -EINVAL; 3052048e328SMark Yao } 3062048e328SMark Yao } 3072048e328SMark Yao 3087707f722SAndrzej Pietrasiewicz static int vop_convert_afbc_format(uint32_t format) 3097707f722SAndrzej Pietrasiewicz { 3107707f722SAndrzej Pietrasiewicz switch (format) { 3117707f722SAndrzej Pietrasiewicz case DRM_FORMAT_XRGB8888: 3127707f722SAndrzej Pietrasiewicz case DRM_FORMAT_ARGB8888: 3137707f722SAndrzej Pietrasiewicz case DRM_FORMAT_XBGR8888: 3147707f722SAndrzej Pietrasiewicz case DRM_FORMAT_ABGR8888: 3157707f722SAndrzej Pietrasiewicz return AFBC_FMT_U8U8U8U8; 3167707f722SAndrzej Pietrasiewicz case DRM_FORMAT_RGB888: 3177707f722SAndrzej Pietrasiewicz case DRM_FORMAT_BGR888: 3187707f722SAndrzej Pietrasiewicz return AFBC_FMT_U8U8U8; 3197707f722SAndrzej Pietrasiewicz case DRM_FORMAT_RGB565: 3207707f722SAndrzej Pietrasiewicz case DRM_FORMAT_BGR565: 3217707f722SAndrzej Pietrasiewicz return AFBC_FMT_RGB565; 3227707f722SAndrzej Pietrasiewicz /* either of the below should not be reachable */ 3237707f722SAndrzej Pietrasiewicz default: 3247707f722SAndrzej Pietrasiewicz DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); 3257707f722SAndrzej Pietrasiewicz return -EINVAL; 3267707f722SAndrzej Pietrasiewicz } 3277707f722SAndrzej Pietrasiewicz 3287707f722SAndrzej Pietrasiewicz return -EINVAL; 3297707f722SAndrzej Pietrasiewicz } 3307707f722SAndrzej Pietrasiewicz 3314c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 3324c156c21SMark Yao uint32_t dst, bool is_horizontal, 3334c156c21SMark Yao int vsu_mode, int *vskiplines) 3344c156c21SMark Yao { 3354c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 3364c156c21SMark Yao 337ce91d373SJeffy Chen if (vskiplines) 338ce91d373SJeffy Chen *vskiplines = 0; 339ce91d373SJeffy Chen 3404c156c21SMark Yao if (is_horizontal) { 3414c156c21SMark Yao if (mode == SCALE_UP) 3424c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3434c156c21SMark Yao else if (mode == SCALE_DOWN) 3444c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3454c156c21SMark Yao } else { 3464c156c21SMark Yao if (mode == SCALE_UP) { 3474c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 3484c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 3494c156c21SMark Yao else 3504c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3514c156c21SMark Yao } else if (mode == SCALE_DOWN) { 3524c156c21SMark Yao if (vskiplines) { 3534c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 3544c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 3554c156c21SMark Yao *vskiplines); 3564c156c21SMark Yao } else { 3574c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3584c156c21SMark Yao } 3594c156c21SMark Yao } 3604c156c21SMark Yao } 3614c156c21SMark Yao 3624c156c21SMark Yao return val; 3634c156c21SMark Yao } 3644c156c21SMark Yao 3654c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3664c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 36745babef0SMaxime Ripard uint32_t dst_h, const struct drm_format_info *info) 3684c156c21SMark Yao { 3694c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3704c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3714c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 372d8bd23d9SAyan Kumar Halder bool is_yuv = false; 373f3e9632cSMaxime Ripard uint16_t cbcr_src_w = src_w / info->hsub; 374f3e9632cSMaxime Ripard uint16_t cbcr_src_h = src_h / info->vsub; 3754c156c21SMark Yao uint16_t vsu_mode; 3764c156c21SMark Yao uint16_t lb_mode; 3774c156c21SMark Yao uint32_t val; 378ce91d373SJeffy Chen int vskiplines; 3794c156c21SMark Yao 380d8bd23d9SAyan Kumar Halder if (info->is_yuv) 381d8bd23d9SAyan Kumar Halder is_yuv = true; 382d8bd23d9SAyan Kumar Halder 3834c156c21SMark Yao if (dst_w > 3840) { 384ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3854c156c21SMark Yao return; 3864c156c21SMark Yao } 3874c156c21SMark Yao 3881194fffbSMark Yao if (!win->phy->scl->ext) { 3891194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3901194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3911194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3921194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3931194fffbSMark Yao if (is_yuv) { 3941194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 395ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3961194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 397ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3981194fffbSMark Yao } 3991194fffbSMark Yao return; 4001194fffbSMark Yao } 4011194fffbSMark Yao 4024c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 4034c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 4044c156c21SMark Yao 4054c156c21SMark Yao if (is_yuv) { 4064c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 4074c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 4084c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 4094c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 4104c156c21SMark Yao else 4114c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 4124c156c21SMark Yao } else { 4134c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 4144c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 4154c156c21SMark Yao else 4164c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 4174c156c21SMark Yao } 4184c156c21SMark Yao 4191194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 4204c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 4214c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 422ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 4234c156c21SMark Yao return; 4244c156c21SMark Yao } 4254c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 426ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 4274c156c21SMark Yao return; 4284c156c21SMark Yao } 4294c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 4304c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 4314c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 4324c156c21SMark Yao } else { 4334c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 4344c156c21SMark Yao } 4354c156c21SMark Yao 4364c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 4374c156c21SMark Yao true, 0, NULL); 4384c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 4394c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 4404c156c21SMark Yao false, vsu_mode, &vskiplines); 4414c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 4424c156c21SMark Yao 4431194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 4441194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 4454c156c21SMark Yao 4461194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 4471194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 4481194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 4491194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 4501194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 4514c156c21SMark Yao if (is_yuv) { 4524c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 4534c156c21SMark Yao dst_w, true, 0, NULL); 4544c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 4554c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 4564c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 4574c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 4584c156c21SMark Yao 4591194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 4601194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4611194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4621194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4631194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4641194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4651194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4664c156c21SMark Yao } 4674c156c21SMark Yao } 4684c156c21SMark Yao 4691067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4701067219bSMark Yao { 4711067219bSMark Yao unsigned long flags; 4721067219bSMark Yao 4731067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4741067219bSMark Yao return; 4751067219bSMark Yao 4761067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4771067219bSMark Yao 478fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 479dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4801067219bSMark Yao 4811067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4821067219bSMark Yao } 4831067219bSMark Yao 4841067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4851067219bSMark Yao { 4861067219bSMark Yao unsigned long flags; 4871067219bSMark Yao 4881067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4891067219bSMark Yao return; 4901067219bSMark Yao 4911067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4921067219bSMark Yao 493dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4941067219bSMark Yao 4951067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4961067219bSMark Yao } 4971067219bSMark Yao 49869c34e41SYakir Yang /* 49969c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 50069c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 50169c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 50269c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 50369c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 50469c34e41SYakir Yang * 50569c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 50669c34e41SYakir Yang * Interrupts 50769c34e41SYakir Yang * LINE_FLAG -------------------------------+ 50869c34e41SYakir Yang * FRAME_SYNC ----+ | 50969c34e41SYakir Yang * | | 51069c34e41SYakir Yang * v v 51169c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 51269c34e41SYakir Yang * ^ ^ ^ ^ 51369c34e41SYakir Yang * | | | | 51469c34e41SYakir Yang * | | | | 51569c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 51669c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 51769c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 51869c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 51969c34e41SYakir Yang */ 52069c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 52169c34e41SYakir Yang { 52269c34e41SYakir Yang uint32_t line_flag_irq; 52369c34e41SYakir Yang unsigned long flags; 52469c34e41SYakir Yang 52569c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 52669c34e41SYakir Yang 52769c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 52869c34e41SYakir Yang 52969c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 53069c34e41SYakir Yang 53169c34e41SYakir Yang return !!line_flag_irq; 53269c34e41SYakir Yang } 53369c34e41SYakir Yang 534459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 53569c34e41SYakir Yang { 53669c34e41SYakir Yang unsigned long flags; 53769c34e41SYakir Yang 53869c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 53969c34e41SYakir Yang return; 54069c34e41SYakir Yang 54169c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 54269c34e41SYakir Yang 543fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 54469c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 54569c34e41SYakir Yang 54669c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 54769c34e41SYakir Yang } 54869c34e41SYakir Yang 54969c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 55069c34e41SYakir Yang { 55169c34e41SYakir Yang unsigned long flags; 55269c34e41SYakir Yang 55369c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 55469c34e41SYakir Yang return; 55569c34e41SYakir Yang 55669c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 55769c34e41SYakir Yang 55869c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 55969c34e41SYakir Yang 56069c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 56169c34e41SYakir Yang } 56269c34e41SYakir Yang 563e2810a71SHeiko Stuebner static int vop_core_clks_enable(struct vop *vop) 564e2810a71SHeiko Stuebner { 565e2810a71SHeiko Stuebner int ret; 566e2810a71SHeiko Stuebner 567e2810a71SHeiko Stuebner ret = clk_enable(vop->hclk); 568e2810a71SHeiko Stuebner if (ret < 0) 569e2810a71SHeiko Stuebner return ret; 570e2810a71SHeiko Stuebner 571e2810a71SHeiko Stuebner ret = clk_enable(vop->aclk); 572e2810a71SHeiko Stuebner if (ret < 0) 573e2810a71SHeiko Stuebner goto err_disable_hclk; 574e2810a71SHeiko Stuebner 575e2810a71SHeiko Stuebner return 0; 576e2810a71SHeiko Stuebner 577e2810a71SHeiko Stuebner err_disable_hclk: 578e2810a71SHeiko Stuebner clk_disable(vop->hclk); 579e2810a71SHeiko Stuebner return ret; 580e2810a71SHeiko Stuebner } 581e2810a71SHeiko Stuebner 582e2810a71SHeiko Stuebner static void vop_core_clks_disable(struct vop *vop) 583e2810a71SHeiko Stuebner { 584e2810a71SHeiko Stuebner clk_disable(vop->aclk); 585e2810a71SHeiko Stuebner clk_disable(vop->hclk); 586e2810a71SHeiko Stuebner } 587e2810a71SHeiko Stuebner 5882b60e11dSSean Paul static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 589e9abc611SJonas Karlman { 5902b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 5912b60e11dSSean Paul 592e9abc611SJonas Karlman if (win->phy->scl && win->phy->scl->ext) { 593e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 594e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 595e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 596e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 597e9abc611SJonas Karlman } 598e9abc611SJonas Karlman 599e9abc611SJonas Karlman VOP_WIN_SET(vop, win, enable, 0); 600bed030a4SSean Paul vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 601e9abc611SJonas Karlman } 602e9abc611SJonas Karlman 6036c836d96SSean Paul static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 6042048e328SMark Yao { 6052048e328SMark Yao struct vop *vop = to_vop(crtc); 60664d77564SMark yao int ret, i; 6072048e328SMark Yao 6085d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 6095d82d1a7SMark Yao if (ret < 0) { 610d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 6115e570373SJeffy Chen return ret; 6125d82d1a7SMark Yao } 6135d82d1a7SMark Yao 614e2810a71SHeiko Stuebner ret = vop_core_clks_enable(vop); 61539a9ad8fSSean Paul if (WARN_ON(ret < 0)) 61639a9ad8fSSean Paul goto err_put_pm_runtime; 6172048e328SMark Yao 6182048e328SMark Yao ret = clk_enable(vop->dclk); 61939a9ad8fSSean Paul if (WARN_ON(ret < 0)) 620e2810a71SHeiko Stuebner goto err_disable_core; 6212048e328SMark Yao 6222048e328SMark Yao /* 6232048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 6242048e328SMark Yao * automatically with this master device via common driver code. 6252048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 6262048e328SMark Yao * mapping. 6272048e328SMark Yao */ 6282048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 6292048e328SMark Yao if (ret) { 630d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 631d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 632e2810a71SHeiko Stuebner goto err_disable_dclk; 6332048e328SMark Yao } 6342048e328SMark Yao 63576f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 63676f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 63776f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 63876f1416eSMarc Zyngier 63964d77564SMark yao /* 64064d77564SMark yao * We need to make sure that all windows are disabled before we 64164d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 64264d77564SMark yao * buffer later. 6436c836d96SSean Paul * 6446c836d96SSean Paul * In the case of enable-after-PSR, we don't need to worry about this 6456c836d96SSean Paul * case since the buffer is guaranteed to be valid and disabling the 6466c836d96SSean Paul * window will result in screen glitches on PSR exit. 64764d77564SMark yao */ 6486c836d96SSean Paul if (!old_state || !old_state->self_refresh_active) { 64964d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 65064d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 65164d77564SMark yao 6522b60e11dSSean Paul vop_win_disable(vop, vop_win); 65364d77564SMark yao } 6546c836d96SSean Paul } 6557707f722SAndrzej Pietrasiewicz 6567707f722SAndrzej Pietrasiewicz if (vop->data->afbc) { 6577707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 6587707f722SAndrzej Pietrasiewicz /* 6597707f722SAndrzej Pietrasiewicz * Disable AFBC and forget there was a vop window with AFBC 6607707f722SAndrzej Pietrasiewicz */ 6617707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, enable, 0); 6627707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc->state); 6637707f722SAndrzej Pietrasiewicz s->enable_afbc = false; 6647707f722SAndrzej Pietrasiewicz } 6657707f722SAndrzej Pietrasiewicz 66617a794d7SChris Zhong vop_cfg_done(vop); 66717a794d7SChris Zhong 6685fa63f07SEmil Velikov spin_unlock(&vop->reg_lock); 6695fa63f07SEmil Velikov 67052ab7891SMark Yao /* 67152ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 67252ab7891SMark Yao */ 67352ab7891SMark Yao vop->is_enabled = true; 67452ab7891SMark Yao 6752048e328SMark Yao spin_lock(&vop->reg_lock); 6762048e328SMark Yao 6779a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6782048e328SMark Yao 6792048e328SMark Yao spin_unlock(&vop->reg_lock); 6802048e328SMark Yao 681b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6822048e328SMark Yao 68339a9ad8fSSean Paul return 0; 6842048e328SMark Yao 6852048e328SMark Yao err_disable_dclk: 6862048e328SMark Yao clk_disable(vop->dclk); 687e2810a71SHeiko Stuebner err_disable_core: 688e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 68939a9ad8fSSean Paul err_put_pm_runtime: 69039a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 69139a9ad8fSSean Paul return ret; 6922048e328SMark Yao } 6932048e328SMark Yao 694bed030a4SSean Paul static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 695bed030a4SSean Paul { 696bed030a4SSean Paul struct vop *vop = to_vop(crtc); 697bed030a4SSean Paul int i; 698bed030a4SSean Paul 699bed030a4SSean Paul spin_lock(&vop->reg_lock); 700bed030a4SSean Paul 701bed030a4SSean Paul for (i = 0; i < vop->data->win_size; i++) { 702bed030a4SSean Paul struct vop_win *vop_win = &vop->win[i]; 703bed030a4SSean Paul const struct vop_win_data *win = vop_win->data; 704bed030a4SSean Paul 705bed030a4SSean Paul VOP_WIN_SET(vop, win, enable, 706bed030a4SSean Paul enabled && (vop->win_enabled & BIT(i))); 707bed030a4SSean Paul } 708bed030a4SSean Paul vop_cfg_done(vop); 709bed030a4SSean Paul 710bed030a4SSean Paul spin_unlock(&vop->reg_lock); 711bed030a4SSean Paul } 712bed030a4SSean Paul 71364581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 714351f950dSMaxime Ripard struct drm_atomic_state *state) 7152048e328SMark Yao { 7162048e328SMark Yao struct vop *vop = to_vop(crtc); 7172048e328SMark Yao 718893b6cadSDaniel Vetter WARN_ON(vop->event); 719893b6cadSDaniel Vetter 720bed030a4SSean Paul if (crtc->state->self_refresh_active) 721bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, false); 722bed030a4SSean Paul 723e334d48bSzain wang mutex_lock(&vop->vop_lock); 7246c836d96SSean Paul 725b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 7262048e328SMark Yao 727bed030a4SSean Paul if (crtc->state->self_refresh_active) 728bed030a4SSean Paul goto out; 729bed030a4SSean Paul 7302048e328SMark Yao /* 7311067219bSMark Yao * Vop standby will take effect at end of current frame, 7321067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 7331067219bSMark Yao * 7341067219bSMark Yao * we must wait standby complete when we want to disable aclk, 7351067219bSMark Yao * if not, memory bus maybe dead. 7362048e328SMark Yao */ 7371067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 7381067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 7391067219bSMark Yao 7402048e328SMark Yao spin_lock(&vop->reg_lock); 7412048e328SMark Yao 7429a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 7432048e328SMark Yao 7442048e328SMark Yao spin_unlock(&vop->reg_lock); 74552ab7891SMark Yao 746085af7d2SBrian Norris if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 747085af7d2SBrian Norris msecs_to_jiffies(200))) 748085af7d2SBrian Norris WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 7492048e328SMark Yao 7501067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 7511067219bSMark Yao 7521067219bSMark Yao vop->is_enabled = false; 7531067219bSMark Yao 7541067219bSMark Yao /* 7551067219bSMark Yao * vop standby complete, so iommu detach is safe. 7561067219bSMark Yao */ 7572048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 7582048e328SMark Yao 7591067219bSMark Yao clk_disable(vop->dclk); 760e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 7615d82d1a7SMark Yao pm_runtime_put(vop->dev); 762bed030a4SSean Paul 763bed030a4SSean Paul out: 764e334d48bSzain wang mutex_unlock(&vop->vop_lock); 765893b6cadSDaniel Vetter 766893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 767893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 768893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 769893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 770893b6cadSDaniel Vetter 771893b6cadSDaniel Vetter crtc->state->event = NULL; 772893b6cadSDaniel Vetter } 7732048e328SMark Yao } 7742048e328SMark Yao 77563ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 7762048e328SMark Yao { 77763ebb9faSMark Yao drm_plane_cleanup(plane); 7782048e328SMark Yao } 7792048e328SMark Yao 7807707f722SAndrzej Pietrasiewicz static inline bool rockchip_afbc(u64 modifier) 7817707f722SAndrzej Pietrasiewicz { 7827707f722SAndrzej Pietrasiewicz return modifier == ROCKCHIP_AFBC_MOD; 7837707f722SAndrzej Pietrasiewicz } 7847707f722SAndrzej Pietrasiewicz 7857707f722SAndrzej Pietrasiewicz static bool rockchip_mod_supported(struct drm_plane *plane, 7867707f722SAndrzej Pietrasiewicz u32 format, u64 modifier) 7877707f722SAndrzej Pietrasiewicz { 7887707f722SAndrzej Pietrasiewicz if (modifier == DRM_FORMAT_MOD_LINEAR) 7897707f722SAndrzej Pietrasiewicz return true; 7907707f722SAndrzej Pietrasiewicz 7917707f722SAndrzej Pietrasiewicz if (!rockchip_afbc(modifier)) { 7926472e4e2SColin Ian King DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 7937707f722SAndrzej Pietrasiewicz 7947707f722SAndrzej Pietrasiewicz return false; 7957707f722SAndrzej Pietrasiewicz } 7967707f722SAndrzej Pietrasiewicz 7977707f722SAndrzej Pietrasiewicz return vop_convert_afbc_format(format) >= 0; 7987707f722SAndrzej Pietrasiewicz } 7997707f722SAndrzej Pietrasiewicz 80063ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 8017c11b99aSMaxime Ripard struct drm_atomic_state *state) 8022048e328SMark Yao { 8037c11b99aSMaxime Ripard struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 8047c11b99aSMaxime Ripard plane); 805ba5c1649SMaxime Ripard struct drm_crtc *crtc = new_plane_state->crtc; 80692915da6SJohn Keeping struct drm_crtc_state *crtc_state; 807ba5c1649SMaxime Ripard struct drm_framebuffer *fb = new_plane_state->fb; 8082048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 8092048e328SMark Yao const struct vop_win_data *win = vop_win->data; 8102048e328SMark Yao int ret; 8114c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 8124c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 8134c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 8144c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 8152048e328SMark Yao 816fd907adeSDaniel Vetter if (!crtc || WARN_ON(!fb)) 817d47a7246STomasz Figa return 0; 81892915da6SJohn Keeping 819dec92020SMaxime Ripard crtc_state = drm_atomic_get_existing_crtc_state(state, 820ba5c1649SMaxime Ripard crtc); 82192915da6SJohn Keeping if (WARN_ON(!crtc_state)) 82292915da6SJohn Keeping return -EINVAL; 82392915da6SJohn Keeping 824ba5c1649SMaxime Ripard ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 825f9b96be0SVille Syrjälä min_scale, max_scale, 826f9b96be0SVille Syrjälä true, true); 8272048e328SMark Yao if (ret) 8282048e328SMark Yao return ret; 8292048e328SMark Yao 830ba5c1649SMaxime Ripard if (!new_plane_state->visible) 831d47a7246STomasz Figa return 0; 8322048e328SMark Yao 833438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 834d47a7246STomasz Figa if (ret < 0) 835d47a7246STomasz Figa return ret; 83684c7f8caSMark Yao 83784c7f8caSMark Yao /* 83884c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 83984c7f8caSMark Yao * need align with 2 pixel. 84084c7f8caSMark Yao */ 841ba5c1649SMaxime Ripard if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 842d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 84363ebb9faSMark Yao return -EINVAL; 844d415fb87SMark yao } 84563ebb9faSMark Yao 846ba5c1649SMaxime Ripard if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 847677e8bbcSDaniele Castagna DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 848677e8bbcSDaniele Castagna return -EINVAL; 849677e8bbcSDaniele Castagna } 850677e8bbcSDaniele Castagna 8517707f722SAndrzej Pietrasiewicz if (rockchip_afbc(fb->modifier)) { 8527707f722SAndrzej Pietrasiewicz struct vop *vop = to_vop(crtc); 8537707f722SAndrzej Pietrasiewicz 8547707f722SAndrzej Pietrasiewicz if (!vop->data->afbc) { 8557707f722SAndrzej Pietrasiewicz DRM_ERROR("vop does not support AFBC\n"); 8567707f722SAndrzej Pietrasiewicz return -EINVAL; 8577707f722SAndrzej Pietrasiewicz } 8587707f722SAndrzej Pietrasiewicz 8597707f722SAndrzej Pietrasiewicz ret = vop_convert_afbc_format(fb->format->format); 8607707f722SAndrzej Pietrasiewicz if (ret < 0) 8617707f722SAndrzej Pietrasiewicz return ret; 8627707f722SAndrzej Pietrasiewicz 863ba5c1649SMaxime Ripard if (new_plane_state->src.x1 || new_plane_state->src.y1) { 864ba5c1649SMaxime Ripard DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", 865ba5c1649SMaxime Ripard new_plane_state->src.x1, 866ba5c1649SMaxime Ripard new_plane_state->src.y1, fb->offsets[0]); 8677707f722SAndrzej Pietrasiewicz return -EINVAL; 8687707f722SAndrzej Pietrasiewicz } 8697707f722SAndrzej Pietrasiewicz 870ba5c1649SMaxime Ripard if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 8717707f722SAndrzej Pietrasiewicz DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 872ba5c1649SMaxime Ripard new_plane_state->rotation); 8737707f722SAndrzej Pietrasiewicz return -EINVAL; 8747707f722SAndrzej Pietrasiewicz } 8757707f722SAndrzej Pietrasiewicz } 8767707f722SAndrzej Pietrasiewicz 87763ebb9faSMark Yao return 0; 87884c7f8caSMark Yao } 87984c7f8caSMark Yao 88063ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 881977697e2SMaxime Ripard struct drm_atomic_state *state) 88263ebb9faSMark Yao { 883977697e2SMaxime Ripard struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 884977697e2SMaxime Ripard plane); 88563ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 88663ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 8872048e328SMark Yao 88863ebb9faSMark Yao if (!old_state->crtc) 88963ebb9faSMark Yao return; 8902048e328SMark Yao 89163ebb9faSMark Yao spin_lock(&vop->reg_lock); 8922048e328SMark Yao 8932b60e11dSSean Paul vop_win_disable(vop, vop_win); 8942048e328SMark Yao 89563ebb9faSMark Yao spin_unlock(&vop->reg_lock); 89663ebb9faSMark Yao } 89763ebb9faSMark Yao 89863ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 899977697e2SMaxime Ripard struct drm_atomic_state *state) 90063ebb9faSMark Yao { 90137418bf1SMaxime Ripard struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 90237418bf1SMaxime Ripard plane); 90341016fe1SMaxime Ripard struct drm_crtc *crtc = new_state->crtc; 90463ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 90563ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 9061c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 90741016fe1SMaxime Ripard struct vop *vop = to_vop(new_state->crtc); 90841016fe1SMaxime Ripard struct drm_framebuffer *fb = new_state->fb; 90963ebb9faSMark Yao unsigned int actual_w, actual_h; 91063ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 91163ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 91241016fe1SMaxime Ripard struct drm_rect *src = &new_state->src; 91341016fe1SMaxime Ripard struct drm_rect *dest = &new_state->dst; 91463ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 91563ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 91663ebb9faSMark Yao unsigned long offset; 91763ebb9faSMark Yao dma_addr_t dma_addr; 91863ebb9faSMark Yao uint32_t val; 9193fa50896SChen-Yu Tsai bool rb_swap, uv_swap; 92058badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 921d47a7246STomasz Figa int format; 9221c21aa8fSDaniele Castagna int is_yuv = fb->format->is_yuv; 9231c21aa8fSDaniele Castagna int i; 92463ebb9faSMark Yao 92563ebb9faSMark Yao /* 92663ebb9faSMark Yao * can't update plane when vop is disabled. 92763ebb9faSMark Yao */ 9284f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 92963ebb9faSMark Yao return; 93063ebb9faSMark Yao 93163ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 93263ebb9faSMark Yao return; 93363ebb9faSMark Yao 93441016fe1SMaxime Ripard if (!new_state->visible) { 935977697e2SMaxime Ripard vop_plane_atomic_disable(plane, state); 93663ebb9faSMark Yao return; 93763ebb9faSMark Yao } 93863ebb9faSMark Yao 939957428f9SDaniel Stone obj = fb->obj[0]; 94063ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 94163ebb9faSMark Yao 94263ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 94363ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 94463ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 94563ebb9faSMark Yao 94663ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 94763ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 94863ebb9faSMark Yao 94963ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 95063ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 95163ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 95263ebb9faSMark Yao 953353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 95463ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 955d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 956d47a7246STomasz Figa 957677e8bbcSDaniele Castagna /* 958677e8bbcSDaniele Castagna * For y-mirroring we need to move address 959677e8bbcSDaniele Castagna * to the beginning of the last line. 960677e8bbcSDaniele Castagna */ 96141016fe1SMaxime Ripard if (new_state->rotation & DRM_MODE_REFLECT_Y) 962677e8bbcSDaniele Castagna dma_addr += (actual_h - 1) * fb->pitches[0]; 963677e8bbcSDaniele Castagna 964438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 96563ebb9faSMark Yao 96663ebb9faSMark Yao spin_lock(&vop->reg_lock); 96763ebb9faSMark Yao 9687707f722SAndrzej Pietrasiewicz if (rockchip_afbc(fb->modifier)) { 9697707f722SAndrzej Pietrasiewicz int afbc_format = vop_convert_afbc_format(fb->format->format); 9707707f722SAndrzej Pietrasiewicz 9717707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 9727707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, hreg_block_split, 0); 9737707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 9747707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 9757707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, pic_size, act_info); 9767707f722SAndrzej Pietrasiewicz } 9777707f722SAndrzej Pietrasiewicz 978d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 979da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 980d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 9811c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 982677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, y_mir_en, 98341016fe1SMaxime Ripard (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 984677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, x_mir_en, 98541016fe1SMaxime Ripard (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 9861c21aa8fSDaniele Castagna 9871c21aa8fSDaniele Castagna if (is_yuv) { 988f3e9632cSMaxime Ripard int hsub = fb->format->hsub; 989f3e9632cSMaxime Ripard int vsub = fb->format->vsub; 990353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 99184c7f8caSMark Yao 992957428f9SDaniel Stone uv_obj = fb->obj[1]; 99384c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 99484c7f8caSMark Yao 99563ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 99663ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 99784c7f8caSMark Yao 99863ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 999da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 100063ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 10011c21aa8fSDaniele Castagna 10021c21aa8fSDaniele Castagna for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 10031c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 10041c21aa8fSDaniele Castagna win_yuv2yuv, 10051c21aa8fSDaniele Castagna y2r_coefficients[i], 10061c21aa8fSDaniele Castagna bt601_yuv2rgb[i]); 10071c21aa8fSDaniele Castagna } 10083fa50896SChen-Yu Tsai 10093fa50896SChen-Yu Tsai uv_swap = has_uv_swapped(fb->format->format); 10103fa50896SChen-Yu Tsai VOP_WIN_SET(vop, win, uv_swap, uv_swap); 101184c7f8caSMark Yao } 10124c156c21SMark Yao 10134c156c21SMark Yao if (win->phy->scl) 10144c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 101563ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 101645babef0SMaxime Ripard fb->format); 10174c156c21SMark Yao 101863ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 101963ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 102063ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 10214c156c21SMark Yao 1022438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 102385a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 10242048e328SMark Yao 102558badaa7SKristian H. Kristensen /* 102658badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 102758badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 102858badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 102958badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 103058badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 103158badaa7SKristian H. Kristensen */ 103258badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 10332048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 10342048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 10352048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 10362048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 10372048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 10382048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 10392048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 10402048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 10412aae8ed1SPaul Kocialkowski 10422aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 10432aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 10442aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_en, 1); 10452048e328SMark Yao } else { 10462048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1047046e0db9SAlex Bee VOP_WIN_SET(vop, win, alpha_en, 0); 10482048e328SMark Yao } 10492048e328SMark Yao 10502048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 1051bed030a4SSean Paul vop->win_enabled |= BIT(win_index); 10522048e328SMark Yao spin_unlock(&vop->reg_lock); 10532048e328SMark Yao } 10542048e328SMark Yao 105515609559SEnric Balletbo i Serra static int vop_plane_atomic_async_check(struct drm_plane *plane, 10565ddb0bd4SMaxime Ripard struct drm_atomic_state *state) 105715609559SEnric Balletbo i Serra { 10585ddb0bd4SMaxime Ripard struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 10595ddb0bd4SMaxime Ripard plane); 106015609559SEnric Balletbo i Serra struct vop_win *vop_win = to_vop_win(plane); 106115609559SEnric Balletbo i Serra const struct vop_win_data *win = vop_win->data; 106215609559SEnric Balletbo i Serra int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 106315609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 106415609559SEnric Balletbo i Serra int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 106515609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 106615609559SEnric Balletbo i Serra struct drm_crtc_state *crtc_state; 106715609559SEnric Balletbo i Serra 10685ddb0bd4SMaxime Ripard if (plane != new_plane_state->crtc->cursor) 106915609559SEnric Balletbo i Serra return -EINVAL; 107015609559SEnric Balletbo i Serra 107115609559SEnric Balletbo i Serra if (!plane->state) 107215609559SEnric Balletbo i Serra return -EINVAL; 107315609559SEnric Balletbo i Serra 107415609559SEnric Balletbo i Serra if (!plane->state->fb) 107515609559SEnric Balletbo i Serra return -EINVAL; 107615609559SEnric Balletbo i Serra 10775ddb0bd4SMaxime Ripard if (state) 10785ddb0bd4SMaxime Ripard crtc_state = drm_atomic_get_existing_crtc_state(state, 10795ddb0bd4SMaxime Ripard new_plane_state->crtc); 108015609559SEnric Balletbo i Serra else /* Special case for asynchronous cursor updates. */ 108115609559SEnric Balletbo i Serra crtc_state = plane->crtc->state; 108215609559SEnric Balletbo i Serra 108315609559SEnric Balletbo i Serra return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 108415609559SEnric Balletbo i Serra min_scale, max_scale, 108515609559SEnric Balletbo i Serra true, true); 108615609559SEnric Balletbo i Serra } 108715609559SEnric Balletbo i Serra 108815609559SEnric Balletbo i Serra static void vop_plane_atomic_async_update(struct drm_plane *plane, 10895ddb0bd4SMaxime Ripard struct drm_atomic_state *state) 109015609559SEnric Balletbo i Serra { 10915ddb0bd4SMaxime Ripard struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 10925ddb0bd4SMaxime Ripard plane); 109315609559SEnric Balletbo i Serra struct vop *vop = to_vop(plane->state->crtc); 1094d985a353SHelen Koike struct drm_framebuffer *old_fb = plane->state->fb; 109515609559SEnric Balletbo i Serra 1096d985a353SHelen Koike plane->state->crtc_x = new_state->crtc_x; 1097d985a353SHelen Koike plane->state->crtc_y = new_state->crtc_y; 1098d985a353SHelen Koike plane->state->crtc_h = new_state->crtc_h; 1099d985a353SHelen Koike plane->state->crtc_w = new_state->crtc_w; 1100d985a353SHelen Koike plane->state->src_x = new_state->src_x; 1101d985a353SHelen Koike plane->state->src_y = new_state->src_y; 1102d985a353SHelen Koike plane->state->src_h = new_state->src_h; 1103d985a353SHelen Koike plane->state->src_w = new_state->src_w; 1104d985a353SHelen Koike swap(plane->state->fb, new_state->fb); 110515609559SEnric Balletbo i Serra 110615609559SEnric Balletbo i Serra if (vop->is_enabled) { 1107977697e2SMaxime Ripard vop_plane_atomic_update(plane, state); 110815609559SEnric Balletbo i Serra spin_lock(&vop->reg_lock); 110915609559SEnric Balletbo i Serra vop_cfg_done(vop); 111015609559SEnric Balletbo i Serra spin_unlock(&vop->reg_lock); 111115609559SEnric Balletbo i Serra 1112d985a353SHelen Koike /* 1113d985a353SHelen Koike * A scanout can still be occurring, so we can't drop the 1114d985a353SHelen Koike * reference to the old framebuffer. To solve this we get a 1115d985a353SHelen Koike * reference to old_fb and set a worker to release it later. 1116d985a353SHelen Koike * FIXME: if we perform 500 async_update calls before the 1117d985a353SHelen Koike * vblank, then we can have 500 different framebuffers waiting 1118d985a353SHelen Koike * to be released. 1119d985a353SHelen Koike */ 1120d985a353SHelen Koike if (old_fb && plane->state->fb != old_fb) { 1121d985a353SHelen Koike drm_framebuffer_get(old_fb); 1122d985a353SHelen Koike WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1123d985a353SHelen Koike drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1124d985a353SHelen Koike set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1125d985a353SHelen Koike } 1126d985a353SHelen Koike } 112715609559SEnric Balletbo i Serra } 112815609559SEnric Balletbo i Serra 112963ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 113063ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 113163ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 113263ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 113315609559SEnric Balletbo i Serra .atomic_async_check = vop_plane_atomic_async_check, 113415609559SEnric Balletbo i Serra .atomic_async_update = vop_plane_atomic_async_update, 113563ebb9faSMark Yao }; 113663ebb9faSMark Yao 11372048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 113863ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 113963ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 11402048e328SMark Yao .destroy = vop_plane_destroy, 1141d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 1142d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1143d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 11447707f722SAndrzej Pietrasiewicz .format_mod_supported = rockchip_mod_supported, 11452048e328SMark Yao }; 11462048e328SMark Yao 11472048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 11482048e328SMark Yao { 11492048e328SMark Yao struct vop *vop = to_vop(crtc); 11502048e328SMark Yao unsigned long flags; 11512048e328SMark Yao 115263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 11532048e328SMark Yao return -EPERM; 11542048e328SMark Yao 11552048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 11562048e328SMark Yao 1157fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1158dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 11592048e328SMark Yao 11602048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11612048e328SMark Yao 11622048e328SMark Yao return 0; 11632048e328SMark Yao } 11642048e328SMark Yao 11652048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 11662048e328SMark Yao { 11672048e328SMark Yao struct vop *vop = to_vop(crtc); 11682048e328SMark Yao unsigned long flags; 11692048e328SMark Yao 117063ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 11712048e328SMark Yao return; 117231e980c5SMark Yao 11732048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1174dbb3d944SMark Yao 1175dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1176dbb3d944SMark Yao 11772048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11782048e328SMark Yao } 11792048e328SMark Yao 11802048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 11812048e328SMark Yao const struct drm_display_mode *mode, 11822048e328SMark Yao struct drm_display_mode *adjusted_mode) 11832048e328SMark Yao { 1184b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 1185287422a9SDouglas Anderson unsigned long rate; 1186b59b8de3SChris Zhong 1187287422a9SDouglas Anderson /* 1188287422a9SDouglas Anderson * Clock craziness. 1189287422a9SDouglas Anderson * 1190287422a9SDouglas Anderson * Key points: 1191287422a9SDouglas Anderson * 1192287422a9SDouglas Anderson * - DRM works in in kHz. 1193287422a9SDouglas Anderson * - Clock framework works in Hz. 1194287422a9SDouglas Anderson * - Rockchip's clock driver picks the clock rate that is the 1195287422a9SDouglas Anderson * same _OR LOWER_ than the one requested. 1196287422a9SDouglas Anderson * 1197287422a9SDouglas Anderson * Action plan: 1198287422a9SDouglas Anderson * 119964ec4912SChris Morgan * 1. Try to set the exact rate first, and confirm the clock framework 120064ec4912SChris Morgan * can provide it. 1201287422a9SDouglas Anderson * 120264ec4912SChris Morgan * 2. If the clock framework cannot provide the exact rate, we should 120364ec4912SChris Morgan * add 999 Hz to the requested rate. That way if the clock we need 120464ec4912SChris Morgan * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 120564ec4912SChris Morgan * the clock framework will actually give us the right clock. 1206287422a9SDouglas Anderson * 120764ec4912SChris Morgan * 3. Get the clock framework to round the rate for us to tell us 1208287422a9SDouglas Anderson * what it will actually make. 1209287422a9SDouglas Anderson * 121064ec4912SChris Morgan * 4. Store the rounded up rate so that we don't need to worry about 1211287422a9SDouglas Anderson * this in the actual clk_set_rate(). 1212287422a9SDouglas Anderson */ 121364ec4912SChris Morgan rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 121464ec4912SChris Morgan if (rate / 1000 != adjusted_mode->clock) 121564ec4912SChris Morgan rate = clk_round_rate(vop->dclk, 121664ec4912SChris Morgan adjusted_mode->clock * 1000 + 999); 1217287422a9SDouglas Anderson adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1218b59b8de3SChris Zhong 12192048e328SMark Yao return true; 12202048e328SMark Yao } 12212048e328SMark Yao 1222b23ab6acSEzequiel Garcia static bool vop_dsp_lut_is_enabled(struct vop *vop) 1223b23ab6acSEzequiel Garcia { 1224b23ab6acSEzequiel Garcia return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1225b23ab6acSEzequiel Garcia } 1226b23ab6acSEzequiel Garcia 1227b23ab6acSEzequiel Garcia static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1228b23ab6acSEzequiel Garcia { 1229b23ab6acSEzequiel Garcia struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1230b23ab6acSEzequiel Garcia unsigned int i; 1231b23ab6acSEzequiel Garcia 1232b23ab6acSEzequiel Garcia for (i = 0; i < crtc->gamma_size; i++) { 1233b23ab6acSEzequiel Garcia u32 word; 1234b23ab6acSEzequiel Garcia 1235b23ab6acSEzequiel Garcia word = (drm_color_lut_extract(lut[i].red, 10) << 20) | 1236b23ab6acSEzequiel Garcia (drm_color_lut_extract(lut[i].green, 10) << 10) | 1237b23ab6acSEzequiel Garcia drm_color_lut_extract(lut[i].blue, 10); 1238b23ab6acSEzequiel Garcia writel(word, vop->lut_regs + i * 4); 1239b23ab6acSEzequiel Garcia } 1240b23ab6acSEzequiel Garcia } 1241b23ab6acSEzequiel Garcia 1242b23ab6acSEzequiel Garcia static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1243b23ab6acSEzequiel Garcia struct drm_crtc_state *old_state) 1244b23ab6acSEzequiel Garcia { 1245b23ab6acSEzequiel Garcia struct drm_crtc_state *state = crtc->state; 1246b23ab6acSEzequiel Garcia unsigned int idle; 1247b23ab6acSEzequiel Garcia int ret; 1248b23ab6acSEzequiel Garcia 1249b23ab6acSEzequiel Garcia if (!vop->lut_regs) 1250b23ab6acSEzequiel Garcia return; 1251b23ab6acSEzequiel Garcia /* 1252b23ab6acSEzequiel Garcia * To disable gamma (gamma_lut is null) or to write 1253b23ab6acSEzequiel Garcia * an update to the LUT, clear dsp_lut_en. 1254b23ab6acSEzequiel Garcia */ 1255b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1256b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 0); 1257b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1258b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1259b23ab6acSEzequiel Garcia 1260b23ab6acSEzequiel Garcia /* 1261b23ab6acSEzequiel Garcia * In order to write the LUT to the internal memory, 1262b23ab6acSEzequiel Garcia * we need to first make sure the dsp_lut_en bit is cleared. 1263b23ab6acSEzequiel Garcia */ 1264b23ab6acSEzequiel Garcia ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1265b23ab6acSEzequiel Garcia idle, !idle, 5, 30 * 1000); 1266b23ab6acSEzequiel Garcia if (ret) { 1267b23ab6acSEzequiel Garcia DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1268b23ab6acSEzequiel Garcia return; 1269b23ab6acSEzequiel Garcia } 1270b23ab6acSEzequiel Garcia 1271b23ab6acSEzequiel Garcia if (!state->gamma_lut) 1272b23ab6acSEzequiel Garcia return; 1273b23ab6acSEzequiel Garcia 1274b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1275b23ab6acSEzequiel Garcia vop_crtc_write_gamma_lut(vop, crtc); 1276b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 1); 1277b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1278b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1279b23ab6acSEzequiel Garcia } 1280b23ab6acSEzequiel Garcia 1281b23ab6acSEzequiel Garcia static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1282f6ebe9f9SMaxime Ripard struct drm_atomic_state *state) 1283b23ab6acSEzequiel Garcia { 1284253f28b6SMaxime Ripard struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1285253f28b6SMaxime Ripard crtc); 1286f6ebe9f9SMaxime Ripard struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1287f6ebe9f9SMaxime Ripard crtc); 1288b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 1289b23ab6acSEzequiel Garcia 1290b23ab6acSEzequiel Garcia /* 1291b23ab6acSEzequiel Garcia * Only update GAMMA if the 'active' flag is not changed, 1292b23ab6acSEzequiel Garcia * otherwise it's updated by .atomic_enable. 1293b23ab6acSEzequiel Garcia */ 1294253f28b6SMaxime Ripard if (crtc_state->color_mgmt_changed && 1295253f28b6SMaxime Ripard !crtc_state->active_changed) 1296b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1297b23ab6acSEzequiel Garcia } 1298b23ab6acSEzequiel Garcia 12990b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1300351f950dSMaxime Ripard struct drm_atomic_state *state) 13012048e328SMark Yao { 1302351f950dSMaxime Ripard struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1303351f950dSMaxime Ripard crtc); 13042048e328SMark Yao struct vop *vop = to_vop(crtc); 1305efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 13064e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 130763ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 13082048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 13092048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 13102048e328SMark Yao u16 htotal = adjusted_mode->htotal; 13112048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 13122048e328SMark Yao u16 hact_end = hact_st + hdisplay; 13132048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 13142048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 13152048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 13162048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 13172048e328SMark Yao u16 vact_end = vact_st + vdisplay; 13180a63bfd0SMark Yao uint32_t pin_pol, val; 1319a5c0fa44SUrja Rannikko int dither_bpc = s->output_bpc ? s->output_bpc : 10; 132039a9ad8fSSean Paul int ret; 13212048e328SMark Yao 1322bed030a4SSean Paul if (old_state && old_state->self_refresh_active) { 1323bed030a4SSean Paul drm_crtc_vblank_on(crtc); 1324bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, true); 1325bed030a4SSean Paul return; 1326bed030a4SSean Paul } 1327bed030a4SSean Paul 1328b23ab6acSEzequiel Garcia /* 1329b23ab6acSEzequiel Garcia * If we have a GAMMA LUT in the state, then let's make sure 1330b23ab6acSEzequiel Garcia * it's updated. We might be coming out of suspend, 1331b23ab6acSEzequiel Garcia * which means the LUT internal memory needs to be re-written. 1332b23ab6acSEzequiel Garcia */ 1333b23ab6acSEzequiel Garcia if (crtc->state->gamma_lut) 1334b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_state); 1335b23ab6acSEzequiel Garcia 1336e334d48bSzain wang mutex_lock(&vop->vop_lock); 1337e334d48bSzain wang 1338893b6cadSDaniel Vetter WARN_ON(vop->event); 1339893b6cadSDaniel Vetter 13406c836d96SSean Paul ret = vop_enable(crtc, old_state); 134139a9ad8fSSean Paul if (ret) { 1342e334d48bSzain wang mutex_unlock(&vop->vop_lock); 134339a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 134439a9ad8fSSean Paul return; 134539a9ad8fSSean Paul } 13461f6c62caSNickey Yang pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1347d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 1348d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1349d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 13509a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 1351cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 13520a63bfd0SMark Yao 13534e257d9eSMark Yao switch (s->output_type) { 13544e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 13551f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 13569a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 13571f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_en, 1); 13584e257d9eSMark Yao break; 13594e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 13601f6c62caSNickey Yang VOP_REG_SET(vop, output, edp_dclk_pol, 1); 13619a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 13629a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 13634e257d9eSMark Yao break; 13644e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 13651f6c62caSNickey Yang VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 13669a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 13679a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 13684e257d9eSMark Yao break; 13694e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 13701f6c62caSNickey Yang VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 13719a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 13729a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 1373cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 1374cf6d100dSHeiko Stuebner !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 13754e257d9eSMark Yao break; 13761a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 13771f6c62caSNickey Yang VOP_REG_SET(vop, output, dp_dclk_pol, 0); 13789a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 13799a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 13801a0f7ed3SChris Zhong break; 13814e257d9eSMark Yao default: 1382ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1383ee4d7899SSean Paul s->output_type); 13844e257d9eSMark Yao } 1385efd11cc8SMark yao 1386efd11cc8SMark yao /* 1387efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 1388efd11cc8SMark yao */ 1389efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1390efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1391efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 13926bda8112SMark Yao 1393a5c0fa44SUrja Rannikko if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 13946bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 13956bda8112SMark Yao else 13966bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 13976bda8112SMark Yao 1398a5c0fa44SUrja Rannikko if (dither_bpc == 6) { 1399a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1400a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1401a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 1); 1402a5c0fa44SUrja Rannikko } else { 1403a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 0); 1404a5c0fa44SUrja Rannikko } 1405a5c0fa44SUrja Rannikko 14069a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 14072048e328SMark Yao 14089a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 14092048e328SMark Yao val = hact_st << 16; 14102048e328SMark Yao val |= hact_end; 14119a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 14129a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 14132048e328SMark Yao 14149a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 14152048e328SMark Yao val = vact_st << 16; 14162048e328SMark Yao val |= vact_end; 14179a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 14189a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 14192048e328SMark Yao 14209a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1421459b086dSJeffy Chen 14222048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1423ce3887edSMark Yao 14249a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 1425e334d48bSzain wang mutex_unlock(&vop->vop_lock); 14262048e328SMark Yao } 14272048e328SMark Yao 14287caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 14297caecdbeSTomasz Figa { 14307caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 14317caecdbeSTomasz Figa } 14327caecdbeSTomasz Figa 14337caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 14347caecdbeSTomasz Figa { 14357caecdbeSTomasz Figa bool pending; 14367caecdbeSTomasz Figa int ret; 14377caecdbeSTomasz Figa 14387caecdbeSTomasz Figa /* 14397caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 14407caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 14417caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 14427caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 14437caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 14447caecdbeSTomasz Figa * shouldn't exceed microseconds range. 14457caecdbeSTomasz Figa */ 14467caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 14477caecdbeSTomasz Figa !pending, 0, 10 * 1000); 14487caecdbeSTomasz Figa if (ret) 14497caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 14507caecdbeSTomasz Figa 14517caecdbeSTomasz Figa synchronize_irq(vop->irq); 14527caecdbeSTomasz Figa } 14537caecdbeSTomasz Figa 1454b23ab6acSEzequiel Garcia static int vop_crtc_atomic_check(struct drm_crtc *crtc, 145529b77ad7SMaxime Ripard struct drm_atomic_state *state) 1456b23ab6acSEzequiel Garcia { 145729b77ad7SMaxime Ripard struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 145829b77ad7SMaxime Ripard crtc); 1459b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 14607707f722SAndrzej Pietrasiewicz struct drm_plane *plane; 14617707f722SAndrzej Pietrasiewicz struct drm_plane_state *plane_state; 14627707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 14637707f722SAndrzej Pietrasiewicz int afbc_planes = 0; 1464b23ab6acSEzequiel Garcia 1465b23ab6acSEzequiel Garcia if (vop->lut_regs && crtc_state->color_mgmt_changed && 1466b23ab6acSEzequiel Garcia crtc_state->gamma_lut) { 1467b23ab6acSEzequiel Garcia unsigned int len; 1468b23ab6acSEzequiel Garcia 1469b23ab6acSEzequiel Garcia len = drm_color_lut_size(crtc_state->gamma_lut); 1470b23ab6acSEzequiel Garcia if (len != crtc->gamma_size) { 1471b23ab6acSEzequiel Garcia DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1472b23ab6acSEzequiel Garcia len, crtc->gamma_size); 1473b23ab6acSEzequiel Garcia return -EINVAL; 1474b23ab6acSEzequiel Garcia } 1475b23ab6acSEzequiel Garcia } 1476b23ab6acSEzequiel Garcia 14777707f722SAndrzej Pietrasiewicz drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 14787707f722SAndrzej Pietrasiewicz plane_state = 14797707f722SAndrzej Pietrasiewicz drm_atomic_get_plane_state(crtc_state->state, plane); 14807707f722SAndrzej Pietrasiewicz if (IS_ERR(plane_state)) { 14817707f722SAndrzej Pietrasiewicz DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 14827707f722SAndrzej Pietrasiewicz plane->name); 14837707f722SAndrzej Pietrasiewicz return PTR_ERR(plane_state); 14847707f722SAndrzej Pietrasiewicz } 14857707f722SAndrzej Pietrasiewicz 14867707f722SAndrzej Pietrasiewicz if (drm_is_afbc(plane_state->fb->modifier)) 14877707f722SAndrzej Pietrasiewicz ++afbc_planes; 14887707f722SAndrzej Pietrasiewicz } 14897707f722SAndrzej Pietrasiewicz 14907707f722SAndrzej Pietrasiewicz if (afbc_planes > 1) { 14917707f722SAndrzej Pietrasiewicz DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 14927707f722SAndrzej Pietrasiewicz return -EINVAL; 14937707f722SAndrzej Pietrasiewicz } 14947707f722SAndrzej Pietrasiewicz 14957707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc_state); 14967707f722SAndrzej Pietrasiewicz s->enable_afbc = afbc_planes > 0; 14977707f722SAndrzej Pietrasiewicz 1498b23ab6acSEzequiel Garcia return 0; 1499b23ab6acSEzequiel Garcia } 1500b23ab6acSEzequiel Garcia 150163ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1502f6ebe9f9SMaxime Ripard struct drm_atomic_state *state) 150363ebb9faSMark Yao { 1504f6ebe9f9SMaxime Ripard struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1505f6ebe9f9SMaxime Ripard crtc); 150647a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1507e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 150863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 150947a7eb45STomasz Figa struct drm_plane *plane; 15107707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 151147a7eb45STomasz Figa int i; 151263ebb9faSMark Yao 151363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 151463ebb9faSMark Yao return; 151563ebb9faSMark Yao 151663ebb9faSMark Yao spin_lock(&vop->reg_lock); 151763ebb9faSMark Yao 15187707f722SAndrzej Pietrasiewicz /* Enable AFBC if there is some AFBC window, disable otherwise. */ 15197707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc->state); 15207707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, enable, s->enable_afbc); 152163ebb9faSMark Yao vop_cfg_done(vop); 152263ebb9faSMark Yao 152363ebb9faSMark Yao spin_unlock(&vop->reg_lock); 15247caecdbeSTomasz Figa 15257caecdbeSTomasz Figa /* 15267caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 15277caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 15287caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 15297caecdbeSTomasz Figa */ 15307caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 153147a7eb45STomasz Figa 153241ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 153341ee4367STomasz Figa if (crtc->state->event) { 153441ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 153541ee4367STomasz Figa WARN_ON(vop->event); 153641ee4367STomasz Figa 153741ee4367STomasz Figa vop->event = crtc->state->event; 153841ee4367STomasz Figa crtc->state->event = NULL; 153941ee4367STomasz Figa } 154041ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 154141ee4367STomasz Figa 1542e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1543e741f2b1SMaarten Lankhorst new_plane_state, i) { 154447a7eb45STomasz Figa if (!old_plane_state->fb) 154547a7eb45STomasz Figa continue; 154647a7eb45STomasz Figa 1547e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 154847a7eb45STomasz Figa continue; 154947a7eb45STomasz Figa 1550adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 15512d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 155247a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 155347a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 155447a7eb45STomasz Figa } 155563ebb9faSMark Yao } 155663ebb9faSMark Yao 15572048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 15582048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 1559b23ab6acSEzequiel Garcia .atomic_check = vop_crtc_atomic_check, 1560b23ab6acSEzequiel Garcia .atomic_begin = vop_crtc_atomic_begin, 156163ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 15620b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 156364581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 15642048e328SMark Yao }; 15652048e328SMark Yao 15662048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 15672048e328SMark Yao { 15682048e328SMark Yao drm_crtc_cleanup(crtc); 15692048e328SMark Yao } 15702048e328SMark Yao 15714e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 15724e257d9eSMark Yao { 15734e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 15744e257d9eSMark Yao 15754e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 15764e257d9eSMark Yao if (!rockchip_state) 15774e257d9eSMark Yao return NULL; 15784e257d9eSMark Yao 15794e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 15804e257d9eSMark Yao return &rockchip_state->base; 15814e257d9eSMark Yao } 15824e257d9eSMark Yao 15834e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 15844e257d9eSMark Yao struct drm_crtc_state *state) 15854e257d9eSMark Yao { 15864e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 15874e257d9eSMark Yao 1588ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 15894e257d9eSMark Yao kfree(s); 15904e257d9eSMark Yao } 15914e257d9eSMark Yao 159201e2eaf4SMaarten Lankhorst static void vop_crtc_reset(struct drm_crtc *crtc) 159301e2eaf4SMaarten Lankhorst { 159401e2eaf4SMaarten Lankhorst struct rockchip_crtc_state *crtc_state = 159501e2eaf4SMaarten Lankhorst kzalloc(sizeof(*crtc_state), GFP_KERNEL); 159601e2eaf4SMaarten Lankhorst 159701e2eaf4SMaarten Lankhorst if (crtc->state) 159801e2eaf4SMaarten Lankhorst vop_crtc_destroy_state(crtc, crtc->state); 159901e2eaf4SMaarten Lankhorst 160001e2eaf4SMaarten Lankhorst __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 160101e2eaf4SMaarten Lankhorst } 160201e2eaf4SMaarten Lankhorst 16036cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 16043190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 16053190e58dSTomeu Vizoso { 16063190e58dSTomeu Vizoso struct drm_connector *connector; 16072cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 16083190e58dSTomeu Vizoso 16092cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 16102cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 16113190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 16122cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 16133190e58dSTomeu Vizoso return connector; 16143190e58dSTomeu Vizoso } 16152cbeb64fSGustavo Padovan } 16162cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 16173190e58dSTomeu Vizoso 16183190e58dSTomeu Vizoso return NULL; 16193190e58dSTomeu Vizoso } 16203190e58dSTomeu Vizoso 16213190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1622c0811a7dSMahesh Kumar const char *source_name) 16233190e58dSTomeu Vizoso { 16243190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 16253190e58dSTomeu Vizoso struct drm_connector *connector; 16263190e58dSTomeu Vizoso int ret; 16273190e58dSTomeu Vizoso 16283190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 16293190e58dSTomeu Vizoso if (!connector) 16303190e58dSTomeu Vizoso return -EINVAL; 16313190e58dSTomeu Vizoso 16323190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 16333190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 16343190e58dSTomeu Vizoso else if (!source_name) 16353190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 16363190e58dSTomeu Vizoso else 16373190e58dSTomeu Vizoso ret = -EINVAL; 16383190e58dSTomeu Vizoso 16393190e58dSTomeu Vizoso return ret; 16403190e58dSTomeu Vizoso } 1641b8d913c0SMahesh Kumar 1642b8d913c0SMahesh Kumar static int 1643b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1644b8d913c0SMahesh Kumar size_t *values_cnt) 1645b8d913c0SMahesh Kumar { 1646b8d913c0SMahesh Kumar if (source_name && strcmp(source_name, "auto") != 0) 1647b8d913c0SMahesh Kumar return -EINVAL; 1648b8d913c0SMahesh Kumar 1649b8d913c0SMahesh Kumar *values_cnt = 3; 1650b8d913c0SMahesh Kumar return 0; 1651b8d913c0SMahesh Kumar } 1652b8d913c0SMahesh Kumar 16536cca3869SSean Paul #else 16546cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1655c0811a7dSMahesh Kumar const char *source_name) 16566cca3869SSean Paul { 16576cca3869SSean Paul return -ENODEV; 16586cca3869SSean Paul } 1659b8d913c0SMahesh Kumar 1660b8d913c0SMahesh Kumar static int 1661b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1662b8d913c0SMahesh Kumar size_t *values_cnt) 1663b8d913c0SMahesh Kumar { 1664b8d913c0SMahesh Kumar return -ENODEV; 1665b8d913c0SMahesh Kumar } 16666cca3869SSean Paul #endif 16673190e58dSTomeu Vizoso 16682048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 166963ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 167063ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 16712048e328SMark Yao .destroy = vop_crtc_destroy, 1672dc0b408fSJohn Keeping .reset = vop_crtc_reset, 16734e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 16744e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1675c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1676c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 16773190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 1678b8d913c0SMahesh Kumar .verify_crc_source = vop_crtc_verify_crc_source, 16792048e328SMark Yao }; 16802048e328SMark Yao 168147a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 168247a7eb45STomasz Figa { 168347a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 168447a7eb45STomasz Figa struct drm_framebuffer *fb = val; 168547a7eb45STomasz Figa 168647a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1687adedbf03SCihangir Akturk drm_framebuffer_put(fb); 168847a7eb45STomasz Figa } 168947a7eb45STomasz Figa 169063ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 16912048e328SMark Yao { 169263ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 169363ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 16942048e328SMark Yao 16951c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1696893b6cadSDaniel Vetter if (vop->event) { 169763ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 16985b680403SSean Paul drm_crtc_vblank_put(crtc); 1699646ec687STomasz Figa vop->event = NULL; 17005b680403SSean Paul } 17011c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1702893b6cadSDaniel Vetter 170347a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 170447a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 17052048e328SMark Yao } 17062048e328SMark Yao 17072048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 17082048e328SMark Yao { 17092048e328SMark Yao struct vop *vop = data; 1710b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1711dbb3d944SMark Yao uint32_t active_irqs; 17121067219bSMark Yao int ret = IRQ_NONE; 17132048e328SMark Yao 17142048e328SMark Yao /* 17156456314fSSandy Huang * The irq is shared with the iommu. If the runtime-pm state of the 17166456314fSSandy Huang * vop-device is disabled the irq has to be targeted at the iommu. 17176456314fSSandy Huang */ 17186456314fSSandy Huang if (!pm_runtime_get_if_in_use(vop->dev)) 17196456314fSSandy Huang return IRQ_NONE; 17206456314fSSandy Huang 17216456314fSSandy Huang if (vop_core_clks_enable(vop)) { 17226456314fSSandy Huang DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 17236456314fSSandy Huang goto out; 17246456314fSSandy Huang } 17256456314fSSandy Huang 17266456314fSSandy Huang /* 1727dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 17282048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 17292048e328SMark Yao */ 17301c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1731dbb3d944SMark Yao 1732dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 17332048e328SMark Yao /* Clear all active interrupt sources */ 17342048e328SMark Yao if (active_irqs) 1735dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1736dbb3d944SMark Yao 17371c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 17382048e328SMark Yao 17392048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 17402048e328SMark Yao if (!active_irqs) 17416456314fSSandy Huang goto out_disable; 17422048e328SMark Yao 17431067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 17441067219bSMark Yao complete(&vop->dsp_hold_completion); 17451067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 17461067219bSMark Yao ret = IRQ_HANDLED; 17472048e328SMark Yao } 17482048e328SMark Yao 174969c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 175069c34e41SYakir Yang complete(&vop->line_flag_completion); 175169c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 175269c34e41SYakir Yang ret = IRQ_HANDLED; 175369c34e41SYakir Yang } 175469c34e41SYakir Yang 17551067219bSMark Yao if (active_irqs & FS_INTR) { 1756b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 175763ebb9faSMark Yao vop_handle_vblank(vop); 17581067219bSMark Yao active_irqs &= ~FS_INTR; 175963ebb9faSMark Yao ret = IRQ_HANDLED; 17601067219bSMark Yao } 17612048e328SMark Yao 17621067219bSMark Yao /* Unhandled irqs are spurious. */ 17631067219bSMark Yao if (active_irqs) 1764ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1765ee4d7899SSean Paul active_irqs); 17661067219bSMark Yao 17676456314fSSandy Huang out_disable: 17686456314fSSandy Huang vop_core_clks_disable(vop); 17696456314fSSandy Huang out: 17706456314fSSandy Huang pm_runtime_put(vop->dev); 17711067219bSMark Yao return ret; 17722048e328SMark Yao } 17732048e328SMark Yao 1774677e8bbcSDaniele Castagna static void vop_plane_add_properties(struct drm_plane *plane, 1775677e8bbcSDaniele Castagna const struct vop_win_data *win_data) 1776677e8bbcSDaniele Castagna { 1777677e8bbcSDaniele Castagna unsigned int flags = 0; 1778677e8bbcSDaniele Castagna 1779677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1780677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1781677e8bbcSDaniele Castagna if (flags) 1782677e8bbcSDaniele Castagna drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1783677e8bbcSDaniele Castagna DRM_MODE_ROTATE_0 | flags); 1784677e8bbcSDaniele Castagna } 1785677e8bbcSDaniele Castagna 17862048e328SMark Yao static int vop_create_crtc(struct vop *vop) 17872048e328SMark Yao { 17882048e328SMark Yao const struct vop_data *vop_data = vop->data; 17892048e328SMark Yao struct device *dev = vop->dev; 17902048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1791328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 17922048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 17932048e328SMark Yao struct device_node *port; 17942048e328SMark Yao int ret; 17952048e328SMark Yao int i; 17962048e328SMark Yao 17972048e328SMark Yao /* 17982048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 17992048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 18002048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 18012048e328SMark Yao */ 18022048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 18032048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 18042048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 18052048e328SMark Yao 18062048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 18072048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 18082048e328SMark Yao continue; 18092048e328SMark Yao 18102048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 18112048e328SMark Yao 0, &vop_plane_funcs, 18122048e328SMark Yao win_data->phy->data_formats, 18132048e328SMark Yao win_data->phy->nformats, 18147707f722SAndrzej Pietrasiewicz win_data->phy->format_modifiers, 18157707f722SAndrzej Pietrasiewicz win_data->type, NULL); 18162048e328SMark Yao if (ret) { 1817ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1818ee4d7899SSean Paul ret); 18192048e328SMark Yao goto err_cleanup_planes; 18202048e328SMark Yao } 18212048e328SMark Yao 18222048e328SMark Yao plane = &vop_win->base; 182363ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 1824677e8bbcSDaniele Castagna vop_plane_add_properties(plane, win_data); 18252048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 18262048e328SMark Yao primary = plane; 18272048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 18282048e328SMark Yao cursor = plane; 18292048e328SMark Yao } 18302048e328SMark Yao 18312048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1832f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 18332048e328SMark Yao if (ret) 1834328b51c0SDouglas Anderson goto err_cleanup_planes; 18352048e328SMark Yao 18362048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1837b23ab6acSEzequiel Garcia if (vop->lut_regs) { 1838b23ab6acSEzequiel Garcia drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1839b23ab6acSEzequiel Garcia drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1840b23ab6acSEzequiel Garcia } 18412048e328SMark Yao 18422048e328SMark Yao /* 18432048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 18442048e328SMark Yao * to the newly created crtc. 18452048e328SMark Yao */ 18462048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 18472048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 18482048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 1849a3e77e16SVille Syrjälä unsigned long possible_crtcs = drm_crtc_mask(crtc); 18502048e328SMark Yao 18512048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 18522048e328SMark Yao continue; 18532048e328SMark Yao 18542048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 18552048e328SMark Yao possible_crtcs, 18562048e328SMark Yao &vop_plane_funcs, 18572048e328SMark Yao win_data->phy->data_formats, 18582048e328SMark Yao win_data->phy->nformats, 18597707f722SAndrzej Pietrasiewicz win_data->phy->format_modifiers, 18607707f722SAndrzej Pietrasiewicz win_data->type, NULL); 18612048e328SMark Yao if (ret) { 1862ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1863ee4d7899SSean Paul ret); 18642048e328SMark Yao goto err_cleanup_crtc; 18652048e328SMark Yao } 186663ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1867677e8bbcSDaniele Castagna vop_plane_add_properties(&vop_win->base, win_data); 18682048e328SMark Yao } 18692048e328SMark Yao 18702048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 18712048e328SMark Yao if (!port) { 18724bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 18734bf99144SRob Herring dev->of_node); 1874328b51c0SDouglas Anderson ret = -ENOENT; 18752048e328SMark Yao goto err_cleanup_crtc; 18762048e328SMark Yao } 18772048e328SMark Yao 187847a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 187947a7eb45STomasz Figa vop_fb_unref_worker); 188047a7eb45STomasz Figa 18811067219bSMark Yao init_completion(&vop->dsp_hold_completion); 188269c34e41SYakir Yang init_completion(&vop->line_flag_completion); 18832048e328SMark Yao crtc->port = port; 18842048e328SMark Yao 1885d4da4e33SSean Paul ret = drm_self_refresh_helper_init(crtc); 18866c836d96SSean Paul if (ret) 18876c836d96SSean Paul DRM_DEV_DEBUG_KMS(vop->dev, 18886c836d96SSean Paul "Failed to init %s with SR helpers %d, ignoring\n", 18896c836d96SSean Paul crtc->name, ret); 18906c836d96SSean Paul 18912048e328SMark Yao return 0; 18922048e328SMark Yao 18932048e328SMark Yao err_cleanup_crtc: 18942048e328SMark Yao drm_crtc_cleanup(crtc); 18952048e328SMark Yao err_cleanup_planes: 1896328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1897328b51c0SDouglas Anderson head) 18982048e328SMark Yao drm_plane_cleanup(plane); 18992048e328SMark Yao return ret; 19002048e328SMark Yao } 19012048e328SMark Yao 19022048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 19032048e328SMark Yao { 19042048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1905328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1906328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 19072048e328SMark Yao 19086c836d96SSean Paul drm_self_refresh_helper_cleanup(crtc); 19096c836d96SSean Paul 19102048e328SMark Yao of_node_put(crtc->port); 1911328b51c0SDouglas Anderson 1912328b51c0SDouglas Anderson /* 1913328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1914328b51c0SDouglas Anderson * 1915328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1916328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1917328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1918328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1919328b51c0SDouglas Anderson */ 1920328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1921328b51c0SDouglas Anderson head) 1922328b51c0SDouglas Anderson vop_plane_destroy(plane); 1923328b51c0SDouglas Anderson 1924328b51c0SDouglas Anderson /* 1925328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1926328b51c0SDouglas Anderson * references the CRTC. 1927328b51c0SDouglas Anderson */ 19282048e328SMark Yao drm_crtc_cleanup(crtc); 192947a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 19302048e328SMark Yao } 19312048e328SMark Yao 19322048e328SMark Yao static int vop_initial(struct vop *vop) 19332048e328SMark Yao { 19342048e328SMark Yao struct reset_control *ahb_rst; 19352048e328SMark Yao int i, ret; 19362048e328SMark Yao 19372048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 19382048e328SMark Yao if (IS_ERR(vop->hclk)) { 1939d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 19402048e328SMark Yao return PTR_ERR(vop->hclk); 19412048e328SMark Yao } 19422048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 19432048e328SMark Yao if (IS_ERR(vop->aclk)) { 1944d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 19452048e328SMark Yao return PTR_ERR(vop->aclk); 19462048e328SMark Yao } 19472048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 19482048e328SMark Yao if (IS_ERR(vop->dclk)) { 1949d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 19502048e328SMark Yao return PTR_ERR(vop->dclk); 19512048e328SMark Yao } 19522048e328SMark Yao 19535e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 19545e570373SJeffy Chen if (ret < 0) { 1955d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 19565e570373SJeffy Chen return ret; 19575e570373SJeffy Chen } 19585e570373SJeffy Chen 19592048e328SMark Yao ret = clk_prepare(vop->dclk); 19602048e328SMark Yao if (ret < 0) { 1961d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 19625e570373SJeffy Chen goto err_put_pm_runtime; 19632048e328SMark Yao } 19642048e328SMark Yao 1965d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1966d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 19672048e328SMark Yao if (ret < 0) { 1968d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 19692048e328SMark Yao goto err_unprepare_dclk; 19702048e328SMark Yao } 19712048e328SMark Yao 1972d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 19732048e328SMark Yao if (ret < 0) { 1974d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1975d7b53fd9SSjoerd Simons goto err_disable_hclk; 19762048e328SMark Yao } 1977d7b53fd9SSjoerd Simons 19782048e328SMark Yao /* 19792048e328SMark Yao * do hclk_reset, reset all vop registers. 19802048e328SMark Yao */ 19812048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 19822048e328SMark Yao if (IS_ERR(ahb_rst)) { 1983d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 19842048e328SMark Yao ret = PTR_ERR(ahb_rst); 1985d7b53fd9SSjoerd Simons goto err_disable_aclk; 19862048e328SMark Yao } 19872048e328SMark Yao reset_control_assert(ahb_rst); 19882048e328SMark Yao usleep_range(10, 20); 19892048e328SMark Yao reset_control_deassert(ahb_rst); 19902048e328SMark Yao 19915f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 19925f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 19935f9e93feSMarc Zyngier 199476f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 199576f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 19962048e328SMark Yao 19979a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 19989a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 19992048e328SMark Yao 20002b60e11dSSean Paul for (i = 0; i < vop->data->win_size; i++) { 20012b60e11dSSean Paul struct vop_win *vop_win = &vop->win[i]; 20022b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 20039dd2aca4SMark yao int channel = i * 2 + 1; 20042048e328SMark Yao 20059dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 20062b60e11dSSean Paul vop_win_disable(vop, vop_win); 200760b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 20082048e328SMark Yao } 20092048e328SMark Yao 20102048e328SMark Yao vop_cfg_done(vop); 20112048e328SMark Yao 20122048e328SMark Yao /* 20132048e328SMark Yao * do dclk_reset, let all config take affect. 20142048e328SMark Yao */ 20152048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 20162048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 2017d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 20182048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 2019d7b53fd9SSjoerd Simons goto err_disable_aclk; 20202048e328SMark Yao } 20212048e328SMark Yao reset_control_assert(vop->dclk_rst); 20222048e328SMark Yao usleep_range(10, 20); 20232048e328SMark Yao reset_control_deassert(vop->dclk_rst); 20242048e328SMark Yao 20252048e328SMark Yao clk_disable(vop->hclk); 2026d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 20272048e328SMark Yao 202831e980c5SMark Yao vop->is_enabled = false; 20292048e328SMark Yao 20305e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 20315e570373SJeffy Chen 20322048e328SMark Yao return 0; 20332048e328SMark Yao 2034d7b53fd9SSjoerd Simons err_disable_aclk: 2035d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 20362048e328SMark Yao err_disable_hclk: 2037d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 20382048e328SMark Yao err_unprepare_dclk: 20392048e328SMark Yao clk_unprepare(vop->dclk); 20405e570373SJeffy Chen err_put_pm_runtime: 20415e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 20422048e328SMark Yao return ret; 20432048e328SMark Yao } 20442048e328SMark Yao 20452048e328SMark Yao /* 20462048e328SMark Yao * Initialize the vop->win array elements. 20472048e328SMark Yao */ 20482048e328SMark Yao static void vop_win_init(struct vop *vop) 20492048e328SMark Yao { 20502048e328SMark Yao const struct vop_data *vop_data = vop->data; 20512048e328SMark Yao unsigned int i; 20522048e328SMark Yao 20532048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 20542048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 20552048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 20562048e328SMark Yao 20572048e328SMark Yao vop_win->data = win_data; 20582048e328SMark Yao vop_win->vop = vop; 2059ce6912b4SHeiko Stuebner 2060ce6912b4SHeiko Stuebner if (vop_data->win_yuv2yuv) 20611c21aa8fSDaniele Castagna vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 20622048e328SMark Yao } 20632048e328SMark Yao } 20642048e328SMark Yao 206569c34e41SYakir Yang /** 2066459b086dSJeffy Chen * rockchip_drm_wait_vact_end 206769c34e41SYakir Yang * @crtc: CRTC to enable line flag 206869c34e41SYakir Yang * @mstimeout: millisecond for timeout 206969c34e41SYakir Yang * 2070459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 207169c34e41SYakir Yang * 207269c34e41SYakir Yang * Returns: 207369c34e41SYakir Yang * Zero on success, negative errno on failure. 207469c34e41SYakir Yang */ 2075459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 207669c34e41SYakir Yang { 207769c34e41SYakir Yang struct vop *vop = to_vop(crtc); 207869c34e41SYakir Yang unsigned long jiffies_left; 2079e334d48bSzain wang int ret = 0; 208069c34e41SYakir Yang 208169c34e41SYakir Yang if (!crtc || !vop->is_enabled) 208269c34e41SYakir Yang return -ENODEV; 208369c34e41SYakir Yang 2084e334d48bSzain wang mutex_lock(&vop->vop_lock); 2085e334d48bSzain wang if (mstimeout <= 0) { 2086e334d48bSzain wang ret = -EINVAL; 2087e334d48bSzain wang goto out; 2088e334d48bSzain wang } 208969c34e41SYakir Yang 2090e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 2091e334d48bSzain wang ret = -EBUSY; 2092e334d48bSzain wang goto out; 2093e334d48bSzain wang } 209469c34e41SYakir Yang 209569c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 2096459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 209769c34e41SYakir Yang 209869c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 209969c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 210069c34e41SYakir Yang vop_line_flag_irq_disable(vop); 210169c34e41SYakir Yang 210269c34e41SYakir Yang if (jiffies_left == 0) { 2103d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2104e334d48bSzain wang ret = -ETIMEDOUT; 2105e334d48bSzain wang goto out; 210669c34e41SYakir Yang } 210769c34e41SYakir Yang 2108e334d48bSzain wang out: 2109e334d48bSzain wang mutex_unlock(&vop->vop_lock); 2110e334d48bSzain wang return ret; 211169c34e41SYakir Yang } 2112459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 211369c34e41SYakir Yang 21142048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 21152048e328SMark Yao { 21162048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 21172048e328SMark Yao const struct vop_data *vop_data; 21182048e328SMark Yao struct drm_device *drm_dev = data; 21192048e328SMark Yao struct vop *vop; 21202048e328SMark Yao struct resource *res; 21213ea68922SHeiko Stuebner int ret, irq; 21222048e328SMark Yao 2123a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 21242048e328SMark Yao if (!vop_data) 21252048e328SMark Yao return -ENODEV; 21262048e328SMark Yao 21272048e328SMark Yao /* Allocate vop struct and its vop_win array */ 212829adeb4fSGustavo A. R. Silva vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 212929adeb4fSGustavo A. R. Silva GFP_KERNEL); 21302048e328SMark Yao if (!vop) 21312048e328SMark Yao return -ENOMEM; 21322048e328SMark Yao 21332048e328SMark Yao vop->dev = dev; 21342048e328SMark Yao vop->data = vop_data; 21352048e328SMark Yao vop->drm_dev = drm_dev; 21362048e328SMark Yao dev_set_drvdata(dev, vop); 21372048e328SMark Yao 21382048e328SMark Yao vop_win_init(vop); 21392048e328SMark Yao 21402048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 21412048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 21422048e328SMark Yao if (IS_ERR(vop->regs)) 21432048e328SMark Yao return PTR_ERR(vop->regs); 2144f8c24290SYang Yingliang vop->len = resource_size(res); 21452048e328SMark Yao 2146b23ab6acSEzequiel Garcia res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2147b23ab6acSEzequiel Garcia if (res) { 2148b23ab6acSEzequiel Garcia if (!vop_data->lut_size) { 2149b23ab6acSEzequiel Garcia DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); 2150b23ab6acSEzequiel Garcia return -EINVAL; 2151b23ab6acSEzequiel Garcia } 2152b23ab6acSEzequiel Garcia vop->lut_regs = devm_ioremap_resource(dev, res); 2153b23ab6acSEzequiel Garcia if (IS_ERR(vop->lut_regs)) 2154b23ab6acSEzequiel Garcia return PTR_ERR(vop->lut_regs); 2155b23ab6acSEzequiel Garcia } 2156b23ab6acSEzequiel Garcia 21572048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 21582048e328SMark Yao if (!vop->regsbak) 21592048e328SMark Yao return -ENOMEM; 21602048e328SMark Yao 21613ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 21623ea68922SHeiko Stuebner if (irq < 0) { 2163d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 21643ea68922SHeiko Stuebner return irq; 21652048e328SMark Yao } 21663ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 21672048e328SMark Yao 21682048e328SMark Yao spin_lock_init(&vop->reg_lock); 21692048e328SMark Yao spin_lock_init(&vop->irq_lock); 2170e334d48bSzain wang mutex_init(&vop->vop_lock); 21712048e328SMark Yao 21722048e328SMark Yao ret = vop_create_crtc(vop); 21732048e328SMark Yao if (ret) 21745f9e93feSMarc Zyngier return ret; 21752048e328SMark Yao 21762048e328SMark Yao pm_runtime_enable(&pdev->dev); 21775182c1a5SYakir Yang 21785e570373SJeffy Chen ret = vop_initial(vop); 21795e570373SJeffy Chen if (ret < 0) { 2180d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 2181d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 21825e570373SJeffy Chen goto err_disable_pm_runtime; 21835e570373SJeffy Chen } 21845e570373SJeffy Chen 21855f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 21865f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 21875f9e93feSMarc Zyngier if (ret) 21885f9e93feSMarc Zyngier goto err_disable_pm_runtime; 21895f9e93feSMarc Zyngier 21901f0f0151SSandy Huang if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 21911f0f0151SSandy Huang vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 21921f0f0151SSandy Huang if (IS_ERR(vop->rgb)) { 21931f0f0151SSandy Huang ret = PTR_ERR(vop->rgb); 21941f0f0151SSandy Huang goto err_disable_pm_runtime; 21951f0f0151SSandy Huang } 21961f0f0151SSandy Huang } 21971f0f0151SSandy Huang 2198421be3eeSRobin Murphy rockchip_drm_dma_init_device(drm_dev, dev); 2199421be3eeSRobin Murphy 22002048e328SMark Yao return 0; 22018c763c9bSSean Paul 22025e570373SJeffy Chen err_disable_pm_runtime: 22035e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 22045e570373SJeffy Chen vop_destroy_crtc(vop); 22058c763c9bSSean Paul return ret; 22062048e328SMark Yao } 22072048e328SMark Yao 22082048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 22092048e328SMark Yao { 22102048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 22112048e328SMark Yao 22121f0f0151SSandy Huang if (vop->rgb) 22131f0f0151SSandy Huang rockchip_rgb_fini(vop->rgb); 22141f0f0151SSandy Huang 22152048e328SMark Yao pm_runtime_disable(dev); 22162048e328SMark Yao vop_destroy_crtc(vop); 2217ec6e7767SJeffy Chen 2218ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 2219ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 2220ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 22212048e328SMark Yao } 22222048e328SMark Yao 2223a67719d1SMark Yao const struct component_ops vop_component_ops = { 22242048e328SMark Yao .bind = vop_bind, 22252048e328SMark Yao .unbind = vop_unbind, 22262048e328SMark Yao }; 222754255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 2228