12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 202048e328SMark Yao #include <drm/drm_plane_helper.h> 212048e328SMark Yao 222048e328SMark Yao #include <linux/kernel.h> 2300fe6148SPaul Gortmaker #include <linux/module.h> 242048e328SMark Yao #include <linux/platform_device.h> 252048e328SMark Yao #include <linux/clk.h> 262048e328SMark Yao #include <linux/of.h> 272048e328SMark Yao #include <linux/of_device.h> 282048e328SMark Yao #include <linux/pm_runtime.h> 292048e328SMark Yao #include <linux/component.h> 302048e328SMark Yao 312048e328SMark Yao #include <linux/reset.h> 322048e328SMark Yao #include <linux/delay.h> 332048e328SMark Yao 342048e328SMark Yao #include "rockchip_drm_drv.h" 352048e328SMark Yao #include "rockchip_drm_gem.h" 362048e328SMark Yao #include "rockchip_drm_fb.h" 372048e328SMark Yao #include "rockchip_drm_vop.h" 382048e328SMark Yao 392048e328SMark Yao #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 402048e328SMark Yao vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 412048e328SMark Yao #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 422048e328SMark Yao vop_mask_write(x, off, (mask) << shift, (v) << shift) 432048e328SMark Yao 442048e328SMark Yao #define REG_SET(x, base, reg, v, mode) \ 452048e328SMark Yao __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 46dbb3d944SMark Yao #define REG_SET_MASK(x, base, reg, v, mode) \ 47dbb3d944SMark Yao __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 482048e328SMark Yao 492048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 502048e328SMark Yao REG_SET(x, win->base, win->phy->name, v, RELAXED) 514c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 524c156c21SMark Yao REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 531194fffbSMark Yao #define VOP_SCL_SET_EXT(x, win, name, v) \ 541194fffbSMark Yao REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) 552048e328SMark Yao #define VOP_CTRL_SET(x, name, v) \ 562048e328SMark Yao REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 572048e328SMark Yao 58dbb3d944SMark Yao #define VOP_INTR_GET(vop, name) \ 59dbb3d944SMark Yao vop_read_reg(vop, 0, &vop->data->ctrl->name) 60dbb3d944SMark Yao 61dbb3d944SMark Yao #define VOP_INTR_SET(vop, name, v) \ 62dbb3d944SMark Yao REG_SET(vop, 0, vop->data->intr->name, v, NORMAL) 63dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 64dbb3d944SMark Yao do { \ 65dbb3d944SMark Yao int i, reg = 0; \ 66dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 67dbb3d944SMark Yao if (vop->data->intr->intrs[i] & type) \ 68dbb3d944SMark Yao reg |= (v) << i; \ 69dbb3d944SMark Yao } \ 70dbb3d944SMark Yao VOP_INTR_SET(vop, name, reg); \ 71dbb3d944SMark Yao } while (0) 72dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 73dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 74dbb3d944SMark Yao 752048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 762048e328SMark Yao vop_read_reg(x, win->base, &win->phy->name) 772048e328SMark Yao 782048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 792048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 802048e328SMark Yao 812048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 822048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 8363ebb9faSMark Yao #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) 842048e328SMark Yao 8563ebb9faSMark Yao struct vop_plane_state { 8663ebb9faSMark Yao struct drm_plane_state base; 8763ebb9faSMark Yao int format; 8863ebb9faSMark Yao struct drm_rect src; 8963ebb9faSMark Yao struct drm_rect dest; 902048e328SMark Yao dma_addr_t yrgb_mst; 9163ebb9faSMark Yao bool enable; 922048e328SMark Yao }; 932048e328SMark Yao 942048e328SMark Yao struct vop_win { 952048e328SMark Yao struct drm_plane base; 962048e328SMark Yao const struct vop_win_data *data; 972048e328SMark Yao struct vop *vop; 982048e328SMark Yao 9963ebb9faSMark Yao struct vop_plane_state state; 1002048e328SMark Yao }; 1012048e328SMark Yao 1022048e328SMark Yao struct vop { 1032048e328SMark Yao struct drm_crtc crtc; 1042048e328SMark Yao struct device *dev; 1052048e328SMark Yao struct drm_device *drm_dev; 10631e980c5SMark Yao bool is_enabled; 1072048e328SMark Yao 1082048e328SMark Yao /* mutex vsync_ work */ 1092048e328SMark Yao struct mutex vsync_mutex; 1102048e328SMark Yao bool vsync_work_pending; 1111067219bSMark Yao struct completion dsp_hold_completion; 11263ebb9faSMark Yao struct completion wait_update_complete; 11363ebb9faSMark Yao struct drm_pending_vblank_event *event; 1142048e328SMark Yao 1152048e328SMark Yao const struct vop_data *data; 1162048e328SMark Yao 1172048e328SMark Yao uint32_t *regsbak; 1182048e328SMark Yao void __iomem *regs; 1192048e328SMark Yao 1202048e328SMark Yao /* physical map length of vop register */ 1212048e328SMark Yao uint32_t len; 1222048e328SMark Yao 1232048e328SMark Yao /* one time only one process allowed to config the register */ 1242048e328SMark Yao spinlock_t reg_lock; 1252048e328SMark Yao /* lock vop irq reg */ 1262048e328SMark Yao spinlock_t irq_lock; 1272048e328SMark Yao 1282048e328SMark Yao unsigned int irq; 1292048e328SMark Yao 1302048e328SMark Yao /* vop AHP clk */ 1312048e328SMark Yao struct clk *hclk; 1322048e328SMark Yao /* vop dclk */ 1332048e328SMark Yao struct clk *dclk; 1342048e328SMark Yao /* vop share memory frequency */ 1352048e328SMark Yao struct clk *aclk; 1362048e328SMark Yao 1372048e328SMark Yao /* vop dclk reset */ 1382048e328SMark Yao struct reset_control *dclk_rst; 1392048e328SMark Yao 1402048e328SMark Yao struct vop_win win[]; 1412048e328SMark Yao }; 1422048e328SMark Yao 1432048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1442048e328SMark Yao { 1452048e328SMark Yao writel(v, vop->regs + offset); 1462048e328SMark Yao vop->regsbak[offset >> 2] = v; 1472048e328SMark Yao } 1482048e328SMark Yao 1492048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1502048e328SMark Yao { 1512048e328SMark Yao return readl(vop->regs + offset); 1522048e328SMark Yao } 1532048e328SMark Yao 1542048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1552048e328SMark Yao const struct vop_reg *reg) 1562048e328SMark Yao { 1572048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1582048e328SMark Yao } 1592048e328SMark Yao 1602048e328SMark Yao static inline void vop_mask_write(struct vop *vop, uint32_t offset, 1612048e328SMark Yao uint32_t mask, uint32_t v) 1622048e328SMark Yao { 1632048e328SMark Yao if (mask) { 1642048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1652048e328SMark Yao 1662048e328SMark Yao cached_val = (cached_val & ~mask) | v; 1672048e328SMark Yao writel(cached_val, vop->regs + offset); 1682048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 1692048e328SMark Yao } 1702048e328SMark Yao } 1712048e328SMark Yao 1722048e328SMark Yao static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 1732048e328SMark Yao uint32_t mask, uint32_t v) 1742048e328SMark Yao { 1752048e328SMark Yao if (mask) { 1762048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1772048e328SMark Yao 1782048e328SMark Yao cached_val = (cached_val & ~mask) | v; 1792048e328SMark Yao writel_relaxed(cached_val, vop->regs + offset); 1802048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 1812048e328SMark Yao } 1822048e328SMark Yao } 1832048e328SMark Yao 184dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 185dbb3d944SMark Yao const struct vop_reg *reg, int type) 186dbb3d944SMark Yao { 187dbb3d944SMark Yao uint32_t i, ret = 0; 188dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 189dbb3d944SMark Yao 190dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 191dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 192dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 193dbb3d944SMark Yao } 194dbb3d944SMark Yao 195dbb3d944SMark Yao return ret; 196dbb3d944SMark Yao } 197dbb3d944SMark Yao 1980cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 1990cf33fe3SMark Yao { 2000cf33fe3SMark Yao VOP_CTRL_SET(vop, cfg_done, 1); 2010cf33fe3SMark Yao } 2020cf33fe3SMark Yao 20385a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 20485a359f2STomasz Figa { 20585a359f2STomasz Figa switch (format) { 20685a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 20785a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 20885a359f2STomasz Figa case DRM_FORMAT_BGR888: 20985a359f2STomasz Figa case DRM_FORMAT_BGR565: 21085a359f2STomasz Figa return true; 21185a359f2STomasz Figa default: 21285a359f2STomasz Figa return false; 21385a359f2STomasz Figa } 21485a359f2STomasz Figa } 21585a359f2STomasz Figa 2162048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2172048e328SMark Yao { 2182048e328SMark Yao switch (format) { 2192048e328SMark Yao case DRM_FORMAT_XRGB8888: 2202048e328SMark Yao case DRM_FORMAT_ARGB8888: 22185a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 22285a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2232048e328SMark Yao return VOP_FMT_ARGB8888; 2242048e328SMark Yao case DRM_FORMAT_RGB888: 22585a359f2STomasz Figa case DRM_FORMAT_BGR888: 2262048e328SMark Yao return VOP_FMT_RGB888; 2272048e328SMark Yao case DRM_FORMAT_RGB565: 22885a359f2STomasz Figa case DRM_FORMAT_BGR565: 2292048e328SMark Yao return VOP_FMT_RGB565; 2302048e328SMark Yao case DRM_FORMAT_NV12: 2312048e328SMark Yao return VOP_FMT_YUV420SP; 2322048e328SMark Yao case DRM_FORMAT_NV16: 2332048e328SMark Yao return VOP_FMT_YUV422SP; 2342048e328SMark Yao case DRM_FORMAT_NV24: 2352048e328SMark Yao return VOP_FMT_YUV444SP; 2362048e328SMark Yao default: 2372048e328SMark Yao DRM_ERROR("unsupport format[%08x]\n", format); 2382048e328SMark Yao return -EINVAL; 2392048e328SMark Yao } 2402048e328SMark Yao } 2412048e328SMark Yao 24284c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 24384c7f8caSMark Yao { 24484c7f8caSMark Yao switch (format) { 24584c7f8caSMark Yao case DRM_FORMAT_NV12: 24684c7f8caSMark Yao case DRM_FORMAT_NV16: 24784c7f8caSMark Yao case DRM_FORMAT_NV24: 24884c7f8caSMark Yao return true; 24984c7f8caSMark Yao default: 25084c7f8caSMark Yao return false; 25184c7f8caSMark Yao } 25284c7f8caSMark Yao } 25384c7f8caSMark Yao 2542048e328SMark Yao static bool is_alpha_support(uint32_t format) 2552048e328SMark Yao { 2562048e328SMark Yao switch (format) { 2572048e328SMark Yao case DRM_FORMAT_ARGB8888: 25885a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2592048e328SMark Yao return true; 2602048e328SMark Yao default: 2612048e328SMark Yao return false; 2622048e328SMark Yao } 2632048e328SMark Yao } 2642048e328SMark Yao 2654c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2664c156c21SMark Yao uint32_t dst, bool is_horizontal, 2674c156c21SMark Yao int vsu_mode, int *vskiplines) 2684c156c21SMark Yao { 2694c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2704c156c21SMark Yao 2714c156c21SMark Yao if (is_horizontal) { 2724c156c21SMark Yao if (mode == SCALE_UP) 2734c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2744c156c21SMark Yao else if (mode == SCALE_DOWN) 2754c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2764c156c21SMark Yao } else { 2774c156c21SMark Yao if (mode == SCALE_UP) { 2784c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2794c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2804c156c21SMark Yao else 2814c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2824c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2834c156c21SMark Yao if (vskiplines) { 2844c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 2854c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 2864c156c21SMark Yao *vskiplines); 2874c156c21SMark Yao } else { 2884c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2894c156c21SMark Yao } 2904c156c21SMark Yao } 2914c156c21SMark Yao } 2924c156c21SMark Yao 2934c156c21SMark Yao return val; 2944c156c21SMark Yao } 2954c156c21SMark Yao 2964c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 2974c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 2984c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 2994c156c21SMark Yao { 3004c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3014c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3024c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 3034c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 3044c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 3054c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 3064c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 3074c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 3084c156c21SMark Yao uint16_t vsu_mode; 3094c156c21SMark Yao uint16_t lb_mode; 3104c156c21SMark Yao uint32_t val; 3114c156c21SMark Yao int vskiplines; 3124c156c21SMark Yao 3134c156c21SMark Yao if (dst_w > 3840) { 3144c156c21SMark Yao DRM_ERROR("Maximum destination width (3840) exceeded\n"); 3154c156c21SMark Yao return; 3164c156c21SMark Yao } 3174c156c21SMark Yao 3181194fffbSMark Yao if (!win->phy->scl->ext) { 3191194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3201194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3211194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3221194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3231194fffbSMark Yao if (is_yuv) { 3241194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 3251194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3261194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 3271194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3281194fffbSMark Yao } 3291194fffbSMark Yao return; 3301194fffbSMark Yao } 3311194fffbSMark Yao 3324c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3334c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3344c156c21SMark Yao 3354c156c21SMark Yao if (is_yuv) { 3364c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3374c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3384c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3394c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3404c156c21SMark Yao else 3414c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3424c156c21SMark Yao } else { 3434c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3444c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3454c156c21SMark Yao else 3464c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3474c156c21SMark Yao } 3484c156c21SMark Yao 3491194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3504c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3514c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 3524c156c21SMark Yao DRM_ERROR("ERROR : not allow yrgb ver scale\n"); 3534c156c21SMark Yao return; 3544c156c21SMark Yao } 3554c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 3564c156c21SMark Yao DRM_ERROR("ERROR : not allow cbcr ver scale\n"); 3574c156c21SMark Yao return; 3584c156c21SMark Yao } 3594c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3604c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3614c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3624c156c21SMark Yao } else { 3634c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3644c156c21SMark Yao } 3654c156c21SMark Yao 3664c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3674c156c21SMark Yao true, 0, NULL); 3684c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3694c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3704c156c21SMark Yao false, vsu_mode, &vskiplines); 3714c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3724c156c21SMark Yao 3731194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3741194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3754c156c21SMark Yao 3761194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3771194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3781194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3791194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3801194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3814c156c21SMark Yao if (is_yuv) { 3824c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3834c156c21SMark Yao dst_w, true, 0, NULL); 3844c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 3854c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 3864c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 3874c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 3884c156c21SMark Yao 3891194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 3901194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 3911194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 3921194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 3931194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 3941194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 3951194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 3964c156c21SMark Yao } 3974c156c21SMark Yao } 3984c156c21SMark Yao 3991067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4001067219bSMark Yao { 4011067219bSMark Yao unsigned long flags; 4021067219bSMark Yao 4031067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4041067219bSMark Yao return; 4051067219bSMark Yao 4061067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4071067219bSMark Yao 408dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4091067219bSMark Yao 4101067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4111067219bSMark Yao } 4121067219bSMark Yao 4131067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4141067219bSMark Yao { 4151067219bSMark Yao unsigned long flags; 4161067219bSMark Yao 4171067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4181067219bSMark Yao return; 4191067219bSMark Yao 4201067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4211067219bSMark Yao 422dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4231067219bSMark Yao 4241067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4251067219bSMark Yao } 4261067219bSMark Yao 42763ebb9faSMark Yao static void vop_enable(struct drm_crtc *crtc) 4282048e328SMark Yao { 4292048e328SMark Yao struct vop *vop = to_vop(crtc); 4302048e328SMark Yao int ret; 4312048e328SMark Yao 43231e980c5SMark Yao if (vop->is_enabled) 43331e980c5SMark Yao return; 43431e980c5SMark Yao 4355d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 4365d82d1a7SMark Yao if (ret < 0) { 4375d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 4385d82d1a7SMark Yao return; 4395d82d1a7SMark Yao } 4405d82d1a7SMark Yao 4412048e328SMark Yao ret = clk_enable(vop->hclk); 4422048e328SMark Yao if (ret < 0) { 4432048e328SMark Yao dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 4442048e328SMark Yao return; 4452048e328SMark Yao } 4462048e328SMark Yao 4472048e328SMark Yao ret = clk_enable(vop->dclk); 4482048e328SMark Yao if (ret < 0) { 4492048e328SMark Yao dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 4502048e328SMark Yao goto err_disable_hclk; 4512048e328SMark Yao } 4522048e328SMark Yao 4532048e328SMark Yao ret = clk_enable(vop->aclk); 4542048e328SMark Yao if (ret < 0) { 4552048e328SMark Yao dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 4562048e328SMark Yao goto err_disable_dclk; 4572048e328SMark Yao } 4582048e328SMark Yao 4592048e328SMark Yao /* 4602048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 4612048e328SMark Yao * automatically with this master device via common driver code. 4622048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 4632048e328SMark Yao * mapping. 4642048e328SMark Yao */ 4652048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 4662048e328SMark Yao if (ret) { 4672048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 4682048e328SMark Yao goto err_disable_aclk; 4692048e328SMark Yao } 4702048e328SMark Yao 47177faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 47252ab7891SMark Yao /* 47352ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 47452ab7891SMark Yao */ 47552ab7891SMark Yao vop->is_enabled = true; 47652ab7891SMark Yao 4772048e328SMark Yao spin_lock(&vop->reg_lock); 4782048e328SMark Yao 4792048e328SMark Yao VOP_CTRL_SET(vop, standby, 0); 4802048e328SMark Yao 4812048e328SMark Yao spin_unlock(&vop->reg_lock); 4822048e328SMark Yao 4832048e328SMark Yao enable_irq(vop->irq); 4842048e328SMark Yao 485b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 4862048e328SMark Yao 4872048e328SMark Yao return; 4882048e328SMark Yao 4892048e328SMark Yao err_disable_aclk: 4902048e328SMark Yao clk_disable(vop->aclk); 4912048e328SMark Yao err_disable_dclk: 4922048e328SMark Yao clk_disable(vop->dclk); 4932048e328SMark Yao err_disable_hclk: 4942048e328SMark Yao clk_disable(vop->hclk); 4952048e328SMark Yao } 4962048e328SMark Yao 4970ad3675dSMark Yao static void vop_crtc_disable(struct drm_crtc *crtc) 4982048e328SMark Yao { 4992048e328SMark Yao struct vop *vop = to_vop(crtc); 5002048e328SMark Yao 50131e980c5SMark Yao if (!vop->is_enabled) 50231e980c5SMark Yao return; 50331e980c5SMark Yao 504b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 5052048e328SMark Yao 5062048e328SMark Yao /* 5071067219bSMark Yao * Vop standby will take effect at end of current frame, 5081067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5091067219bSMark Yao * 5101067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5111067219bSMark Yao * if not, memory bus maybe dead. 5122048e328SMark Yao */ 5131067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 5141067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 5151067219bSMark Yao 5162048e328SMark Yao spin_lock(&vop->reg_lock); 5172048e328SMark Yao 5182048e328SMark Yao VOP_CTRL_SET(vop, standby, 1); 5192048e328SMark Yao 5202048e328SMark Yao spin_unlock(&vop->reg_lock); 52152ab7891SMark Yao 5221067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 5232048e328SMark Yao 5241067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 5251067219bSMark Yao 5261067219bSMark Yao disable_irq(vop->irq); 5271067219bSMark Yao 5281067219bSMark Yao vop->is_enabled = false; 5291067219bSMark Yao 5301067219bSMark Yao /* 5311067219bSMark Yao * vop standby complete, so iommu detach is safe. 5321067219bSMark Yao */ 5332048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 5342048e328SMark Yao 5351067219bSMark Yao clk_disable(vop->dclk); 5362048e328SMark Yao clk_disable(vop->aclk); 5372048e328SMark Yao clk_disable(vop->hclk); 5385d82d1a7SMark Yao pm_runtime_put(vop->dev); 5392048e328SMark Yao } 5402048e328SMark Yao 54163ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 5422048e328SMark Yao { 54363ebb9faSMark Yao drm_plane_cleanup(plane); 5442048e328SMark Yao } 5452048e328SMark Yao 54663ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 54763ebb9faSMark Yao struct drm_plane_state *state) 5482048e328SMark Yao { 54963ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 55063ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 5512048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 55263ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 5532048e328SMark Yao const struct vop_win_data *win = vop_win->data; 5542048e328SMark Yao bool visible; 5552048e328SMark Yao int ret; 55663ebb9faSMark Yao struct drm_rect *dest = &vop_plane_state->dest; 55763ebb9faSMark Yao struct drm_rect *src = &vop_plane_state->src; 55863ebb9faSMark Yao struct drm_rect clip; 5594c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 5604c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 5614c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 5624c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 5632048e328SMark Yao 56463ebb9faSMark Yao crtc = crtc ? crtc : plane->state->crtc; 56563ebb9faSMark Yao /* 56663ebb9faSMark Yao * Both crtc or plane->state->crtc can be null. 56763ebb9faSMark Yao */ 56863ebb9faSMark Yao if (!crtc || !fb) 56963ebb9faSMark Yao goto out_disable; 57063ebb9faSMark Yao src->x1 = state->src_x; 57163ebb9faSMark Yao src->y1 = state->src_y; 57263ebb9faSMark Yao src->x2 = state->src_x + state->src_w; 57363ebb9faSMark Yao src->y2 = state->src_y + state->src_h; 57463ebb9faSMark Yao dest->x1 = state->crtc_x; 57563ebb9faSMark Yao dest->y1 = state->crtc_y; 57663ebb9faSMark Yao dest->x2 = state->crtc_x + state->crtc_w; 57763ebb9faSMark Yao dest->y2 = state->crtc_y + state->crtc_h; 57863ebb9faSMark Yao 57963ebb9faSMark Yao clip.x1 = 0; 58063ebb9faSMark Yao clip.y1 = 0; 58163ebb9faSMark Yao clip.x2 = crtc->mode.hdisplay; 58263ebb9faSMark Yao clip.y2 = crtc->mode.vdisplay; 58363ebb9faSMark Yao 58463ebb9faSMark Yao ret = drm_plane_helper_check_update(plane, crtc, state->fb, 58563ebb9faSMark Yao src, dest, &clip, 5864c156c21SMark Yao min_scale, 5874c156c21SMark Yao max_scale, 58863ebb9faSMark Yao true, true, &visible); 5892048e328SMark Yao if (ret) 5902048e328SMark Yao return ret; 5912048e328SMark Yao 5922048e328SMark Yao if (!visible) 59363ebb9faSMark Yao goto out_disable; 5942048e328SMark Yao 59563ebb9faSMark Yao vop_plane_state->format = vop_convert_format(fb->pixel_format); 59663ebb9faSMark Yao if (vop_plane_state->format < 0) 59763ebb9faSMark Yao return vop_plane_state->format; 59884c7f8caSMark Yao 59984c7f8caSMark Yao /* 60084c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 60184c7f8caSMark Yao * need align with 2 pixel. 60284c7f8caSMark Yao */ 60363ebb9faSMark Yao if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) 60463ebb9faSMark Yao return -EINVAL; 60563ebb9faSMark Yao 60663ebb9faSMark Yao vop_plane_state->enable = true; 60763ebb9faSMark Yao 60863ebb9faSMark Yao return 0; 60963ebb9faSMark Yao 61063ebb9faSMark Yao out_disable: 61163ebb9faSMark Yao vop_plane_state->enable = false; 61263ebb9faSMark Yao return 0; 61384c7f8caSMark Yao } 61484c7f8caSMark Yao 61563ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 61663ebb9faSMark Yao struct drm_plane_state *old_state) 61763ebb9faSMark Yao { 61863ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); 61963ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 62063ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 62163ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 6222048e328SMark Yao 62363ebb9faSMark Yao if (!old_state->crtc) 62463ebb9faSMark Yao return; 6252048e328SMark Yao 62663ebb9faSMark Yao spin_lock(&vop->reg_lock); 6272048e328SMark Yao 62863ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 6292048e328SMark Yao 63063ebb9faSMark Yao spin_unlock(&vop->reg_lock); 63163ebb9faSMark Yao 63263ebb9faSMark Yao vop_plane_state->enable = false; 63363ebb9faSMark Yao } 63463ebb9faSMark Yao 63563ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 63663ebb9faSMark Yao struct drm_plane_state *old_state) 63763ebb9faSMark Yao { 63863ebb9faSMark Yao struct drm_plane_state *state = plane->state; 63963ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 64063ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 64163ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 64263ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 64363ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 64463ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 64563ebb9faSMark Yao unsigned int actual_w, actual_h; 64663ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 64763ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 64863ebb9faSMark Yao struct drm_rect *src = &vop_plane_state->src; 64963ebb9faSMark Yao struct drm_rect *dest = &vop_plane_state->dest; 65063ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 65163ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 65263ebb9faSMark Yao unsigned long offset; 65363ebb9faSMark Yao dma_addr_t dma_addr; 65463ebb9faSMark Yao uint32_t val; 65563ebb9faSMark Yao bool rb_swap; 65663ebb9faSMark Yao 65763ebb9faSMark Yao /* 65863ebb9faSMark Yao * can't update plane when vop is disabled. 65963ebb9faSMark Yao */ 66063ebb9faSMark Yao if (!crtc) 66163ebb9faSMark Yao return; 66263ebb9faSMark Yao 66363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 66463ebb9faSMark Yao return; 66563ebb9faSMark Yao 66663ebb9faSMark Yao if (!vop_plane_state->enable) { 66763ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 66863ebb9faSMark Yao return; 66963ebb9faSMark Yao } 67063ebb9faSMark Yao 67163ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 67263ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 67363ebb9faSMark Yao 67463ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 67563ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 67663ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 67763ebb9faSMark Yao 67863ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 67963ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 68063ebb9faSMark Yao 68163ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 68263ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 68363ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 68463ebb9faSMark Yao 68563ebb9faSMark Yao offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 68663ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 68763ebb9faSMark Yao vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 68863ebb9faSMark Yao 68963ebb9faSMark Yao spin_lock(&vop->reg_lock); 69063ebb9faSMark Yao 69163ebb9faSMark Yao VOP_WIN_SET(vop, win, format, vop_plane_state->format); 69263ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 69363ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); 69463ebb9faSMark Yao if (is_yuv_support(fb->pixel_format)) { 69584c7f8caSMark Yao int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 69684c7f8caSMark Yao int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 69784c7f8caSMark Yao int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 69884c7f8caSMark Yao 69984c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 70084c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 70184c7f8caSMark Yao 70263ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 70363ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 70484c7f8caSMark Yao 70563ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 70663ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 70763ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 70884c7f8caSMark Yao } 7094c156c21SMark Yao 7104c156c21SMark Yao if (win->phy->scl) 7114c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 71263ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 7134c156c21SMark Yao fb->pixel_format); 7144c156c21SMark Yao 71563ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 71663ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 71763ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 7184c156c21SMark Yao 71963ebb9faSMark Yao rb_swap = has_rb_swapped(fb->pixel_format); 72085a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 7212048e328SMark Yao 72263ebb9faSMark Yao if (is_alpha_support(fb->pixel_format)) { 7232048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 7242048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 7252048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 7262048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 7272048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 7282048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 7292048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 7302048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 7312048e328SMark Yao } else { 7322048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 7332048e328SMark Yao } 7342048e328SMark Yao 7352048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 7362048e328SMark Yao spin_unlock(&vop->reg_lock); 7372048e328SMark Yao } 7382048e328SMark Yao 73963ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 74063ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 74163ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 74263ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 74363ebb9faSMark Yao }; 74463ebb9faSMark Yao 74563ebb9faSMark Yao void vop_atomic_plane_reset(struct drm_plane *plane) 7462048e328SMark Yao { 74763ebb9faSMark Yao struct vop_plane_state *vop_plane_state = 74863ebb9faSMark Yao to_vop_plane_state(plane->state); 74963ebb9faSMark Yao 75063ebb9faSMark Yao if (plane->state && plane->state->fb) 75163ebb9faSMark Yao drm_framebuffer_unreference(plane->state->fb); 75263ebb9faSMark Yao 75363ebb9faSMark Yao kfree(vop_plane_state); 75463ebb9faSMark Yao vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); 75563ebb9faSMark Yao if (!vop_plane_state) 75663ebb9faSMark Yao return; 75763ebb9faSMark Yao 75863ebb9faSMark Yao plane->state = &vop_plane_state->base; 75963ebb9faSMark Yao plane->state->plane = plane; 7602048e328SMark Yao } 7612048e328SMark Yao 76263ebb9faSMark Yao struct drm_plane_state * 76363ebb9faSMark Yao vop_atomic_plane_duplicate_state(struct drm_plane *plane) 7642048e328SMark Yao { 76563ebb9faSMark Yao struct vop_plane_state *old_vop_plane_state; 76663ebb9faSMark Yao struct vop_plane_state *vop_plane_state; 7672048e328SMark Yao 76863ebb9faSMark Yao if (WARN_ON(!plane->state)) 76963ebb9faSMark Yao return NULL; 7702048e328SMark Yao 77163ebb9faSMark Yao old_vop_plane_state = to_vop_plane_state(plane->state); 77263ebb9faSMark Yao vop_plane_state = kmemdup(old_vop_plane_state, 77363ebb9faSMark Yao sizeof(*vop_plane_state), GFP_KERNEL); 77463ebb9faSMark Yao if (!vop_plane_state) 77563ebb9faSMark Yao return NULL; 77663ebb9faSMark Yao 77763ebb9faSMark Yao __drm_atomic_helper_plane_duplicate_state(plane, 77863ebb9faSMark Yao &vop_plane_state->base); 77963ebb9faSMark Yao 78063ebb9faSMark Yao return &vop_plane_state->base; 7812048e328SMark Yao } 7822048e328SMark Yao 78363ebb9faSMark Yao static void vop_atomic_plane_destroy_state(struct drm_plane *plane, 78463ebb9faSMark Yao struct drm_plane_state *state) 7852048e328SMark Yao { 78663ebb9faSMark Yao struct vop_plane_state *vop_state = to_vop_plane_state(state); 7872048e328SMark Yao 78863ebb9faSMark Yao __drm_atomic_helper_plane_destroy_state(plane, state); 7892048e328SMark Yao 79063ebb9faSMark Yao kfree(vop_state); 7912048e328SMark Yao } 7922048e328SMark Yao 7932048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 79463ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 79563ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 7962048e328SMark Yao .destroy = vop_plane_destroy, 79763ebb9faSMark Yao .reset = vop_atomic_plane_reset, 79863ebb9faSMark Yao .atomic_duplicate_state = vop_atomic_plane_duplicate_state, 79963ebb9faSMark Yao .atomic_destroy_state = vop_atomic_plane_destroy_state, 8002048e328SMark Yao }; 8012048e328SMark Yao 8022048e328SMark Yao int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, 8032048e328SMark Yao int connector_type, 8042048e328SMark Yao int out_mode) 8052048e328SMark Yao { 8062048e328SMark Yao struct vop *vop = to_vop(crtc); 8072048e328SMark Yao 808d0e20d0eSMark Yao if (WARN_ON(!vop->is_enabled)) 809d0e20d0eSMark Yao return -EINVAL; 810d0e20d0eSMark Yao 811d0e20d0eSMark Yao switch (connector_type) { 812d0e20d0eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 813d0e20d0eSMark Yao VOP_CTRL_SET(vop, rgb_en, 1); 814d0e20d0eSMark Yao break; 815d0e20d0eSMark Yao case DRM_MODE_CONNECTOR_eDP: 816d0e20d0eSMark Yao VOP_CTRL_SET(vop, edp_en, 1); 817d0e20d0eSMark Yao break; 818d0e20d0eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 819d0e20d0eSMark Yao VOP_CTRL_SET(vop, hdmi_en, 1); 820d0e20d0eSMark Yao break; 82184e05408SChris Zhong case DRM_MODE_CONNECTOR_DSI: 82284e05408SChris Zhong VOP_CTRL_SET(vop, mipi_en, 1); 82384e05408SChris Zhong break; 824d0e20d0eSMark Yao default: 825d0e20d0eSMark Yao DRM_ERROR("unsupport connector_type[%d]\n", connector_type); 826d0e20d0eSMark Yao return -EINVAL; 827d0e20d0eSMark Yao }; 828d0e20d0eSMark Yao VOP_CTRL_SET(vop, out_mode, out_mode); 8292048e328SMark Yao 8302048e328SMark Yao return 0; 8312048e328SMark Yao } 832f66a1627SPhilipp Zabel EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); 8332048e328SMark Yao 8342048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 8352048e328SMark Yao { 8362048e328SMark Yao struct vop *vop = to_vop(crtc); 8372048e328SMark Yao unsigned long flags; 8382048e328SMark Yao 83963ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8402048e328SMark Yao return -EPERM; 8412048e328SMark Yao 8422048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 8432048e328SMark Yao 844dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 8452048e328SMark Yao 8462048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8472048e328SMark Yao 8482048e328SMark Yao return 0; 8492048e328SMark Yao } 8502048e328SMark Yao 8512048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 8522048e328SMark Yao { 8532048e328SMark Yao struct vop *vop = to_vop(crtc); 8542048e328SMark Yao unsigned long flags; 8552048e328SMark Yao 85663ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8572048e328SMark Yao return; 85831e980c5SMark Yao 8592048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 860dbb3d944SMark Yao 861dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 862dbb3d944SMark Yao 8632048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8642048e328SMark Yao } 8652048e328SMark Yao 86663ebb9faSMark Yao static void vop_crtc_wait_for_update(struct drm_crtc *crtc) 86763ebb9faSMark Yao { 86863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 86963ebb9faSMark Yao 87063ebb9faSMark Yao reinit_completion(&vop->wait_update_complete); 87163ebb9faSMark Yao WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); 87263ebb9faSMark Yao } 87363ebb9faSMark Yao 8742048e328SMark Yao static const struct rockchip_crtc_funcs private_crtc_funcs = { 8752048e328SMark Yao .enable_vblank = vop_crtc_enable_vblank, 8762048e328SMark Yao .disable_vblank = vop_crtc_disable_vblank, 87763ebb9faSMark Yao .wait_for_update = vop_crtc_wait_for_update, 8782048e328SMark Yao }; 8792048e328SMark Yao 8802048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 8812048e328SMark Yao const struct drm_display_mode *mode, 8822048e328SMark Yao struct drm_display_mode *adjusted_mode) 8832048e328SMark Yao { 884b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 885b59b8de3SChris Zhong 8862048e328SMark Yao if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) 8872048e328SMark Yao return false; 8882048e328SMark Yao 889b59b8de3SChris Zhong adjusted_mode->clock = 890b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 891b59b8de3SChris Zhong 8922048e328SMark Yao return true; 8932048e328SMark Yao } 8942048e328SMark Yao 89563ebb9faSMark Yao static void vop_crtc_enable(struct drm_crtc *crtc) 8962048e328SMark Yao { 8972048e328SMark Yao struct vop *vop = to_vop(crtc); 89863ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 8992048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 9002048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 9012048e328SMark Yao u16 htotal = adjusted_mode->htotal; 9022048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 9032048e328SMark Yao u16 hact_end = hact_st + hdisplay; 9042048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 9052048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 9062048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 9072048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 9082048e328SMark Yao u16 vact_end = vact_st + vdisplay; 9092048e328SMark Yao uint32_t val; 9102048e328SMark Yao 91163ebb9faSMark Yao vop_enable(crtc); 9122048e328SMark Yao /* 913ce3887edSMark Yao * If dclk rate is zero, mean that scanout is stop, 914ce3887edSMark Yao * we don't need wait any more. 9152048e328SMark Yao */ 916ce3887edSMark Yao if (clk_get_rate(vop->dclk)) { 917ce3887edSMark Yao /* 918ce3887edSMark Yao * Rk3288 vop timing register is immediately, when configure 919ce3887edSMark Yao * display timing on display time, may cause tearing. 920ce3887edSMark Yao * 921ce3887edSMark Yao * Vop standby will take effect at end of current frame, 922ce3887edSMark Yao * if dsp hold valid irq happen, it means standby complete. 923ce3887edSMark Yao * 924ce3887edSMark Yao * mode set: 925ce3887edSMark Yao * standby and wait complete --> |---- 926ce3887edSMark Yao * | display time 927ce3887edSMark Yao * |---- 928ce3887edSMark Yao * |---> dsp hold irq 929ce3887edSMark Yao * configure display timing --> | 930ce3887edSMark Yao * standby exit | 931ce3887edSMark Yao * | new frame start. 932ce3887edSMark Yao */ 933ce3887edSMark Yao 934ce3887edSMark Yao reinit_completion(&vop->dsp_hold_completion); 935ce3887edSMark Yao vop_dsp_hold_valid_irq_enable(vop); 936ce3887edSMark Yao 937ce3887edSMark Yao spin_lock(&vop->reg_lock); 938ce3887edSMark Yao 939ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 1); 940ce3887edSMark Yao 941ce3887edSMark Yao spin_unlock(&vop->reg_lock); 942ce3887edSMark Yao 943ce3887edSMark Yao wait_for_completion(&vop->dsp_hold_completion); 944ce3887edSMark Yao 945ce3887edSMark Yao vop_dsp_hold_valid_irq_disable(vop); 946ce3887edSMark Yao } 9472048e328SMark Yao 9482048e328SMark Yao val = 0x8; 94944ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 95044ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 9512048e328SMark Yao VOP_CTRL_SET(vop, pin_pol, val); 9522048e328SMark Yao 9532048e328SMark Yao VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 9542048e328SMark Yao val = hact_st << 16; 9552048e328SMark Yao val |= hact_end; 9562048e328SMark Yao VOP_CTRL_SET(vop, hact_st_end, val); 9572048e328SMark Yao VOP_CTRL_SET(vop, hpost_st_end, val); 9582048e328SMark Yao 9592048e328SMark Yao VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 9602048e328SMark Yao val = vact_st << 16; 9612048e328SMark Yao val |= vact_end; 9622048e328SMark Yao VOP_CTRL_SET(vop, vact_st_end, val); 9632048e328SMark Yao VOP_CTRL_SET(vop, vpost_st_end, val); 9642048e328SMark Yao 9652048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 966ce3887edSMark Yao 967ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 0); 9682048e328SMark Yao } 9692048e328SMark Yao 97063ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 97163ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 97263ebb9faSMark Yao { 97363ebb9faSMark Yao struct vop *vop = to_vop(crtc); 97463ebb9faSMark Yao 97563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 97663ebb9faSMark Yao return; 97763ebb9faSMark Yao 97863ebb9faSMark Yao spin_lock(&vop->reg_lock); 97963ebb9faSMark Yao 98063ebb9faSMark Yao vop_cfg_done(vop); 98163ebb9faSMark Yao 98263ebb9faSMark Yao spin_unlock(&vop->reg_lock); 98363ebb9faSMark Yao } 98463ebb9faSMark Yao 98563ebb9faSMark Yao static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 98663ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 98763ebb9faSMark Yao { 98863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 98963ebb9faSMark Yao 99063ebb9faSMark Yao if (crtc->state->event) { 99163ebb9faSMark Yao WARN_ON(drm_crtc_vblank_get(crtc) != 0); 99263ebb9faSMark Yao 99363ebb9faSMark Yao vop->event = crtc->state->event; 99463ebb9faSMark Yao crtc->state->event = NULL; 99563ebb9faSMark Yao } 9962048e328SMark Yao } 9972048e328SMark Yao 9982048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 9990ad3675dSMark Yao .enable = vop_crtc_enable, 10000ad3675dSMark Yao .disable = vop_crtc_disable, 10012048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 100263ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 100363ebb9faSMark Yao .atomic_begin = vop_crtc_atomic_begin, 10042048e328SMark Yao }; 10052048e328SMark Yao 10062048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 10072048e328SMark Yao { 10082048e328SMark Yao drm_crtc_cleanup(crtc); 10092048e328SMark Yao } 10102048e328SMark Yao 10112048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 101263ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 101363ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 10142048e328SMark Yao .destroy = vop_crtc_destroy, 101563ebb9faSMark Yao .reset = drm_atomic_helper_crtc_reset, 101663ebb9faSMark Yao .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 101763ebb9faSMark Yao .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 10182048e328SMark Yao }; 10192048e328SMark Yao 102063ebb9faSMark Yao static bool vop_win_pending_is_complete(struct vop_win *vop_win) 10212048e328SMark Yao { 102263ebb9faSMark Yao struct drm_plane *plane = &vop_win->base; 102363ebb9faSMark Yao struct vop_plane_state *state = to_vop_plane_state(plane->state); 10242048e328SMark Yao dma_addr_t yrgb_mst; 10252048e328SMark Yao 102663ebb9faSMark Yao if (!state->enable) 102763ebb9faSMark Yao return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; 102863ebb9faSMark Yao 10292048e328SMark Yao yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 10302048e328SMark Yao 103163ebb9faSMark Yao return yrgb_mst == state->yrgb_mst; 10322048e328SMark Yao } 10332048e328SMark Yao 103463ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 10352048e328SMark Yao { 103663ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 103763ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 103863ebb9faSMark Yao unsigned long flags; 103963ebb9faSMark Yao int i; 10402048e328SMark Yao 104163ebb9faSMark Yao for (i = 0; i < vop->data->win_size; i++) { 104263ebb9faSMark Yao if (!vop_win_pending_is_complete(&vop->win[i])) 10432048e328SMark Yao return; 10442048e328SMark Yao } 10452048e328SMark Yao 104663ebb9faSMark Yao if (vop->event) { 104763ebb9faSMark Yao spin_lock_irqsave(&drm->event_lock, flags); 10482048e328SMark Yao 104963ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 105063ebb9faSMark Yao drm_crtc_vblank_put(crtc); 105163ebb9faSMark Yao vop->event = NULL; 105263ebb9faSMark Yao 105363ebb9faSMark Yao spin_unlock_irqrestore(&drm->event_lock, flags); 10542048e328SMark Yao } 105563ebb9faSMark Yao if (!completion_done(&vop->wait_update_complete)) 105663ebb9faSMark Yao complete(&vop->wait_update_complete); 10572048e328SMark Yao } 10582048e328SMark Yao 10592048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 10602048e328SMark Yao { 10612048e328SMark Yao struct vop *vop = data; 1062b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1063dbb3d944SMark Yao uint32_t active_irqs; 10642048e328SMark Yao unsigned long flags; 10651067219bSMark Yao int ret = IRQ_NONE; 10662048e328SMark Yao 10672048e328SMark Yao /* 1068dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 10692048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 10702048e328SMark Yao */ 10712048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1072dbb3d944SMark Yao 1073dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 10742048e328SMark Yao /* Clear all active interrupt sources */ 10752048e328SMark Yao if (active_irqs) 1076dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1077dbb3d944SMark Yao 10782048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10792048e328SMark Yao 10802048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 10812048e328SMark Yao if (!active_irqs) 10822048e328SMark Yao return IRQ_NONE; 10832048e328SMark Yao 10841067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 10851067219bSMark Yao complete(&vop->dsp_hold_completion); 10861067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 10871067219bSMark Yao ret = IRQ_HANDLED; 10882048e328SMark Yao } 10892048e328SMark Yao 10901067219bSMark Yao if (active_irqs & FS_INTR) { 1091b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 109263ebb9faSMark Yao vop_handle_vblank(vop); 10931067219bSMark Yao active_irqs &= ~FS_INTR; 109463ebb9faSMark Yao ret = IRQ_HANDLED; 10951067219bSMark Yao } 10962048e328SMark Yao 10971067219bSMark Yao /* Unhandled irqs are spurious. */ 10981067219bSMark Yao if (active_irqs) 10991067219bSMark Yao DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 11001067219bSMark Yao 11011067219bSMark Yao return ret; 11022048e328SMark Yao } 11032048e328SMark Yao 11042048e328SMark Yao static int vop_create_crtc(struct vop *vop) 11052048e328SMark Yao { 11062048e328SMark Yao const struct vop_data *vop_data = vop->data; 11072048e328SMark Yao struct device *dev = vop->dev; 11082048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 11092048e328SMark Yao struct drm_plane *primary = NULL, *cursor = NULL, *plane; 11102048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 11112048e328SMark Yao struct device_node *port; 11122048e328SMark Yao int ret; 11132048e328SMark Yao int i; 11142048e328SMark Yao 11152048e328SMark Yao /* 11162048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 11172048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 11182048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 11192048e328SMark Yao */ 11202048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 11212048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 11222048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 11232048e328SMark Yao 11242048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 11252048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 11262048e328SMark Yao continue; 11272048e328SMark Yao 11282048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 11292048e328SMark Yao 0, &vop_plane_funcs, 11302048e328SMark Yao win_data->phy->data_formats, 11312048e328SMark Yao win_data->phy->nformats, 1132b0b3b795SVille Syrjälä win_data->type, NULL); 11332048e328SMark Yao if (ret) { 11342048e328SMark Yao DRM_ERROR("failed to initialize plane\n"); 11352048e328SMark Yao goto err_cleanup_planes; 11362048e328SMark Yao } 11372048e328SMark Yao 11382048e328SMark Yao plane = &vop_win->base; 113963ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 11402048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 11412048e328SMark Yao primary = plane; 11422048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 11432048e328SMark Yao cursor = plane; 11442048e328SMark Yao } 11452048e328SMark Yao 11462048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1147f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 11482048e328SMark Yao if (ret) 11492048e328SMark Yao return ret; 11502048e328SMark Yao 11512048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 11522048e328SMark Yao 11532048e328SMark Yao /* 11542048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 11552048e328SMark Yao * to the newly created crtc. 11562048e328SMark Yao */ 11572048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 11582048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 11592048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 11602048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 11612048e328SMark Yao 11622048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 11632048e328SMark Yao continue; 11642048e328SMark Yao 11652048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 11662048e328SMark Yao possible_crtcs, 11672048e328SMark Yao &vop_plane_funcs, 11682048e328SMark Yao win_data->phy->data_formats, 11692048e328SMark Yao win_data->phy->nformats, 1170b0b3b795SVille Syrjälä win_data->type, NULL); 11712048e328SMark Yao if (ret) { 11722048e328SMark Yao DRM_ERROR("failed to initialize overlay plane\n"); 11732048e328SMark Yao goto err_cleanup_crtc; 11742048e328SMark Yao } 117563ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 11762048e328SMark Yao } 11772048e328SMark Yao 11782048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 11792048e328SMark Yao if (!port) { 11802048e328SMark Yao DRM_ERROR("no port node found in %s\n", 11812048e328SMark Yao dev->of_node->full_name); 11822048e328SMark Yao goto err_cleanup_crtc; 11832048e328SMark Yao } 11842048e328SMark Yao 11851067219bSMark Yao init_completion(&vop->dsp_hold_completion); 118663ebb9faSMark Yao init_completion(&vop->wait_update_complete); 11872048e328SMark Yao crtc->port = port; 1188b5f7b755SMark Yao rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); 11892048e328SMark Yao 11902048e328SMark Yao return 0; 11912048e328SMark Yao 11922048e328SMark Yao err_cleanup_crtc: 11932048e328SMark Yao drm_crtc_cleanup(crtc); 11942048e328SMark Yao err_cleanup_planes: 11952048e328SMark Yao list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) 11962048e328SMark Yao drm_plane_cleanup(plane); 11972048e328SMark Yao return ret; 11982048e328SMark Yao } 11992048e328SMark Yao 12002048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 12012048e328SMark Yao { 12022048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12032048e328SMark Yao 1204b5f7b755SMark Yao rockchip_unregister_crtc_funcs(crtc); 12052048e328SMark Yao of_node_put(crtc->port); 12062048e328SMark Yao drm_crtc_cleanup(crtc); 12072048e328SMark Yao } 12082048e328SMark Yao 12092048e328SMark Yao static int vop_initial(struct vop *vop) 12102048e328SMark Yao { 12112048e328SMark Yao const struct vop_data *vop_data = vop->data; 12122048e328SMark Yao const struct vop_reg_data *init_table = vop_data->init_table; 12132048e328SMark Yao struct reset_control *ahb_rst; 12142048e328SMark Yao int i, ret; 12152048e328SMark Yao 12162048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 12172048e328SMark Yao if (IS_ERR(vop->hclk)) { 12182048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 12192048e328SMark Yao return PTR_ERR(vop->hclk); 12202048e328SMark Yao } 12212048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 12222048e328SMark Yao if (IS_ERR(vop->aclk)) { 12232048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 12242048e328SMark Yao return PTR_ERR(vop->aclk); 12252048e328SMark Yao } 12262048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 12272048e328SMark Yao if (IS_ERR(vop->dclk)) { 12282048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 12292048e328SMark Yao return PTR_ERR(vop->dclk); 12302048e328SMark Yao } 12312048e328SMark Yao 12322048e328SMark Yao ret = clk_prepare(vop->dclk); 12332048e328SMark Yao if (ret < 0) { 12342048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 1235d7b53fd9SSjoerd Simons return ret; 12362048e328SMark Yao } 12372048e328SMark Yao 1238d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1239d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 12402048e328SMark Yao if (ret < 0) { 1241d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable hclk\n"); 12422048e328SMark Yao goto err_unprepare_dclk; 12432048e328SMark Yao } 12442048e328SMark Yao 1245d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 12462048e328SMark Yao if (ret < 0) { 1247d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1248d7b53fd9SSjoerd Simons goto err_disable_hclk; 12492048e328SMark Yao } 1250d7b53fd9SSjoerd Simons 12512048e328SMark Yao /* 12522048e328SMark Yao * do hclk_reset, reset all vop registers. 12532048e328SMark Yao */ 12542048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 12552048e328SMark Yao if (IS_ERR(ahb_rst)) { 12562048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 12572048e328SMark Yao ret = PTR_ERR(ahb_rst); 1258d7b53fd9SSjoerd Simons goto err_disable_aclk; 12592048e328SMark Yao } 12602048e328SMark Yao reset_control_assert(ahb_rst); 12612048e328SMark Yao usleep_range(10, 20); 12622048e328SMark Yao reset_control_deassert(ahb_rst); 12632048e328SMark Yao 12642048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 12652048e328SMark Yao 12662048e328SMark Yao for (i = 0; i < vop_data->table_size; i++) 12672048e328SMark Yao vop_writel(vop, init_table[i].offset, init_table[i].value); 12682048e328SMark Yao 12692048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12702048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 12712048e328SMark Yao 12722048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 12732048e328SMark Yao } 12742048e328SMark Yao 12752048e328SMark Yao vop_cfg_done(vop); 12762048e328SMark Yao 12772048e328SMark Yao /* 12782048e328SMark Yao * do dclk_reset, let all config take affect. 12792048e328SMark Yao */ 12802048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 12812048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 12822048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 12832048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1284d7b53fd9SSjoerd Simons goto err_disable_aclk; 12852048e328SMark Yao } 12862048e328SMark Yao reset_control_assert(vop->dclk_rst); 12872048e328SMark Yao usleep_range(10, 20); 12882048e328SMark Yao reset_control_deassert(vop->dclk_rst); 12892048e328SMark Yao 12902048e328SMark Yao clk_disable(vop->hclk); 1291d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 12922048e328SMark Yao 129331e980c5SMark Yao vop->is_enabled = false; 12942048e328SMark Yao 12952048e328SMark Yao return 0; 12962048e328SMark Yao 1297d7b53fd9SSjoerd Simons err_disable_aclk: 1298d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 12992048e328SMark Yao err_disable_hclk: 1300d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 13012048e328SMark Yao err_unprepare_dclk: 13022048e328SMark Yao clk_unprepare(vop->dclk); 13032048e328SMark Yao return ret; 13042048e328SMark Yao } 13052048e328SMark Yao 13062048e328SMark Yao /* 13072048e328SMark Yao * Initialize the vop->win array elements. 13082048e328SMark Yao */ 13092048e328SMark Yao static void vop_win_init(struct vop *vop) 13102048e328SMark Yao { 13112048e328SMark Yao const struct vop_data *vop_data = vop->data; 13122048e328SMark Yao unsigned int i; 13132048e328SMark Yao 13142048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13152048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13162048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 13172048e328SMark Yao 13182048e328SMark Yao vop_win->data = win_data; 13192048e328SMark Yao vop_win->vop = vop; 13202048e328SMark Yao } 13212048e328SMark Yao } 13222048e328SMark Yao 13232048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 13242048e328SMark Yao { 13252048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 13262048e328SMark Yao const struct vop_data *vop_data; 13272048e328SMark Yao struct drm_device *drm_dev = data; 13282048e328SMark Yao struct vop *vop; 13292048e328SMark Yao struct resource *res; 13302048e328SMark Yao size_t alloc_size; 13313ea68922SHeiko Stuebner int ret, irq; 13322048e328SMark Yao 1333a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 13342048e328SMark Yao if (!vop_data) 13352048e328SMark Yao return -ENODEV; 13362048e328SMark Yao 13372048e328SMark Yao /* Allocate vop struct and its vop_win array */ 13382048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 13392048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 13402048e328SMark Yao if (!vop) 13412048e328SMark Yao return -ENOMEM; 13422048e328SMark Yao 13432048e328SMark Yao vop->dev = dev; 13442048e328SMark Yao vop->data = vop_data; 13452048e328SMark Yao vop->drm_dev = drm_dev; 13462048e328SMark Yao dev_set_drvdata(dev, vop); 13472048e328SMark Yao 13482048e328SMark Yao vop_win_init(vop); 13492048e328SMark Yao 13502048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 13512048e328SMark Yao vop->len = resource_size(res); 13522048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 13532048e328SMark Yao if (IS_ERR(vop->regs)) 13542048e328SMark Yao return PTR_ERR(vop->regs); 13552048e328SMark Yao 13562048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 13572048e328SMark Yao if (!vop->regsbak) 13582048e328SMark Yao return -ENOMEM; 13592048e328SMark Yao 13602048e328SMark Yao ret = vop_initial(vop); 13612048e328SMark Yao if (ret < 0) { 13622048e328SMark Yao dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 13632048e328SMark Yao return ret; 13642048e328SMark Yao } 13652048e328SMark Yao 13663ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 13673ea68922SHeiko Stuebner if (irq < 0) { 13682048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 13693ea68922SHeiko Stuebner return irq; 13702048e328SMark Yao } 13713ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 13722048e328SMark Yao 13732048e328SMark Yao spin_lock_init(&vop->reg_lock); 13742048e328SMark Yao spin_lock_init(&vop->irq_lock); 13752048e328SMark Yao 13762048e328SMark Yao mutex_init(&vop->vsync_mutex); 13772048e328SMark Yao 137863ebb9faSMark Yao ret = devm_request_irq(dev, vop->irq, vop_isr, 13792048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 13802048e328SMark Yao if (ret) 13812048e328SMark Yao return ret; 13822048e328SMark Yao 13832048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 13842048e328SMark Yao disable_irq(vop->irq); 13852048e328SMark Yao 13862048e328SMark Yao ret = vop_create_crtc(vop); 13872048e328SMark Yao if (ret) 13882048e328SMark Yao return ret; 13892048e328SMark Yao 13902048e328SMark Yao pm_runtime_enable(&pdev->dev); 13912048e328SMark Yao return 0; 13922048e328SMark Yao } 13932048e328SMark Yao 13942048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 13952048e328SMark Yao { 13962048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 13972048e328SMark Yao 13982048e328SMark Yao pm_runtime_disable(dev); 13992048e328SMark Yao vop_destroy_crtc(vop); 14002048e328SMark Yao } 14012048e328SMark Yao 1402a67719d1SMark Yao const struct component_ops vop_component_ops = { 14032048e328SMark Yao .bind = vop_bind, 14042048e328SMark Yao .unbind = vop_unbind, 14052048e328SMark Yao }; 140654255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1407