12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 2047a7eb45STomasz Figa #include <drm/drm_flip_work.h> 212048e328SMark Yao #include <drm/drm_plane_helper.h> 226cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 233190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 246cca3869SSean Paul #endif 252048e328SMark Yao 262048e328SMark Yao #include <linux/kernel.h> 2700fe6148SPaul Gortmaker #include <linux/module.h> 282048e328SMark Yao #include <linux/platform_device.h> 292048e328SMark Yao #include <linux/clk.h> 307caecdbeSTomasz Figa #include <linux/iopoll.h> 312048e328SMark Yao #include <linux/of.h> 322048e328SMark Yao #include <linux/of_device.h> 332048e328SMark Yao #include <linux/pm_runtime.h> 342048e328SMark Yao #include <linux/component.h> 352048e328SMark Yao 362048e328SMark Yao #include <linux/reset.h> 372048e328SMark Yao #include <linux/delay.h> 382048e328SMark Yao 392048e328SMark Yao #include "rockchip_drm_drv.h" 402048e328SMark Yao #include "rockchip_drm_gem.h" 412048e328SMark Yao #include "rockchip_drm_fb.h" 425182c1a5SYakir Yang #include "rockchip_drm_psr.h" 432048e328SMark Yao #include "rockchip_drm_vop.h" 442048e328SMark Yao 452048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 469a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 474c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 489a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 491194fffbSMark Yao #define VOP_SCL_SET_EXT(x, win, name, v) \ 509a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 519a61c54bSMark yao win->base, ~0, v, #name) 52ac6560dfSMark yao 53ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 549a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 559a61c54bSMark yao 569a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 579a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58ac6560dfSMark yao 59dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60dbb3d944SMark Yao do { \ 61c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 62dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 64dbb3d944SMark Yao reg |= (v) << i; \ 65c7647f86SJohn Keeping mask |= 1 << i; \ 66dbb3d944SMark Yao } \ 67c7647f86SJohn Keeping } \ 68ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69dbb3d944SMark Yao } while (0) 70dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 71dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 72dbb3d944SMark Yao 732048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 749a61c54bSMark yao vop_read_reg(x, win->offset, win->phy->name) 752048e328SMark Yao 762048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 772048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 782048e328SMark Yao 792048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 802048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 812048e328SMark Yao 8247a7eb45STomasz Figa enum vop_pending { 8347a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 8447a7eb45STomasz Figa }; 8547a7eb45STomasz Figa 862048e328SMark Yao struct vop_win { 872048e328SMark Yao struct drm_plane base; 882048e328SMark Yao const struct vop_win_data *data; 892048e328SMark Yao struct vop *vop; 902048e328SMark Yao }; 912048e328SMark Yao 922048e328SMark Yao struct vop { 932048e328SMark Yao struct drm_crtc crtc; 942048e328SMark Yao struct device *dev; 952048e328SMark Yao struct drm_device *drm_dev; 9631e980c5SMark Yao bool is_enabled; 972048e328SMark Yao 981067219bSMark Yao struct completion dsp_hold_completion; 994f9d39a7SDaniel Vetter 1004f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 10163ebb9faSMark Yao struct drm_pending_vblank_event *event; 1022048e328SMark Yao 10347a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 10447a7eb45STomasz Figa unsigned long pending; 10547a7eb45STomasz Figa 10669c34e41SYakir Yang struct completion line_flag_completion; 10769c34e41SYakir Yang 1082048e328SMark Yao const struct vop_data *data; 1092048e328SMark Yao 1102048e328SMark Yao uint32_t *regsbak; 1112048e328SMark Yao void __iomem *regs; 1122048e328SMark Yao 1132048e328SMark Yao /* physical map length of vop register */ 1142048e328SMark Yao uint32_t len; 1152048e328SMark Yao 1162048e328SMark Yao /* one time only one process allowed to config the register */ 1172048e328SMark Yao spinlock_t reg_lock; 1182048e328SMark Yao /* lock vop irq reg */ 1192048e328SMark Yao spinlock_t irq_lock; 1202048e328SMark Yao 1212048e328SMark Yao unsigned int irq; 1222048e328SMark Yao 1232048e328SMark Yao /* vop AHP clk */ 1242048e328SMark Yao struct clk *hclk; 1252048e328SMark Yao /* vop dclk */ 1262048e328SMark Yao struct clk *dclk; 1272048e328SMark Yao /* vop share memory frequency */ 1282048e328SMark Yao struct clk *aclk; 1292048e328SMark Yao 1302048e328SMark Yao /* vop dclk reset */ 1312048e328SMark Yao struct reset_control *dclk_rst; 1322048e328SMark Yao 1332048e328SMark Yao struct vop_win win[]; 1342048e328SMark Yao }; 1352048e328SMark Yao 1362048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1372048e328SMark Yao { 1382048e328SMark Yao writel(v, vop->regs + offset); 1392048e328SMark Yao vop->regsbak[offset >> 2] = v; 1402048e328SMark Yao } 1412048e328SMark Yao 1422048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1432048e328SMark Yao { 1442048e328SMark Yao return readl(vop->regs + offset); 1452048e328SMark Yao } 1462048e328SMark Yao 1472048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1482048e328SMark Yao const struct vop_reg *reg) 1492048e328SMark Yao { 1502048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1512048e328SMark Yao } 1522048e328SMark Yao 1539a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 1549a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 1559a61c54bSMark yao const char *reg_name) 1562048e328SMark Yao { 1579a61c54bSMark yao int offset, mask, shift; 158d49463ecSMark Yao 1599a61c54bSMark yao if (!reg || !reg->mask) { 160d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 1619a61c54bSMark yao return; 1629a61c54bSMark yao } 1639a61c54bSMark yao 1649a61c54bSMark yao offset = reg->offset + _offset; 1659a61c54bSMark yao mask = reg->mask & _mask; 1669a61c54bSMark yao shift = reg->shift; 1679a61c54bSMark yao 1689a61c54bSMark yao if (reg->write_mask) { 169d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 170d49463ecSMark Yao } else { 1712048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1722048e328SMark Yao 173d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 174d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 1752048e328SMark Yao } 1762048e328SMark Yao 1779a61c54bSMark yao if (reg->relaxed) 178d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 179d49463ecSMark Yao else 180d49463ecSMark Yao writel(v, vop->regs + offset); 1812048e328SMark Yao } 1822048e328SMark Yao 183dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 184dbb3d944SMark Yao const struct vop_reg *reg, int type) 185dbb3d944SMark Yao { 186dbb3d944SMark Yao uint32_t i, ret = 0; 187dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 188dbb3d944SMark Yao 189dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 190dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 191dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 192dbb3d944SMark Yao } 193dbb3d944SMark Yao 194dbb3d944SMark Yao return ret; 195dbb3d944SMark Yao } 196dbb3d944SMark Yao 1970cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 1980cf33fe3SMark Yao { 1999a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2000cf33fe3SMark Yao } 2010cf33fe3SMark Yao 20285a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 20385a359f2STomasz Figa { 20485a359f2STomasz Figa switch (format) { 20585a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 20685a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 20785a359f2STomasz Figa case DRM_FORMAT_BGR888: 20885a359f2STomasz Figa case DRM_FORMAT_BGR565: 20985a359f2STomasz Figa return true; 21085a359f2STomasz Figa default: 21185a359f2STomasz Figa return false; 21285a359f2STomasz Figa } 21385a359f2STomasz Figa } 21485a359f2STomasz Figa 2152048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2162048e328SMark Yao { 2172048e328SMark Yao switch (format) { 2182048e328SMark Yao case DRM_FORMAT_XRGB8888: 2192048e328SMark Yao case DRM_FORMAT_ARGB8888: 22085a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 22185a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2222048e328SMark Yao return VOP_FMT_ARGB8888; 2232048e328SMark Yao case DRM_FORMAT_RGB888: 22485a359f2STomasz Figa case DRM_FORMAT_BGR888: 2252048e328SMark Yao return VOP_FMT_RGB888; 2262048e328SMark Yao case DRM_FORMAT_RGB565: 22785a359f2STomasz Figa case DRM_FORMAT_BGR565: 2282048e328SMark Yao return VOP_FMT_RGB565; 2292048e328SMark Yao case DRM_FORMAT_NV12: 2302048e328SMark Yao return VOP_FMT_YUV420SP; 2312048e328SMark Yao case DRM_FORMAT_NV16: 2322048e328SMark Yao return VOP_FMT_YUV422SP; 2332048e328SMark Yao case DRM_FORMAT_NV24: 2342048e328SMark Yao return VOP_FMT_YUV444SP; 2352048e328SMark Yao default: 236ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2372048e328SMark Yao return -EINVAL; 2382048e328SMark Yao } 2392048e328SMark Yao } 2402048e328SMark Yao 24184c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 24284c7f8caSMark Yao { 24384c7f8caSMark Yao switch (format) { 24484c7f8caSMark Yao case DRM_FORMAT_NV12: 24584c7f8caSMark Yao case DRM_FORMAT_NV16: 24684c7f8caSMark Yao case DRM_FORMAT_NV24: 24784c7f8caSMark Yao return true; 24884c7f8caSMark Yao default: 24984c7f8caSMark Yao return false; 25084c7f8caSMark Yao } 25184c7f8caSMark Yao } 25284c7f8caSMark Yao 2534c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2544c156c21SMark Yao uint32_t dst, bool is_horizontal, 2554c156c21SMark Yao int vsu_mode, int *vskiplines) 2564c156c21SMark Yao { 2574c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2584c156c21SMark Yao 259ce91d373SJeffy Chen if (vskiplines) 260ce91d373SJeffy Chen *vskiplines = 0; 261ce91d373SJeffy Chen 2624c156c21SMark Yao if (is_horizontal) { 2634c156c21SMark Yao if (mode == SCALE_UP) 2644c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2654c156c21SMark Yao else if (mode == SCALE_DOWN) 2664c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2674c156c21SMark Yao } else { 2684c156c21SMark Yao if (mode == SCALE_UP) { 2694c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2704c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2714c156c21SMark Yao else 2724c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2734c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2744c156c21SMark Yao if (vskiplines) { 2754c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 2764c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 2774c156c21SMark Yao *vskiplines); 2784c156c21SMark Yao } else { 2794c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2804c156c21SMark Yao } 2814c156c21SMark Yao } 2824c156c21SMark Yao } 2834c156c21SMark Yao 2844c156c21SMark Yao return val; 2854c156c21SMark Yao } 2864c156c21SMark Yao 2874c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 2884c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 2894c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 2904c156c21SMark Yao { 2914c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 2924c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 2934c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 2944c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 2954c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 2964c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 2974c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 2984c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 2994c156c21SMark Yao uint16_t vsu_mode; 3004c156c21SMark Yao uint16_t lb_mode; 3014c156c21SMark Yao uint32_t val; 302ce91d373SJeffy Chen int vskiplines; 3034c156c21SMark Yao 3044c156c21SMark Yao if (dst_w > 3840) { 305ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3064c156c21SMark Yao return; 3074c156c21SMark Yao } 3084c156c21SMark Yao 3091194fffbSMark Yao if (!win->phy->scl->ext) { 3101194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3111194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3121194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3131194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3141194fffbSMark Yao if (is_yuv) { 3151194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 316ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3171194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 318ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3191194fffbSMark Yao } 3201194fffbSMark Yao return; 3211194fffbSMark Yao } 3221194fffbSMark Yao 3234c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3244c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3254c156c21SMark Yao 3264c156c21SMark Yao if (is_yuv) { 3274c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3284c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3294c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3304c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3314c156c21SMark Yao else 3324c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3334c156c21SMark Yao } else { 3344c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3354c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3364c156c21SMark Yao else 3374c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3384c156c21SMark Yao } 3394c156c21SMark Yao 3401194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3414c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3424c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 343ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3444c156c21SMark Yao return; 3454c156c21SMark Yao } 3464c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 347ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3484c156c21SMark Yao return; 3494c156c21SMark Yao } 3504c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3514c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3524c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3534c156c21SMark Yao } else { 3544c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3554c156c21SMark Yao } 3564c156c21SMark Yao 3574c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3584c156c21SMark Yao true, 0, NULL); 3594c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3604c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3614c156c21SMark Yao false, vsu_mode, &vskiplines); 3624c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3634c156c21SMark Yao 3641194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3651194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3664c156c21SMark Yao 3671194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3681194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3691194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3701194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3711194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3724c156c21SMark Yao if (is_yuv) { 3734c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3744c156c21SMark Yao dst_w, true, 0, NULL); 3754c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 3764c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 3774c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 3784c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 3794c156c21SMark Yao 3801194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 3811194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 3821194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 3831194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 3841194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 3851194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 3861194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 3874c156c21SMark Yao } 3884c156c21SMark Yao } 3894c156c21SMark Yao 3901067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 3911067219bSMark Yao { 3921067219bSMark Yao unsigned long flags; 3931067219bSMark Yao 3941067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 3951067219bSMark Yao return; 3961067219bSMark Yao 3971067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 3981067219bSMark Yao 399fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 400dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4011067219bSMark Yao 4021067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4031067219bSMark Yao } 4041067219bSMark Yao 4051067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4061067219bSMark Yao { 4071067219bSMark Yao unsigned long flags; 4081067219bSMark Yao 4091067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4101067219bSMark Yao return; 4111067219bSMark Yao 4121067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4131067219bSMark Yao 414dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4151067219bSMark Yao 4161067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4171067219bSMark Yao } 4181067219bSMark Yao 41969c34e41SYakir Yang /* 42069c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 42169c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 42269c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 42369c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 42469c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 42569c34e41SYakir Yang * 42669c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 42769c34e41SYakir Yang * Interrupts 42869c34e41SYakir Yang * LINE_FLAG -------------------------------+ 42969c34e41SYakir Yang * FRAME_SYNC ----+ | 43069c34e41SYakir Yang * | | 43169c34e41SYakir Yang * v v 43269c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 43369c34e41SYakir Yang * ^ ^ ^ ^ 43469c34e41SYakir Yang * | | | | 43569c34e41SYakir Yang * | | | | 43669c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 43769c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 43869c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 43969c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 44069c34e41SYakir Yang */ 44169c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 44269c34e41SYakir Yang { 44369c34e41SYakir Yang uint32_t line_flag_irq; 44469c34e41SYakir Yang unsigned long flags; 44569c34e41SYakir Yang 44669c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 44769c34e41SYakir Yang 44869c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 44969c34e41SYakir Yang 45069c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 45169c34e41SYakir Yang 45269c34e41SYakir Yang return !!line_flag_irq; 45369c34e41SYakir Yang } 45469c34e41SYakir Yang 455459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 45669c34e41SYakir Yang { 45769c34e41SYakir Yang unsigned long flags; 45869c34e41SYakir Yang 45969c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 46069c34e41SYakir Yang return; 46169c34e41SYakir Yang 46269c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 46369c34e41SYakir Yang 464fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 46569c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 46669c34e41SYakir Yang 46769c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 46869c34e41SYakir Yang } 46969c34e41SYakir Yang 47069c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 47169c34e41SYakir Yang { 47269c34e41SYakir Yang unsigned long flags; 47369c34e41SYakir Yang 47469c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 47569c34e41SYakir Yang return; 47669c34e41SYakir Yang 47769c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 47869c34e41SYakir Yang 47969c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 48069c34e41SYakir Yang 48169c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 48269c34e41SYakir Yang } 48369c34e41SYakir Yang 48439a9ad8fSSean Paul static int vop_enable(struct drm_crtc *crtc) 4852048e328SMark Yao { 4862048e328SMark Yao struct vop *vop = to_vop(crtc); 48764d77564SMark yao int ret, i; 4882048e328SMark Yao 4895d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 4905d82d1a7SMark Yao if (ret < 0) { 491d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 4925e570373SJeffy Chen return ret; 4935d82d1a7SMark Yao } 4945d82d1a7SMark Yao 4952048e328SMark Yao ret = clk_enable(vop->hclk); 49639a9ad8fSSean Paul if (WARN_ON(ret < 0)) 49739a9ad8fSSean Paul goto err_put_pm_runtime; 4982048e328SMark Yao 4992048e328SMark Yao ret = clk_enable(vop->dclk); 50039a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5012048e328SMark Yao goto err_disable_hclk; 5022048e328SMark Yao 5032048e328SMark Yao ret = clk_enable(vop->aclk); 50439a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5052048e328SMark Yao goto err_disable_dclk; 5062048e328SMark Yao 5072048e328SMark Yao /* 5082048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5092048e328SMark Yao * automatically with this master device via common driver code. 5102048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5112048e328SMark Yao * mapping. 5122048e328SMark Yao */ 5132048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5142048e328SMark Yao if (ret) { 515d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 516d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 5172048e328SMark Yao goto err_disable_aclk; 5182048e328SMark Yao } 5192048e328SMark Yao 52077faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 52164d77564SMark yao /* 52264d77564SMark yao * We need to make sure that all windows are disabled before we 52364d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 52464d77564SMark yao * buffer later. 52564d77564SMark yao */ 52664d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 52764d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 52864d77564SMark yao const struct vop_win_data *win = vop_win->data; 52964d77564SMark yao 53064d77564SMark yao spin_lock(&vop->reg_lock); 53164d77564SMark yao VOP_WIN_SET(vop, win, enable, 0); 53264d77564SMark yao spin_unlock(&vop->reg_lock); 53364d77564SMark yao } 53464d77564SMark yao 53517a794d7SChris Zhong vop_cfg_done(vop); 53617a794d7SChris Zhong 53752ab7891SMark Yao /* 53852ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 53952ab7891SMark Yao */ 54052ab7891SMark Yao vop->is_enabled = true; 54152ab7891SMark Yao 5422048e328SMark Yao spin_lock(&vop->reg_lock); 5432048e328SMark Yao 5449a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 5452048e328SMark Yao 5462048e328SMark Yao spin_unlock(&vop->reg_lock); 5472048e328SMark Yao 5482048e328SMark Yao enable_irq(vop->irq); 5492048e328SMark Yao 550b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 5512048e328SMark Yao 55239a9ad8fSSean Paul return 0; 5532048e328SMark Yao 5542048e328SMark Yao err_disable_aclk: 5552048e328SMark Yao clk_disable(vop->aclk); 5562048e328SMark Yao err_disable_dclk: 5572048e328SMark Yao clk_disable(vop->dclk); 5582048e328SMark Yao err_disable_hclk: 5592048e328SMark Yao clk_disable(vop->hclk); 56039a9ad8fSSean Paul err_put_pm_runtime: 56139a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 56239a9ad8fSSean Paul return ret; 5632048e328SMark Yao } 5642048e328SMark Yao 56564581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 56664581714SLaurent Pinchart struct drm_crtc_state *old_state) 5672048e328SMark Yao { 5682048e328SMark Yao struct vop *vop = to_vop(crtc); 5692048e328SMark Yao 570893b6cadSDaniel Vetter WARN_ON(vop->event); 571893b6cadSDaniel Vetter 572b883c9baSSean Paul rockchip_drm_psr_deactivate(&vop->crtc); 573b883c9baSSean Paul 574b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 5752048e328SMark Yao 5762048e328SMark Yao /* 5771067219bSMark Yao * Vop standby will take effect at end of current frame, 5781067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5791067219bSMark Yao * 5801067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5811067219bSMark Yao * if not, memory bus maybe dead. 5822048e328SMark Yao */ 5831067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 5841067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 5851067219bSMark Yao 5862048e328SMark Yao spin_lock(&vop->reg_lock); 5872048e328SMark Yao 5889a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 5892048e328SMark Yao 5902048e328SMark Yao spin_unlock(&vop->reg_lock); 59152ab7891SMark Yao 5921067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 5932048e328SMark Yao 5941067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 5951067219bSMark Yao 5961067219bSMark Yao disable_irq(vop->irq); 5971067219bSMark Yao 5981067219bSMark Yao vop->is_enabled = false; 5991067219bSMark Yao 6001067219bSMark Yao /* 6011067219bSMark Yao * vop standby complete, so iommu detach is safe. 6021067219bSMark Yao */ 6032048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6042048e328SMark Yao 6051067219bSMark Yao clk_disable(vop->dclk); 6062048e328SMark Yao clk_disable(vop->aclk); 6072048e328SMark Yao clk_disable(vop->hclk); 6085d82d1a7SMark Yao pm_runtime_put(vop->dev); 609893b6cadSDaniel Vetter 610893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 611893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 612893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 613893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 614893b6cadSDaniel Vetter 615893b6cadSDaniel Vetter crtc->state->event = NULL; 616893b6cadSDaniel Vetter } 6172048e328SMark Yao } 6182048e328SMark Yao 61963ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 6202048e328SMark Yao { 62163ebb9faSMark Yao drm_plane_cleanup(plane); 6222048e328SMark Yao } 6232048e328SMark Yao 62463ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 62563ebb9faSMark Yao struct drm_plane_state *state) 6262048e328SMark Yao { 62763ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 62892915da6SJohn Keeping struct drm_crtc_state *crtc_state; 62963ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 6302048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 6312048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6322048e328SMark Yao int ret; 6334c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 6344c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6354c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 6364c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6372048e328SMark Yao 63863ebb9faSMark Yao if (!crtc || !fb) 639d47a7246STomasz Figa return 0; 64092915da6SJohn Keeping 64192915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 64292915da6SJohn Keeping if (WARN_ON(!crtc_state)) 64392915da6SJohn Keeping return -EINVAL; 64492915da6SJohn Keeping 64581af63a4SVille Syrjälä ret = drm_atomic_helper_check_plane_state(state, crtc_state, 646f9b96be0SVille Syrjälä min_scale, max_scale, 647f9b96be0SVille Syrjälä true, true); 6482048e328SMark Yao if (ret) 6492048e328SMark Yao return ret; 6502048e328SMark Yao 651f9b96be0SVille Syrjälä if (!state->visible) 652d47a7246STomasz Figa return 0; 6532048e328SMark Yao 654438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 655d47a7246STomasz Figa if (ret < 0) 656d47a7246STomasz Figa return ret; 65784c7f8caSMark Yao 65884c7f8caSMark Yao /* 65984c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 66084c7f8caSMark Yao * need align with 2 pixel. 66184c7f8caSMark Yao */ 662d415fb87SMark yao if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) { 663d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 66463ebb9faSMark Yao return -EINVAL; 665d415fb87SMark yao } 66663ebb9faSMark Yao 66763ebb9faSMark Yao return 0; 66884c7f8caSMark Yao } 66984c7f8caSMark Yao 67063ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 67163ebb9faSMark Yao struct drm_plane_state *old_state) 67263ebb9faSMark Yao { 67363ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 67463ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 67563ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 6762048e328SMark Yao 67763ebb9faSMark Yao if (!old_state->crtc) 67863ebb9faSMark Yao return; 6792048e328SMark Yao 68063ebb9faSMark Yao spin_lock(&vop->reg_lock); 6812048e328SMark Yao 68263ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 6832048e328SMark Yao 68463ebb9faSMark Yao spin_unlock(&vop->reg_lock); 68563ebb9faSMark Yao } 68663ebb9faSMark Yao 68763ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 68863ebb9faSMark Yao struct drm_plane_state *old_state) 68963ebb9faSMark Yao { 69063ebb9faSMark Yao struct drm_plane_state *state = plane->state; 69163ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 69263ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 69363ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 69463ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 69563ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 69663ebb9faSMark Yao unsigned int actual_w, actual_h; 69763ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 69863ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 699ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 700ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 70163ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 70263ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 70363ebb9faSMark Yao unsigned long offset; 70463ebb9faSMark Yao dma_addr_t dma_addr; 70563ebb9faSMark Yao uint32_t val; 70663ebb9faSMark Yao bool rb_swap; 707d47a7246STomasz Figa int format; 70863ebb9faSMark Yao 70963ebb9faSMark Yao /* 71063ebb9faSMark Yao * can't update plane when vop is disabled. 71163ebb9faSMark Yao */ 7124f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 71363ebb9faSMark Yao return; 71463ebb9faSMark Yao 71563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 71663ebb9faSMark Yao return; 71763ebb9faSMark Yao 718d47a7246STomasz Figa if (!state->visible) { 71963ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 72063ebb9faSMark Yao return; 72163ebb9faSMark Yao } 72263ebb9faSMark Yao 72363ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 72463ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 72563ebb9faSMark Yao 72663ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 72763ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 72863ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 72963ebb9faSMark Yao 73063ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 73163ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 73263ebb9faSMark Yao 73363ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 73463ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 73563ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 73663ebb9faSMark Yao 737353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 73863ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 739d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 740d47a7246STomasz Figa 741438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 74263ebb9faSMark Yao 74363ebb9faSMark Yao spin_lock(&vop->reg_lock); 74463ebb9faSMark Yao 745d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 746da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 747d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 748438b74a5SVille Syrjälä if (is_yuv_support(fb->format->format)) { 749438b74a5SVille Syrjälä int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 750438b74a5SVille Syrjälä int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 751353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 75284c7f8caSMark Yao 75384c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 75484c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 75584c7f8caSMark Yao 75663ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 75763ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 75884c7f8caSMark Yao 75963ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 760da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 76163ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 76284c7f8caSMark Yao } 7634c156c21SMark Yao 7644c156c21SMark Yao if (win->phy->scl) 7654c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 76663ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 767438b74a5SVille Syrjälä fb->format->format); 7684c156c21SMark Yao 76963ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 77063ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 77163ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 7724c156c21SMark Yao 773438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 77485a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 7752048e328SMark Yao 7761f072d6aSMaxime Ripard if (fb->format->has_alpha) { 7772048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 7782048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 7792048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 7802048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 7812048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 7822048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 7832048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 7842048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 7852048e328SMark Yao } else { 7862048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 7872048e328SMark Yao } 7882048e328SMark Yao 7892048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 7902048e328SMark Yao spin_unlock(&vop->reg_lock); 7912048e328SMark Yao } 7922048e328SMark Yao 79363ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 79463ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 79563ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 79663ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 79763ebb9faSMark Yao }; 79863ebb9faSMark Yao 7992048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 80063ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 80163ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 8022048e328SMark Yao .destroy = vop_plane_destroy, 803d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 804d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 805d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 8062048e328SMark Yao }; 8072048e328SMark Yao 8082048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 8092048e328SMark Yao { 8102048e328SMark Yao struct vop *vop = to_vop(crtc); 8112048e328SMark Yao unsigned long flags; 8122048e328SMark Yao 81363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8142048e328SMark Yao return -EPERM; 8152048e328SMark Yao 8162048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 8172048e328SMark Yao 818fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 819dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 8202048e328SMark Yao 8212048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8222048e328SMark Yao 8232048e328SMark Yao return 0; 8242048e328SMark Yao } 8252048e328SMark Yao 8262048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 8272048e328SMark Yao { 8282048e328SMark Yao struct vop *vop = to_vop(crtc); 8292048e328SMark Yao unsigned long flags; 8302048e328SMark Yao 83163ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8322048e328SMark Yao return; 83331e980c5SMark Yao 8342048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 835dbb3d944SMark Yao 836dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 837dbb3d944SMark Yao 8382048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8392048e328SMark Yao } 8402048e328SMark Yao 8412048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 8422048e328SMark Yao const struct drm_display_mode *mode, 8432048e328SMark Yao struct drm_display_mode *adjusted_mode) 8442048e328SMark Yao { 845b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 846b59b8de3SChris Zhong 847b59b8de3SChris Zhong adjusted_mode->clock = 848b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 849b59b8de3SChris Zhong 8502048e328SMark Yao return true; 8512048e328SMark Yao } 8522048e328SMark Yao 8530b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 8540b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 8552048e328SMark Yao { 8562048e328SMark Yao struct vop *vop = to_vop(crtc); 857efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 8584e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 85963ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 8602048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 8612048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 8622048e328SMark Yao u16 htotal = adjusted_mode->htotal; 8632048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 8642048e328SMark Yao u16 hact_end = hact_st + hdisplay; 8652048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 8662048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 8672048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 8682048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 8692048e328SMark Yao u16 vact_end = vact_st + vdisplay; 8700a63bfd0SMark Yao uint32_t pin_pol, val; 87139a9ad8fSSean Paul int ret; 8722048e328SMark Yao 873893b6cadSDaniel Vetter WARN_ON(vop->event); 874893b6cadSDaniel Vetter 87539a9ad8fSSean Paul ret = vop_enable(crtc); 87639a9ad8fSSean Paul if (ret) { 87739a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 87839a9ad8fSSean Paul return; 87939a9ad8fSSean Paul } 88039a9ad8fSSean Paul 8811a0f7ed3SChris Zhong pin_pol = BIT(DCLK_INVERT); 882d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 883d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 884d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 885d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 8869a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 8870a63bfd0SMark Yao 8884e257d9eSMark Yao switch (s->output_type) { 8894e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 8909a61c54bSMark yao VOP_REG_SET(vop, output, rgb_en, 1); 8919a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 8924e257d9eSMark Yao break; 8934e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 8949a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 8959a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 8964e257d9eSMark Yao break; 8974e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 8989a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 8999a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 9004e257d9eSMark Yao break; 9014e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 9029a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 9039a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 9044e257d9eSMark Yao break; 9051a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 9061a0f7ed3SChris Zhong pin_pol &= ~BIT(DCLK_INVERT); 9079a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 9089a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 9091a0f7ed3SChris Zhong break; 9104e257d9eSMark Yao default: 911ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 912ee4d7899SSean Paul s->output_type); 9134e257d9eSMark Yao } 914efd11cc8SMark yao 915efd11cc8SMark yao /* 916efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 917efd11cc8SMark yao */ 918efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 919efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 920efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 9219a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 9222048e328SMark Yao 9239a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 9242048e328SMark Yao val = hact_st << 16; 9252048e328SMark Yao val |= hact_end; 9269a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 9279a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 9282048e328SMark Yao 9299a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 9302048e328SMark Yao val = vact_st << 16; 9312048e328SMark Yao val |= vact_end; 9329a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 9339a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 9342048e328SMark Yao 9359a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 936459b086dSJeffy Chen 9372048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 938ce3887edSMark Yao 9399a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 940b883c9baSSean Paul 941b883c9baSSean Paul rockchip_drm_psr_activate(&vop->crtc); 9422048e328SMark Yao } 9432048e328SMark Yao 9447caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 9457caecdbeSTomasz Figa { 9467caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 9477caecdbeSTomasz Figa } 9487caecdbeSTomasz Figa 9497caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 9507caecdbeSTomasz Figa { 9517caecdbeSTomasz Figa bool pending; 9527caecdbeSTomasz Figa int ret; 9537caecdbeSTomasz Figa 9547caecdbeSTomasz Figa /* 9557caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 9567caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 9577caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 9587caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 9597caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 9607caecdbeSTomasz Figa * shouldn't exceed microseconds range. 9617caecdbeSTomasz Figa */ 9627caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 9637caecdbeSTomasz Figa !pending, 0, 10 * 1000); 9647caecdbeSTomasz Figa if (ret) 9657caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 9667caecdbeSTomasz Figa 9677caecdbeSTomasz Figa synchronize_irq(vop->irq); 9687caecdbeSTomasz Figa } 9697caecdbeSTomasz Figa 97063ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 97163ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 97263ebb9faSMark Yao { 97347a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 974e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 97563ebb9faSMark Yao struct vop *vop = to_vop(crtc); 97647a7eb45STomasz Figa struct drm_plane *plane; 97747a7eb45STomasz Figa int i; 97863ebb9faSMark Yao 97963ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 98063ebb9faSMark Yao return; 98163ebb9faSMark Yao 98263ebb9faSMark Yao spin_lock(&vop->reg_lock); 98363ebb9faSMark Yao 98463ebb9faSMark Yao vop_cfg_done(vop); 98563ebb9faSMark Yao 98663ebb9faSMark Yao spin_unlock(&vop->reg_lock); 9877caecdbeSTomasz Figa 9887caecdbeSTomasz Figa /* 9897caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 9907caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 9917caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 9927caecdbeSTomasz Figa */ 9937caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 99447a7eb45STomasz Figa 99541ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 99641ee4367STomasz Figa if (crtc->state->event) { 99741ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 99841ee4367STomasz Figa WARN_ON(vop->event); 99941ee4367STomasz Figa 100041ee4367STomasz Figa vop->event = crtc->state->event; 100141ee4367STomasz Figa crtc->state->event = NULL; 100241ee4367STomasz Figa } 100341ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 100441ee4367STomasz Figa 1005e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1006e741f2b1SMaarten Lankhorst new_plane_state, i) { 100747a7eb45STomasz Figa if (!old_plane_state->fb) 100847a7eb45STomasz Figa continue; 100947a7eb45STomasz Figa 1010e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 101147a7eb45STomasz Figa continue; 101247a7eb45STomasz Figa 1013adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 101447a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 101547a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 101647a7eb45STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 101747a7eb45STomasz Figa } 101863ebb9faSMark Yao } 101963ebb9faSMark Yao 102063ebb9faSMark Yao static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 102163ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 102263ebb9faSMark Yao { 1023b883c9baSSean Paul rockchip_drm_psr_flush(crtc); 10242048e328SMark Yao } 10252048e328SMark Yao 10262048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 10272048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 102863ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 102963ebb9faSMark Yao .atomic_begin = vop_crtc_atomic_begin, 10300b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 103164581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 10322048e328SMark Yao }; 10332048e328SMark Yao 10342048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 10352048e328SMark Yao { 10362048e328SMark Yao drm_crtc_cleanup(crtc); 10372048e328SMark Yao } 10382048e328SMark Yao 1039dc0b408fSJohn Keeping static void vop_crtc_reset(struct drm_crtc *crtc) 1040dc0b408fSJohn Keeping { 1041dc0b408fSJohn Keeping if (crtc->state) 1042dc0b408fSJohn Keeping __drm_atomic_helper_crtc_destroy_state(crtc->state); 1043dc0b408fSJohn Keeping kfree(crtc->state); 1044dc0b408fSJohn Keeping 1045dc0b408fSJohn Keeping crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1046dc0b408fSJohn Keeping if (crtc->state) 1047dc0b408fSJohn Keeping crtc->state->crtc = crtc; 1048dc0b408fSJohn Keeping } 1049dc0b408fSJohn Keeping 10504e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 10514e257d9eSMark Yao { 10524e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 10534e257d9eSMark Yao 10544e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 10554e257d9eSMark Yao if (!rockchip_state) 10564e257d9eSMark Yao return NULL; 10574e257d9eSMark Yao 10584e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 10594e257d9eSMark Yao return &rockchip_state->base; 10604e257d9eSMark Yao } 10614e257d9eSMark Yao 10624e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 10634e257d9eSMark Yao struct drm_crtc_state *state) 10644e257d9eSMark Yao { 10654e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 10664e257d9eSMark Yao 1067ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 10684e257d9eSMark Yao kfree(s); 10694e257d9eSMark Yao } 10704e257d9eSMark Yao 10716cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 10723190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 10733190e58dSTomeu Vizoso { 10743190e58dSTomeu Vizoso struct drm_connector *connector; 10752cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 10763190e58dSTomeu Vizoso 10772cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 10782cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 10793190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 10802cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 10813190e58dSTomeu Vizoso return connector; 10823190e58dSTomeu Vizoso } 10832cbeb64fSGustavo Padovan } 10842cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 10853190e58dSTomeu Vizoso 10863190e58dSTomeu Vizoso return NULL; 10873190e58dSTomeu Vizoso } 10883190e58dSTomeu Vizoso 10893190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 10903190e58dSTomeu Vizoso const char *source_name, size_t *values_cnt) 10913190e58dSTomeu Vizoso { 10923190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 10933190e58dSTomeu Vizoso struct drm_connector *connector; 10943190e58dSTomeu Vizoso int ret; 10953190e58dSTomeu Vizoso 10963190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 10973190e58dSTomeu Vizoso if (!connector) 10983190e58dSTomeu Vizoso return -EINVAL; 10993190e58dSTomeu Vizoso 11003190e58dSTomeu Vizoso *values_cnt = 3; 11013190e58dSTomeu Vizoso 11023190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 11033190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 11043190e58dSTomeu Vizoso else if (!source_name) 11053190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 11063190e58dSTomeu Vizoso else 11073190e58dSTomeu Vizoso ret = -EINVAL; 11083190e58dSTomeu Vizoso 11093190e58dSTomeu Vizoso return ret; 11103190e58dSTomeu Vizoso } 11116cca3869SSean Paul #else 11126cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 11136cca3869SSean Paul const char *source_name, size_t *values_cnt) 11146cca3869SSean Paul { 11156cca3869SSean Paul return -ENODEV; 11166cca3869SSean Paul } 11176cca3869SSean Paul #endif 11183190e58dSTomeu Vizoso 11192048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 112063ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 112163ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 11222048e328SMark Yao .destroy = vop_crtc_destroy, 1123dc0b408fSJohn Keeping .reset = vop_crtc_reset, 11244e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 11254e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1126c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1127c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 11283190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 11292048e328SMark Yao }; 11302048e328SMark Yao 113147a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 113247a7eb45STomasz Figa { 113347a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 113447a7eb45STomasz Figa struct drm_framebuffer *fb = val; 113547a7eb45STomasz Figa 113647a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1137adedbf03SCihangir Akturk drm_framebuffer_put(fb); 113847a7eb45STomasz Figa } 113947a7eb45STomasz Figa 114063ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 11412048e328SMark Yao { 114263ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 114363ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 114463ebb9faSMark Yao unsigned long flags; 11452048e328SMark Yao 114663ebb9faSMark Yao spin_lock_irqsave(&drm->event_lock, flags); 1147893b6cadSDaniel Vetter if (vop->event) { 114863ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 11495b680403SSean Paul drm_crtc_vblank_put(crtc); 1150646ec687STomasz Figa vop->event = NULL; 11515b680403SSean Paul } 1152893b6cadSDaniel Vetter spin_unlock_irqrestore(&drm->event_lock, flags); 1153893b6cadSDaniel Vetter 115447a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 115547a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 11562048e328SMark Yao } 11572048e328SMark Yao 11582048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 11592048e328SMark Yao { 11602048e328SMark Yao struct vop *vop = data; 1161b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1162dbb3d944SMark Yao uint32_t active_irqs; 11632048e328SMark Yao unsigned long flags; 11641067219bSMark Yao int ret = IRQ_NONE; 11652048e328SMark Yao 11662048e328SMark Yao /* 1167dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 11682048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 11692048e328SMark Yao */ 11702048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1171dbb3d944SMark Yao 1172dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 11732048e328SMark Yao /* Clear all active interrupt sources */ 11742048e328SMark Yao if (active_irqs) 1175dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1176dbb3d944SMark Yao 11772048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11782048e328SMark Yao 11792048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 11802048e328SMark Yao if (!active_irqs) 11812048e328SMark Yao return IRQ_NONE; 11822048e328SMark Yao 11831067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 11841067219bSMark Yao complete(&vop->dsp_hold_completion); 11851067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 11861067219bSMark Yao ret = IRQ_HANDLED; 11872048e328SMark Yao } 11882048e328SMark Yao 118969c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 119069c34e41SYakir Yang complete(&vop->line_flag_completion); 119169c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 119269c34e41SYakir Yang ret = IRQ_HANDLED; 119369c34e41SYakir Yang } 119469c34e41SYakir Yang 11951067219bSMark Yao if (active_irqs & FS_INTR) { 1196b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 119763ebb9faSMark Yao vop_handle_vblank(vop); 11981067219bSMark Yao active_irqs &= ~FS_INTR; 119963ebb9faSMark Yao ret = IRQ_HANDLED; 12001067219bSMark Yao } 12012048e328SMark Yao 12021067219bSMark Yao /* Unhandled irqs are spurious. */ 12031067219bSMark Yao if (active_irqs) 1204ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1205ee4d7899SSean Paul active_irqs); 12061067219bSMark Yao 12071067219bSMark Yao return ret; 12082048e328SMark Yao } 12092048e328SMark Yao 12102048e328SMark Yao static int vop_create_crtc(struct vop *vop) 12112048e328SMark Yao { 12122048e328SMark Yao const struct vop_data *vop_data = vop->data; 12132048e328SMark Yao struct device *dev = vop->dev; 12142048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1215328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 12162048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12172048e328SMark Yao struct device_node *port; 12182048e328SMark Yao int ret; 12192048e328SMark Yao int i; 12202048e328SMark Yao 12212048e328SMark Yao /* 12222048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 12232048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 12242048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 12252048e328SMark Yao */ 12262048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12272048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12282048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12292048e328SMark Yao 12302048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 12312048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 12322048e328SMark Yao continue; 12332048e328SMark Yao 12342048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12352048e328SMark Yao 0, &vop_plane_funcs, 12362048e328SMark Yao win_data->phy->data_formats, 12372048e328SMark Yao win_data->phy->nformats, 1238e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 12392048e328SMark Yao if (ret) { 1240ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1241ee4d7899SSean Paul ret); 12422048e328SMark Yao goto err_cleanup_planes; 12432048e328SMark Yao } 12442048e328SMark Yao 12452048e328SMark Yao plane = &vop_win->base; 124663ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 12472048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 12482048e328SMark Yao primary = plane; 12492048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 12502048e328SMark Yao cursor = plane; 12512048e328SMark Yao } 12522048e328SMark Yao 12532048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1254f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 12552048e328SMark Yao if (ret) 1256328b51c0SDouglas Anderson goto err_cleanup_planes; 12572048e328SMark Yao 12582048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 12592048e328SMark Yao 12602048e328SMark Yao /* 12612048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 12622048e328SMark Yao * to the newly created crtc. 12632048e328SMark Yao */ 12642048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12652048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12662048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12672048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 12682048e328SMark Yao 12692048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 12702048e328SMark Yao continue; 12712048e328SMark Yao 12722048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12732048e328SMark Yao possible_crtcs, 12742048e328SMark Yao &vop_plane_funcs, 12752048e328SMark Yao win_data->phy->data_formats, 12762048e328SMark Yao win_data->phy->nformats, 1277e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 12782048e328SMark Yao if (ret) { 1279ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1280ee4d7899SSean Paul ret); 12812048e328SMark Yao goto err_cleanup_crtc; 12822048e328SMark Yao } 128363ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 12842048e328SMark Yao } 12852048e328SMark Yao 12862048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 12872048e328SMark Yao if (!port) { 12884bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 12894bf99144SRob Herring dev->of_node); 1290328b51c0SDouglas Anderson ret = -ENOENT; 12912048e328SMark Yao goto err_cleanup_crtc; 12922048e328SMark Yao } 12932048e328SMark Yao 129447a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 129547a7eb45STomasz Figa vop_fb_unref_worker); 129647a7eb45STomasz Figa 12971067219bSMark Yao init_completion(&vop->dsp_hold_completion); 129869c34e41SYakir Yang init_completion(&vop->line_flag_completion); 12992048e328SMark Yao crtc->port = port; 13002048e328SMark Yao 13012048e328SMark Yao return 0; 13022048e328SMark Yao 13032048e328SMark Yao err_cleanup_crtc: 13042048e328SMark Yao drm_crtc_cleanup(crtc); 13052048e328SMark Yao err_cleanup_planes: 1306328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1307328b51c0SDouglas Anderson head) 13082048e328SMark Yao drm_plane_cleanup(plane); 13092048e328SMark Yao return ret; 13102048e328SMark Yao } 13112048e328SMark Yao 13122048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 13132048e328SMark Yao { 13142048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1315328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1316328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 13172048e328SMark Yao 13182048e328SMark Yao of_node_put(crtc->port); 1319328b51c0SDouglas Anderson 1320328b51c0SDouglas Anderson /* 1321328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1322328b51c0SDouglas Anderson * 1323328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1324328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1325328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1326328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1327328b51c0SDouglas Anderson */ 1328328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1329328b51c0SDouglas Anderson head) 1330328b51c0SDouglas Anderson vop_plane_destroy(plane); 1331328b51c0SDouglas Anderson 1332328b51c0SDouglas Anderson /* 1333328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1334328b51c0SDouglas Anderson * references the CRTC. 1335328b51c0SDouglas Anderson */ 13362048e328SMark Yao drm_crtc_cleanup(crtc); 133747a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 13382048e328SMark Yao } 13392048e328SMark Yao 13402048e328SMark Yao static int vop_initial(struct vop *vop) 13412048e328SMark Yao { 13422048e328SMark Yao const struct vop_data *vop_data = vop->data; 13432048e328SMark Yao struct reset_control *ahb_rst; 13442048e328SMark Yao int i, ret; 13452048e328SMark Yao 13462048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 13472048e328SMark Yao if (IS_ERR(vop->hclk)) { 1348d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 13492048e328SMark Yao return PTR_ERR(vop->hclk); 13502048e328SMark Yao } 13512048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 13522048e328SMark Yao if (IS_ERR(vop->aclk)) { 1353d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 13542048e328SMark Yao return PTR_ERR(vop->aclk); 13552048e328SMark Yao } 13562048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 13572048e328SMark Yao if (IS_ERR(vop->dclk)) { 1358d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 13592048e328SMark Yao return PTR_ERR(vop->dclk); 13602048e328SMark Yao } 13612048e328SMark Yao 13625e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 13635e570373SJeffy Chen if (ret < 0) { 1364d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 13655e570373SJeffy Chen return ret; 13665e570373SJeffy Chen } 13675e570373SJeffy Chen 13682048e328SMark Yao ret = clk_prepare(vop->dclk); 13692048e328SMark Yao if (ret < 0) { 1370d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 13715e570373SJeffy Chen goto err_put_pm_runtime; 13722048e328SMark Yao } 13732048e328SMark Yao 1374d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1375d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 13762048e328SMark Yao if (ret < 0) { 1377d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 13782048e328SMark Yao goto err_unprepare_dclk; 13792048e328SMark Yao } 13802048e328SMark Yao 1381d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 13822048e328SMark Yao if (ret < 0) { 1383d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1384d7b53fd9SSjoerd Simons goto err_disable_hclk; 13852048e328SMark Yao } 1386d7b53fd9SSjoerd Simons 13872048e328SMark Yao /* 13882048e328SMark Yao * do hclk_reset, reset all vop registers. 13892048e328SMark Yao */ 13902048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 13912048e328SMark Yao if (IS_ERR(ahb_rst)) { 1392d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 13932048e328SMark Yao ret = PTR_ERR(ahb_rst); 1394d7b53fd9SSjoerd Simons goto err_disable_aclk; 13952048e328SMark Yao } 13962048e328SMark Yao reset_control_assert(ahb_rst); 13972048e328SMark Yao usleep_range(10, 20); 13982048e328SMark Yao reset_control_deassert(ahb_rst); 13992048e328SMark Yao 14002048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 14012048e328SMark Yao 14029a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 14039a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 14042048e328SMark Yao 14052048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14062048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 14079dd2aca4SMark yao int channel = i * 2 + 1; 14082048e328SMark Yao 14099dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 14102048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 141160b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 14122048e328SMark Yao } 14132048e328SMark Yao 14142048e328SMark Yao vop_cfg_done(vop); 14152048e328SMark Yao 14162048e328SMark Yao /* 14172048e328SMark Yao * do dclk_reset, let all config take affect. 14182048e328SMark Yao */ 14192048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 14202048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1421d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 14222048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1423d7b53fd9SSjoerd Simons goto err_disable_aclk; 14242048e328SMark Yao } 14252048e328SMark Yao reset_control_assert(vop->dclk_rst); 14262048e328SMark Yao usleep_range(10, 20); 14272048e328SMark Yao reset_control_deassert(vop->dclk_rst); 14282048e328SMark Yao 14292048e328SMark Yao clk_disable(vop->hclk); 1430d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 14312048e328SMark Yao 143231e980c5SMark Yao vop->is_enabled = false; 14332048e328SMark Yao 14345e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14355e570373SJeffy Chen 14362048e328SMark Yao return 0; 14372048e328SMark Yao 1438d7b53fd9SSjoerd Simons err_disable_aclk: 1439d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 14402048e328SMark Yao err_disable_hclk: 1441d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 14422048e328SMark Yao err_unprepare_dclk: 14432048e328SMark Yao clk_unprepare(vop->dclk); 14445e570373SJeffy Chen err_put_pm_runtime: 14455e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14462048e328SMark Yao return ret; 14472048e328SMark Yao } 14482048e328SMark Yao 14492048e328SMark Yao /* 14502048e328SMark Yao * Initialize the vop->win array elements. 14512048e328SMark Yao */ 14522048e328SMark Yao static void vop_win_init(struct vop *vop) 14532048e328SMark Yao { 14542048e328SMark Yao const struct vop_data *vop_data = vop->data; 14552048e328SMark Yao unsigned int i; 14562048e328SMark Yao 14572048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14582048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14592048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 14602048e328SMark Yao 14612048e328SMark Yao vop_win->data = win_data; 14622048e328SMark Yao vop_win->vop = vop; 14632048e328SMark Yao } 14642048e328SMark Yao } 14652048e328SMark Yao 146669c34e41SYakir Yang /** 1467459b086dSJeffy Chen * rockchip_drm_wait_vact_end 146869c34e41SYakir Yang * @crtc: CRTC to enable line flag 146969c34e41SYakir Yang * @mstimeout: millisecond for timeout 147069c34e41SYakir Yang * 1471459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 147269c34e41SYakir Yang * 147369c34e41SYakir Yang * Returns: 147469c34e41SYakir Yang * Zero on success, negative errno on failure. 147569c34e41SYakir Yang */ 1476459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 147769c34e41SYakir Yang { 147869c34e41SYakir Yang struct vop *vop = to_vop(crtc); 147969c34e41SYakir Yang unsigned long jiffies_left; 148069c34e41SYakir Yang 148169c34e41SYakir Yang if (!crtc || !vop->is_enabled) 148269c34e41SYakir Yang return -ENODEV; 148369c34e41SYakir Yang 1484459b086dSJeffy Chen if (mstimeout <= 0) 148569c34e41SYakir Yang return -EINVAL; 148669c34e41SYakir Yang 148769c34e41SYakir Yang if (vop_line_flag_irq_is_enabled(vop)) 148869c34e41SYakir Yang return -EBUSY; 148969c34e41SYakir Yang 149069c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1491459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 149269c34e41SYakir Yang 149369c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 149469c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 149569c34e41SYakir Yang vop_line_flag_irq_disable(vop); 149669c34e41SYakir Yang 149769c34e41SYakir Yang if (jiffies_left == 0) { 1498d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 149969c34e41SYakir Yang return -ETIMEDOUT; 150069c34e41SYakir Yang } 150169c34e41SYakir Yang 150269c34e41SYakir Yang return 0; 150369c34e41SYakir Yang } 1504459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 150569c34e41SYakir Yang 15062048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 15072048e328SMark Yao { 15082048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 15092048e328SMark Yao const struct vop_data *vop_data; 15102048e328SMark Yao struct drm_device *drm_dev = data; 15112048e328SMark Yao struct vop *vop; 15122048e328SMark Yao struct resource *res; 15132048e328SMark Yao size_t alloc_size; 15143ea68922SHeiko Stuebner int ret, irq; 15152048e328SMark Yao 1516a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 15172048e328SMark Yao if (!vop_data) 15182048e328SMark Yao return -ENODEV; 15192048e328SMark Yao 15202048e328SMark Yao /* Allocate vop struct and its vop_win array */ 15212048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 15222048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 15232048e328SMark Yao if (!vop) 15242048e328SMark Yao return -ENOMEM; 15252048e328SMark Yao 15262048e328SMark Yao vop->dev = dev; 15272048e328SMark Yao vop->data = vop_data; 15282048e328SMark Yao vop->drm_dev = drm_dev; 15292048e328SMark Yao dev_set_drvdata(dev, vop); 15302048e328SMark Yao 15312048e328SMark Yao vop_win_init(vop); 15322048e328SMark Yao 15332048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15342048e328SMark Yao vop->len = resource_size(res); 15352048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 15362048e328SMark Yao if (IS_ERR(vop->regs)) 15372048e328SMark Yao return PTR_ERR(vop->regs); 15382048e328SMark Yao 15392048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 15402048e328SMark Yao if (!vop->regsbak) 15412048e328SMark Yao return -ENOMEM; 15422048e328SMark Yao 15433ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 15443ea68922SHeiko Stuebner if (irq < 0) { 1545d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 15463ea68922SHeiko Stuebner return irq; 15472048e328SMark Yao } 15483ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 15492048e328SMark Yao 15502048e328SMark Yao spin_lock_init(&vop->reg_lock); 15512048e328SMark Yao spin_lock_init(&vop->irq_lock); 15522048e328SMark Yao 155363ebb9faSMark Yao ret = devm_request_irq(dev, vop->irq, vop_isr, 15542048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 15552048e328SMark Yao if (ret) 15562048e328SMark Yao return ret; 15572048e328SMark Yao 15582048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 15592048e328SMark Yao disable_irq(vop->irq); 15602048e328SMark Yao 15612048e328SMark Yao ret = vop_create_crtc(vop); 15622048e328SMark Yao if (ret) 15638c763c9bSSean Paul goto err_enable_irq; 15642048e328SMark Yao 15652048e328SMark Yao pm_runtime_enable(&pdev->dev); 15665182c1a5SYakir Yang 15675e570373SJeffy Chen ret = vop_initial(vop); 15685e570373SJeffy Chen if (ret < 0) { 1569d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 1570d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 15715e570373SJeffy Chen goto err_disable_pm_runtime; 15725e570373SJeffy Chen } 15735e570373SJeffy Chen 15742048e328SMark Yao return 0; 15758c763c9bSSean Paul 15765e570373SJeffy Chen err_disable_pm_runtime: 15775e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 15785e570373SJeffy Chen vop_destroy_crtc(vop); 15798c763c9bSSean Paul err_enable_irq: 15808c763c9bSSean Paul enable_irq(vop->irq); /* To balance out the disable_irq above */ 15818c763c9bSSean Paul return ret; 15822048e328SMark Yao } 15832048e328SMark Yao 15842048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 15852048e328SMark Yao { 15862048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 15872048e328SMark Yao 15882048e328SMark Yao pm_runtime_disable(dev); 15892048e328SMark Yao vop_destroy_crtc(vop); 1590ec6e7767SJeffy Chen 1591ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 1592ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 1593ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 15942048e328SMark Yao } 15952048e328SMark Yao 1596a67719d1SMark Yao const struct component_ops vop_component_ops = { 15972048e328SMark Yao .bind = vop_bind, 15982048e328SMark Yao .unbind = vop_unbind, 15992048e328SMark Yao }; 160054255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1601