12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 172048e328SMark Yao #include <drm/drm_crtc.h> 182048e328SMark Yao #include <drm/drm_crtc_helper.h> 192048e328SMark Yao #include <drm/drm_plane_helper.h> 202048e328SMark Yao 212048e328SMark Yao #include <linux/kernel.h> 2200fe6148SPaul Gortmaker #include <linux/module.h> 232048e328SMark Yao #include <linux/platform_device.h> 242048e328SMark Yao #include <linux/clk.h> 252048e328SMark Yao #include <linux/of.h> 262048e328SMark Yao #include <linux/of_device.h> 272048e328SMark Yao #include <linux/pm_runtime.h> 282048e328SMark Yao #include <linux/component.h> 292048e328SMark Yao 302048e328SMark Yao #include <linux/reset.h> 312048e328SMark Yao #include <linux/delay.h> 322048e328SMark Yao 332048e328SMark Yao #include "rockchip_drm_drv.h" 342048e328SMark Yao #include "rockchip_drm_gem.h" 352048e328SMark Yao #include "rockchip_drm_fb.h" 362048e328SMark Yao #include "rockchip_drm_vop.h" 372048e328SMark Yao 382048e328SMark Yao #define VOP_REG(off, _mask, s) \ 392048e328SMark Yao {.offset = off, \ 402048e328SMark Yao .mask = _mask, \ 412048e328SMark Yao .shift = s,} 422048e328SMark Yao 432048e328SMark Yao #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 442048e328SMark Yao vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 452048e328SMark Yao #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 462048e328SMark Yao vop_mask_write(x, off, (mask) << shift, (v) << shift) 472048e328SMark Yao 482048e328SMark Yao #define REG_SET(x, base, reg, v, mode) \ 492048e328SMark Yao __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 502048e328SMark Yao 512048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 522048e328SMark Yao REG_SET(x, win->base, win->phy->name, v, RELAXED) 532048e328SMark Yao #define VOP_CTRL_SET(x, name, v) \ 542048e328SMark Yao REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 552048e328SMark Yao 562048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 572048e328SMark Yao vop_read_reg(x, win->base, &win->phy->name) 582048e328SMark Yao 592048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 602048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 612048e328SMark Yao 622048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 632048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 642048e328SMark Yao 652048e328SMark Yao struct vop_win_state { 662048e328SMark Yao struct list_head head; 672048e328SMark Yao struct drm_framebuffer *fb; 682048e328SMark Yao dma_addr_t yrgb_mst; 692048e328SMark Yao struct drm_pending_vblank_event *event; 702048e328SMark Yao }; 712048e328SMark Yao 722048e328SMark Yao struct vop_win { 732048e328SMark Yao struct drm_plane base; 742048e328SMark Yao const struct vop_win_data *data; 752048e328SMark Yao struct vop *vop; 762048e328SMark Yao 772048e328SMark Yao struct list_head pending; 782048e328SMark Yao struct vop_win_state *active; 792048e328SMark Yao }; 802048e328SMark Yao 812048e328SMark Yao struct vop { 822048e328SMark Yao struct drm_crtc crtc; 832048e328SMark Yao struct device *dev; 842048e328SMark Yao struct drm_device *drm_dev; 8531e980c5SMark Yao bool is_enabled; 862048e328SMark Yao 872048e328SMark Yao int connector_type; 882048e328SMark Yao int connector_out_mode; 892048e328SMark Yao 902048e328SMark Yao /* mutex vsync_ work */ 912048e328SMark Yao struct mutex vsync_mutex; 922048e328SMark Yao bool vsync_work_pending; 931067219bSMark Yao struct completion dsp_hold_completion; 942048e328SMark Yao 952048e328SMark Yao const struct vop_data *data; 962048e328SMark Yao 972048e328SMark Yao uint32_t *regsbak; 982048e328SMark Yao void __iomem *regs; 992048e328SMark Yao 1002048e328SMark Yao /* physical map length of vop register */ 1012048e328SMark Yao uint32_t len; 1022048e328SMark Yao 1032048e328SMark Yao /* one time only one process allowed to config the register */ 1042048e328SMark Yao spinlock_t reg_lock; 1052048e328SMark Yao /* lock vop irq reg */ 1062048e328SMark Yao spinlock_t irq_lock; 1072048e328SMark Yao 1082048e328SMark Yao unsigned int irq; 1092048e328SMark Yao 1102048e328SMark Yao /* vop AHP clk */ 1112048e328SMark Yao struct clk *hclk; 1122048e328SMark Yao /* vop dclk */ 1132048e328SMark Yao struct clk *dclk; 1142048e328SMark Yao /* vop share memory frequency */ 1152048e328SMark Yao struct clk *aclk; 1162048e328SMark Yao 1172048e328SMark Yao /* vop dclk reset */ 1182048e328SMark Yao struct reset_control *dclk_rst; 1192048e328SMark Yao 1202048e328SMark Yao int pipe; 1212048e328SMark Yao 1222048e328SMark Yao struct vop_win win[]; 1232048e328SMark Yao }; 1242048e328SMark Yao 1252048e328SMark Yao enum vop_data_format { 1262048e328SMark Yao VOP_FMT_ARGB8888 = 0, 1272048e328SMark Yao VOP_FMT_RGB888, 1282048e328SMark Yao VOP_FMT_RGB565, 1292048e328SMark Yao VOP_FMT_YUV420SP = 4, 1302048e328SMark Yao VOP_FMT_YUV422SP, 1312048e328SMark Yao VOP_FMT_YUV444SP, 1322048e328SMark Yao }; 1332048e328SMark Yao 1342048e328SMark Yao struct vop_reg_data { 1352048e328SMark Yao uint32_t offset; 1362048e328SMark Yao uint32_t value; 1372048e328SMark Yao }; 1382048e328SMark Yao 1392048e328SMark Yao struct vop_reg { 1402048e328SMark Yao uint32_t offset; 1412048e328SMark Yao uint32_t shift; 1422048e328SMark Yao uint32_t mask; 1432048e328SMark Yao }; 1442048e328SMark Yao 1452048e328SMark Yao struct vop_ctrl { 1462048e328SMark Yao struct vop_reg standby; 1472048e328SMark Yao struct vop_reg data_blank; 1482048e328SMark Yao struct vop_reg gate_en; 1492048e328SMark Yao struct vop_reg mmu_en; 1502048e328SMark Yao struct vop_reg rgb_en; 1512048e328SMark Yao struct vop_reg edp_en; 1522048e328SMark Yao struct vop_reg hdmi_en; 1532048e328SMark Yao struct vop_reg mipi_en; 1542048e328SMark Yao struct vop_reg out_mode; 1552048e328SMark Yao struct vop_reg dither_down; 1562048e328SMark Yao struct vop_reg dither_up; 1572048e328SMark Yao struct vop_reg pin_pol; 1582048e328SMark Yao 1592048e328SMark Yao struct vop_reg htotal_pw; 1602048e328SMark Yao struct vop_reg hact_st_end; 1612048e328SMark Yao struct vop_reg vtotal_pw; 1622048e328SMark Yao struct vop_reg vact_st_end; 1632048e328SMark Yao struct vop_reg hpost_st_end; 1642048e328SMark Yao struct vop_reg vpost_st_end; 1652048e328SMark Yao }; 1662048e328SMark Yao 1672048e328SMark Yao struct vop_win_phy { 1682048e328SMark Yao const uint32_t *data_formats; 1692048e328SMark Yao uint32_t nformats; 1702048e328SMark Yao 1712048e328SMark Yao struct vop_reg enable; 1722048e328SMark Yao struct vop_reg format; 17385a359f2STomasz Figa struct vop_reg rb_swap; 1742048e328SMark Yao struct vop_reg act_info; 1752048e328SMark Yao struct vop_reg dsp_info; 1762048e328SMark Yao struct vop_reg dsp_st; 1772048e328SMark Yao struct vop_reg yrgb_mst; 1782048e328SMark Yao struct vop_reg uv_mst; 1792048e328SMark Yao struct vop_reg yrgb_vir; 1802048e328SMark Yao struct vop_reg uv_vir; 1812048e328SMark Yao 1822048e328SMark Yao struct vop_reg dst_alpha_ctl; 1832048e328SMark Yao struct vop_reg src_alpha_ctl; 1842048e328SMark Yao }; 1852048e328SMark Yao 1862048e328SMark Yao struct vop_win_data { 1872048e328SMark Yao uint32_t base; 1882048e328SMark Yao const struct vop_win_phy *phy; 1892048e328SMark Yao enum drm_plane_type type; 1902048e328SMark Yao }; 1912048e328SMark Yao 1922048e328SMark Yao struct vop_data { 1932048e328SMark Yao const struct vop_reg_data *init_table; 1942048e328SMark Yao unsigned int table_size; 1952048e328SMark Yao const struct vop_ctrl *ctrl; 1962048e328SMark Yao const struct vop_win_data *win; 1972048e328SMark Yao unsigned int win_size; 1982048e328SMark Yao }; 1992048e328SMark Yao 2002048e328SMark Yao static const uint32_t formats_01[] = { 2012048e328SMark Yao DRM_FORMAT_XRGB8888, 2022048e328SMark Yao DRM_FORMAT_ARGB8888, 20385a359f2STomasz Figa DRM_FORMAT_XBGR8888, 20485a359f2STomasz Figa DRM_FORMAT_ABGR8888, 2052048e328SMark Yao DRM_FORMAT_RGB888, 20685a359f2STomasz Figa DRM_FORMAT_BGR888, 2072048e328SMark Yao DRM_FORMAT_RGB565, 20885a359f2STomasz Figa DRM_FORMAT_BGR565, 2092048e328SMark Yao DRM_FORMAT_NV12, 2102048e328SMark Yao DRM_FORMAT_NV16, 2112048e328SMark Yao DRM_FORMAT_NV24, 2122048e328SMark Yao }; 2132048e328SMark Yao 2142048e328SMark Yao static const uint32_t formats_234[] = { 2152048e328SMark Yao DRM_FORMAT_XRGB8888, 2162048e328SMark Yao DRM_FORMAT_ARGB8888, 21785a359f2STomasz Figa DRM_FORMAT_XBGR8888, 21885a359f2STomasz Figa DRM_FORMAT_ABGR8888, 2192048e328SMark Yao DRM_FORMAT_RGB888, 22085a359f2STomasz Figa DRM_FORMAT_BGR888, 2212048e328SMark Yao DRM_FORMAT_RGB565, 22285a359f2STomasz Figa DRM_FORMAT_BGR565, 2232048e328SMark Yao }; 2242048e328SMark Yao 2252048e328SMark Yao static const struct vop_win_phy win01_data = { 2262048e328SMark Yao .data_formats = formats_01, 2272048e328SMark Yao .nformats = ARRAY_SIZE(formats_01), 2282048e328SMark Yao .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), 2292048e328SMark Yao .format = VOP_REG(WIN0_CTRL0, 0x7, 1), 23085a359f2STomasz Figa .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12), 2312048e328SMark Yao .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0), 2322048e328SMark Yao .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0), 2332048e328SMark Yao .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0), 2342048e328SMark Yao .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0), 2352048e328SMark Yao .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0), 2362048e328SMark Yao .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0), 2372048e328SMark Yao .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16), 2382048e328SMark Yao .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0), 2392048e328SMark Yao .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0), 2402048e328SMark Yao }; 2412048e328SMark Yao 2422048e328SMark Yao static const struct vop_win_phy win23_data = { 2432048e328SMark Yao .data_formats = formats_234, 2442048e328SMark Yao .nformats = ARRAY_SIZE(formats_234), 2452048e328SMark Yao .enable = VOP_REG(WIN2_CTRL0, 0x1, 0), 2462048e328SMark Yao .format = VOP_REG(WIN2_CTRL0, 0x7, 1), 24785a359f2STomasz Figa .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12), 2482048e328SMark Yao .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0), 2492048e328SMark Yao .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0), 2502048e328SMark Yao .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0), 2512048e328SMark Yao .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0), 2522048e328SMark Yao .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0), 2532048e328SMark Yao .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0), 2542048e328SMark Yao }; 2552048e328SMark Yao 2562048e328SMark Yao static const struct vop_ctrl ctrl_data = { 2572048e328SMark Yao .standby = VOP_REG(SYS_CTRL, 0x1, 22), 2582048e328SMark Yao .gate_en = VOP_REG(SYS_CTRL, 0x1, 23), 2592048e328SMark Yao .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20), 2602048e328SMark Yao .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12), 2612048e328SMark Yao .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13), 2622048e328SMark Yao .edp_en = VOP_REG(SYS_CTRL, 0x1, 14), 2632048e328SMark Yao .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15), 2642048e328SMark Yao .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1), 2652048e328SMark Yao .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6), 2662048e328SMark Yao .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19), 2672048e328SMark Yao .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0), 2682048e328SMark Yao .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4), 2692048e328SMark Yao .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 2702048e328SMark Yao .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0), 2712048e328SMark Yao .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 2722048e328SMark Yao .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0), 2732048e328SMark Yao .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0), 2742048e328SMark Yao .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0), 2752048e328SMark Yao }; 2762048e328SMark Yao 2772048e328SMark Yao static const struct vop_reg_data vop_init_reg_table[] = { 2782048e328SMark Yao {SYS_CTRL, 0x00c00000}, 2792048e328SMark Yao {DSP_CTRL0, 0x00000000}, 2802048e328SMark Yao {WIN0_CTRL0, 0x00000080}, 2812048e328SMark Yao {WIN1_CTRL0, 0x00000080}, 282c1998f08SMark Yao /* TODO: Win2/3 support multiple area function, but we haven't found 283c1998f08SMark Yao * a suitable way to use it yet, so let's just use them as other windows 284c1998f08SMark Yao * with only area 0 enabled. 285c1998f08SMark Yao */ 286c1998f08SMark Yao {WIN2_CTRL0, 0x00000010}, 287c1998f08SMark Yao {WIN3_CTRL0, 0x00000010}, 2882048e328SMark Yao }; 2892048e328SMark Yao 2902048e328SMark Yao /* 2912048e328SMark Yao * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 2922048e328SMark Yao * special support to get alpha blending working. For now, just use overlay 293d3cae7dfSyao mark * window 3 for the drm cursor. 294d3cae7dfSyao mark * 2952048e328SMark Yao */ 2962048e328SMark Yao static const struct vop_win_data rk3288_vop_win_data[] = { 2972048e328SMark Yao { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, 298d3cae7dfSyao mark { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY }, 2992048e328SMark Yao { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, 300d3cae7dfSyao mark { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR }, 3012048e328SMark Yao }; 3022048e328SMark Yao 3032048e328SMark Yao static const struct vop_data rk3288_vop = { 3042048e328SMark Yao .init_table = vop_init_reg_table, 3052048e328SMark Yao .table_size = ARRAY_SIZE(vop_init_reg_table), 3062048e328SMark Yao .ctrl = &ctrl_data, 3072048e328SMark Yao .win = rk3288_vop_win_data, 3082048e328SMark Yao .win_size = ARRAY_SIZE(rk3288_vop_win_data), 3092048e328SMark Yao }; 3102048e328SMark Yao 3112048e328SMark Yao static const struct of_device_id vop_driver_dt_match[] = { 3122048e328SMark Yao { .compatible = "rockchip,rk3288-vop", 3132048e328SMark Yao .data = &rk3288_vop }, 3142048e328SMark Yao {}, 3152048e328SMark Yao }; 3162048e328SMark Yao 3172048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 3182048e328SMark Yao { 3192048e328SMark Yao writel(v, vop->regs + offset); 3202048e328SMark Yao vop->regsbak[offset >> 2] = v; 3212048e328SMark Yao } 3222048e328SMark Yao 3232048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 3242048e328SMark Yao { 3252048e328SMark Yao return readl(vop->regs + offset); 3262048e328SMark Yao } 3272048e328SMark Yao 3282048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 3292048e328SMark Yao const struct vop_reg *reg) 3302048e328SMark Yao { 3312048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 3322048e328SMark Yao } 3332048e328SMark Yao 3342048e328SMark Yao static inline void vop_cfg_done(struct vop *vop) 3352048e328SMark Yao { 3362048e328SMark Yao writel(0x01, vop->regs + REG_CFG_DONE); 3372048e328SMark Yao } 3382048e328SMark Yao 3392048e328SMark Yao static inline void vop_mask_write(struct vop *vop, uint32_t offset, 3402048e328SMark Yao uint32_t mask, uint32_t v) 3412048e328SMark Yao { 3422048e328SMark Yao if (mask) { 3432048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 3442048e328SMark Yao 3452048e328SMark Yao cached_val = (cached_val & ~mask) | v; 3462048e328SMark Yao writel(cached_val, vop->regs + offset); 3472048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 3482048e328SMark Yao } 3492048e328SMark Yao } 3502048e328SMark Yao 3512048e328SMark Yao static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 3522048e328SMark Yao uint32_t mask, uint32_t v) 3532048e328SMark Yao { 3542048e328SMark Yao if (mask) { 3552048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 3562048e328SMark Yao 3572048e328SMark Yao cached_val = (cached_val & ~mask) | v; 3582048e328SMark Yao writel_relaxed(cached_val, vop->regs + offset); 3592048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 3602048e328SMark Yao } 3612048e328SMark Yao } 3622048e328SMark Yao 36385a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 36485a359f2STomasz Figa { 36585a359f2STomasz Figa switch (format) { 36685a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 36785a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 36885a359f2STomasz Figa case DRM_FORMAT_BGR888: 36985a359f2STomasz Figa case DRM_FORMAT_BGR565: 37085a359f2STomasz Figa return true; 37185a359f2STomasz Figa default: 37285a359f2STomasz Figa return false; 37385a359f2STomasz Figa } 37485a359f2STomasz Figa } 37585a359f2STomasz Figa 3762048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 3772048e328SMark Yao { 3782048e328SMark Yao switch (format) { 3792048e328SMark Yao case DRM_FORMAT_XRGB8888: 3802048e328SMark Yao case DRM_FORMAT_ARGB8888: 38185a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 38285a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 3832048e328SMark Yao return VOP_FMT_ARGB8888; 3842048e328SMark Yao case DRM_FORMAT_RGB888: 38585a359f2STomasz Figa case DRM_FORMAT_BGR888: 3862048e328SMark Yao return VOP_FMT_RGB888; 3872048e328SMark Yao case DRM_FORMAT_RGB565: 38885a359f2STomasz Figa case DRM_FORMAT_BGR565: 3892048e328SMark Yao return VOP_FMT_RGB565; 3902048e328SMark Yao case DRM_FORMAT_NV12: 3912048e328SMark Yao return VOP_FMT_YUV420SP; 3922048e328SMark Yao case DRM_FORMAT_NV16: 3932048e328SMark Yao return VOP_FMT_YUV422SP; 3942048e328SMark Yao case DRM_FORMAT_NV24: 3952048e328SMark Yao return VOP_FMT_YUV444SP; 3962048e328SMark Yao default: 3972048e328SMark Yao DRM_ERROR("unsupport format[%08x]\n", format); 3982048e328SMark Yao return -EINVAL; 3992048e328SMark Yao } 4002048e328SMark Yao } 4012048e328SMark Yao 40284c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 40384c7f8caSMark Yao { 40484c7f8caSMark Yao switch (format) { 40584c7f8caSMark Yao case DRM_FORMAT_NV12: 40684c7f8caSMark Yao case DRM_FORMAT_NV16: 40784c7f8caSMark Yao case DRM_FORMAT_NV24: 40884c7f8caSMark Yao return true; 40984c7f8caSMark Yao default: 41084c7f8caSMark Yao return false; 41184c7f8caSMark Yao } 41284c7f8caSMark Yao } 41384c7f8caSMark Yao 4142048e328SMark Yao static bool is_alpha_support(uint32_t format) 4152048e328SMark Yao { 4162048e328SMark Yao switch (format) { 4172048e328SMark Yao case DRM_FORMAT_ARGB8888: 41885a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 4192048e328SMark Yao return true; 4202048e328SMark Yao default: 4212048e328SMark Yao return false; 4222048e328SMark Yao } 4232048e328SMark Yao } 4242048e328SMark Yao 4251067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4261067219bSMark Yao { 4271067219bSMark Yao unsigned long flags; 4281067219bSMark Yao 4291067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4301067219bSMark Yao return; 4311067219bSMark Yao 4321067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4331067219bSMark Yao 4341067219bSMark Yao vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 4351067219bSMark Yao DSP_HOLD_VALID_INTR_EN(1)); 4361067219bSMark Yao 4371067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4381067219bSMark Yao } 4391067219bSMark Yao 4401067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4411067219bSMark Yao { 4421067219bSMark Yao unsigned long flags; 4431067219bSMark Yao 4441067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4451067219bSMark Yao return; 4461067219bSMark Yao 4471067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4481067219bSMark Yao 4491067219bSMark Yao vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 4501067219bSMark Yao DSP_HOLD_VALID_INTR_EN(0)); 4511067219bSMark Yao 4521067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4531067219bSMark Yao } 4541067219bSMark Yao 4552048e328SMark Yao static void vop_enable(struct drm_crtc *crtc) 4562048e328SMark Yao { 4572048e328SMark Yao struct vop *vop = to_vop(crtc); 4582048e328SMark Yao int ret; 4592048e328SMark Yao 46031e980c5SMark Yao if (vop->is_enabled) 46131e980c5SMark Yao return; 46231e980c5SMark Yao 4635d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 4645d82d1a7SMark Yao if (ret < 0) { 4655d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 4665d82d1a7SMark Yao return; 4675d82d1a7SMark Yao } 4685d82d1a7SMark Yao 4692048e328SMark Yao ret = clk_enable(vop->hclk); 4702048e328SMark Yao if (ret < 0) { 4712048e328SMark Yao dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 4722048e328SMark Yao return; 4732048e328SMark Yao } 4742048e328SMark Yao 4752048e328SMark Yao ret = clk_enable(vop->dclk); 4762048e328SMark Yao if (ret < 0) { 4772048e328SMark Yao dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 4782048e328SMark Yao goto err_disable_hclk; 4792048e328SMark Yao } 4802048e328SMark Yao 4812048e328SMark Yao ret = clk_enable(vop->aclk); 4822048e328SMark Yao if (ret < 0) { 4832048e328SMark Yao dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 4842048e328SMark Yao goto err_disable_dclk; 4852048e328SMark Yao } 4862048e328SMark Yao 4872048e328SMark Yao /* 4882048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 4892048e328SMark Yao * automatically with this master device via common driver code. 4902048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 4912048e328SMark Yao * mapping. 4922048e328SMark Yao */ 4932048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 4942048e328SMark Yao if (ret) { 4952048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 4962048e328SMark Yao goto err_disable_aclk; 4972048e328SMark Yao } 4982048e328SMark Yao 49977faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 50052ab7891SMark Yao /* 50152ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 50252ab7891SMark Yao */ 50352ab7891SMark Yao vop->is_enabled = true; 50452ab7891SMark Yao 5052048e328SMark Yao spin_lock(&vop->reg_lock); 5062048e328SMark Yao 5072048e328SMark Yao VOP_CTRL_SET(vop, standby, 0); 5082048e328SMark Yao 5092048e328SMark Yao spin_unlock(&vop->reg_lock); 5102048e328SMark Yao 5112048e328SMark Yao enable_irq(vop->irq); 5122048e328SMark Yao 5132048e328SMark Yao drm_vblank_on(vop->drm_dev, vop->pipe); 5142048e328SMark Yao 5152048e328SMark Yao return; 5162048e328SMark Yao 5172048e328SMark Yao err_disable_aclk: 5182048e328SMark Yao clk_disable(vop->aclk); 5192048e328SMark Yao err_disable_dclk: 5202048e328SMark Yao clk_disable(vop->dclk); 5212048e328SMark Yao err_disable_hclk: 5222048e328SMark Yao clk_disable(vop->hclk); 5232048e328SMark Yao } 5242048e328SMark Yao 5252048e328SMark Yao static void vop_disable(struct drm_crtc *crtc) 5262048e328SMark Yao { 5272048e328SMark Yao struct vop *vop = to_vop(crtc); 5282048e328SMark Yao 52931e980c5SMark Yao if (!vop->is_enabled) 53031e980c5SMark Yao return; 53131e980c5SMark Yao 5322048e328SMark Yao drm_vblank_off(crtc->dev, vop->pipe); 5332048e328SMark Yao 5342048e328SMark Yao /* 5351067219bSMark Yao * Vop standby will take effect at end of current frame, 5361067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5371067219bSMark Yao * 5381067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5391067219bSMark Yao * if not, memory bus maybe dead. 5402048e328SMark Yao */ 5411067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 5421067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 5431067219bSMark Yao 5442048e328SMark Yao spin_lock(&vop->reg_lock); 5452048e328SMark Yao 5462048e328SMark Yao VOP_CTRL_SET(vop, standby, 1); 5472048e328SMark Yao 5482048e328SMark Yao spin_unlock(&vop->reg_lock); 54952ab7891SMark Yao 5501067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 5512048e328SMark Yao 5521067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 5531067219bSMark Yao 5541067219bSMark Yao disable_irq(vop->irq); 5551067219bSMark Yao 5561067219bSMark Yao vop->is_enabled = false; 5571067219bSMark Yao 5581067219bSMark Yao /* 5591067219bSMark Yao * vop standby complete, so iommu detach is safe. 5601067219bSMark Yao */ 5612048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 5622048e328SMark Yao 5631067219bSMark Yao clk_disable(vop->dclk); 5642048e328SMark Yao clk_disable(vop->aclk); 5652048e328SMark Yao clk_disable(vop->hclk); 5665d82d1a7SMark Yao pm_runtime_put(vop->dev); 5672048e328SMark Yao } 5682048e328SMark Yao 5692048e328SMark Yao /* 5702048e328SMark Yao * Caller must hold vsync_mutex. 5712048e328SMark Yao */ 5722048e328SMark Yao static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win) 5732048e328SMark Yao { 5742048e328SMark Yao struct vop_win_state *last; 5752048e328SMark Yao struct vop_win_state *active = vop_win->active; 5762048e328SMark Yao 5772048e328SMark Yao if (list_empty(&vop_win->pending)) 5782048e328SMark Yao return active ? active->fb : NULL; 5792048e328SMark Yao 5802048e328SMark Yao last = list_last_entry(&vop_win->pending, struct vop_win_state, head); 5812048e328SMark Yao return last ? last->fb : NULL; 5822048e328SMark Yao } 5832048e328SMark Yao 5842048e328SMark Yao /* 5852048e328SMark Yao * Caller must hold vsync_mutex. 5862048e328SMark Yao */ 5872048e328SMark Yao static int vop_win_queue_fb(struct vop_win *vop_win, 5882048e328SMark Yao struct drm_framebuffer *fb, dma_addr_t yrgb_mst, 5892048e328SMark Yao struct drm_pending_vblank_event *event) 5902048e328SMark Yao { 5912048e328SMark Yao struct vop_win_state *state; 5922048e328SMark Yao 5932048e328SMark Yao state = kzalloc(sizeof(*state), GFP_KERNEL); 5942048e328SMark Yao if (!state) 5952048e328SMark Yao return -ENOMEM; 5962048e328SMark Yao 5972048e328SMark Yao state->fb = fb; 5982048e328SMark Yao state->yrgb_mst = yrgb_mst; 5992048e328SMark Yao state->event = event; 6002048e328SMark Yao 6012048e328SMark Yao list_add_tail(&state->head, &vop_win->pending); 6022048e328SMark Yao 6032048e328SMark Yao return 0; 6042048e328SMark Yao } 6052048e328SMark Yao 6062048e328SMark Yao static int vop_update_plane_event(struct drm_plane *plane, 6072048e328SMark Yao struct drm_crtc *crtc, 6082048e328SMark Yao struct drm_framebuffer *fb, int crtc_x, 6092048e328SMark Yao int crtc_y, unsigned int crtc_w, 6102048e328SMark Yao unsigned int crtc_h, uint32_t src_x, 6112048e328SMark Yao uint32_t src_y, uint32_t src_w, 6122048e328SMark Yao uint32_t src_h, 6132048e328SMark Yao struct drm_pending_vblank_event *event) 6142048e328SMark Yao { 6152048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 6162048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6172048e328SMark Yao struct vop *vop = to_vop(crtc); 6182048e328SMark Yao struct drm_gem_object *obj; 6192048e328SMark Yao struct rockchip_gem_object *rk_obj; 62084c7f8caSMark Yao struct drm_gem_object *uv_obj; 62184c7f8caSMark Yao struct rockchip_gem_object *rk_uv_obj; 6222048e328SMark Yao unsigned long offset; 6232048e328SMark Yao unsigned int actual_w; 6242048e328SMark Yao unsigned int actual_h; 6252048e328SMark Yao unsigned int dsp_stx; 6262048e328SMark Yao unsigned int dsp_sty; 6272048e328SMark Yao unsigned int y_vir_stride; 62884c7f8caSMark Yao unsigned int uv_vir_stride = 0; 6292048e328SMark Yao dma_addr_t yrgb_mst; 63084c7f8caSMark Yao dma_addr_t uv_mst = 0; 6312048e328SMark Yao enum vop_data_format format; 6322048e328SMark Yao uint32_t val; 6332048e328SMark Yao bool is_alpha; 63485a359f2STomasz Figa bool rb_swap; 63584c7f8caSMark Yao bool is_yuv; 6362048e328SMark Yao bool visible; 6372048e328SMark Yao int ret; 6382048e328SMark Yao struct drm_rect dest = { 6392048e328SMark Yao .x1 = crtc_x, 6402048e328SMark Yao .y1 = crtc_y, 6412048e328SMark Yao .x2 = crtc_x + crtc_w, 6422048e328SMark Yao .y2 = crtc_y + crtc_h, 6432048e328SMark Yao }; 6442048e328SMark Yao struct drm_rect src = { 6452048e328SMark Yao /* 16.16 fixed point */ 6462048e328SMark Yao .x1 = src_x, 6472048e328SMark Yao .y1 = src_y, 6482048e328SMark Yao .x2 = src_x + src_w, 6492048e328SMark Yao .y2 = src_y + src_h, 6502048e328SMark Yao }; 6512048e328SMark Yao const struct drm_rect clip = { 6522048e328SMark Yao .x2 = crtc->mode.hdisplay, 6532048e328SMark Yao .y2 = crtc->mode.vdisplay, 6542048e328SMark Yao }; 6552048e328SMark Yao bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY; 6562048e328SMark Yao 6572048e328SMark Yao ret = drm_plane_helper_check_update(plane, crtc, fb, 6582048e328SMark Yao &src, &dest, &clip, 6592048e328SMark Yao DRM_PLANE_HELPER_NO_SCALING, 6602048e328SMark Yao DRM_PLANE_HELPER_NO_SCALING, 6612048e328SMark Yao can_position, false, &visible); 6622048e328SMark Yao if (ret) 6632048e328SMark Yao return ret; 6642048e328SMark Yao 6652048e328SMark Yao if (!visible) 6662048e328SMark Yao return 0; 6672048e328SMark Yao 6682048e328SMark Yao is_alpha = is_alpha_support(fb->pixel_format); 66985a359f2STomasz Figa rb_swap = has_rb_swapped(fb->pixel_format); 67084c7f8caSMark Yao is_yuv = is_yuv_support(fb->pixel_format); 67184c7f8caSMark Yao 6722048e328SMark Yao format = vop_convert_format(fb->pixel_format); 6732048e328SMark Yao if (format < 0) 6742048e328SMark Yao return format; 6752048e328SMark Yao 6762048e328SMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 6772048e328SMark Yao if (!obj) { 6782048e328SMark Yao DRM_ERROR("fail to get rockchip gem object from framebuffer\n"); 6792048e328SMark Yao return -EINVAL; 6802048e328SMark Yao } 6812048e328SMark Yao 6822048e328SMark Yao rk_obj = to_rockchip_obj(obj); 6832048e328SMark Yao 68484c7f8caSMark Yao if (is_yuv) { 68584c7f8caSMark Yao /* 68684c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 68784c7f8caSMark Yao * need align with 2 pixel. 68884c7f8caSMark Yao */ 68984c7f8caSMark Yao val = (src.x1 >> 16) % 2; 69084c7f8caSMark Yao src.x1 += val << 16; 69184c7f8caSMark Yao src.x2 += val << 16; 69284c7f8caSMark Yao } 69384c7f8caSMark Yao 6942048e328SMark Yao actual_w = (src.x2 - src.x1) >> 16; 6952048e328SMark Yao actual_h = (src.y2 - src.y1) >> 16; 6962048e328SMark Yao 697acf8c3e0SMark Yao dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start; 698acf8c3e0SMark Yao dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 6992048e328SMark Yao 70084c7f8caSMark Yao offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 7012048e328SMark Yao offset += (src.y1 >> 16) * fb->pitches[0]; 7022048e328SMark Yao 70384c7f8caSMark Yao yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 704f1c79abeSMark Yao y_vir_stride = fb->pitches[0] >> 2; 7052048e328SMark Yao 70684c7f8caSMark Yao if (is_yuv) { 70784c7f8caSMark Yao int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 70884c7f8caSMark Yao int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 70984c7f8caSMark Yao int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 71084c7f8caSMark Yao 71184c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 71284c7f8caSMark Yao if (!uv_obj) { 71384c7f8caSMark Yao DRM_ERROR("fail to get uv object from framebuffer\n"); 71484c7f8caSMark Yao return -EINVAL; 71584c7f8caSMark Yao } 71684c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 71784c7f8caSMark Yao uv_vir_stride = fb->pitches[1] >> 2; 71884c7f8caSMark Yao 71984c7f8caSMark Yao offset = (src.x1 >> 16) * bpp / hsub; 72084c7f8caSMark Yao offset += (src.y1 >> 16) * fb->pitches[1] / vsub; 72184c7f8caSMark Yao 72284c7f8caSMark Yao uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 72384c7f8caSMark Yao } 72484c7f8caSMark Yao 7252048e328SMark Yao /* 7262048e328SMark Yao * If this plane update changes the plane's framebuffer, (or more 7272048e328SMark Yao * precisely, if this update has a different framebuffer than the last 7282048e328SMark Yao * update), enqueue it so we can track when it completes. 7292048e328SMark Yao * 7302048e328SMark Yao * Only when we discover that this update has completed, can we 7312048e328SMark Yao * unreference any previous framebuffers. 7322048e328SMark Yao */ 7332048e328SMark Yao mutex_lock(&vop->vsync_mutex); 7342048e328SMark Yao if (fb != vop_win_last_pending_fb(vop_win)) { 7352048e328SMark Yao ret = drm_vblank_get(plane->dev, vop->pipe); 7362048e328SMark Yao if (ret) { 7372048e328SMark Yao DRM_ERROR("failed to get vblank, %d\n", ret); 7382048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 7392048e328SMark Yao return ret; 7402048e328SMark Yao } 7412048e328SMark Yao 7422048e328SMark Yao drm_framebuffer_reference(fb); 7432048e328SMark Yao 7442048e328SMark Yao ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event); 7452048e328SMark Yao if (ret) { 7462048e328SMark Yao drm_vblank_put(plane->dev, vop->pipe); 7472048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 7482048e328SMark Yao return ret; 7492048e328SMark Yao } 7502048e328SMark Yao 7512048e328SMark Yao vop->vsync_work_pending = true; 7522048e328SMark Yao } 7532048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 7542048e328SMark Yao 7552048e328SMark Yao spin_lock(&vop->reg_lock); 7562048e328SMark Yao 7572048e328SMark Yao VOP_WIN_SET(vop, win, format, format); 7582048e328SMark Yao VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride); 7592048e328SMark Yao VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst); 76084c7f8caSMark Yao if (is_yuv) { 76184c7f8caSMark Yao VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride); 76284c7f8caSMark Yao VOP_WIN_SET(vop, win, uv_mst, uv_mst); 76384c7f8caSMark Yao } 7642048e328SMark Yao val = (actual_h - 1) << 16; 7652048e328SMark Yao val |= (actual_w - 1) & 0xffff; 7662048e328SMark Yao VOP_WIN_SET(vop, win, act_info, val); 7672048e328SMark Yao VOP_WIN_SET(vop, win, dsp_info, val); 7682048e328SMark Yao val = (dsp_sty - 1) << 16; 7692048e328SMark Yao val |= (dsp_stx - 1) & 0xffff; 7702048e328SMark Yao VOP_WIN_SET(vop, win, dsp_st, val); 77185a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 7722048e328SMark Yao 7732048e328SMark Yao if (is_alpha) { 7742048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 7752048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 7762048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 7772048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 7782048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 7792048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 7802048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 7812048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 7822048e328SMark Yao } else { 7832048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 7842048e328SMark Yao } 7852048e328SMark Yao 7862048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 7872048e328SMark Yao 7882048e328SMark Yao vop_cfg_done(vop); 7892048e328SMark Yao spin_unlock(&vop->reg_lock); 7902048e328SMark Yao 7912048e328SMark Yao return 0; 7922048e328SMark Yao } 7932048e328SMark Yao 7942048e328SMark Yao static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 7952048e328SMark Yao struct drm_framebuffer *fb, int crtc_x, int crtc_y, 7962048e328SMark Yao unsigned int crtc_w, unsigned int crtc_h, 7972048e328SMark Yao uint32_t src_x, uint32_t src_y, uint32_t src_w, 7982048e328SMark Yao uint32_t src_h) 7992048e328SMark Yao { 8002048e328SMark Yao return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w, 8012048e328SMark Yao crtc_h, src_x, src_y, src_w, src_h, 8022048e328SMark Yao NULL); 8032048e328SMark Yao } 8042048e328SMark Yao 8052048e328SMark Yao static int vop_update_primary_plane(struct drm_crtc *crtc, 8062048e328SMark Yao struct drm_pending_vblank_event *event) 8072048e328SMark Yao { 8082048e328SMark Yao unsigned int crtc_w, crtc_h; 8092048e328SMark Yao 8102048e328SMark Yao crtc_w = crtc->primary->fb->width - crtc->x; 8112048e328SMark Yao crtc_h = crtc->primary->fb->height - crtc->y; 8122048e328SMark Yao 8132048e328SMark Yao return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb, 8142048e328SMark Yao 0, 0, crtc_w, crtc_h, crtc->x << 16, 8152048e328SMark Yao crtc->y << 16, crtc_w << 16, 8162048e328SMark Yao crtc_h << 16, event); 8172048e328SMark Yao } 8182048e328SMark Yao 8192048e328SMark Yao static int vop_disable_plane(struct drm_plane *plane) 8202048e328SMark Yao { 8212048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 8222048e328SMark Yao const struct vop_win_data *win = vop_win->data; 8232048e328SMark Yao struct vop *vop; 8242048e328SMark Yao int ret; 8252048e328SMark Yao 8262048e328SMark Yao if (!plane->crtc) 8272048e328SMark Yao return 0; 8282048e328SMark Yao 8292048e328SMark Yao vop = to_vop(plane->crtc); 8302048e328SMark Yao 8312048e328SMark Yao ret = drm_vblank_get(plane->dev, vop->pipe); 8322048e328SMark Yao if (ret) { 8332048e328SMark Yao DRM_ERROR("failed to get vblank, %d\n", ret); 8342048e328SMark Yao return ret; 8352048e328SMark Yao } 8362048e328SMark Yao 8372048e328SMark Yao mutex_lock(&vop->vsync_mutex); 8382048e328SMark Yao 8392048e328SMark Yao ret = vop_win_queue_fb(vop_win, NULL, 0, NULL); 8402048e328SMark Yao if (ret) { 8412048e328SMark Yao drm_vblank_put(plane->dev, vop->pipe); 8422048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 8432048e328SMark Yao return ret; 8442048e328SMark Yao } 8452048e328SMark Yao 8462048e328SMark Yao vop->vsync_work_pending = true; 8472048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 8482048e328SMark Yao 8492048e328SMark Yao spin_lock(&vop->reg_lock); 8502048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 8512048e328SMark Yao vop_cfg_done(vop); 8522048e328SMark Yao spin_unlock(&vop->reg_lock); 8532048e328SMark Yao 8542048e328SMark Yao return 0; 8552048e328SMark Yao } 8562048e328SMark Yao 8572048e328SMark Yao static void vop_plane_destroy(struct drm_plane *plane) 8582048e328SMark Yao { 8592048e328SMark Yao vop_disable_plane(plane); 8602048e328SMark Yao drm_plane_cleanup(plane); 8612048e328SMark Yao } 8622048e328SMark Yao 8632048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 8642048e328SMark Yao .update_plane = vop_update_plane, 8652048e328SMark Yao .disable_plane = vop_disable_plane, 8662048e328SMark Yao .destroy = vop_plane_destroy, 8672048e328SMark Yao }; 8682048e328SMark Yao 8692048e328SMark Yao int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, 8702048e328SMark Yao int connector_type, 8712048e328SMark Yao int out_mode) 8722048e328SMark Yao { 8732048e328SMark Yao struct vop *vop = to_vop(crtc); 8742048e328SMark Yao 8752048e328SMark Yao vop->connector_type = connector_type; 8762048e328SMark Yao vop->connector_out_mode = out_mode; 8772048e328SMark Yao 8782048e328SMark Yao return 0; 8792048e328SMark Yao } 880f66a1627SPhilipp Zabel EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); 8812048e328SMark Yao 8822048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 8832048e328SMark Yao { 8842048e328SMark Yao struct vop *vop = to_vop(crtc); 8852048e328SMark Yao unsigned long flags; 8862048e328SMark Yao 88731e980c5SMark Yao if (!vop->is_enabled) 8882048e328SMark Yao return -EPERM; 8892048e328SMark Yao 8902048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 8912048e328SMark Yao 8922048e328SMark Yao vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1)); 8932048e328SMark Yao 8942048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8952048e328SMark Yao 8962048e328SMark Yao return 0; 8972048e328SMark Yao } 8982048e328SMark Yao 8992048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 9002048e328SMark Yao { 9012048e328SMark Yao struct vop *vop = to_vop(crtc); 9022048e328SMark Yao unsigned long flags; 9032048e328SMark Yao 90431e980c5SMark Yao if (!vop->is_enabled) 9052048e328SMark Yao return; 90631e980c5SMark Yao 9072048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 9082048e328SMark Yao vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0)); 9092048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 9102048e328SMark Yao } 9112048e328SMark Yao 9122048e328SMark Yao static const struct rockchip_crtc_funcs private_crtc_funcs = { 9132048e328SMark Yao .enable_vblank = vop_crtc_enable_vblank, 9142048e328SMark Yao .disable_vblank = vop_crtc_disable_vblank, 9152048e328SMark Yao }; 9162048e328SMark Yao 9172048e328SMark Yao static void vop_crtc_dpms(struct drm_crtc *crtc, int mode) 9182048e328SMark Yao { 9192048e328SMark Yao DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode); 9202048e328SMark Yao 9212048e328SMark Yao switch (mode) { 9222048e328SMark Yao case DRM_MODE_DPMS_ON: 9232048e328SMark Yao vop_enable(crtc); 9242048e328SMark Yao break; 9252048e328SMark Yao case DRM_MODE_DPMS_STANDBY: 9262048e328SMark Yao case DRM_MODE_DPMS_SUSPEND: 9272048e328SMark Yao case DRM_MODE_DPMS_OFF: 9282048e328SMark Yao vop_disable(crtc); 9292048e328SMark Yao break; 9302048e328SMark Yao default: 9312048e328SMark Yao DRM_DEBUG_KMS("unspecified mode %d\n", mode); 9322048e328SMark Yao break; 9332048e328SMark Yao } 9342048e328SMark Yao } 9352048e328SMark Yao 9362048e328SMark Yao static void vop_crtc_prepare(struct drm_crtc *crtc) 9372048e328SMark Yao { 9382048e328SMark Yao vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 9392048e328SMark Yao } 9402048e328SMark Yao 9412048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 9422048e328SMark Yao const struct drm_display_mode *mode, 9432048e328SMark Yao struct drm_display_mode *adjusted_mode) 9442048e328SMark Yao { 9452048e328SMark Yao if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) 9462048e328SMark Yao return false; 9472048e328SMark Yao 9482048e328SMark Yao return true; 9492048e328SMark Yao } 9502048e328SMark Yao 9512048e328SMark Yao static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 9522048e328SMark Yao struct drm_framebuffer *old_fb) 9532048e328SMark Yao { 9542048e328SMark Yao int ret; 9552048e328SMark Yao 9562048e328SMark Yao crtc->x = x; 9572048e328SMark Yao crtc->y = y; 9582048e328SMark Yao 9592048e328SMark Yao ret = vop_update_primary_plane(crtc, NULL); 9602048e328SMark Yao if (ret < 0) { 9612048e328SMark Yao DRM_ERROR("fail to update plane\n"); 9622048e328SMark Yao return ret; 9632048e328SMark Yao } 9642048e328SMark Yao 9652048e328SMark Yao return 0; 9662048e328SMark Yao } 9672048e328SMark Yao 9682048e328SMark Yao static int vop_crtc_mode_set(struct drm_crtc *crtc, 9692048e328SMark Yao struct drm_display_mode *mode, 9702048e328SMark Yao struct drm_display_mode *adjusted_mode, 9712048e328SMark Yao int x, int y, struct drm_framebuffer *fb) 9722048e328SMark Yao { 9732048e328SMark Yao struct vop *vop = to_vop(crtc); 9742048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 9752048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 9762048e328SMark Yao u16 htotal = adjusted_mode->htotal; 9772048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 9782048e328SMark Yao u16 hact_end = hact_st + hdisplay; 9792048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 9802048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 9812048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 9822048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 9832048e328SMark Yao u16 vact_end = vact_st + vdisplay; 9847f53fbbaSHeiko Stuebner int ret, ret_clk; 9852048e328SMark Yao uint32_t val; 9862048e328SMark Yao 9872048e328SMark Yao /* 9882048e328SMark Yao * disable dclk to stop frame scan, so that we can safe config mode and 9892048e328SMark Yao * enable iommu. 9902048e328SMark Yao */ 9912048e328SMark Yao clk_disable(vop->dclk); 9922048e328SMark Yao 9932048e328SMark Yao switch (vop->connector_type) { 9942048e328SMark Yao case DRM_MODE_CONNECTOR_LVDS: 9952048e328SMark Yao VOP_CTRL_SET(vop, rgb_en, 1); 9962048e328SMark Yao break; 9972048e328SMark Yao case DRM_MODE_CONNECTOR_eDP: 9982048e328SMark Yao VOP_CTRL_SET(vop, edp_en, 1); 9992048e328SMark Yao break; 10002048e328SMark Yao case DRM_MODE_CONNECTOR_HDMIA: 10012048e328SMark Yao VOP_CTRL_SET(vop, hdmi_en, 1); 10022048e328SMark Yao break; 10032048e328SMark Yao default: 10042048e328SMark Yao DRM_ERROR("unsupport connector_type[%d]\n", 10052048e328SMark Yao vop->connector_type); 10067f53fbbaSHeiko Stuebner ret = -EINVAL; 10077f53fbbaSHeiko Stuebner goto out; 10082048e328SMark Yao }; 10092048e328SMark Yao VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode); 10102048e328SMark Yao 10112048e328SMark Yao val = 0x8; 101244ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 101344ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 10142048e328SMark Yao VOP_CTRL_SET(vop, pin_pol, val); 10152048e328SMark Yao 10162048e328SMark Yao VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 10172048e328SMark Yao val = hact_st << 16; 10182048e328SMark Yao val |= hact_end; 10192048e328SMark Yao VOP_CTRL_SET(vop, hact_st_end, val); 10202048e328SMark Yao VOP_CTRL_SET(vop, hpost_st_end, val); 10212048e328SMark Yao 10222048e328SMark Yao VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 10232048e328SMark Yao val = vact_st << 16; 10242048e328SMark Yao val |= vact_end; 10252048e328SMark Yao VOP_CTRL_SET(vop, vact_st_end, val); 10262048e328SMark Yao VOP_CTRL_SET(vop, vpost_st_end, val); 10272048e328SMark Yao 10282048e328SMark Yao ret = vop_crtc_mode_set_base(crtc, x, y, fb); 10292048e328SMark Yao if (ret) 10307f53fbbaSHeiko Stuebner goto out; 10312048e328SMark Yao 10322048e328SMark Yao /* 10332048e328SMark Yao * reset dclk, take all mode config affect, so the clk would run in 10342048e328SMark Yao * correct frame. 10352048e328SMark Yao */ 10362048e328SMark Yao reset_control_assert(vop->dclk_rst); 10372048e328SMark Yao usleep_range(10, 20); 10382048e328SMark Yao reset_control_deassert(vop->dclk_rst); 10392048e328SMark Yao 10402048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 10417f53fbbaSHeiko Stuebner out: 10427f53fbbaSHeiko Stuebner ret_clk = clk_enable(vop->dclk); 10437f53fbbaSHeiko Stuebner if (ret_clk < 0) { 10447f53fbbaSHeiko Stuebner dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk); 10457f53fbbaSHeiko Stuebner return ret_clk; 10462048e328SMark Yao } 10472048e328SMark Yao 10487f53fbbaSHeiko Stuebner return ret; 10492048e328SMark Yao } 10502048e328SMark Yao 10512048e328SMark Yao static void vop_crtc_commit(struct drm_crtc *crtc) 10522048e328SMark Yao { 10532048e328SMark Yao } 10542048e328SMark Yao 10552048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 10562048e328SMark Yao .dpms = vop_crtc_dpms, 10572048e328SMark Yao .prepare = vop_crtc_prepare, 10582048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 10592048e328SMark Yao .mode_set = vop_crtc_mode_set, 10602048e328SMark Yao .mode_set_base = vop_crtc_mode_set_base, 10612048e328SMark Yao .commit = vop_crtc_commit, 10622048e328SMark Yao }; 10632048e328SMark Yao 10642048e328SMark Yao static int vop_crtc_page_flip(struct drm_crtc *crtc, 10652048e328SMark Yao struct drm_framebuffer *fb, 10662048e328SMark Yao struct drm_pending_vblank_event *event, 10672048e328SMark Yao uint32_t page_flip_flags) 10682048e328SMark Yao { 10692048e328SMark Yao struct vop *vop = to_vop(crtc); 10702048e328SMark Yao struct drm_framebuffer *old_fb = crtc->primary->fb; 10712048e328SMark Yao int ret; 10722048e328SMark Yao 107331e980c5SMark Yao /* when the page flip is requested, crtc should be on */ 107431e980c5SMark Yao if (!vop->is_enabled) { 107531e980c5SMark Yao DRM_DEBUG("page flip request rejected because crtc is off.\n"); 10762048e328SMark Yao return 0; 10772048e328SMark Yao } 10782048e328SMark Yao 10792048e328SMark Yao crtc->primary->fb = fb; 10802048e328SMark Yao 10812048e328SMark Yao ret = vop_update_primary_plane(crtc, event); 10822048e328SMark Yao if (ret) 10832048e328SMark Yao crtc->primary->fb = old_fb; 10842048e328SMark Yao 10852048e328SMark Yao return ret; 10862048e328SMark Yao } 10872048e328SMark Yao 10882048e328SMark Yao static void vop_win_state_complete(struct vop_win *vop_win, 10892048e328SMark Yao struct vop_win_state *state) 10902048e328SMark Yao { 10912048e328SMark Yao struct vop *vop = vop_win->vop; 10922048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 10932048e328SMark Yao struct drm_device *drm = crtc->dev; 10942048e328SMark Yao unsigned long flags; 10952048e328SMark Yao 10962048e328SMark Yao if (state->event) { 10972048e328SMark Yao spin_lock_irqsave(&drm->event_lock, flags); 10982048e328SMark Yao drm_send_vblank_event(drm, -1, state->event); 10992048e328SMark Yao spin_unlock_irqrestore(&drm->event_lock, flags); 11002048e328SMark Yao } 11012048e328SMark Yao 11022048e328SMark Yao list_del(&state->head); 11032048e328SMark Yao drm_vblank_put(crtc->dev, vop->pipe); 11042048e328SMark Yao } 11052048e328SMark Yao 11062048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 11072048e328SMark Yao { 11082048e328SMark Yao drm_crtc_cleanup(crtc); 11092048e328SMark Yao } 11102048e328SMark Yao 11112048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 11122048e328SMark Yao .set_config = drm_crtc_helper_set_config, 11132048e328SMark Yao .page_flip = vop_crtc_page_flip, 11142048e328SMark Yao .destroy = vop_crtc_destroy, 11152048e328SMark Yao }; 11162048e328SMark Yao 11172048e328SMark Yao static bool vop_win_state_is_active(struct vop_win *vop_win, 11182048e328SMark Yao struct vop_win_state *state) 11192048e328SMark Yao { 11202048e328SMark Yao bool active = false; 11212048e328SMark Yao 11222048e328SMark Yao if (state->fb) { 11232048e328SMark Yao dma_addr_t yrgb_mst; 11242048e328SMark Yao 11252048e328SMark Yao /* check yrgb_mst to tell if pending_fb is now front */ 11262048e328SMark Yao yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 11272048e328SMark Yao 11282048e328SMark Yao active = (yrgb_mst == state->yrgb_mst); 11292048e328SMark Yao } else { 11302048e328SMark Yao bool enabled; 11312048e328SMark Yao 11322048e328SMark Yao /* if enable bit is clear, plane is now disabled */ 11332048e328SMark Yao enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable); 11342048e328SMark Yao 11352048e328SMark Yao active = (enabled == 0); 11362048e328SMark Yao } 11372048e328SMark Yao 11382048e328SMark Yao return active; 11392048e328SMark Yao } 11402048e328SMark Yao 11412048e328SMark Yao static void vop_win_state_destroy(struct vop_win_state *state) 11422048e328SMark Yao { 11432048e328SMark Yao struct drm_framebuffer *fb = state->fb; 11442048e328SMark Yao 11452048e328SMark Yao if (fb) 11462048e328SMark Yao drm_framebuffer_unreference(fb); 11472048e328SMark Yao 11482048e328SMark Yao kfree(state); 11492048e328SMark Yao } 11502048e328SMark Yao 11512048e328SMark Yao static void vop_win_update_state(struct vop_win *vop_win) 11522048e328SMark Yao { 11532048e328SMark Yao struct vop_win_state *state, *n, *new_active = NULL; 11542048e328SMark Yao 11552048e328SMark Yao /* Check if any pending states are now active */ 11562048e328SMark Yao list_for_each_entry(state, &vop_win->pending, head) 11572048e328SMark Yao if (vop_win_state_is_active(vop_win, state)) { 11582048e328SMark Yao new_active = state; 11592048e328SMark Yao break; 11602048e328SMark Yao } 11612048e328SMark Yao 11622048e328SMark Yao if (!new_active) 11632048e328SMark Yao return; 11642048e328SMark Yao 11652048e328SMark Yao /* 11662048e328SMark Yao * Destroy any 'skipped' pending states - states that were queued 11672048e328SMark Yao * before the newly active state. 11682048e328SMark Yao */ 11692048e328SMark Yao list_for_each_entry_safe(state, n, &vop_win->pending, head) { 11702048e328SMark Yao if (state == new_active) 11712048e328SMark Yao break; 11722048e328SMark Yao vop_win_state_complete(vop_win, state); 11732048e328SMark Yao vop_win_state_destroy(state); 11742048e328SMark Yao } 11752048e328SMark Yao 11762048e328SMark Yao vop_win_state_complete(vop_win, new_active); 11772048e328SMark Yao 11782048e328SMark Yao if (vop_win->active) 11792048e328SMark Yao vop_win_state_destroy(vop_win->active); 11802048e328SMark Yao vop_win->active = new_active; 11812048e328SMark Yao } 11822048e328SMark Yao 11832048e328SMark Yao static bool vop_win_has_pending_state(struct vop_win *vop_win) 11842048e328SMark Yao { 11852048e328SMark Yao return !list_empty(&vop_win->pending); 11862048e328SMark Yao } 11872048e328SMark Yao 11882048e328SMark Yao static irqreturn_t vop_isr_thread(int irq, void *data) 11892048e328SMark Yao { 11902048e328SMark Yao struct vop *vop = data; 11912048e328SMark Yao const struct vop_data *vop_data = vop->data; 11922048e328SMark Yao unsigned int i; 11932048e328SMark Yao 11942048e328SMark Yao mutex_lock(&vop->vsync_mutex); 11952048e328SMark Yao 11962048e328SMark Yao if (!vop->vsync_work_pending) 11972048e328SMark Yao goto done; 11982048e328SMark Yao 11992048e328SMark Yao vop->vsync_work_pending = false; 12002048e328SMark Yao 12012048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12022048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12032048e328SMark Yao 12042048e328SMark Yao vop_win_update_state(vop_win); 12052048e328SMark Yao if (vop_win_has_pending_state(vop_win)) 12062048e328SMark Yao vop->vsync_work_pending = true; 12072048e328SMark Yao } 12082048e328SMark Yao 12092048e328SMark Yao done: 12102048e328SMark Yao mutex_unlock(&vop->vsync_mutex); 12112048e328SMark Yao 12122048e328SMark Yao return IRQ_HANDLED; 12132048e328SMark Yao } 12142048e328SMark Yao 12152048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 12162048e328SMark Yao { 12172048e328SMark Yao struct vop *vop = data; 12182048e328SMark Yao uint32_t intr0_reg, active_irqs; 12192048e328SMark Yao unsigned long flags; 12201067219bSMark Yao int ret = IRQ_NONE; 12212048e328SMark Yao 12222048e328SMark Yao /* 12232048e328SMark Yao * INTR_CTRL0 register has interrupt status, enable and clear bits, we 12242048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 12252048e328SMark Yao */ 12262048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 12272048e328SMark Yao intr0_reg = vop_readl(vop, INTR_CTRL0); 12282048e328SMark Yao active_irqs = intr0_reg & INTR_MASK; 12292048e328SMark Yao /* Clear all active interrupt sources */ 12302048e328SMark Yao if (active_irqs) 12312048e328SMark Yao vop_writel(vop, INTR_CTRL0, 12322048e328SMark Yao intr0_reg | (active_irqs << INTR_CLR_SHIFT)); 12332048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 12342048e328SMark Yao 12352048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 12362048e328SMark Yao if (!active_irqs) 12372048e328SMark Yao return IRQ_NONE; 12382048e328SMark Yao 12391067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 12401067219bSMark Yao complete(&vop->dsp_hold_completion); 12411067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 12421067219bSMark Yao ret = IRQ_HANDLED; 12432048e328SMark Yao } 12442048e328SMark Yao 12451067219bSMark Yao if (active_irqs & FS_INTR) { 12462048e328SMark Yao drm_handle_vblank(vop->drm_dev, vop->pipe); 12471067219bSMark Yao active_irqs &= ~FS_INTR; 12481067219bSMark Yao ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 12491067219bSMark Yao } 12502048e328SMark Yao 12511067219bSMark Yao /* Unhandled irqs are spurious. */ 12521067219bSMark Yao if (active_irqs) 12531067219bSMark Yao DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 12541067219bSMark Yao 12551067219bSMark Yao return ret; 12562048e328SMark Yao } 12572048e328SMark Yao 12582048e328SMark Yao static int vop_create_crtc(struct vop *vop) 12592048e328SMark Yao { 12602048e328SMark Yao const struct vop_data *vop_data = vop->data; 12612048e328SMark Yao struct device *dev = vop->dev; 12622048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 12632048e328SMark Yao struct drm_plane *primary = NULL, *cursor = NULL, *plane; 12642048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12652048e328SMark Yao struct device_node *port; 12662048e328SMark Yao int ret; 12672048e328SMark Yao int i; 12682048e328SMark Yao 12692048e328SMark Yao /* 12702048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 12712048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 12722048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 12732048e328SMark Yao */ 12742048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12752048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12762048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12772048e328SMark Yao 12782048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 12792048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 12802048e328SMark Yao continue; 12812048e328SMark Yao 12822048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12832048e328SMark Yao 0, &vop_plane_funcs, 12842048e328SMark Yao win_data->phy->data_formats, 12852048e328SMark Yao win_data->phy->nformats, 12862048e328SMark Yao win_data->type); 12872048e328SMark Yao if (ret) { 12882048e328SMark Yao DRM_ERROR("failed to initialize plane\n"); 12892048e328SMark Yao goto err_cleanup_planes; 12902048e328SMark Yao } 12912048e328SMark Yao 12922048e328SMark Yao plane = &vop_win->base; 12932048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 12942048e328SMark Yao primary = plane; 12952048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 12962048e328SMark Yao cursor = plane; 12972048e328SMark Yao } 12982048e328SMark Yao 12992048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 13002048e328SMark Yao &vop_crtc_funcs); 13012048e328SMark Yao if (ret) 13022048e328SMark Yao return ret; 13032048e328SMark Yao 13042048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 13052048e328SMark Yao 13062048e328SMark Yao /* 13072048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 13082048e328SMark Yao * to the newly created crtc. 13092048e328SMark Yao */ 13102048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13112048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13122048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 13132048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 13142048e328SMark Yao 13152048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 13162048e328SMark Yao continue; 13172048e328SMark Yao 13182048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 13192048e328SMark Yao possible_crtcs, 13202048e328SMark Yao &vop_plane_funcs, 13212048e328SMark Yao win_data->phy->data_formats, 13222048e328SMark Yao win_data->phy->nformats, 13232048e328SMark Yao win_data->type); 13242048e328SMark Yao if (ret) { 13252048e328SMark Yao DRM_ERROR("failed to initialize overlay plane\n"); 13262048e328SMark Yao goto err_cleanup_crtc; 13272048e328SMark Yao } 13282048e328SMark Yao } 13292048e328SMark Yao 13302048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 13312048e328SMark Yao if (!port) { 13322048e328SMark Yao DRM_ERROR("no port node found in %s\n", 13332048e328SMark Yao dev->of_node->full_name); 13342048e328SMark Yao goto err_cleanup_crtc; 13352048e328SMark Yao } 13362048e328SMark Yao 13371067219bSMark Yao init_completion(&vop->dsp_hold_completion); 13382048e328SMark Yao crtc->port = port; 13392048e328SMark Yao vop->pipe = drm_crtc_index(crtc); 13402048e328SMark Yao rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe); 13412048e328SMark Yao 13422048e328SMark Yao return 0; 13432048e328SMark Yao 13442048e328SMark Yao err_cleanup_crtc: 13452048e328SMark Yao drm_crtc_cleanup(crtc); 13462048e328SMark Yao err_cleanup_planes: 13472048e328SMark Yao list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) 13482048e328SMark Yao drm_plane_cleanup(plane); 13492048e328SMark Yao return ret; 13502048e328SMark Yao } 13512048e328SMark Yao 13522048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 13532048e328SMark Yao { 13542048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 13552048e328SMark Yao 13562048e328SMark Yao rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe); 13572048e328SMark Yao of_node_put(crtc->port); 13582048e328SMark Yao drm_crtc_cleanup(crtc); 13592048e328SMark Yao } 13602048e328SMark Yao 13612048e328SMark Yao static int vop_initial(struct vop *vop) 13622048e328SMark Yao { 13632048e328SMark Yao const struct vop_data *vop_data = vop->data; 13642048e328SMark Yao const struct vop_reg_data *init_table = vop_data->init_table; 13652048e328SMark Yao struct reset_control *ahb_rst; 13662048e328SMark Yao int i, ret; 13672048e328SMark Yao 13682048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 13692048e328SMark Yao if (IS_ERR(vop->hclk)) { 13702048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 13712048e328SMark Yao return PTR_ERR(vop->hclk); 13722048e328SMark Yao } 13732048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 13742048e328SMark Yao if (IS_ERR(vop->aclk)) { 13752048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 13762048e328SMark Yao return PTR_ERR(vop->aclk); 13772048e328SMark Yao } 13782048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 13792048e328SMark Yao if (IS_ERR(vop->dclk)) { 13802048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 13812048e328SMark Yao return PTR_ERR(vop->dclk); 13822048e328SMark Yao } 13832048e328SMark Yao 13842048e328SMark Yao ret = clk_prepare(vop->hclk); 13852048e328SMark Yao if (ret < 0) { 13862048e328SMark Yao dev_err(vop->dev, "failed to prepare hclk\n"); 13872048e328SMark Yao return ret; 13882048e328SMark Yao } 13892048e328SMark Yao 13902048e328SMark Yao ret = clk_prepare(vop->dclk); 13912048e328SMark Yao if (ret < 0) { 13922048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 13932048e328SMark Yao goto err_unprepare_hclk; 13942048e328SMark Yao } 13952048e328SMark Yao 13962048e328SMark Yao ret = clk_prepare(vop->aclk); 13972048e328SMark Yao if (ret < 0) { 13982048e328SMark Yao dev_err(vop->dev, "failed to prepare aclk\n"); 13992048e328SMark Yao goto err_unprepare_dclk; 14002048e328SMark Yao } 14012048e328SMark Yao 14022048e328SMark Yao /* 14032048e328SMark Yao * enable hclk, so that we can config vop register. 14042048e328SMark Yao */ 14052048e328SMark Yao ret = clk_enable(vop->hclk); 14062048e328SMark Yao if (ret < 0) { 14072048e328SMark Yao dev_err(vop->dev, "failed to prepare aclk\n"); 14082048e328SMark Yao goto err_unprepare_aclk; 14092048e328SMark Yao } 14102048e328SMark Yao /* 14112048e328SMark Yao * do hclk_reset, reset all vop registers. 14122048e328SMark Yao */ 14132048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 14142048e328SMark Yao if (IS_ERR(ahb_rst)) { 14152048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 14162048e328SMark Yao ret = PTR_ERR(ahb_rst); 14172048e328SMark Yao goto err_disable_hclk; 14182048e328SMark Yao } 14192048e328SMark Yao reset_control_assert(ahb_rst); 14202048e328SMark Yao usleep_range(10, 20); 14212048e328SMark Yao reset_control_deassert(ahb_rst); 14222048e328SMark Yao 14232048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 14242048e328SMark Yao 14252048e328SMark Yao for (i = 0; i < vop_data->table_size; i++) 14262048e328SMark Yao vop_writel(vop, init_table[i].offset, init_table[i].value); 14272048e328SMark Yao 14282048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14292048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 14302048e328SMark Yao 14312048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 14322048e328SMark Yao } 14332048e328SMark Yao 14342048e328SMark Yao vop_cfg_done(vop); 14352048e328SMark Yao 14362048e328SMark Yao /* 14372048e328SMark Yao * do dclk_reset, let all config take affect. 14382048e328SMark Yao */ 14392048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 14402048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 14412048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 14422048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 14432048e328SMark Yao goto err_unprepare_aclk; 14442048e328SMark Yao } 14452048e328SMark Yao reset_control_assert(vop->dclk_rst); 14462048e328SMark Yao usleep_range(10, 20); 14472048e328SMark Yao reset_control_deassert(vop->dclk_rst); 14482048e328SMark Yao 14492048e328SMark Yao clk_disable(vop->hclk); 14502048e328SMark Yao 145131e980c5SMark Yao vop->is_enabled = false; 14522048e328SMark Yao 14532048e328SMark Yao return 0; 14542048e328SMark Yao 14552048e328SMark Yao err_disable_hclk: 14562048e328SMark Yao clk_disable(vop->hclk); 14572048e328SMark Yao err_unprepare_aclk: 14582048e328SMark Yao clk_unprepare(vop->aclk); 14592048e328SMark Yao err_unprepare_dclk: 14602048e328SMark Yao clk_unprepare(vop->dclk); 14612048e328SMark Yao err_unprepare_hclk: 14622048e328SMark Yao clk_unprepare(vop->hclk); 14632048e328SMark Yao return ret; 14642048e328SMark Yao } 14652048e328SMark Yao 14662048e328SMark Yao /* 14672048e328SMark Yao * Initialize the vop->win array elements. 14682048e328SMark Yao */ 14692048e328SMark Yao static void vop_win_init(struct vop *vop) 14702048e328SMark Yao { 14712048e328SMark Yao const struct vop_data *vop_data = vop->data; 14722048e328SMark Yao unsigned int i; 14732048e328SMark Yao 14742048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14752048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14762048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 14772048e328SMark Yao 14782048e328SMark Yao vop_win->data = win_data; 14792048e328SMark Yao vop_win->vop = vop; 14802048e328SMark Yao INIT_LIST_HEAD(&vop_win->pending); 14812048e328SMark Yao } 14822048e328SMark Yao } 14832048e328SMark Yao 14842048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 14852048e328SMark Yao { 14862048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 14872048e328SMark Yao const struct of_device_id *of_id; 14882048e328SMark Yao const struct vop_data *vop_data; 14892048e328SMark Yao struct drm_device *drm_dev = data; 14902048e328SMark Yao struct vop *vop; 14912048e328SMark Yao struct resource *res; 14922048e328SMark Yao size_t alloc_size; 14933ea68922SHeiko Stuebner int ret, irq; 14942048e328SMark Yao 14952048e328SMark Yao of_id = of_match_device(vop_driver_dt_match, dev); 14962048e328SMark Yao vop_data = of_id->data; 14972048e328SMark Yao if (!vop_data) 14982048e328SMark Yao return -ENODEV; 14992048e328SMark Yao 15002048e328SMark Yao /* Allocate vop struct and its vop_win array */ 15012048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 15022048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 15032048e328SMark Yao if (!vop) 15042048e328SMark Yao return -ENOMEM; 15052048e328SMark Yao 15062048e328SMark Yao vop->dev = dev; 15072048e328SMark Yao vop->data = vop_data; 15082048e328SMark Yao vop->drm_dev = drm_dev; 15092048e328SMark Yao dev_set_drvdata(dev, vop); 15102048e328SMark Yao 15112048e328SMark Yao vop_win_init(vop); 15122048e328SMark Yao 15132048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15142048e328SMark Yao vop->len = resource_size(res); 15152048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 15162048e328SMark Yao if (IS_ERR(vop->regs)) 15172048e328SMark Yao return PTR_ERR(vop->regs); 15182048e328SMark Yao 15192048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 15202048e328SMark Yao if (!vop->regsbak) 15212048e328SMark Yao return -ENOMEM; 15222048e328SMark Yao 15232048e328SMark Yao ret = vop_initial(vop); 15242048e328SMark Yao if (ret < 0) { 15252048e328SMark Yao dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 15262048e328SMark Yao return ret; 15272048e328SMark Yao } 15282048e328SMark Yao 15293ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 15303ea68922SHeiko Stuebner if (irq < 0) { 15312048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 15323ea68922SHeiko Stuebner return irq; 15332048e328SMark Yao } 15343ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 15352048e328SMark Yao 15362048e328SMark Yao spin_lock_init(&vop->reg_lock); 15372048e328SMark Yao spin_lock_init(&vop->irq_lock); 15382048e328SMark Yao 15392048e328SMark Yao mutex_init(&vop->vsync_mutex); 15402048e328SMark Yao 15412048e328SMark Yao ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread, 15422048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 15432048e328SMark Yao if (ret) 15442048e328SMark Yao return ret; 15452048e328SMark Yao 15462048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 15472048e328SMark Yao disable_irq(vop->irq); 15482048e328SMark Yao 15492048e328SMark Yao ret = vop_create_crtc(vop); 15502048e328SMark Yao if (ret) 15512048e328SMark Yao return ret; 15522048e328SMark Yao 15532048e328SMark Yao pm_runtime_enable(&pdev->dev); 15542048e328SMark Yao return 0; 15552048e328SMark Yao } 15562048e328SMark Yao 15572048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 15582048e328SMark Yao { 15592048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 15602048e328SMark Yao 15612048e328SMark Yao pm_runtime_disable(dev); 15622048e328SMark Yao vop_destroy_crtc(vop); 15632048e328SMark Yao } 15642048e328SMark Yao 15652048e328SMark Yao static const struct component_ops vop_component_ops = { 15662048e328SMark Yao .bind = vop_bind, 15672048e328SMark Yao .unbind = vop_unbind, 15682048e328SMark Yao }; 15692048e328SMark Yao 15702048e328SMark Yao static int vop_probe(struct platform_device *pdev) 15712048e328SMark Yao { 15722048e328SMark Yao struct device *dev = &pdev->dev; 15732048e328SMark Yao 15742048e328SMark Yao if (!dev->of_node) { 15752048e328SMark Yao dev_err(dev, "can't find vop devices\n"); 15762048e328SMark Yao return -ENODEV; 15772048e328SMark Yao } 15782048e328SMark Yao 15792048e328SMark Yao return component_add(dev, &vop_component_ops); 15802048e328SMark Yao } 15812048e328SMark Yao 15822048e328SMark Yao static int vop_remove(struct platform_device *pdev) 15832048e328SMark Yao { 15842048e328SMark Yao component_del(&pdev->dev, &vop_component_ops); 15852048e328SMark Yao 15862048e328SMark Yao return 0; 15872048e328SMark Yao } 15882048e328SMark Yao 15892048e328SMark Yao struct platform_driver vop_platform_driver = { 15902048e328SMark Yao .probe = vop_probe, 15912048e328SMark Yao .remove = vop_remove, 15922048e328SMark Yao .driver = { 15932048e328SMark Yao .name = "rockchip-vop", 15942048e328SMark Yao .owner = THIS_MODULE, 15952048e328SMark Yao .of_match_table = of_match_ptr(vop_driver_dt_match), 15962048e328SMark Yao }, 15972048e328SMark Yao }; 15982048e328SMark Yao 15992048e328SMark Yao module_platform_driver(vop_platform_driver); 16002048e328SMark Yao 16012048e328SMark Yao MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>"); 16022048e328SMark Yao MODULE_DESCRIPTION("ROCKCHIP VOP Driver"); 16032048e328SMark Yao MODULE_LICENSE("GPL v2"); 1604