12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 2047a7eb45STomasz Figa #include <drm/drm_flip_work.h> 212048e328SMark Yao #include <drm/drm_plane_helper.h> 226cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 233190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 246cca3869SSean Paul #endif 252048e328SMark Yao 262048e328SMark Yao #include <linux/kernel.h> 2700fe6148SPaul Gortmaker #include <linux/module.h> 282048e328SMark Yao #include <linux/platform_device.h> 292048e328SMark Yao #include <linux/clk.h> 307caecdbeSTomasz Figa #include <linux/iopoll.h> 312048e328SMark Yao #include <linux/of.h> 322048e328SMark Yao #include <linux/of_device.h> 332048e328SMark Yao #include <linux/pm_runtime.h> 342048e328SMark Yao #include <linux/component.h> 352048e328SMark Yao 362048e328SMark Yao #include <linux/reset.h> 372048e328SMark Yao #include <linux/delay.h> 382048e328SMark Yao 392048e328SMark Yao #include "rockchip_drm_drv.h" 402048e328SMark Yao #include "rockchip_drm_gem.h" 412048e328SMark Yao #include "rockchip_drm_fb.h" 425182c1a5SYakir Yang #include "rockchip_drm_psr.h" 432048e328SMark Yao #include "rockchip_drm_vop.h" 442048e328SMark Yao 452048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 469a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 474c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 489a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 491194fffbSMark Yao #define VOP_SCL_SET_EXT(x, win, name, v) \ 509a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 519a61c54bSMark yao win->base, ~0, v, #name) 52ac6560dfSMark yao 53ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 549a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 559a61c54bSMark yao 569a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 579a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58ac6560dfSMark yao 59dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60dbb3d944SMark Yao do { \ 61c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 62dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 64dbb3d944SMark Yao reg |= (v) << i; \ 65c7647f86SJohn Keeping mask |= 1 << i; \ 66dbb3d944SMark Yao } \ 67c7647f86SJohn Keeping } \ 68ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69dbb3d944SMark Yao } while (0) 70dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 71dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 72dbb3d944SMark Yao 732048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 749a61c54bSMark yao vop_read_reg(x, win->offset, win->phy->name) 752048e328SMark Yao 762048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 772048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 782048e328SMark Yao 7958badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 8058badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 8158badaa7SKristian H. Kristensen 822048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 832048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 842048e328SMark Yao 8547a7eb45STomasz Figa enum vop_pending { 8647a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 8747a7eb45STomasz Figa }; 8847a7eb45STomasz Figa 892048e328SMark Yao struct vop_win { 902048e328SMark Yao struct drm_plane base; 912048e328SMark Yao const struct vop_win_data *data; 922048e328SMark Yao struct vop *vop; 932048e328SMark Yao }; 942048e328SMark Yao 952048e328SMark Yao struct vop { 962048e328SMark Yao struct drm_crtc crtc; 972048e328SMark Yao struct device *dev; 982048e328SMark Yao struct drm_device *drm_dev; 9931e980c5SMark Yao bool is_enabled; 1002048e328SMark Yao 1011067219bSMark Yao struct completion dsp_hold_completion; 1024f9d39a7SDaniel Vetter 1034f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 10463ebb9faSMark Yao struct drm_pending_vblank_event *event; 1052048e328SMark Yao 10647a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 10747a7eb45STomasz Figa unsigned long pending; 10847a7eb45STomasz Figa 10969c34e41SYakir Yang struct completion line_flag_completion; 11069c34e41SYakir Yang 1112048e328SMark Yao const struct vop_data *data; 1122048e328SMark Yao 1132048e328SMark Yao uint32_t *regsbak; 1142048e328SMark Yao void __iomem *regs; 1152048e328SMark Yao 1162048e328SMark Yao /* physical map length of vop register */ 1172048e328SMark Yao uint32_t len; 1182048e328SMark Yao 1192048e328SMark Yao /* one time only one process allowed to config the register */ 1202048e328SMark Yao spinlock_t reg_lock; 1212048e328SMark Yao /* lock vop irq reg */ 1222048e328SMark Yao spinlock_t irq_lock; 123e334d48bSzain wang /* protects crtc enable/disable */ 124e334d48bSzain wang struct mutex vop_lock; 1252048e328SMark Yao 1262048e328SMark Yao unsigned int irq; 1272048e328SMark Yao 1282048e328SMark Yao /* vop AHP clk */ 1292048e328SMark Yao struct clk *hclk; 1302048e328SMark Yao /* vop dclk */ 1312048e328SMark Yao struct clk *dclk; 1322048e328SMark Yao /* vop share memory frequency */ 1332048e328SMark Yao struct clk *aclk; 1342048e328SMark Yao 1352048e328SMark Yao /* vop dclk reset */ 1362048e328SMark Yao struct reset_control *dclk_rst; 1372048e328SMark Yao 1382048e328SMark Yao struct vop_win win[]; 1392048e328SMark Yao }; 1402048e328SMark Yao 1412048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1422048e328SMark Yao { 1432048e328SMark Yao writel(v, vop->regs + offset); 1442048e328SMark Yao vop->regsbak[offset >> 2] = v; 1452048e328SMark Yao } 1462048e328SMark Yao 1472048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1482048e328SMark Yao { 1492048e328SMark Yao return readl(vop->regs + offset); 1502048e328SMark Yao } 1512048e328SMark Yao 1522048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1532048e328SMark Yao const struct vop_reg *reg) 1542048e328SMark Yao { 1552048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1562048e328SMark Yao } 1572048e328SMark Yao 1589a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 1599a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 1609a61c54bSMark yao const char *reg_name) 1612048e328SMark Yao { 1629a61c54bSMark yao int offset, mask, shift; 163d49463ecSMark Yao 1649a61c54bSMark yao if (!reg || !reg->mask) { 165d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 1669a61c54bSMark yao return; 1679a61c54bSMark yao } 1689a61c54bSMark yao 1699a61c54bSMark yao offset = reg->offset + _offset; 1709a61c54bSMark yao mask = reg->mask & _mask; 1719a61c54bSMark yao shift = reg->shift; 1729a61c54bSMark yao 1739a61c54bSMark yao if (reg->write_mask) { 174d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 175d49463ecSMark Yao } else { 1762048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1772048e328SMark Yao 178d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 179d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 1802048e328SMark Yao } 1812048e328SMark Yao 1829a61c54bSMark yao if (reg->relaxed) 183d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 184d49463ecSMark Yao else 185d49463ecSMark Yao writel(v, vop->regs + offset); 1862048e328SMark Yao } 1872048e328SMark Yao 188dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 189dbb3d944SMark Yao const struct vop_reg *reg, int type) 190dbb3d944SMark Yao { 191dbb3d944SMark Yao uint32_t i, ret = 0; 192dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 193dbb3d944SMark Yao 194dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 195dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 196dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 197dbb3d944SMark Yao } 198dbb3d944SMark Yao 199dbb3d944SMark Yao return ret; 200dbb3d944SMark Yao } 201dbb3d944SMark Yao 2020cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2030cf33fe3SMark Yao { 2049a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2050cf33fe3SMark Yao } 2060cf33fe3SMark Yao 20785a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 20885a359f2STomasz Figa { 20985a359f2STomasz Figa switch (format) { 21085a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 21185a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 21285a359f2STomasz Figa case DRM_FORMAT_BGR888: 21385a359f2STomasz Figa case DRM_FORMAT_BGR565: 21485a359f2STomasz Figa return true; 21585a359f2STomasz Figa default: 21685a359f2STomasz Figa return false; 21785a359f2STomasz Figa } 21885a359f2STomasz Figa } 21985a359f2STomasz Figa 2202048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2212048e328SMark Yao { 2222048e328SMark Yao switch (format) { 2232048e328SMark Yao case DRM_FORMAT_XRGB8888: 2242048e328SMark Yao case DRM_FORMAT_ARGB8888: 22585a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 22685a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2272048e328SMark Yao return VOP_FMT_ARGB8888; 2282048e328SMark Yao case DRM_FORMAT_RGB888: 22985a359f2STomasz Figa case DRM_FORMAT_BGR888: 2302048e328SMark Yao return VOP_FMT_RGB888; 2312048e328SMark Yao case DRM_FORMAT_RGB565: 23285a359f2STomasz Figa case DRM_FORMAT_BGR565: 2332048e328SMark Yao return VOP_FMT_RGB565; 2342048e328SMark Yao case DRM_FORMAT_NV12: 2352048e328SMark Yao return VOP_FMT_YUV420SP; 2362048e328SMark Yao case DRM_FORMAT_NV16: 2372048e328SMark Yao return VOP_FMT_YUV422SP; 2382048e328SMark Yao case DRM_FORMAT_NV24: 2392048e328SMark Yao return VOP_FMT_YUV444SP; 2402048e328SMark Yao default: 241ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2422048e328SMark Yao return -EINVAL; 2432048e328SMark Yao } 2442048e328SMark Yao } 2452048e328SMark Yao 24684c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 24784c7f8caSMark Yao { 24884c7f8caSMark Yao switch (format) { 24984c7f8caSMark Yao case DRM_FORMAT_NV12: 25084c7f8caSMark Yao case DRM_FORMAT_NV16: 25184c7f8caSMark Yao case DRM_FORMAT_NV24: 25284c7f8caSMark Yao return true; 25384c7f8caSMark Yao default: 25484c7f8caSMark Yao return false; 25584c7f8caSMark Yao } 25684c7f8caSMark Yao } 25784c7f8caSMark Yao 2584c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2594c156c21SMark Yao uint32_t dst, bool is_horizontal, 2604c156c21SMark Yao int vsu_mode, int *vskiplines) 2614c156c21SMark Yao { 2624c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2634c156c21SMark Yao 264ce91d373SJeffy Chen if (vskiplines) 265ce91d373SJeffy Chen *vskiplines = 0; 266ce91d373SJeffy Chen 2674c156c21SMark Yao if (is_horizontal) { 2684c156c21SMark Yao if (mode == SCALE_UP) 2694c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2704c156c21SMark Yao else if (mode == SCALE_DOWN) 2714c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2724c156c21SMark Yao } else { 2734c156c21SMark Yao if (mode == SCALE_UP) { 2744c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2754c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2764c156c21SMark Yao else 2774c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2784c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2794c156c21SMark Yao if (vskiplines) { 2804c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 2814c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 2824c156c21SMark Yao *vskiplines); 2834c156c21SMark Yao } else { 2844c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2854c156c21SMark Yao } 2864c156c21SMark Yao } 2874c156c21SMark Yao } 2884c156c21SMark Yao 2894c156c21SMark Yao return val; 2904c156c21SMark Yao } 2914c156c21SMark Yao 2924c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 2934c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 2944c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 2954c156c21SMark Yao { 2964c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 2974c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 2984c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 2994c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 3004c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 3014c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 3024c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 3034c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 3044c156c21SMark Yao uint16_t vsu_mode; 3054c156c21SMark Yao uint16_t lb_mode; 3064c156c21SMark Yao uint32_t val; 307ce91d373SJeffy Chen int vskiplines; 3084c156c21SMark Yao 3094c156c21SMark Yao if (dst_w > 3840) { 310ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3114c156c21SMark Yao return; 3124c156c21SMark Yao } 3134c156c21SMark Yao 3141194fffbSMark Yao if (!win->phy->scl->ext) { 3151194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3161194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3171194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3181194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3191194fffbSMark Yao if (is_yuv) { 3201194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 321ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3221194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 323ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3241194fffbSMark Yao } 3251194fffbSMark Yao return; 3261194fffbSMark Yao } 3271194fffbSMark Yao 3284c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3294c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3304c156c21SMark Yao 3314c156c21SMark Yao if (is_yuv) { 3324c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3334c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3344c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3354c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3364c156c21SMark Yao else 3374c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3384c156c21SMark Yao } else { 3394c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3404c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3414c156c21SMark Yao else 3424c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3434c156c21SMark Yao } 3444c156c21SMark Yao 3451194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3464c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3474c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 348ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3494c156c21SMark Yao return; 3504c156c21SMark Yao } 3514c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 352ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3534c156c21SMark Yao return; 3544c156c21SMark Yao } 3554c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3564c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3574c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3584c156c21SMark Yao } else { 3594c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3604c156c21SMark Yao } 3614c156c21SMark Yao 3624c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3634c156c21SMark Yao true, 0, NULL); 3644c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3654c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3664c156c21SMark Yao false, vsu_mode, &vskiplines); 3674c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3684c156c21SMark Yao 3691194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3701194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3714c156c21SMark Yao 3721194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3731194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3741194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3751194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3761194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3774c156c21SMark Yao if (is_yuv) { 3784c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3794c156c21SMark Yao dst_w, true, 0, NULL); 3804c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 3814c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 3824c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 3834c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 3844c156c21SMark Yao 3851194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 3861194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 3871194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 3881194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 3891194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 3901194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 3911194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 3924c156c21SMark Yao } 3934c156c21SMark Yao } 3944c156c21SMark Yao 3951067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 3961067219bSMark Yao { 3971067219bSMark Yao unsigned long flags; 3981067219bSMark Yao 3991067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4001067219bSMark Yao return; 4011067219bSMark Yao 4021067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4031067219bSMark Yao 404fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 405dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4061067219bSMark Yao 4071067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4081067219bSMark Yao } 4091067219bSMark Yao 4101067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4111067219bSMark Yao { 4121067219bSMark Yao unsigned long flags; 4131067219bSMark Yao 4141067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4151067219bSMark Yao return; 4161067219bSMark Yao 4171067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4181067219bSMark Yao 419dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4201067219bSMark Yao 4211067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4221067219bSMark Yao } 4231067219bSMark Yao 42469c34e41SYakir Yang /* 42569c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 42669c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 42769c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 42869c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 42969c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 43069c34e41SYakir Yang * 43169c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 43269c34e41SYakir Yang * Interrupts 43369c34e41SYakir Yang * LINE_FLAG -------------------------------+ 43469c34e41SYakir Yang * FRAME_SYNC ----+ | 43569c34e41SYakir Yang * | | 43669c34e41SYakir Yang * v v 43769c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 43869c34e41SYakir Yang * ^ ^ ^ ^ 43969c34e41SYakir Yang * | | | | 44069c34e41SYakir Yang * | | | | 44169c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 44269c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 44369c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 44469c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 44569c34e41SYakir Yang */ 44669c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 44769c34e41SYakir Yang { 44869c34e41SYakir Yang uint32_t line_flag_irq; 44969c34e41SYakir Yang unsigned long flags; 45069c34e41SYakir Yang 45169c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 45269c34e41SYakir Yang 45369c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 45469c34e41SYakir Yang 45569c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 45669c34e41SYakir Yang 45769c34e41SYakir Yang return !!line_flag_irq; 45869c34e41SYakir Yang } 45969c34e41SYakir Yang 460459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 46169c34e41SYakir Yang { 46269c34e41SYakir Yang unsigned long flags; 46369c34e41SYakir Yang 46469c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 46569c34e41SYakir Yang return; 46669c34e41SYakir Yang 46769c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 46869c34e41SYakir Yang 469fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 47069c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 47169c34e41SYakir Yang 47269c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 47369c34e41SYakir Yang } 47469c34e41SYakir Yang 47569c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 47669c34e41SYakir Yang { 47769c34e41SYakir Yang unsigned long flags; 47869c34e41SYakir Yang 47969c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 48069c34e41SYakir Yang return; 48169c34e41SYakir Yang 48269c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 48369c34e41SYakir Yang 48469c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 48569c34e41SYakir Yang 48669c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 48769c34e41SYakir Yang } 48869c34e41SYakir Yang 48939a9ad8fSSean Paul static int vop_enable(struct drm_crtc *crtc) 4902048e328SMark Yao { 4912048e328SMark Yao struct vop *vop = to_vop(crtc); 49264d77564SMark yao int ret, i; 4932048e328SMark Yao 4945d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 4955d82d1a7SMark Yao if (ret < 0) { 496d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 4975e570373SJeffy Chen return ret; 4985d82d1a7SMark Yao } 4995d82d1a7SMark Yao 5002048e328SMark Yao ret = clk_enable(vop->hclk); 50139a9ad8fSSean Paul if (WARN_ON(ret < 0)) 50239a9ad8fSSean Paul goto err_put_pm_runtime; 5032048e328SMark Yao 5042048e328SMark Yao ret = clk_enable(vop->dclk); 50539a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5062048e328SMark Yao goto err_disable_hclk; 5072048e328SMark Yao 5082048e328SMark Yao ret = clk_enable(vop->aclk); 50939a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5102048e328SMark Yao goto err_disable_dclk; 5112048e328SMark Yao 5122048e328SMark Yao /* 5132048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5142048e328SMark Yao * automatically with this master device via common driver code. 5152048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5162048e328SMark Yao * mapping. 5172048e328SMark Yao */ 5182048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5192048e328SMark Yao if (ret) { 520d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 521d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 5222048e328SMark Yao goto err_disable_aclk; 5232048e328SMark Yao } 5242048e328SMark Yao 52576f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 52676f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 52776f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 52876f1416eSMarc Zyngier 52964d77564SMark yao /* 53064d77564SMark yao * We need to make sure that all windows are disabled before we 53164d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 53264d77564SMark yao * buffer later. 53364d77564SMark yao */ 53464d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 53564d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 53664d77564SMark yao const struct vop_win_data *win = vop_win->data; 53764d77564SMark yao 53864d77564SMark yao VOP_WIN_SET(vop, win, enable, 0); 53964d77564SMark yao } 54076f1416eSMarc Zyngier spin_unlock(&vop->reg_lock); 54164d77564SMark yao 54217a794d7SChris Zhong vop_cfg_done(vop); 54317a794d7SChris Zhong 54452ab7891SMark Yao /* 54552ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 54652ab7891SMark Yao */ 54752ab7891SMark Yao vop->is_enabled = true; 54852ab7891SMark Yao 5492048e328SMark Yao spin_lock(&vop->reg_lock); 5502048e328SMark Yao 5519a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 5522048e328SMark Yao 5532048e328SMark Yao spin_unlock(&vop->reg_lock); 5542048e328SMark Yao 5552048e328SMark Yao enable_irq(vop->irq); 5562048e328SMark Yao 557b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 5582048e328SMark Yao 55939a9ad8fSSean Paul return 0; 5602048e328SMark Yao 5612048e328SMark Yao err_disable_aclk: 5622048e328SMark Yao clk_disable(vop->aclk); 5632048e328SMark Yao err_disable_dclk: 5642048e328SMark Yao clk_disable(vop->dclk); 5652048e328SMark Yao err_disable_hclk: 5662048e328SMark Yao clk_disable(vop->hclk); 56739a9ad8fSSean Paul err_put_pm_runtime: 56839a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 56939a9ad8fSSean Paul return ret; 5702048e328SMark Yao } 5712048e328SMark Yao 57264581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 57364581714SLaurent Pinchart struct drm_crtc_state *old_state) 5742048e328SMark Yao { 5752048e328SMark Yao struct vop *vop = to_vop(crtc); 5762048e328SMark Yao 577893b6cadSDaniel Vetter WARN_ON(vop->event); 578893b6cadSDaniel Vetter 579e334d48bSzain wang mutex_lock(&vop->vop_lock); 580b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 5812048e328SMark Yao 5822048e328SMark Yao /* 5831067219bSMark Yao * Vop standby will take effect at end of current frame, 5841067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5851067219bSMark Yao * 5861067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5871067219bSMark Yao * if not, memory bus maybe dead. 5882048e328SMark Yao */ 5891067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 5901067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 5911067219bSMark Yao 5922048e328SMark Yao spin_lock(&vop->reg_lock); 5932048e328SMark Yao 5949a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 5952048e328SMark Yao 5962048e328SMark Yao spin_unlock(&vop->reg_lock); 59752ab7891SMark Yao 5981067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 5992048e328SMark Yao 6001067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6011067219bSMark Yao 6021067219bSMark Yao disable_irq(vop->irq); 6031067219bSMark Yao 6041067219bSMark Yao vop->is_enabled = false; 6051067219bSMark Yao 6061067219bSMark Yao /* 6071067219bSMark Yao * vop standby complete, so iommu detach is safe. 6081067219bSMark Yao */ 6092048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6102048e328SMark Yao 6111067219bSMark Yao clk_disable(vop->dclk); 6122048e328SMark Yao clk_disable(vop->aclk); 6132048e328SMark Yao clk_disable(vop->hclk); 6145d82d1a7SMark Yao pm_runtime_put(vop->dev); 615e334d48bSzain wang mutex_unlock(&vop->vop_lock); 616893b6cadSDaniel Vetter 617893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 618893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 619893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 620893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 621893b6cadSDaniel Vetter 622893b6cadSDaniel Vetter crtc->state->event = NULL; 623893b6cadSDaniel Vetter } 6242048e328SMark Yao } 6252048e328SMark Yao 62663ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 6272048e328SMark Yao { 62863ebb9faSMark Yao drm_plane_cleanup(plane); 6292048e328SMark Yao } 6302048e328SMark Yao 63163ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 63263ebb9faSMark Yao struct drm_plane_state *state) 6332048e328SMark Yao { 63463ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 63592915da6SJohn Keeping struct drm_crtc_state *crtc_state; 63663ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 6372048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 6382048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6392048e328SMark Yao int ret; 6404c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 6414c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6424c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 6434c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6442048e328SMark Yao 64563ebb9faSMark Yao if (!crtc || !fb) 646d47a7246STomasz Figa return 0; 64792915da6SJohn Keeping 64892915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 64992915da6SJohn Keeping if (WARN_ON(!crtc_state)) 65092915da6SJohn Keeping return -EINVAL; 65192915da6SJohn Keeping 65281af63a4SVille Syrjälä ret = drm_atomic_helper_check_plane_state(state, crtc_state, 653f9b96be0SVille Syrjälä min_scale, max_scale, 654f9b96be0SVille Syrjälä true, true); 6552048e328SMark Yao if (ret) 6562048e328SMark Yao return ret; 6572048e328SMark Yao 658f9b96be0SVille Syrjälä if (!state->visible) 659d47a7246STomasz Figa return 0; 6602048e328SMark Yao 661438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 662d47a7246STomasz Figa if (ret < 0) 663d47a7246STomasz Figa return ret; 66484c7f8caSMark Yao 66584c7f8caSMark Yao /* 66684c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 66784c7f8caSMark Yao * need align with 2 pixel. 66884c7f8caSMark Yao */ 669d415fb87SMark yao if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) { 670d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 67163ebb9faSMark Yao return -EINVAL; 672d415fb87SMark yao } 67363ebb9faSMark Yao 67463ebb9faSMark Yao return 0; 67584c7f8caSMark Yao } 67684c7f8caSMark Yao 67763ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 67863ebb9faSMark Yao struct drm_plane_state *old_state) 67963ebb9faSMark Yao { 68063ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 68163ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 68263ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 6832048e328SMark Yao 68463ebb9faSMark Yao if (!old_state->crtc) 68563ebb9faSMark Yao return; 6862048e328SMark Yao 68763ebb9faSMark Yao spin_lock(&vop->reg_lock); 6882048e328SMark Yao 68963ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 6902048e328SMark Yao 69163ebb9faSMark Yao spin_unlock(&vop->reg_lock); 69263ebb9faSMark Yao } 69363ebb9faSMark Yao 69463ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 69563ebb9faSMark Yao struct drm_plane_state *old_state) 69663ebb9faSMark Yao { 69763ebb9faSMark Yao struct drm_plane_state *state = plane->state; 69863ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 69963ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 70063ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 70163ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 70263ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 70363ebb9faSMark Yao unsigned int actual_w, actual_h; 70463ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 70563ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 706ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 707ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 70863ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 70963ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 71063ebb9faSMark Yao unsigned long offset; 71163ebb9faSMark Yao dma_addr_t dma_addr; 71263ebb9faSMark Yao uint32_t val; 71363ebb9faSMark Yao bool rb_swap; 71458badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 715d47a7246STomasz Figa int format; 71663ebb9faSMark Yao 71763ebb9faSMark Yao /* 71863ebb9faSMark Yao * can't update plane when vop is disabled. 71963ebb9faSMark Yao */ 7204f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 72163ebb9faSMark Yao return; 72263ebb9faSMark Yao 72363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 72463ebb9faSMark Yao return; 72563ebb9faSMark Yao 726d47a7246STomasz Figa if (!state->visible) { 72763ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 72863ebb9faSMark Yao return; 72963ebb9faSMark Yao } 73063ebb9faSMark Yao 73163ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 73263ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 73363ebb9faSMark Yao 73463ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 73563ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 73663ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 73763ebb9faSMark Yao 73863ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 73963ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 74063ebb9faSMark Yao 74163ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 74263ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 74363ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 74463ebb9faSMark Yao 745353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 74663ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 747d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 748d47a7246STomasz Figa 749438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 75063ebb9faSMark Yao 75163ebb9faSMark Yao spin_lock(&vop->reg_lock); 75263ebb9faSMark Yao 753d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 754da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 755d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 756438b74a5SVille Syrjälä if (is_yuv_support(fb->format->format)) { 757438b74a5SVille Syrjälä int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 758438b74a5SVille Syrjälä int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 759353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 76084c7f8caSMark Yao 76184c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 76284c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 76384c7f8caSMark Yao 76463ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 76563ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 76684c7f8caSMark Yao 76763ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 768da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 76963ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 77084c7f8caSMark Yao } 7714c156c21SMark Yao 7724c156c21SMark Yao if (win->phy->scl) 7734c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 77463ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 775438b74a5SVille Syrjälä fb->format->format); 7764c156c21SMark Yao 77763ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 77863ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 77963ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 7804c156c21SMark Yao 781438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 78285a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 7832048e328SMark Yao 78458badaa7SKristian H. Kristensen /* 78558badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 78658badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 78758badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 78858badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 78958badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 79058badaa7SKristian H. Kristensen */ 79158badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 7922048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 7932048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 7942048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 7952048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 7962048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 7972048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 7982048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 7992048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 8002048e328SMark Yao } else { 8012048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 8022048e328SMark Yao } 8032048e328SMark Yao 8042048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 8052048e328SMark Yao spin_unlock(&vop->reg_lock); 8062048e328SMark Yao } 8072048e328SMark Yao 80863ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 80963ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 81063ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 81163ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 81263ebb9faSMark Yao }; 81363ebb9faSMark Yao 8142048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 81563ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 81663ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 8172048e328SMark Yao .destroy = vop_plane_destroy, 818d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 819d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 820d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 8212048e328SMark Yao }; 8222048e328SMark Yao 8232048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 8242048e328SMark Yao { 8252048e328SMark Yao struct vop *vop = to_vop(crtc); 8262048e328SMark Yao unsigned long flags; 8272048e328SMark Yao 82863ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8292048e328SMark Yao return -EPERM; 8302048e328SMark Yao 8312048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 8322048e328SMark Yao 833fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 834dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 8352048e328SMark Yao 8362048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8372048e328SMark Yao 8382048e328SMark Yao return 0; 8392048e328SMark Yao } 8402048e328SMark Yao 8412048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 8422048e328SMark Yao { 8432048e328SMark Yao struct vop *vop = to_vop(crtc); 8442048e328SMark Yao unsigned long flags; 8452048e328SMark Yao 84663ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8472048e328SMark Yao return; 84831e980c5SMark Yao 8492048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 850dbb3d944SMark Yao 851dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 852dbb3d944SMark Yao 8532048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8542048e328SMark Yao } 8552048e328SMark Yao 8562048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 8572048e328SMark Yao const struct drm_display_mode *mode, 8582048e328SMark Yao struct drm_display_mode *adjusted_mode) 8592048e328SMark Yao { 860b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 861b59b8de3SChris Zhong 862b59b8de3SChris Zhong adjusted_mode->clock = 863b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 864b59b8de3SChris Zhong 8652048e328SMark Yao return true; 8662048e328SMark Yao } 8672048e328SMark Yao 8680b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 8690b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 8702048e328SMark Yao { 8712048e328SMark Yao struct vop *vop = to_vop(crtc); 872efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 8734e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 87463ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 8752048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 8762048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 8772048e328SMark Yao u16 htotal = adjusted_mode->htotal; 8782048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 8792048e328SMark Yao u16 hact_end = hact_st + hdisplay; 8802048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 8812048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 8822048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 8832048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 8842048e328SMark Yao u16 vact_end = vact_st + vdisplay; 8850a63bfd0SMark Yao uint32_t pin_pol, val; 88639a9ad8fSSean Paul int ret; 8872048e328SMark Yao 888e334d48bSzain wang mutex_lock(&vop->vop_lock); 889e334d48bSzain wang 890893b6cadSDaniel Vetter WARN_ON(vop->event); 891893b6cadSDaniel Vetter 89239a9ad8fSSean Paul ret = vop_enable(crtc); 89339a9ad8fSSean Paul if (ret) { 894e334d48bSzain wang mutex_unlock(&vop->vop_lock); 89539a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 89639a9ad8fSSean Paul return; 89739a9ad8fSSean Paul } 89839a9ad8fSSean Paul 8991a0f7ed3SChris Zhong pin_pol = BIT(DCLK_INVERT); 900d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 901d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 902d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 903d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 9049a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 9050a63bfd0SMark Yao 9064e257d9eSMark Yao switch (s->output_type) { 9074e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 9089a61c54bSMark yao VOP_REG_SET(vop, output, rgb_en, 1); 9099a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 9104e257d9eSMark Yao break; 9114e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 9129a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 9139a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 9144e257d9eSMark Yao break; 9154e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 9169a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 9179a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 9184e257d9eSMark Yao break; 9194e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 9209a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 9219a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 9224e257d9eSMark Yao break; 9231a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 9241a0f7ed3SChris Zhong pin_pol &= ~BIT(DCLK_INVERT); 9259a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 9269a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 9271a0f7ed3SChris Zhong break; 9284e257d9eSMark Yao default: 929ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 930ee4d7899SSean Paul s->output_type); 9314e257d9eSMark Yao } 932efd11cc8SMark yao 933efd11cc8SMark yao /* 934efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 935efd11cc8SMark yao */ 936efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 937efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 938efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 9396bda8112SMark Yao 9406bda8112SMark Yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8) 9416bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 9426bda8112SMark Yao else 9436bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 9446bda8112SMark Yao 9459a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 9462048e328SMark Yao 9479a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 9482048e328SMark Yao val = hact_st << 16; 9492048e328SMark Yao val |= hact_end; 9509a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 9519a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 9522048e328SMark Yao 9539a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 9542048e328SMark Yao val = vact_st << 16; 9552048e328SMark Yao val |= vact_end; 9569a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 9579a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 9582048e328SMark Yao 9599a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 960459b086dSJeffy Chen 9612048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 962ce3887edSMark Yao 9639a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 964e334d48bSzain wang mutex_unlock(&vop->vop_lock); 9652048e328SMark Yao } 9662048e328SMark Yao 9677caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 9687caecdbeSTomasz Figa { 9697caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 9707caecdbeSTomasz Figa } 9717caecdbeSTomasz Figa 9727caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 9737caecdbeSTomasz Figa { 9747caecdbeSTomasz Figa bool pending; 9757caecdbeSTomasz Figa int ret; 9767caecdbeSTomasz Figa 9777caecdbeSTomasz Figa /* 9787caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 9797caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 9807caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 9817caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 9827caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 9837caecdbeSTomasz Figa * shouldn't exceed microseconds range. 9847caecdbeSTomasz Figa */ 9857caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 9867caecdbeSTomasz Figa !pending, 0, 10 * 1000); 9877caecdbeSTomasz Figa if (ret) 9887caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 9897caecdbeSTomasz Figa 9907caecdbeSTomasz Figa synchronize_irq(vop->irq); 9917caecdbeSTomasz Figa } 9927caecdbeSTomasz Figa 99363ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 99463ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 99563ebb9faSMark Yao { 99647a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 997e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 99863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 99947a7eb45STomasz Figa struct drm_plane *plane; 100047a7eb45STomasz Figa int i; 100163ebb9faSMark Yao 100263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 100363ebb9faSMark Yao return; 100463ebb9faSMark Yao 100563ebb9faSMark Yao spin_lock(&vop->reg_lock); 100663ebb9faSMark Yao 100763ebb9faSMark Yao vop_cfg_done(vop); 100863ebb9faSMark Yao 100963ebb9faSMark Yao spin_unlock(&vop->reg_lock); 10107caecdbeSTomasz Figa 10117caecdbeSTomasz Figa /* 10127caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 10137caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 10147caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 10157caecdbeSTomasz Figa */ 10167caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 101747a7eb45STomasz Figa 101841ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 101941ee4367STomasz Figa if (crtc->state->event) { 102041ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 102141ee4367STomasz Figa WARN_ON(vop->event); 102241ee4367STomasz Figa 102341ee4367STomasz Figa vop->event = crtc->state->event; 102441ee4367STomasz Figa crtc->state->event = NULL; 102541ee4367STomasz Figa } 102641ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 102741ee4367STomasz Figa 1028e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1029e741f2b1SMaarten Lankhorst new_plane_state, i) { 103047a7eb45STomasz Figa if (!old_plane_state->fb) 103147a7eb45STomasz Figa continue; 103247a7eb45STomasz Figa 1033e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 103447a7eb45STomasz Figa continue; 103547a7eb45STomasz Figa 1036adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 10372d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 103847a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 103947a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 104047a7eb45STomasz Figa } 104163ebb9faSMark Yao } 104263ebb9faSMark Yao 10432048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 10442048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 104563ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 10460b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 104764581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 10482048e328SMark Yao }; 10492048e328SMark Yao 10502048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 10512048e328SMark Yao { 10522048e328SMark Yao drm_crtc_cleanup(crtc); 10532048e328SMark Yao } 10542048e328SMark Yao 1055dc0b408fSJohn Keeping static void vop_crtc_reset(struct drm_crtc *crtc) 1056dc0b408fSJohn Keeping { 1057dc0b408fSJohn Keeping if (crtc->state) 1058dc0b408fSJohn Keeping __drm_atomic_helper_crtc_destroy_state(crtc->state); 1059dc0b408fSJohn Keeping kfree(crtc->state); 1060dc0b408fSJohn Keeping 1061dc0b408fSJohn Keeping crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1062dc0b408fSJohn Keeping if (crtc->state) 1063dc0b408fSJohn Keeping crtc->state->crtc = crtc; 1064dc0b408fSJohn Keeping } 1065dc0b408fSJohn Keeping 10664e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 10674e257d9eSMark Yao { 10684e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 10694e257d9eSMark Yao 10704e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 10714e257d9eSMark Yao if (!rockchip_state) 10724e257d9eSMark Yao return NULL; 10734e257d9eSMark Yao 10744e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 10754e257d9eSMark Yao return &rockchip_state->base; 10764e257d9eSMark Yao } 10774e257d9eSMark Yao 10784e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 10794e257d9eSMark Yao struct drm_crtc_state *state) 10804e257d9eSMark Yao { 10814e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 10824e257d9eSMark Yao 1083ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 10844e257d9eSMark Yao kfree(s); 10854e257d9eSMark Yao } 10864e257d9eSMark Yao 10876cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 10883190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 10893190e58dSTomeu Vizoso { 10903190e58dSTomeu Vizoso struct drm_connector *connector; 10912cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 10923190e58dSTomeu Vizoso 10932cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 10942cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 10953190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 10962cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 10973190e58dSTomeu Vizoso return connector; 10983190e58dSTomeu Vizoso } 10992cbeb64fSGustavo Padovan } 11002cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 11013190e58dSTomeu Vizoso 11023190e58dSTomeu Vizoso return NULL; 11033190e58dSTomeu Vizoso } 11043190e58dSTomeu Vizoso 11053190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 11063190e58dSTomeu Vizoso const char *source_name, size_t *values_cnt) 11073190e58dSTomeu Vizoso { 11083190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 11093190e58dSTomeu Vizoso struct drm_connector *connector; 11103190e58dSTomeu Vizoso int ret; 11113190e58dSTomeu Vizoso 11123190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 11133190e58dSTomeu Vizoso if (!connector) 11143190e58dSTomeu Vizoso return -EINVAL; 11153190e58dSTomeu Vizoso 11163190e58dSTomeu Vizoso *values_cnt = 3; 11173190e58dSTomeu Vizoso 11183190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 11193190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 11203190e58dSTomeu Vizoso else if (!source_name) 11213190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 11223190e58dSTomeu Vizoso else 11233190e58dSTomeu Vizoso ret = -EINVAL; 11243190e58dSTomeu Vizoso 11253190e58dSTomeu Vizoso return ret; 11263190e58dSTomeu Vizoso } 11276cca3869SSean Paul #else 11286cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 11296cca3869SSean Paul const char *source_name, size_t *values_cnt) 11306cca3869SSean Paul { 11316cca3869SSean Paul return -ENODEV; 11326cca3869SSean Paul } 11336cca3869SSean Paul #endif 11343190e58dSTomeu Vizoso 11352048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 113663ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 113763ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 11382048e328SMark Yao .destroy = vop_crtc_destroy, 1139dc0b408fSJohn Keeping .reset = vop_crtc_reset, 11404e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 11414e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1142c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1143c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 11443190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 11452048e328SMark Yao }; 11462048e328SMark Yao 114747a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 114847a7eb45STomasz Figa { 114947a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 115047a7eb45STomasz Figa struct drm_framebuffer *fb = val; 115147a7eb45STomasz Figa 115247a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1153adedbf03SCihangir Akturk drm_framebuffer_put(fb); 115447a7eb45STomasz Figa } 115547a7eb45STomasz Figa 115663ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 11572048e328SMark Yao { 115863ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 115963ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 11602048e328SMark Yao 11611c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1162893b6cadSDaniel Vetter if (vop->event) { 116363ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 11645b680403SSean Paul drm_crtc_vblank_put(crtc); 1165646ec687STomasz Figa vop->event = NULL; 11665b680403SSean Paul } 11671c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1168893b6cadSDaniel Vetter 116947a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 117047a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 11712048e328SMark Yao } 11722048e328SMark Yao 11732048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 11742048e328SMark Yao { 11752048e328SMark Yao struct vop *vop = data; 1176b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1177dbb3d944SMark Yao uint32_t active_irqs; 11781067219bSMark Yao int ret = IRQ_NONE; 11792048e328SMark Yao 11802048e328SMark Yao /* 1181dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 11822048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 11832048e328SMark Yao */ 11841c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1185dbb3d944SMark Yao 1186dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 11872048e328SMark Yao /* Clear all active interrupt sources */ 11882048e328SMark Yao if (active_irqs) 1189dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1190dbb3d944SMark Yao 11911c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 11922048e328SMark Yao 11932048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 11942048e328SMark Yao if (!active_irqs) 11952048e328SMark Yao return IRQ_NONE; 11962048e328SMark Yao 11971067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 11981067219bSMark Yao complete(&vop->dsp_hold_completion); 11991067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 12001067219bSMark Yao ret = IRQ_HANDLED; 12012048e328SMark Yao } 12022048e328SMark Yao 120369c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 120469c34e41SYakir Yang complete(&vop->line_flag_completion); 120569c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 120669c34e41SYakir Yang ret = IRQ_HANDLED; 120769c34e41SYakir Yang } 120869c34e41SYakir Yang 12091067219bSMark Yao if (active_irqs & FS_INTR) { 1210b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 121163ebb9faSMark Yao vop_handle_vblank(vop); 12121067219bSMark Yao active_irqs &= ~FS_INTR; 121363ebb9faSMark Yao ret = IRQ_HANDLED; 12141067219bSMark Yao } 12152048e328SMark Yao 12161067219bSMark Yao /* Unhandled irqs are spurious. */ 12171067219bSMark Yao if (active_irqs) 1218ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1219ee4d7899SSean Paul active_irqs); 12201067219bSMark Yao 12211067219bSMark Yao return ret; 12222048e328SMark Yao } 12232048e328SMark Yao 12242048e328SMark Yao static int vop_create_crtc(struct vop *vop) 12252048e328SMark Yao { 12262048e328SMark Yao const struct vop_data *vop_data = vop->data; 12272048e328SMark Yao struct device *dev = vop->dev; 12282048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1229328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 12302048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12312048e328SMark Yao struct device_node *port; 12322048e328SMark Yao int ret; 12332048e328SMark Yao int i; 12342048e328SMark Yao 12352048e328SMark Yao /* 12362048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 12372048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 12382048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 12392048e328SMark Yao */ 12402048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12412048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12422048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12432048e328SMark Yao 12442048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 12452048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 12462048e328SMark Yao continue; 12472048e328SMark Yao 12482048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12492048e328SMark Yao 0, &vop_plane_funcs, 12502048e328SMark Yao win_data->phy->data_formats, 12512048e328SMark Yao win_data->phy->nformats, 1252e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 12532048e328SMark Yao if (ret) { 1254ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1255ee4d7899SSean Paul ret); 12562048e328SMark Yao goto err_cleanup_planes; 12572048e328SMark Yao } 12582048e328SMark Yao 12592048e328SMark Yao plane = &vop_win->base; 126063ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 12612048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 12622048e328SMark Yao primary = plane; 12632048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 12642048e328SMark Yao cursor = plane; 12652048e328SMark Yao } 12662048e328SMark Yao 12672048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1268f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 12692048e328SMark Yao if (ret) 1270328b51c0SDouglas Anderson goto err_cleanup_planes; 12712048e328SMark Yao 12722048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 12732048e328SMark Yao 12742048e328SMark Yao /* 12752048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 12762048e328SMark Yao * to the newly created crtc. 12772048e328SMark Yao */ 12782048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12792048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12802048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12812048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 12822048e328SMark Yao 12832048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 12842048e328SMark Yao continue; 12852048e328SMark Yao 12862048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12872048e328SMark Yao possible_crtcs, 12882048e328SMark Yao &vop_plane_funcs, 12892048e328SMark Yao win_data->phy->data_formats, 12902048e328SMark Yao win_data->phy->nformats, 1291e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 12922048e328SMark Yao if (ret) { 1293ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1294ee4d7899SSean Paul ret); 12952048e328SMark Yao goto err_cleanup_crtc; 12962048e328SMark Yao } 129763ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 12982048e328SMark Yao } 12992048e328SMark Yao 13002048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 13012048e328SMark Yao if (!port) { 13024bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 13034bf99144SRob Herring dev->of_node); 1304328b51c0SDouglas Anderson ret = -ENOENT; 13052048e328SMark Yao goto err_cleanup_crtc; 13062048e328SMark Yao } 13072048e328SMark Yao 130847a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 130947a7eb45STomasz Figa vop_fb_unref_worker); 131047a7eb45STomasz Figa 13111067219bSMark Yao init_completion(&vop->dsp_hold_completion); 131269c34e41SYakir Yang init_completion(&vop->line_flag_completion); 13132048e328SMark Yao crtc->port = port; 13142048e328SMark Yao 13152048e328SMark Yao return 0; 13162048e328SMark Yao 13172048e328SMark Yao err_cleanup_crtc: 13182048e328SMark Yao drm_crtc_cleanup(crtc); 13192048e328SMark Yao err_cleanup_planes: 1320328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1321328b51c0SDouglas Anderson head) 13222048e328SMark Yao drm_plane_cleanup(plane); 13232048e328SMark Yao return ret; 13242048e328SMark Yao } 13252048e328SMark Yao 13262048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 13272048e328SMark Yao { 13282048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1329328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1330328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 13312048e328SMark Yao 13322048e328SMark Yao of_node_put(crtc->port); 1333328b51c0SDouglas Anderson 1334328b51c0SDouglas Anderson /* 1335328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1336328b51c0SDouglas Anderson * 1337328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1338328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1339328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1340328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1341328b51c0SDouglas Anderson */ 1342328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1343328b51c0SDouglas Anderson head) 1344328b51c0SDouglas Anderson vop_plane_destroy(plane); 1345328b51c0SDouglas Anderson 1346328b51c0SDouglas Anderson /* 1347328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1348328b51c0SDouglas Anderson * references the CRTC. 1349328b51c0SDouglas Anderson */ 13502048e328SMark Yao drm_crtc_cleanup(crtc); 135147a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 13522048e328SMark Yao } 13532048e328SMark Yao 13542048e328SMark Yao static int vop_initial(struct vop *vop) 13552048e328SMark Yao { 13562048e328SMark Yao const struct vop_data *vop_data = vop->data; 13572048e328SMark Yao struct reset_control *ahb_rst; 13582048e328SMark Yao int i, ret; 13592048e328SMark Yao 13602048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 13612048e328SMark Yao if (IS_ERR(vop->hclk)) { 1362d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 13632048e328SMark Yao return PTR_ERR(vop->hclk); 13642048e328SMark Yao } 13652048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 13662048e328SMark Yao if (IS_ERR(vop->aclk)) { 1367d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 13682048e328SMark Yao return PTR_ERR(vop->aclk); 13692048e328SMark Yao } 13702048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 13712048e328SMark Yao if (IS_ERR(vop->dclk)) { 1372d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 13732048e328SMark Yao return PTR_ERR(vop->dclk); 13742048e328SMark Yao } 13752048e328SMark Yao 13765e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 13775e570373SJeffy Chen if (ret < 0) { 1378d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 13795e570373SJeffy Chen return ret; 13805e570373SJeffy Chen } 13815e570373SJeffy Chen 13822048e328SMark Yao ret = clk_prepare(vop->dclk); 13832048e328SMark Yao if (ret < 0) { 1384d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 13855e570373SJeffy Chen goto err_put_pm_runtime; 13862048e328SMark Yao } 13872048e328SMark Yao 1388d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1389d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 13902048e328SMark Yao if (ret < 0) { 1391d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 13922048e328SMark Yao goto err_unprepare_dclk; 13932048e328SMark Yao } 13942048e328SMark Yao 1395d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 13962048e328SMark Yao if (ret < 0) { 1397d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1398d7b53fd9SSjoerd Simons goto err_disable_hclk; 13992048e328SMark Yao } 1400d7b53fd9SSjoerd Simons 14012048e328SMark Yao /* 14022048e328SMark Yao * do hclk_reset, reset all vop registers. 14032048e328SMark Yao */ 14042048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 14052048e328SMark Yao if (IS_ERR(ahb_rst)) { 1406d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 14072048e328SMark Yao ret = PTR_ERR(ahb_rst); 1408d7b53fd9SSjoerd Simons goto err_disable_aclk; 14092048e328SMark Yao } 14102048e328SMark Yao reset_control_assert(ahb_rst); 14112048e328SMark Yao usleep_range(10, 20); 14122048e328SMark Yao reset_control_deassert(ahb_rst); 14132048e328SMark Yao 14145f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 14155f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 14165f9e93feSMarc Zyngier 141776f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 141876f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 14192048e328SMark Yao 14209a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 14219a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 14222048e328SMark Yao 14232048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14242048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 14259dd2aca4SMark yao int channel = i * 2 + 1; 14262048e328SMark Yao 14279dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 14282048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 142960b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 14302048e328SMark Yao } 14312048e328SMark Yao 14322048e328SMark Yao vop_cfg_done(vop); 14332048e328SMark Yao 14342048e328SMark Yao /* 14352048e328SMark Yao * do dclk_reset, let all config take affect. 14362048e328SMark Yao */ 14372048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 14382048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1439d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 14402048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1441d7b53fd9SSjoerd Simons goto err_disable_aclk; 14422048e328SMark Yao } 14432048e328SMark Yao reset_control_assert(vop->dclk_rst); 14442048e328SMark Yao usleep_range(10, 20); 14452048e328SMark Yao reset_control_deassert(vop->dclk_rst); 14462048e328SMark Yao 14472048e328SMark Yao clk_disable(vop->hclk); 1448d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 14492048e328SMark Yao 145031e980c5SMark Yao vop->is_enabled = false; 14512048e328SMark Yao 14525e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14535e570373SJeffy Chen 14542048e328SMark Yao return 0; 14552048e328SMark Yao 1456d7b53fd9SSjoerd Simons err_disable_aclk: 1457d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 14582048e328SMark Yao err_disable_hclk: 1459d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 14602048e328SMark Yao err_unprepare_dclk: 14612048e328SMark Yao clk_unprepare(vop->dclk); 14625e570373SJeffy Chen err_put_pm_runtime: 14635e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14642048e328SMark Yao return ret; 14652048e328SMark Yao } 14662048e328SMark Yao 14672048e328SMark Yao /* 14682048e328SMark Yao * Initialize the vop->win array elements. 14692048e328SMark Yao */ 14702048e328SMark Yao static void vop_win_init(struct vop *vop) 14712048e328SMark Yao { 14722048e328SMark Yao const struct vop_data *vop_data = vop->data; 14732048e328SMark Yao unsigned int i; 14742048e328SMark Yao 14752048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14762048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14772048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 14782048e328SMark Yao 14792048e328SMark Yao vop_win->data = win_data; 14802048e328SMark Yao vop_win->vop = vop; 14812048e328SMark Yao } 14822048e328SMark Yao } 14832048e328SMark Yao 148469c34e41SYakir Yang /** 1485459b086dSJeffy Chen * rockchip_drm_wait_vact_end 148669c34e41SYakir Yang * @crtc: CRTC to enable line flag 148769c34e41SYakir Yang * @mstimeout: millisecond for timeout 148869c34e41SYakir Yang * 1489459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 149069c34e41SYakir Yang * 149169c34e41SYakir Yang * Returns: 149269c34e41SYakir Yang * Zero on success, negative errno on failure. 149369c34e41SYakir Yang */ 1494459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 149569c34e41SYakir Yang { 149669c34e41SYakir Yang struct vop *vop = to_vop(crtc); 149769c34e41SYakir Yang unsigned long jiffies_left; 1498e334d48bSzain wang int ret = 0; 149969c34e41SYakir Yang 150069c34e41SYakir Yang if (!crtc || !vop->is_enabled) 150169c34e41SYakir Yang return -ENODEV; 150269c34e41SYakir Yang 1503e334d48bSzain wang mutex_lock(&vop->vop_lock); 1504e334d48bSzain wang if (mstimeout <= 0) { 1505e334d48bSzain wang ret = -EINVAL; 1506e334d48bSzain wang goto out; 1507e334d48bSzain wang } 150869c34e41SYakir Yang 1509e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 1510e334d48bSzain wang ret = -EBUSY; 1511e334d48bSzain wang goto out; 1512e334d48bSzain wang } 151369c34e41SYakir Yang 151469c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1515459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 151669c34e41SYakir Yang 151769c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 151869c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 151969c34e41SYakir Yang vop_line_flag_irq_disable(vop); 152069c34e41SYakir Yang 152169c34e41SYakir Yang if (jiffies_left == 0) { 1522d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1523e334d48bSzain wang ret = -ETIMEDOUT; 1524e334d48bSzain wang goto out; 152569c34e41SYakir Yang } 152669c34e41SYakir Yang 1527e334d48bSzain wang out: 1528e334d48bSzain wang mutex_unlock(&vop->vop_lock); 1529e334d48bSzain wang return ret; 153069c34e41SYakir Yang } 1531459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 153269c34e41SYakir Yang 15332048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 15342048e328SMark Yao { 15352048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 15362048e328SMark Yao const struct vop_data *vop_data; 15372048e328SMark Yao struct drm_device *drm_dev = data; 15382048e328SMark Yao struct vop *vop; 15392048e328SMark Yao struct resource *res; 15402048e328SMark Yao size_t alloc_size; 15413ea68922SHeiko Stuebner int ret, irq; 15422048e328SMark Yao 1543a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 15442048e328SMark Yao if (!vop_data) 15452048e328SMark Yao return -ENODEV; 15462048e328SMark Yao 15472048e328SMark Yao /* Allocate vop struct and its vop_win array */ 15482048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 15492048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 15502048e328SMark Yao if (!vop) 15512048e328SMark Yao return -ENOMEM; 15522048e328SMark Yao 15532048e328SMark Yao vop->dev = dev; 15542048e328SMark Yao vop->data = vop_data; 15552048e328SMark Yao vop->drm_dev = drm_dev; 15562048e328SMark Yao dev_set_drvdata(dev, vop); 15572048e328SMark Yao 15582048e328SMark Yao vop_win_init(vop); 15592048e328SMark Yao 15602048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15612048e328SMark Yao vop->len = resource_size(res); 15622048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 15632048e328SMark Yao if (IS_ERR(vop->regs)) 15642048e328SMark Yao return PTR_ERR(vop->regs); 15652048e328SMark Yao 15662048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 15672048e328SMark Yao if (!vop->regsbak) 15682048e328SMark Yao return -ENOMEM; 15692048e328SMark Yao 15703ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 15713ea68922SHeiko Stuebner if (irq < 0) { 1572d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 15733ea68922SHeiko Stuebner return irq; 15742048e328SMark Yao } 15753ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 15762048e328SMark Yao 15772048e328SMark Yao spin_lock_init(&vop->reg_lock); 15782048e328SMark Yao spin_lock_init(&vop->irq_lock); 1579e334d48bSzain wang mutex_init(&vop->vop_lock); 15802048e328SMark Yao 15812048e328SMark Yao ret = vop_create_crtc(vop); 15822048e328SMark Yao if (ret) 15835f9e93feSMarc Zyngier return ret; 15842048e328SMark Yao 15852048e328SMark Yao pm_runtime_enable(&pdev->dev); 15865182c1a5SYakir Yang 15875e570373SJeffy Chen ret = vop_initial(vop); 15885e570373SJeffy Chen if (ret < 0) { 1589d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 1590d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 15915e570373SJeffy Chen goto err_disable_pm_runtime; 15925e570373SJeffy Chen } 15935e570373SJeffy Chen 15945f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 15955f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 15965f9e93feSMarc Zyngier if (ret) 15975f9e93feSMarc Zyngier goto err_disable_pm_runtime; 15985f9e93feSMarc Zyngier 15995f9e93feSMarc Zyngier /* IRQ is initially disabled; it gets enabled in power_on */ 16005f9e93feSMarc Zyngier disable_irq(vop->irq); 16015f9e93feSMarc Zyngier 16022048e328SMark Yao return 0; 16038c763c9bSSean Paul 16045e570373SJeffy Chen err_disable_pm_runtime: 16055e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 16065e570373SJeffy Chen vop_destroy_crtc(vop); 16078c763c9bSSean Paul return ret; 16082048e328SMark Yao } 16092048e328SMark Yao 16102048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 16112048e328SMark Yao { 16122048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 16132048e328SMark Yao 16142048e328SMark Yao pm_runtime_disable(dev); 16152048e328SMark Yao vop_destroy_crtc(vop); 1616ec6e7767SJeffy Chen 1617ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 1618ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 1619ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 16202048e328SMark Yao } 16212048e328SMark Yao 1622a67719d1SMark Yao const struct component_ops vop_component_ops = { 16232048e328SMark Yao .bind = vop_bind, 16242048e328SMark Yao .unbind = vop_unbind, 16252048e328SMark Yao }; 162654255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1627