12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 1815609559SEnric Balletbo i Serra #include <drm/drm_atomic_uapi.h> 192048e328SMark Yao #include <drm/drm_crtc.h> 2047a7eb45STomasz Figa #include <drm/drm_flip_work.h> 2163d5e06aSHeiko Stuebner #include <drm/drm_gem_framebuffer_helper.h> 222048e328SMark Yao #include <drm/drm_plane_helper.h> 23fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 246cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 253190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 266cca3869SSean Paul #endif 272048e328SMark Yao 282048e328SMark Yao #include <linux/kernel.h> 2900fe6148SPaul Gortmaker #include <linux/module.h> 302048e328SMark Yao #include <linux/platform_device.h> 312048e328SMark Yao #include <linux/clk.h> 327caecdbeSTomasz Figa #include <linux/iopoll.h> 332048e328SMark Yao #include <linux/of.h> 342048e328SMark Yao #include <linux/of_device.h> 352048e328SMark Yao #include <linux/pm_runtime.h> 362048e328SMark Yao #include <linux/component.h> 3729adeb4fSGustavo A. R. Silva #include <linux/overflow.h> 382048e328SMark Yao 392048e328SMark Yao #include <linux/reset.h> 402048e328SMark Yao #include <linux/delay.h> 412048e328SMark Yao 422048e328SMark Yao #include "rockchip_drm_drv.h" 432048e328SMark Yao #include "rockchip_drm_gem.h" 442048e328SMark Yao #include "rockchip_drm_fb.h" 455182c1a5SYakir Yang #include "rockchip_drm_psr.h" 462048e328SMark Yao #include "rockchip_drm_vop.h" 471f0f0151SSandy Huang #include "rockchip_rgb.h" 482048e328SMark Yao 492996fb75SEzequiel Garcia #define VOP_WIN_SET(vop, win, name, v) \ 509a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 512996fb75SEzequiel Garcia #define VOP_SCL_SET(vop, win, name, v) \ 529a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 532996fb75SEzequiel Garcia #define VOP_SCL_SET_EXT(vop, win, name, v) \ 549a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 559a61c54bSMark yao win->base, ~0, v, #name) 56ac6560dfSMark yao 572996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 581c21aa8fSDaniele Castagna do { \ 591c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 601c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 611c21aa8fSDaniele Castagna } while (0) 621c21aa8fSDaniele Castagna 632996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 641c21aa8fSDaniele Castagna do { \ 651c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 661c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 671c21aa8fSDaniele Castagna } while (0) 681c21aa8fSDaniele Castagna 69ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 709a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 719a61c54bSMark yao 729a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 739a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 74ac6560dfSMark yao 75dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 76dbb3d944SMark Yao do { \ 77c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 78dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 79c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 80dbb3d944SMark Yao reg |= (v) << i; \ 81c7647f86SJohn Keeping mask |= 1 << i; \ 82dbb3d944SMark Yao } \ 83c7647f86SJohn Keeping } \ 84ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 85dbb3d944SMark Yao } while (0) 86dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 87dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 88dbb3d944SMark Yao 892996fb75SEzequiel Garcia #define VOP_WIN_GET(vop, win, name) \ 902996fb75SEzequiel Garcia vop_read_reg(vop, win->offset, win->phy->name) 912048e328SMark Yao 92677e8bbcSDaniele Castagna #define VOP_WIN_HAS_REG(win, name) \ 93677e8bbcSDaniele Castagna (!!(win->phy->name.mask)) 94677e8bbcSDaniele Castagna 952048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 962048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 972048e328SMark Yao 9858badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 9958badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 10058badaa7SKristian H. Kristensen 1012048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 1022048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 1032048e328SMark Yao 1041c21aa8fSDaniele Castagna /* 1051c21aa8fSDaniele Castagna * The coefficients of the following matrix are all fixed points. 1061c21aa8fSDaniele Castagna * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 1071c21aa8fSDaniele Castagna * They are all represented in two's complement. 1081c21aa8fSDaniele Castagna */ 1091c21aa8fSDaniele Castagna static const uint32_t bt601_yuv2rgb[] = { 1101c21aa8fSDaniele Castagna 0x4A8, 0x0, 0x662, 1111c21aa8fSDaniele Castagna 0x4A8, 0x1E6F, 0x1CBF, 1121c21aa8fSDaniele Castagna 0x4A8, 0x812, 0x0, 1131c21aa8fSDaniele Castagna 0x321168, 0x0877CF, 0x2EB127 1141c21aa8fSDaniele Castagna }; 1151c21aa8fSDaniele Castagna 11647a7eb45STomasz Figa enum vop_pending { 11747a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 11847a7eb45STomasz Figa }; 11947a7eb45STomasz Figa 1202048e328SMark Yao struct vop_win { 1212048e328SMark Yao struct drm_plane base; 1222048e328SMark Yao const struct vop_win_data *data; 1231c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *yuv2yuv_data; 1242048e328SMark Yao struct vop *vop; 1252048e328SMark Yao }; 1262048e328SMark Yao 1271f0f0151SSandy Huang struct rockchip_rgb; 1282048e328SMark Yao struct vop { 1292048e328SMark Yao struct drm_crtc crtc; 1302048e328SMark Yao struct device *dev; 1312048e328SMark Yao struct drm_device *drm_dev; 13231e980c5SMark Yao bool is_enabled; 1332048e328SMark Yao 1341067219bSMark Yao struct completion dsp_hold_completion; 1354f9d39a7SDaniel Vetter 1364f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 13763ebb9faSMark Yao struct drm_pending_vblank_event *event; 1382048e328SMark Yao 13947a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 14047a7eb45STomasz Figa unsigned long pending; 14147a7eb45STomasz Figa 14269c34e41SYakir Yang struct completion line_flag_completion; 14369c34e41SYakir Yang 1442048e328SMark Yao const struct vop_data *data; 1452048e328SMark Yao 1462048e328SMark Yao uint32_t *regsbak; 1472048e328SMark Yao void __iomem *regs; 1482048e328SMark Yao 1492048e328SMark Yao /* physical map length of vop register */ 1502048e328SMark Yao uint32_t len; 1512048e328SMark Yao 1522048e328SMark Yao /* one time only one process allowed to config the register */ 1532048e328SMark Yao spinlock_t reg_lock; 1542048e328SMark Yao /* lock vop irq reg */ 1552048e328SMark Yao spinlock_t irq_lock; 156e334d48bSzain wang /* protects crtc enable/disable */ 157e334d48bSzain wang struct mutex vop_lock; 1582048e328SMark Yao 1592048e328SMark Yao unsigned int irq; 1602048e328SMark Yao 1612048e328SMark Yao /* vop AHP clk */ 1622048e328SMark Yao struct clk *hclk; 1632048e328SMark Yao /* vop dclk */ 1642048e328SMark Yao struct clk *dclk; 1652048e328SMark Yao /* vop share memory frequency */ 1662048e328SMark Yao struct clk *aclk; 1672048e328SMark Yao 1682048e328SMark Yao /* vop dclk reset */ 1692048e328SMark Yao struct reset_control *dclk_rst; 1702048e328SMark Yao 1711f0f0151SSandy Huang /* optional internal rgb encoder */ 1721f0f0151SSandy Huang struct rockchip_rgb *rgb; 1731f0f0151SSandy Huang 1742048e328SMark Yao struct vop_win win[]; 1752048e328SMark Yao }; 1762048e328SMark Yao 1772048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1782048e328SMark Yao { 1792048e328SMark Yao writel(v, vop->regs + offset); 1802048e328SMark Yao vop->regsbak[offset >> 2] = v; 1812048e328SMark Yao } 1822048e328SMark Yao 1832048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1842048e328SMark Yao { 1852048e328SMark Yao return readl(vop->regs + offset); 1862048e328SMark Yao } 1872048e328SMark Yao 1882048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1892048e328SMark Yao const struct vop_reg *reg) 1902048e328SMark Yao { 1912048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1922048e328SMark Yao } 1932048e328SMark Yao 1949a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 1959a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 1969a61c54bSMark yao const char *reg_name) 1972048e328SMark Yao { 1989a61c54bSMark yao int offset, mask, shift; 199d49463ecSMark Yao 2009a61c54bSMark yao if (!reg || !reg->mask) { 201d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 2029a61c54bSMark yao return; 2039a61c54bSMark yao } 2049a61c54bSMark yao 2059a61c54bSMark yao offset = reg->offset + _offset; 2069a61c54bSMark yao mask = reg->mask & _mask; 2079a61c54bSMark yao shift = reg->shift; 2089a61c54bSMark yao 2099a61c54bSMark yao if (reg->write_mask) { 210d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 211d49463ecSMark Yao } else { 2122048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 2132048e328SMark Yao 214d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 215d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 2162048e328SMark Yao } 2172048e328SMark Yao 2189a61c54bSMark yao if (reg->relaxed) 219d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 220d49463ecSMark Yao else 221d49463ecSMark Yao writel(v, vop->regs + offset); 2222048e328SMark Yao } 2232048e328SMark Yao 224dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 225dbb3d944SMark Yao const struct vop_reg *reg, int type) 226dbb3d944SMark Yao { 227dbb3d944SMark Yao uint32_t i, ret = 0; 228dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 229dbb3d944SMark Yao 230dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 231dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 232dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 233dbb3d944SMark Yao } 234dbb3d944SMark Yao 235dbb3d944SMark Yao return ret; 236dbb3d944SMark Yao } 237dbb3d944SMark Yao 2380cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2390cf33fe3SMark Yao { 2409a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2410cf33fe3SMark Yao } 2420cf33fe3SMark Yao 24385a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 24485a359f2STomasz Figa { 24585a359f2STomasz Figa switch (format) { 24685a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 24785a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 24885a359f2STomasz Figa case DRM_FORMAT_BGR888: 24985a359f2STomasz Figa case DRM_FORMAT_BGR565: 25085a359f2STomasz Figa return true; 25185a359f2STomasz Figa default: 25285a359f2STomasz Figa return false; 25385a359f2STomasz Figa } 25485a359f2STomasz Figa } 25585a359f2STomasz Figa 2562048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2572048e328SMark Yao { 2582048e328SMark Yao switch (format) { 2592048e328SMark Yao case DRM_FORMAT_XRGB8888: 2602048e328SMark Yao case DRM_FORMAT_ARGB8888: 26185a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 26285a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2632048e328SMark Yao return VOP_FMT_ARGB8888; 2642048e328SMark Yao case DRM_FORMAT_RGB888: 26585a359f2STomasz Figa case DRM_FORMAT_BGR888: 2662048e328SMark Yao return VOP_FMT_RGB888; 2672048e328SMark Yao case DRM_FORMAT_RGB565: 26885a359f2STomasz Figa case DRM_FORMAT_BGR565: 2692048e328SMark Yao return VOP_FMT_RGB565; 2702048e328SMark Yao case DRM_FORMAT_NV12: 2712048e328SMark Yao return VOP_FMT_YUV420SP; 2722048e328SMark Yao case DRM_FORMAT_NV16: 2732048e328SMark Yao return VOP_FMT_YUV422SP; 2742048e328SMark Yao case DRM_FORMAT_NV24: 2752048e328SMark Yao return VOP_FMT_YUV444SP; 2762048e328SMark Yao default: 277ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2782048e328SMark Yao return -EINVAL; 2792048e328SMark Yao } 2802048e328SMark Yao } 2812048e328SMark Yao 2824c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2834c156c21SMark Yao uint32_t dst, bool is_horizontal, 2844c156c21SMark Yao int vsu_mode, int *vskiplines) 2854c156c21SMark Yao { 2864c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2874c156c21SMark Yao 288ce91d373SJeffy Chen if (vskiplines) 289ce91d373SJeffy Chen *vskiplines = 0; 290ce91d373SJeffy Chen 2914c156c21SMark Yao if (is_horizontal) { 2924c156c21SMark Yao if (mode == SCALE_UP) 2934c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2944c156c21SMark Yao else if (mode == SCALE_DOWN) 2954c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2964c156c21SMark Yao } else { 2974c156c21SMark Yao if (mode == SCALE_UP) { 2984c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2994c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 3004c156c21SMark Yao else 3014c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3024c156c21SMark Yao } else if (mode == SCALE_DOWN) { 3034c156c21SMark Yao if (vskiplines) { 3044c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 3054c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 3064c156c21SMark Yao *vskiplines); 3074c156c21SMark Yao } else { 3084c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3094c156c21SMark Yao } 3104c156c21SMark Yao } 3114c156c21SMark Yao } 3124c156c21SMark Yao 3134c156c21SMark Yao return val; 3144c156c21SMark Yao } 3154c156c21SMark Yao 3164c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3174c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 31845babef0SMaxime Ripard uint32_t dst_h, const struct drm_format_info *info) 3194c156c21SMark Yao { 3204c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3214c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3224c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 323d8bd23d9SAyan Kumar Halder bool is_yuv = false; 324f3e9632cSMaxime Ripard uint16_t cbcr_src_w = src_w / info->hsub; 325f3e9632cSMaxime Ripard uint16_t cbcr_src_h = src_h / info->vsub; 3264c156c21SMark Yao uint16_t vsu_mode; 3274c156c21SMark Yao uint16_t lb_mode; 3284c156c21SMark Yao uint32_t val; 329ce91d373SJeffy Chen int vskiplines; 3304c156c21SMark Yao 331d8bd23d9SAyan Kumar Halder if (info->is_yuv) 332d8bd23d9SAyan Kumar Halder is_yuv = true; 333d8bd23d9SAyan Kumar Halder 3344c156c21SMark Yao if (dst_w > 3840) { 335ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3364c156c21SMark Yao return; 3374c156c21SMark Yao } 3384c156c21SMark Yao 3391194fffbSMark Yao if (!win->phy->scl->ext) { 3401194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3411194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3421194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3431194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3441194fffbSMark Yao if (is_yuv) { 3451194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 346ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3471194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 348ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3491194fffbSMark Yao } 3501194fffbSMark Yao return; 3511194fffbSMark Yao } 3521194fffbSMark Yao 3534c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3544c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3554c156c21SMark Yao 3564c156c21SMark Yao if (is_yuv) { 3574c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3584c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3594c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3604c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3614c156c21SMark Yao else 3624c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3634c156c21SMark Yao } else { 3644c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3654c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3664c156c21SMark Yao else 3674c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3684c156c21SMark Yao } 3694c156c21SMark Yao 3701194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3714c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3724c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 373ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3744c156c21SMark Yao return; 3754c156c21SMark Yao } 3764c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 377ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3784c156c21SMark Yao return; 3794c156c21SMark Yao } 3804c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3814c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3824c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3834c156c21SMark Yao } else { 3844c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3854c156c21SMark Yao } 3864c156c21SMark Yao 3874c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3884c156c21SMark Yao true, 0, NULL); 3894c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3904c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3914c156c21SMark Yao false, vsu_mode, &vskiplines); 3924c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3934c156c21SMark Yao 3941194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3951194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3964c156c21SMark Yao 3971194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3981194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3991194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 4001194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 4011194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 4024c156c21SMark Yao if (is_yuv) { 4034c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 4044c156c21SMark Yao dst_w, true, 0, NULL); 4054c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 4064c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 4074c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 4084c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 4094c156c21SMark Yao 4101194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 4111194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4121194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4131194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4141194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4151194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4161194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4174c156c21SMark Yao } 4184c156c21SMark Yao } 4194c156c21SMark Yao 4201067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4211067219bSMark Yao { 4221067219bSMark Yao unsigned long flags; 4231067219bSMark Yao 4241067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4251067219bSMark Yao return; 4261067219bSMark Yao 4271067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4281067219bSMark Yao 429fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 430dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4311067219bSMark Yao 4321067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4331067219bSMark Yao } 4341067219bSMark Yao 4351067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4361067219bSMark Yao { 4371067219bSMark Yao unsigned long flags; 4381067219bSMark Yao 4391067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4401067219bSMark Yao return; 4411067219bSMark Yao 4421067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4431067219bSMark Yao 444dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4451067219bSMark Yao 4461067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4471067219bSMark Yao } 4481067219bSMark Yao 44969c34e41SYakir Yang /* 45069c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 45169c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 45269c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 45369c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 45469c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 45569c34e41SYakir Yang * 45669c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 45769c34e41SYakir Yang * Interrupts 45869c34e41SYakir Yang * LINE_FLAG -------------------------------+ 45969c34e41SYakir Yang * FRAME_SYNC ----+ | 46069c34e41SYakir Yang * | | 46169c34e41SYakir Yang * v v 46269c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 46369c34e41SYakir Yang * ^ ^ ^ ^ 46469c34e41SYakir Yang * | | | | 46569c34e41SYakir Yang * | | | | 46669c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 46769c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 46869c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 46969c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 47069c34e41SYakir Yang */ 47169c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 47269c34e41SYakir Yang { 47369c34e41SYakir Yang uint32_t line_flag_irq; 47469c34e41SYakir Yang unsigned long flags; 47569c34e41SYakir Yang 47669c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 47769c34e41SYakir Yang 47869c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 47969c34e41SYakir Yang 48069c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 48169c34e41SYakir Yang 48269c34e41SYakir Yang return !!line_flag_irq; 48369c34e41SYakir Yang } 48469c34e41SYakir Yang 485459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 48669c34e41SYakir Yang { 48769c34e41SYakir Yang unsigned long flags; 48869c34e41SYakir Yang 48969c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 49069c34e41SYakir Yang return; 49169c34e41SYakir Yang 49269c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 49369c34e41SYakir Yang 494fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 49569c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 49669c34e41SYakir Yang 49769c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 49869c34e41SYakir Yang } 49969c34e41SYakir Yang 50069c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 50169c34e41SYakir Yang { 50269c34e41SYakir Yang unsigned long flags; 50369c34e41SYakir Yang 50469c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 50569c34e41SYakir Yang return; 50669c34e41SYakir Yang 50769c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 50869c34e41SYakir Yang 50969c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 51069c34e41SYakir Yang 51169c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 51269c34e41SYakir Yang } 51369c34e41SYakir Yang 514e2810a71SHeiko Stuebner static int vop_core_clks_enable(struct vop *vop) 515e2810a71SHeiko Stuebner { 516e2810a71SHeiko Stuebner int ret; 517e2810a71SHeiko Stuebner 518e2810a71SHeiko Stuebner ret = clk_enable(vop->hclk); 519e2810a71SHeiko Stuebner if (ret < 0) 520e2810a71SHeiko Stuebner return ret; 521e2810a71SHeiko Stuebner 522e2810a71SHeiko Stuebner ret = clk_enable(vop->aclk); 523e2810a71SHeiko Stuebner if (ret < 0) 524e2810a71SHeiko Stuebner goto err_disable_hclk; 525e2810a71SHeiko Stuebner 526e2810a71SHeiko Stuebner return 0; 527e2810a71SHeiko Stuebner 528e2810a71SHeiko Stuebner err_disable_hclk: 529e2810a71SHeiko Stuebner clk_disable(vop->hclk); 530e2810a71SHeiko Stuebner return ret; 531e2810a71SHeiko Stuebner } 532e2810a71SHeiko Stuebner 533e2810a71SHeiko Stuebner static void vop_core_clks_disable(struct vop *vop) 534e2810a71SHeiko Stuebner { 535e2810a71SHeiko Stuebner clk_disable(vop->aclk); 536e2810a71SHeiko Stuebner clk_disable(vop->hclk); 537e2810a71SHeiko Stuebner } 538e2810a71SHeiko Stuebner 539e9abc611SJonas Karlman static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) 540e9abc611SJonas Karlman { 541e9abc611SJonas Karlman if (win->phy->scl && win->phy->scl->ext) { 542e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 543e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 544e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 545e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 546e9abc611SJonas Karlman } 547e9abc611SJonas Karlman 548e9abc611SJonas Karlman VOP_WIN_SET(vop, win, enable, 0); 549e9abc611SJonas Karlman } 550e9abc611SJonas Karlman 55139a9ad8fSSean Paul static int vop_enable(struct drm_crtc *crtc) 5522048e328SMark Yao { 5532048e328SMark Yao struct vop *vop = to_vop(crtc); 55464d77564SMark yao int ret, i; 5552048e328SMark Yao 5565d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5575d82d1a7SMark Yao if (ret < 0) { 558d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 5595e570373SJeffy Chen return ret; 5605d82d1a7SMark Yao } 5615d82d1a7SMark Yao 562e2810a71SHeiko Stuebner ret = vop_core_clks_enable(vop); 56339a9ad8fSSean Paul if (WARN_ON(ret < 0)) 56439a9ad8fSSean Paul goto err_put_pm_runtime; 5652048e328SMark Yao 5662048e328SMark Yao ret = clk_enable(vop->dclk); 56739a9ad8fSSean Paul if (WARN_ON(ret < 0)) 568e2810a71SHeiko Stuebner goto err_disable_core; 5692048e328SMark Yao 5702048e328SMark Yao /* 5712048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5722048e328SMark Yao * automatically with this master device via common driver code. 5732048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5742048e328SMark Yao * mapping. 5752048e328SMark Yao */ 5762048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5772048e328SMark Yao if (ret) { 578d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 579d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 580e2810a71SHeiko Stuebner goto err_disable_dclk; 5812048e328SMark Yao } 5822048e328SMark Yao 58376f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 58476f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 58576f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 58676f1416eSMarc Zyngier 58764d77564SMark yao /* 58864d77564SMark yao * We need to make sure that all windows are disabled before we 58964d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 59064d77564SMark yao * buffer later. 59164d77564SMark yao */ 59264d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 59364d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 59464d77564SMark yao const struct vop_win_data *win = vop_win->data; 59564d77564SMark yao 596e9abc611SJonas Karlman vop_win_disable(vop, win); 59764d77564SMark yao } 59876f1416eSMarc Zyngier spin_unlock(&vop->reg_lock); 59964d77564SMark yao 60017a794d7SChris Zhong vop_cfg_done(vop); 60117a794d7SChris Zhong 60252ab7891SMark Yao /* 60352ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 60452ab7891SMark Yao */ 60552ab7891SMark Yao vop->is_enabled = true; 60652ab7891SMark Yao 6072048e328SMark Yao spin_lock(&vop->reg_lock); 6082048e328SMark Yao 6099a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6102048e328SMark Yao 6112048e328SMark Yao spin_unlock(&vop->reg_lock); 6122048e328SMark Yao 613b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6142048e328SMark Yao 61539a9ad8fSSean Paul return 0; 6162048e328SMark Yao 6172048e328SMark Yao err_disable_dclk: 6182048e328SMark Yao clk_disable(vop->dclk); 619e2810a71SHeiko Stuebner err_disable_core: 620e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 62139a9ad8fSSean Paul err_put_pm_runtime: 62239a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 62339a9ad8fSSean Paul return ret; 6242048e328SMark Yao } 6252048e328SMark Yao 62664581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 62764581714SLaurent Pinchart struct drm_crtc_state *old_state) 6282048e328SMark Yao { 6292048e328SMark Yao struct vop *vop = to_vop(crtc); 6302048e328SMark Yao 631893b6cadSDaniel Vetter WARN_ON(vop->event); 632893b6cadSDaniel Vetter 633e334d48bSzain wang mutex_lock(&vop->vop_lock); 634b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 6352048e328SMark Yao 6362048e328SMark Yao /* 6371067219bSMark Yao * Vop standby will take effect at end of current frame, 6381067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 6391067219bSMark Yao * 6401067219bSMark Yao * we must wait standby complete when we want to disable aclk, 6411067219bSMark Yao * if not, memory bus maybe dead. 6422048e328SMark Yao */ 6431067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 6441067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 6451067219bSMark Yao 6462048e328SMark Yao spin_lock(&vop->reg_lock); 6472048e328SMark Yao 6489a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6492048e328SMark Yao 6502048e328SMark Yao spin_unlock(&vop->reg_lock); 65152ab7891SMark Yao 6521067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 6532048e328SMark Yao 6541067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6551067219bSMark Yao 6561067219bSMark Yao vop->is_enabled = false; 6571067219bSMark Yao 6581067219bSMark Yao /* 6591067219bSMark Yao * vop standby complete, so iommu detach is safe. 6601067219bSMark Yao */ 6612048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6622048e328SMark Yao 6631067219bSMark Yao clk_disable(vop->dclk); 664e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 6655d82d1a7SMark Yao pm_runtime_put(vop->dev); 666e334d48bSzain wang mutex_unlock(&vop->vop_lock); 667893b6cadSDaniel Vetter 668893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 669893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 670893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 671893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 672893b6cadSDaniel Vetter 673893b6cadSDaniel Vetter crtc->state->event = NULL; 674893b6cadSDaniel Vetter } 6752048e328SMark Yao } 6762048e328SMark Yao 67763ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 6782048e328SMark Yao { 67963ebb9faSMark Yao drm_plane_cleanup(plane); 6802048e328SMark Yao } 6812048e328SMark Yao 68263ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 68363ebb9faSMark Yao struct drm_plane_state *state) 6842048e328SMark Yao { 68563ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 68692915da6SJohn Keeping struct drm_crtc_state *crtc_state; 68763ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 6882048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 6892048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6902048e328SMark Yao int ret; 6914c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 6924c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6934c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 6944c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6952048e328SMark Yao 69663ebb9faSMark Yao if (!crtc || !fb) 697d47a7246STomasz Figa return 0; 69892915da6SJohn Keeping 69992915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 70092915da6SJohn Keeping if (WARN_ON(!crtc_state)) 70192915da6SJohn Keeping return -EINVAL; 70292915da6SJohn Keeping 70381af63a4SVille Syrjälä ret = drm_atomic_helper_check_plane_state(state, crtc_state, 704f9b96be0SVille Syrjälä min_scale, max_scale, 705f9b96be0SVille Syrjälä true, true); 7062048e328SMark Yao if (ret) 7072048e328SMark Yao return ret; 7082048e328SMark Yao 709f9b96be0SVille Syrjälä if (!state->visible) 710d47a7246STomasz Figa return 0; 7112048e328SMark Yao 712438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 713d47a7246STomasz Figa if (ret < 0) 714d47a7246STomasz Figa return ret; 71584c7f8caSMark Yao 71684c7f8caSMark Yao /* 71784c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 71884c7f8caSMark Yao * need align with 2 pixel. 71984c7f8caSMark Yao */ 720d8bd23d9SAyan Kumar Halder if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 721d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 72263ebb9faSMark Yao return -EINVAL; 723d415fb87SMark yao } 72463ebb9faSMark Yao 725677e8bbcSDaniele Castagna if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 726677e8bbcSDaniele Castagna DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 727677e8bbcSDaniele Castagna return -EINVAL; 728677e8bbcSDaniele Castagna } 729677e8bbcSDaniele Castagna 73063ebb9faSMark Yao return 0; 73184c7f8caSMark Yao } 73284c7f8caSMark Yao 73363ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 73463ebb9faSMark Yao struct drm_plane_state *old_state) 73563ebb9faSMark Yao { 73663ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 73763ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 73863ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 7392048e328SMark Yao 74063ebb9faSMark Yao if (!old_state->crtc) 74163ebb9faSMark Yao return; 7422048e328SMark Yao 74363ebb9faSMark Yao spin_lock(&vop->reg_lock); 7442048e328SMark Yao 745e9abc611SJonas Karlman vop_win_disable(vop, win); 7462048e328SMark Yao 74763ebb9faSMark Yao spin_unlock(&vop->reg_lock); 74863ebb9faSMark Yao } 74963ebb9faSMark Yao 75063ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 75163ebb9faSMark Yao struct drm_plane_state *old_state) 75263ebb9faSMark Yao { 75363ebb9faSMark Yao struct drm_plane_state *state = plane->state; 75463ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 75563ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 75663ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 7571c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 75863ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 75963ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 76063ebb9faSMark Yao unsigned int actual_w, actual_h; 76163ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 76263ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 763ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 764ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 76563ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 76663ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 76763ebb9faSMark Yao unsigned long offset; 76863ebb9faSMark Yao dma_addr_t dma_addr; 76963ebb9faSMark Yao uint32_t val; 77063ebb9faSMark Yao bool rb_swap; 77158badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 772d47a7246STomasz Figa int format; 7731c21aa8fSDaniele Castagna int is_yuv = fb->format->is_yuv; 7741c21aa8fSDaniele Castagna int i; 77563ebb9faSMark Yao 77663ebb9faSMark Yao /* 77763ebb9faSMark Yao * can't update plane when vop is disabled. 77863ebb9faSMark Yao */ 7794f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 78063ebb9faSMark Yao return; 78163ebb9faSMark Yao 78263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 78363ebb9faSMark Yao return; 78463ebb9faSMark Yao 785d47a7246STomasz Figa if (!state->visible) { 78663ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 78763ebb9faSMark Yao return; 78863ebb9faSMark Yao } 78963ebb9faSMark Yao 790957428f9SDaniel Stone obj = fb->obj[0]; 79163ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 79263ebb9faSMark Yao 79363ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 79463ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 79563ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 79663ebb9faSMark Yao 79763ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 79863ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 79963ebb9faSMark Yao 80063ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 80163ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 80263ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 80363ebb9faSMark Yao 804353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 80563ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 806d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 807d47a7246STomasz Figa 808677e8bbcSDaniele Castagna /* 809677e8bbcSDaniele Castagna * For y-mirroring we need to move address 810677e8bbcSDaniele Castagna * to the beginning of the last line. 811677e8bbcSDaniele Castagna */ 812677e8bbcSDaniele Castagna if (state->rotation & DRM_MODE_REFLECT_Y) 813677e8bbcSDaniele Castagna dma_addr += (actual_h - 1) * fb->pitches[0]; 814677e8bbcSDaniele Castagna 815438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 81663ebb9faSMark Yao 81763ebb9faSMark Yao spin_lock(&vop->reg_lock); 81863ebb9faSMark Yao 819d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 820da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 821d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 8221c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 823677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, y_mir_en, 824677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 825677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, x_mir_en, 826677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 8271c21aa8fSDaniele Castagna 8281c21aa8fSDaniele Castagna if (is_yuv) { 829f3e9632cSMaxime Ripard int hsub = fb->format->hsub; 830f3e9632cSMaxime Ripard int vsub = fb->format->vsub; 831353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 83284c7f8caSMark Yao 833957428f9SDaniel Stone uv_obj = fb->obj[1]; 83484c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 83584c7f8caSMark Yao 83663ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 83763ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 83884c7f8caSMark Yao 83963ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 840da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 84163ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 8421c21aa8fSDaniele Castagna 8431c21aa8fSDaniele Castagna for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 8441c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 8451c21aa8fSDaniele Castagna win_yuv2yuv, 8461c21aa8fSDaniele Castagna y2r_coefficients[i], 8471c21aa8fSDaniele Castagna bt601_yuv2rgb[i]); 8481c21aa8fSDaniele Castagna } 84984c7f8caSMark Yao } 8504c156c21SMark Yao 8514c156c21SMark Yao if (win->phy->scl) 8524c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 85363ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 85445babef0SMaxime Ripard fb->format); 8554c156c21SMark Yao 85663ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 85763ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 85863ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 8594c156c21SMark Yao 860438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 86185a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 8622048e328SMark Yao 86358badaa7SKristian H. Kristensen /* 86458badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 86558badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 86658badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 86758badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 86858badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 86958badaa7SKristian H. Kristensen */ 87058badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 8712048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 8722048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 8732048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 8742048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 8752048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 8762048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 8772048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 8782048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 8792048e328SMark Yao } else { 8802048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 8812048e328SMark Yao } 8822048e328SMark Yao 8832048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 8842048e328SMark Yao spin_unlock(&vop->reg_lock); 8852048e328SMark Yao } 8862048e328SMark Yao 88715609559SEnric Balletbo i Serra static int vop_plane_atomic_async_check(struct drm_plane *plane, 88815609559SEnric Balletbo i Serra struct drm_plane_state *state) 88915609559SEnric Balletbo i Serra { 89015609559SEnric Balletbo i Serra struct vop_win *vop_win = to_vop_win(plane); 89115609559SEnric Balletbo i Serra const struct vop_win_data *win = vop_win->data; 89215609559SEnric Balletbo i Serra int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 89315609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 89415609559SEnric Balletbo i Serra int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 89515609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 89615609559SEnric Balletbo i Serra struct drm_crtc_state *crtc_state; 89715609559SEnric Balletbo i Serra 89815609559SEnric Balletbo i Serra if (plane != state->crtc->cursor) 89915609559SEnric Balletbo i Serra return -EINVAL; 90015609559SEnric Balletbo i Serra 90115609559SEnric Balletbo i Serra if (!plane->state) 90215609559SEnric Balletbo i Serra return -EINVAL; 90315609559SEnric Balletbo i Serra 90415609559SEnric Balletbo i Serra if (!plane->state->fb) 90515609559SEnric Balletbo i Serra return -EINVAL; 90615609559SEnric Balletbo i Serra 90715609559SEnric Balletbo i Serra if (state->state) 90815609559SEnric Balletbo i Serra crtc_state = drm_atomic_get_existing_crtc_state(state->state, 90915609559SEnric Balletbo i Serra state->crtc); 91015609559SEnric Balletbo i Serra else /* Special case for asynchronous cursor updates. */ 91115609559SEnric Balletbo i Serra crtc_state = plane->crtc->state; 91215609559SEnric Balletbo i Serra 91315609559SEnric Balletbo i Serra return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 91415609559SEnric Balletbo i Serra min_scale, max_scale, 91515609559SEnric Balletbo i Serra true, true); 91615609559SEnric Balletbo i Serra } 91715609559SEnric Balletbo i Serra 91815609559SEnric Balletbo i Serra static void vop_plane_atomic_async_update(struct drm_plane *plane, 91915609559SEnric Balletbo i Serra struct drm_plane_state *new_state) 92015609559SEnric Balletbo i Serra { 92115609559SEnric Balletbo i Serra struct vop *vop = to_vop(plane->state->crtc); 92215609559SEnric Balletbo i Serra struct drm_plane_state *plane_state; 92315609559SEnric Balletbo i Serra 92415609559SEnric Balletbo i Serra plane_state = plane->funcs->atomic_duplicate_state(plane); 92515609559SEnric Balletbo i Serra plane_state->crtc_x = new_state->crtc_x; 92615609559SEnric Balletbo i Serra plane_state->crtc_y = new_state->crtc_y; 92715609559SEnric Balletbo i Serra plane_state->crtc_h = new_state->crtc_h; 92815609559SEnric Balletbo i Serra plane_state->crtc_w = new_state->crtc_w; 92915609559SEnric Balletbo i Serra plane_state->src_x = new_state->src_x; 93015609559SEnric Balletbo i Serra plane_state->src_y = new_state->src_y; 93115609559SEnric Balletbo i Serra plane_state->src_h = new_state->src_h; 93215609559SEnric Balletbo i Serra plane_state->src_w = new_state->src_w; 93315609559SEnric Balletbo i Serra 93415609559SEnric Balletbo i Serra if (plane_state->fb != new_state->fb) 93515609559SEnric Balletbo i Serra drm_atomic_set_fb_for_plane(plane_state, new_state->fb); 93615609559SEnric Balletbo i Serra 93715609559SEnric Balletbo i Serra swap(plane_state, plane->state); 93815609559SEnric Balletbo i Serra 93915609559SEnric Balletbo i Serra if (plane->state->fb && plane->state->fb != new_state->fb) { 94015609559SEnric Balletbo i Serra drm_framebuffer_get(plane->state->fb); 94115609559SEnric Balletbo i Serra WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 94215609559SEnric Balletbo i Serra drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb); 94315609559SEnric Balletbo i Serra set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 94415609559SEnric Balletbo i Serra } 94515609559SEnric Balletbo i Serra 94615609559SEnric Balletbo i Serra if (vop->is_enabled) { 94715609559SEnric Balletbo i Serra rockchip_drm_psr_inhibit_get_state(new_state->state); 94815609559SEnric Balletbo i Serra vop_plane_atomic_update(plane, plane->state); 94915609559SEnric Balletbo i Serra spin_lock(&vop->reg_lock); 95015609559SEnric Balletbo i Serra vop_cfg_done(vop); 95115609559SEnric Balletbo i Serra spin_unlock(&vop->reg_lock); 95215609559SEnric Balletbo i Serra rockchip_drm_psr_inhibit_put_state(new_state->state); 95315609559SEnric Balletbo i Serra } 95415609559SEnric Balletbo i Serra 95515609559SEnric Balletbo i Serra plane->funcs->atomic_destroy_state(plane, plane_state); 95615609559SEnric Balletbo i Serra } 95715609559SEnric Balletbo i Serra 95863ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 95963ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 96063ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 96163ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 96215609559SEnric Balletbo i Serra .atomic_async_check = vop_plane_atomic_async_check, 96315609559SEnric Balletbo i Serra .atomic_async_update = vop_plane_atomic_async_update, 96463d5e06aSHeiko Stuebner .prepare_fb = drm_gem_fb_prepare_fb, 96563ebb9faSMark Yao }; 96663ebb9faSMark Yao 9672048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 96863ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 96963ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 9702048e328SMark Yao .destroy = vop_plane_destroy, 971d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 972d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 973d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 9742048e328SMark Yao }; 9752048e328SMark Yao 9762048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 9772048e328SMark Yao { 9782048e328SMark Yao struct vop *vop = to_vop(crtc); 9792048e328SMark Yao unsigned long flags; 9802048e328SMark Yao 98163ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 9822048e328SMark Yao return -EPERM; 9832048e328SMark Yao 9842048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 9852048e328SMark Yao 986fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 987dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 9882048e328SMark Yao 9892048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 9902048e328SMark Yao 9912048e328SMark Yao return 0; 9922048e328SMark Yao } 9932048e328SMark Yao 9942048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 9952048e328SMark Yao { 9962048e328SMark Yao struct vop *vop = to_vop(crtc); 9972048e328SMark Yao unsigned long flags; 9982048e328SMark Yao 99963ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10002048e328SMark Yao return; 100131e980c5SMark Yao 10022048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1003dbb3d944SMark Yao 1004dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1005dbb3d944SMark Yao 10062048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10072048e328SMark Yao } 10082048e328SMark Yao 10092048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 10102048e328SMark Yao const struct drm_display_mode *mode, 10112048e328SMark Yao struct drm_display_mode *adjusted_mode) 10122048e328SMark Yao { 1013b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 1014b59b8de3SChris Zhong 1015b59b8de3SChris Zhong adjusted_mode->clock = 1016527e4ca3SDouglas Anderson DIV_ROUND_UP(clk_round_rate(vop->dclk, 1017527e4ca3SDouglas Anderson adjusted_mode->clock * 1000), 1000); 1018b59b8de3SChris Zhong 10192048e328SMark Yao return true; 10202048e328SMark Yao } 10212048e328SMark Yao 10220b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 10230b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 10242048e328SMark Yao { 10252048e328SMark Yao struct vop *vop = to_vop(crtc); 1026efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 10274e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 102863ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 10292048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 10302048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 10312048e328SMark Yao u16 htotal = adjusted_mode->htotal; 10322048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 10332048e328SMark Yao u16 hact_end = hact_st + hdisplay; 10342048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 10352048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 10362048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 10372048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 10382048e328SMark Yao u16 vact_end = vact_st + vdisplay; 10390a63bfd0SMark Yao uint32_t pin_pol, val; 1040a5c0fa44SUrja Rannikko int dither_bpc = s->output_bpc ? s->output_bpc : 10; 104139a9ad8fSSean Paul int ret; 10422048e328SMark Yao 1043e334d48bSzain wang mutex_lock(&vop->vop_lock); 1044e334d48bSzain wang 1045893b6cadSDaniel Vetter WARN_ON(vop->event); 1046893b6cadSDaniel Vetter 104739a9ad8fSSean Paul ret = vop_enable(crtc); 104839a9ad8fSSean Paul if (ret) { 1049e334d48bSzain wang mutex_unlock(&vop->vop_lock); 105039a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 105139a9ad8fSSean Paul return; 105239a9ad8fSSean Paul } 105339a9ad8fSSean Paul 10541a0f7ed3SChris Zhong pin_pol = BIT(DCLK_INVERT); 1055d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1056d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 1057d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1058d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 10599a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 1060cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 10610a63bfd0SMark Yao 10624e257d9eSMark Yao switch (s->output_type) { 10634e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 10649a61c54bSMark yao VOP_REG_SET(vop, output, rgb_en, 1); 10659a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 10664e257d9eSMark Yao break; 10674e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 10689a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 10699a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 10704e257d9eSMark Yao break; 10714e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 10729a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 10739a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 10744e257d9eSMark Yao break; 10754e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 10769a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 10779a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 1078cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 1079cf6d100dSHeiko Stuebner !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 10804e257d9eSMark Yao break; 10811a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 10821a0f7ed3SChris Zhong pin_pol &= ~BIT(DCLK_INVERT); 10839a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 10849a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 10851a0f7ed3SChris Zhong break; 10864e257d9eSMark Yao default: 1087ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1088ee4d7899SSean Paul s->output_type); 10894e257d9eSMark Yao } 1090efd11cc8SMark yao 1091efd11cc8SMark yao /* 1092efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 1093efd11cc8SMark yao */ 1094efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1095efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1096efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 10976bda8112SMark Yao 1098a5c0fa44SUrja Rannikko if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 10996bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 11006bda8112SMark Yao else 11016bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 11026bda8112SMark Yao 1103a5c0fa44SUrja Rannikko if (dither_bpc == 6) { 1104a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1105a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1106a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 1); 1107a5c0fa44SUrja Rannikko } else { 1108a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 0); 1109a5c0fa44SUrja Rannikko } 1110a5c0fa44SUrja Rannikko 11119a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 11122048e328SMark Yao 11139a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 11142048e328SMark Yao val = hact_st << 16; 11152048e328SMark Yao val |= hact_end; 11169a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 11179a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 11182048e328SMark Yao 11199a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 11202048e328SMark Yao val = vact_st << 16; 11212048e328SMark Yao val |= vact_end; 11229a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 11239a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 11242048e328SMark Yao 11259a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1126459b086dSJeffy Chen 11272048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1128ce3887edSMark Yao 11299a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 1130e334d48bSzain wang mutex_unlock(&vop->vop_lock); 11312048e328SMark Yao } 11322048e328SMark Yao 11337caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 11347caecdbeSTomasz Figa { 11357caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 11367caecdbeSTomasz Figa } 11377caecdbeSTomasz Figa 11387caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 11397caecdbeSTomasz Figa { 11407caecdbeSTomasz Figa bool pending; 11417caecdbeSTomasz Figa int ret; 11427caecdbeSTomasz Figa 11437caecdbeSTomasz Figa /* 11447caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 11457caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 11467caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 11477caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 11487caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 11497caecdbeSTomasz Figa * shouldn't exceed microseconds range. 11507caecdbeSTomasz Figa */ 11517caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 11527caecdbeSTomasz Figa !pending, 0, 10 * 1000); 11537caecdbeSTomasz Figa if (ret) 11547caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 11557caecdbeSTomasz Figa 11567caecdbeSTomasz Figa synchronize_irq(vop->irq); 11577caecdbeSTomasz Figa } 11587caecdbeSTomasz Figa 115963ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 116063ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 116163ebb9faSMark Yao { 116247a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1163e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 116463ebb9faSMark Yao struct vop *vop = to_vop(crtc); 116547a7eb45STomasz Figa struct drm_plane *plane; 116647a7eb45STomasz Figa int i; 116763ebb9faSMark Yao 116863ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 116963ebb9faSMark Yao return; 117063ebb9faSMark Yao 117163ebb9faSMark Yao spin_lock(&vop->reg_lock); 117263ebb9faSMark Yao 117363ebb9faSMark Yao vop_cfg_done(vop); 117463ebb9faSMark Yao 117563ebb9faSMark Yao spin_unlock(&vop->reg_lock); 11767caecdbeSTomasz Figa 11777caecdbeSTomasz Figa /* 11787caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 11797caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 11807caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 11817caecdbeSTomasz Figa */ 11827caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 118347a7eb45STomasz Figa 118441ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 118541ee4367STomasz Figa if (crtc->state->event) { 118641ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 118741ee4367STomasz Figa WARN_ON(vop->event); 118841ee4367STomasz Figa 118941ee4367STomasz Figa vop->event = crtc->state->event; 119041ee4367STomasz Figa crtc->state->event = NULL; 119141ee4367STomasz Figa } 119241ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 119341ee4367STomasz Figa 1194e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1195e741f2b1SMaarten Lankhorst new_plane_state, i) { 119647a7eb45STomasz Figa if (!old_plane_state->fb) 119747a7eb45STomasz Figa continue; 119847a7eb45STomasz Figa 1199e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 120047a7eb45STomasz Figa continue; 120147a7eb45STomasz Figa 1202adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 12032d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 120447a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 120547a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 120647a7eb45STomasz Figa } 120763ebb9faSMark Yao } 120863ebb9faSMark Yao 12092048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 12102048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 121163ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 12120b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 121364581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 12142048e328SMark Yao }; 12152048e328SMark Yao 12162048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 12172048e328SMark Yao { 12182048e328SMark Yao drm_crtc_cleanup(crtc); 12192048e328SMark Yao } 12202048e328SMark Yao 12214e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 12224e257d9eSMark Yao { 12234e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 12244e257d9eSMark Yao 12254e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 12264e257d9eSMark Yao if (!rockchip_state) 12274e257d9eSMark Yao return NULL; 12284e257d9eSMark Yao 12294e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 12304e257d9eSMark Yao return &rockchip_state->base; 12314e257d9eSMark Yao } 12324e257d9eSMark Yao 12334e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 12344e257d9eSMark Yao struct drm_crtc_state *state) 12354e257d9eSMark Yao { 12364e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 12374e257d9eSMark Yao 1238ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 12394e257d9eSMark Yao kfree(s); 12404e257d9eSMark Yao } 12414e257d9eSMark Yao 124201e2eaf4SMaarten Lankhorst static void vop_crtc_reset(struct drm_crtc *crtc) 124301e2eaf4SMaarten Lankhorst { 124401e2eaf4SMaarten Lankhorst struct rockchip_crtc_state *crtc_state = 124501e2eaf4SMaarten Lankhorst kzalloc(sizeof(*crtc_state), GFP_KERNEL); 124601e2eaf4SMaarten Lankhorst 124701e2eaf4SMaarten Lankhorst if (crtc->state) 124801e2eaf4SMaarten Lankhorst vop_crtc_destroy_state(crtc, crtc->state); 124901e2eaf4SMaarten Lankhorst 125001e2eaf4SMaarten Lankhorst __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 125101e2eaf4SMaarten Lankhorst } 125201e2eaf4SMaarten Lankhorst 12536cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 12543190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 12553190e58dSTomeu Vizoso { 12563190e58dSTomeu Vizoso struct drm_connector *connector; 12572cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 12583190e58dSTomeu Vizoso 12592cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 12602cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 12613190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 12622cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 12633190e58dSTomeu Vizoso return connector; 12643190e58dSTomeu Vizoso } 12652cbeb64fSGustavo Padovan } 12662cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 12673190e58dSTomeu Vizoso 12683190e58dSTomeu Vizoso return NULL; 12693190e58dSTomeu Vizoso } 12703190e58dSTomeu Vizoso 12713190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1272c0811a7dSMahesh Kumar const char *source_name) 12733190e58dSTomeu Vizoso { 12743190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 12753190e58dSTomeu Vizoso struct drm_connector *connector; 12763190e58dSTomeu Vizoso int ret; 12773190e58dSTomeu Vizoso 12783190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 12793190e58dSTomeu Vizoso if (!connector) 12803190e58dSTomeu Vizoso return -EINVAL; 12813190e58dSTomeu Vizoso 12823190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 12833190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 12843190e58dSTomeu Vizoso else if (!source_name) 12853190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 12863190e58dSTomeu Vizoso else 12873190e58dSTomeu Vizoso ret = -EINVAL; 12883190e58dSTomeu Vizoso 12893190e58dSTomeu Vizoso return ret; 12903190e58dSTomeu Vizoso } 1291b8d913c0SMahesh Kumar 1292b8d913c0SMahesh Kumar static int 1293b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1294b8d913c0SMahesh Kumar size_t *values_cnt) 1295b8d913c0SMahesh Kumar { 1296b8d913c0SMahesh Kumar if (source_name && strcmp(source_name, "auto") != 0) 1297b8d913c0SMahesh Kumar return -EINVAL; 1298b8d913c0SMahesh Kumar 1299b8d913c0SMahesh Kumar *values_cnt = 3; 1300b8d913c0SMahesh Kumar return 0; 1301b8d913c0SMahesh Kumar } 1302b8d913c0SMahesh Kumar 13036cca3869SSean Paul #else 13046cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1305c0811a7dSMahesh Kumar const char *source_name) 13066cca3869SSean Paul { 13076cca3869SSean Paul return -ENODEV; 13086cca3869SSean Paul } 1309b8d913c0SMahesh Kumar 1310b8d913c0SMahesh Kumar static int 1311b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1312b8d913c0SMahesh Kumar size_t *values_cnt) 1313b8d913c0SMahesh Kumar { 1314b8d913c0SMahesh Kumar return -ENODEV; 1315b8d913c0SMahesh Kumar } 13166cca3869SSean Paul #endif 13173190e58dSTomeu Vizoso 13182048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 131963ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 132063ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 13212048e328SMark Yao .destroy = vop_crtc_destroy, 1322dc0b408fSJohn Keeping .reset = vop_crtc_reset, 13234e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 13244e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1325c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1326c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 13273190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 1328b8d913c0SMahesh Kumar .verify_crc_source = vop_crtc_verify_crc_source, 13292048e328SMark Yao }; 13302048e328SMark Yao 133147a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 133247a7eb45STomasz Figa { 133347a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 133447a7eb45STomasz Figa struct drm_framebuffer *fb = val; 133547a7eb45STomasz Figa 133647a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1337adedbf03SCihangir Akturk drm_framebuffer_put(fb); 133847a7eb45STomasz Figa } 133947a7eb45STomasz Figa 134063ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 13412048e328SMark Yao { 134263ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 134363ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 13442048e328SMark Yao 13451c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1346893b6cadSDaniel Vetter if (vop->event) { 134763ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 13485b680403SSean Paul drm_crtc_vblank_put(crtc); 1349646ec687STomasz Figa vop->event = NULL; 13505b680403SSean Paul } 13511c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1352893b6cadSDaniel Vetter 135347a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 135447a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 13552048e328SMark Yao } 13562048e328SMark Yao 13572048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 13582048e328SMark Yao { 13592048e328SMark Yao struct vop *vop = data; 1360b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1361dbb3d944SMark Yao uint32_t active_irqs; 13621067219bSMark Yao int ret = IRQ_NONE; 13632048e328SMark Yao 13642048e328SMark Yao /* 13656456314fSSandy Huang * The irq is shared with the iommu. If the runtime-pm state of the 13666456314fSSandy Huang * vop-device is disabled the irq has to be targeted at the iommu. 13676456314fSSandy Huang */ 13686456314fSSandy Huang if (!pm_runtime_get_if_in_use(vop->dev)) 13696456314fSSandy Huang return IRQ_NONE; 13706456314fSSandy Huang 13716456314fSSandy Huang if (vop_core_clks_enable(vop)) { 13726456314fSSandy Huang DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 13736456314fSSandy Huang goto out; 13746456314fSSandy Huang } 13756456314fSSandy Huang 13766456314fSSandy Huang /* 1377dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 13782048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 13792048e328SMark Yao */ 13801c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1381dbb3d944SMark Yao 1382dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 13832048e328SMark Yao /* Clear all active interrupt sources */ 13842048e328SMark Yao if (active_irqs) 1385dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1386dbb3d944SMark Yao 13871c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 13882048e328SMark Yao 13892048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 13902048e328SMark Yao if (!active_irqs) 13916456314fSSandy Huang goto out_disable; 13922048e328SMark Yao 13931067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 13941067219bSMark Yao complete(&vop->dsp_hold_completion); 13951067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 13961067219bSMark Yao ret = IRQ_HANDLED; 13972048e328SMark Yao } 13982048e328SMark Yao 139969c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 140069c34e41SYakir Yang complete(&vop->line_flag_completion); 140169c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 140269c34e41SYakir Yang ret = IRQ_HANDLED; 140369c34e41SYakir Yang } 140469c34e41SYakir Yang 14051067219bSMark Yao if (active_irqs & FS_INTR) { 1406b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 140763ebb9faSMark Yao vop_handle_vblank(vop); 14081067219bSMark Yao active_irqs &= ~FS_INTR; 140963ebb9faSMark Yao ret = IRQ_HANDLED; 14101067219bSMark Yao } 14112048e328SMark Yao 14121067219bSMark Yao /* Unhandled irqs are spurious. */ 14131067219bSMark Yao if (active_irqs) 1414ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1415ee4d7899SSean Paul active_irqs); 14161067219bSMark Yao 14176456314fSSandy Huang out_disable: 14186456314fSSandy Huang vop_core_clks_disable(vop); 14196456314fSSandy Huang out: 14206456314fSSandy Huang pm_runtime_put(vop->dev); 14211067219bSMark Yao return ret; 14222048e328SMark Yao } 14232048e328SMark Yao 1424677e8bbcSDaniele Castagna static void vop_plane_add_properties(struct drm_plane *plane, 1425677e8bbcSDaniele Castagna const struct vop_win_data *win_data) 1426677e8bbcSDaniele Castagna { 1427677e8bbcSDaniele Castagna unsigned int flags = 0; 1428677e8bbcSDaniele Castagna 1429677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1430677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1431677e8bbcSDaniele Castagna if (flags) 1432677e8bbcSDaniele Castagna drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1433677e8bbcSDaniele Castagna DRM_MODE_ROTATE_0 | flags); 1434677e8bbcSDaniele Castagna } 1435677e8bbcSDaniele Castagna 14362048e328SMark Yao static int vop_create_crtc(struct vop *vop) 14372048e328SMark Yao { 14382048e328SMark Yao const struct vop_data *vop_data = vop->data; 14392048e328SMark Yao struct device *dev = vop->dev; 14402048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1441328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 14422048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 14432048e328SMark Yao struct device_node *port; 14442048e328SMark Yao int ret; 14452048e328SMark Yao int i; 14462048e328SMark Yao 14472048e328SMark Yao /* 14482048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 14492048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 14502048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 14512048e328SMark Yao */ 14522048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14532048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14542048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 14552048e328SMark Yao 14562048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 14572048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 14582048e328SMark Yao continue; 14592048e328SMark Yao 14602048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 14612048e328SMark Yao 0, &vop_plane_funcs, 14622048e328SMark Yao win_data->phy->data_formats, 14632048e328SMark Yao win_data->phy->nformats, 1464e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 14652048e328SMark Yao if (ret) { 1466ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1467ee4d7899SSean Paul ret); 14682048e328SMark Yao goto err_cleanup_planes; 14692048e328SMark Yao } 14702048e328SMark Yao 14712048e328SMark Yao plane = &vop_win->base; 147263ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 1473677e8bbcSDaniele Castagna vop_plane_add_properties(plane, win_data); 14742048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 14752048e328SMark Yao primary = plane; 14762048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 14772048e328SMark Yao cursor = plane; 14782048e328SMark Yao } 14792048e328SMark Yao 14802048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1481f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 14822048e328SMark Yao if (ret) 1483328b51c0SDouglas Anderson goto err_cleanup_planes; 14842048e328SMark Yao 14852048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 14862048e328SMark Yao 14872048e328SMark Yao /* 14882048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 14892048e328SMark Yao * to the newly created crtc. 14902048e328SMark Yao */ 14912048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14922048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 14932048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 1494a3e77e16SVille Syrjälä unsigned long possible_crtcs = drm_crtc_mask(crtc); 14952048e328SMark Yao 14962048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 14972048e328SMark Yao continue; 14982048e328SMark Yao 14992048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 15002048e328SMark Yao possible_crtcs, 15012048e328SMark Yao &vop_plane_funcs, 15022048e328SMark Yao win_data->phy->data_formats, 15032048e328SMark Yao win_data->phy->nformats, 1504e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 15052048e328SMark Yao if (ret) { 1506ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1507ee4d7899SSean Paul ret); 15082048e328SMark Yao goto err_cleanup_crtc; 15092048e328SMark Yao } 151063ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1511677e8bbcSDaniele Castagna vop_plane_add_properties(&vop_win->base, win_data); 15122048e328SMark Yao } 15132048e328SMark Yao 15142048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 15152048e328SMark Yao if (!port) { 15164bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 15174bf99144SRob Herring dev->of_node); 1518328b51c0SDouglas Anderson ret = -ENOENT; 15192048e328SMark Yao goto err_cleanup_crtc; 15202048e328SMark Yao } 15212048e328SMark Yao 152247a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 152347a7eb45STomasz Figa vop_fb_unref_worker); 152447a7eb45STomasz Figa 15251067219bSMark Yao init_completion(&vop->dsp_hold_completion); 152669c34e41SYakir Yang init_completion(&vop->line_flag_completion); 15272048e328SMark Yao crtc->port = port; 15282048e328SMark Yao 15292048e328SMark Yao return 0; 15302048e328SMark Yao 15312048e328SMark Yao err_cleanup_crtc: 15322048e328SMark Yao drm_crtc_cleanup(crtc); 15332048e328SMark Yao err_cleanup_planes: 1534328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1535328b51c0SDouglas Anderson head) 15362048e328SMark Yao drm_plane_cleanup(plane); 15372048e328SMark Yao return ret; 15382048e328SMark Yao } 15392048e328SMark Yao 15402048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 15412048e328SMark Yao { 15422048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1543328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1544328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 15452048e328SMark Yao 15462048e328SMark Yao of_node_put(crtc->port); 1547328b51c0SDouglas Anderson 1548328b51c0SDouglas Anderson /* 1549328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1550328b51c0SDouglas Anderson * 1551328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1552328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1553328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1554328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1555328b51c0SDouglas Anderson */ 1556328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1557328b51c0SDouglas Anderson head) 1558328b51c0SDouglas Anderson vop_plane_destroy(plane); 1559328b51c0SDouglas Anderson 1560328b51c0SDouglas Anderson /* 1561328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1562328b51c0SDouglas Anderson * references the CRTC. 1563328b51c0SDouglas Anderson */ 15642048e328SMark Yao drm_crtc_cleanup(crtc); 156547a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 15662048e328SMark Yao } 15672048e328SMark Yao 15682048e328SMark Yao static int vop_initial(struct vop *vop) 15692048e328SMark Yao { 15702048e328SMark Yao const struct vop_data *vop_data = vop->data; 15712048e328SMark Yao struct reset_control *ahb_rst; 15722048e328SMark Yao int i, ret; 15732048e328SMark Yao 15742048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 15752048e328SMark Yao if (IS_ERR(vop->hclk)) { 1576d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 15772048e328SMark Yao return PTR_ERR(vop->hclk); 15782048e328SMark Yao } 15792048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 15802048e328SMark Yao if (IS_ERR(vop->aclk)) { 1581d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 15822048e328SMark Yao return PTR_ERR(vop->aclk); 15832048e328SMark Yao } 15842048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 15852048e328SMark Yao if (IS_ERR(vop->dclk)) { 1586d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 15872048e328SMark Yao return PTR_ERR(vop->dclk); 15882048e328SMark Yao } 15892048e328SMark Yao 15905e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 15915e570373SJeffy Chen if (ret < 0) { 1592d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 15935e570373SJeffy Chen return ret; 15945e570373SJeffy Chen } 15955e570373SJeffy Chen 15962048e328SMark Yao ret = clk_prepare(vop->dclk); 15972048e328SMark Yao if (ret < 0) { 1598d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 15995e570373SJeffy Chen goto err_put_pm_runtime; 16002048e328SMark Yao } 16012048e328SMark Yao 1602d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1603d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 16042048e328SMark Yao if (ret < 0) { 1605d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 16062048e328SMark Yao goto err_unprepare_dclk; 16072048e328SMark Yao } 16082048e328SMark Yao 1609d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 16102048e328SMark Yao if (ret < 0) { 1611d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1612d7b53fd9SSjoerd Simons goto err_disable_hclk; 16132048e328SMark Yao } 1614d7b53fd9SSjoerd Simons 16152048e328SMark Yao /* 16162048e328SMark Yao * do hclk_reset, reset all vop registers. 16172048e328SMark Yao */ 16182048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 16192048e328SMark Yao if (IS_ERR(ahb_rst)) { 1620d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 16212048e328SMark Yao ret = PTR_ERR(ahb_rst); 1622d7b53fd9SSjoerd Simons goto err_disable_aclk; 16232048e328SMark Yao } 16242048e328SMark Yao reset_control_assert(ahb_rst); 16252048e328SMark Yao usleep_range(10, 20); 16262048e328SMark Yao reset_control_deassert(ahb_rst); 16272048e328SMark Yao 16285f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 16295f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 16305f9e93feSMarc Zyngier 163176f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 163276f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 16332048e328SMark Yao 16349a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 16359a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 16362048e328SMark Yao 16372048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16382048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 16399dd2aca4SMark yao int channel = i * 2 + 1; 16402048e328SMark Yao 16419dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1642e9abc611SJonas Karlman vop_win_disable(vop, win); 164360b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 16442048e328SMark Yao } 16452048e328SMark Yao 16462048e328SMark Yao vop_cfg_done(vop); 16472048e328SMark Yao 16482048e328SMark Yao /* 16492048e328SMark Yao * do dclk_reset, let all config take affect. 16502048e328SMark Yao */ 16512048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 16522048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1653d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 16542048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1655d7b53fd9SSjoerd Simons goto err_disable_aclk; 16562048e328SMark Yao } 16572048e328SMark Yao reset_control_assert(vop->dclk_rst); 16582048e328SMark Yao usleep_range(10, 20); 16592048e328SMark Yao reset_control_deassert(vop->dclk_rst); 16602048e328SMark Yao 16612048e328SMark Yao clk_disable(vop->hclk); 1662d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 16632048e328SMark Yao 166431e980c5SMark Yao vop->is_enabled = false; 16652048e328SMark Yao 16665e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 16675e570373SJeffy Chen 16682048e328SMark Yao return 0; 16692048e328SMark Yao 1670d7b53fd9SSjoerd Simons err_disable_aclk: 1671d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 16722048e328SMark Yao err_disable_hclk: 1673d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 16742048e328SMark Yao err_unprepare_dclk: 16752048e328SMark Yao clk_unprepare(vop->dclk); 16765e570373SJeffy Chen err_put_pm_runtime: 16775e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 16782048e328SMark Yao return ret; 16792048e328SMark Yao } 16802048e328SMark Yao 16812048e328SMark Yao /* 16822048e328SMark Yao * Initialize the vop->win array elements. 16832048e328SMark Yao */ 16842048e328SMark Yao static void vop_win_init(struct vop *vop) 16852048e328SMark Yao { 16862048e328SMark Yao const struct vop_data *vop_data = vop->data; 16872048e328SMark Yao unsigned int i; 16882048e328SMark Yao 16892048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16902048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 16912048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 16922048e328SMark Yao 16932048e328SMark Yao vop_win->data = win_data; 16942048e328SMark Yao vop_win->vop = vop; 1695ce6912b4SHeiko Stuebner 1696ce6912b4SHeiko Stuebner if (vop_data->win_yuv2yuv) 16971c21aa8fSDaniele Castagna vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 16982048e328SMark Yao } 16992048e328SMark Yao } 17002048e328SMark Yao 170169c34e41SYakir Yang /** 1702459b086dSJeffy Chen * rockchip_drm_wait_vact_end 170369c34e41SYakir Yang * @crtc: CRTC to enable line flag 170469c34e41SYakir Yang * @mstimeout: millisecond for timeout 170569c34e41SYakir Yang * 1706459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 170769c34e41SYakir Yang * 170869c34e41SYakir Yang * Returns: 170969c34e41SYakir Yang * Zero on success, negative errno on failure. 171069c34e41SYakir Yang */ 1711459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 171269c34e41SYakir Yang { 171369c34e41SYakir Yang struct vop *vop = to_vop(crtc); 171469c34e41SYakir Yang unsigned long jiffies_left; 1715e334d48bSzain wang int ret = 0; 171669c34e41SYakir Yang 171769c34e41SYakir Yang if (!crtc || !vop->is_enabled) 171869c34e41SYakir Yang return -ENODEV; 171969c34e41SYakir Yang 1720e334d48bSzain wang mutex_lock(&vop->vop_lock); 1721e334d48bSzain wang if (mstimeout <= 0) { 1722e334d48bSzain wang ret = -EINVAL; 1723e334d48bSzain wang goto out; 1724e334d48bSzain wang } 172569c34e41SYakir Yang 1726e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 1727e334d48bSzain wang ret = -EBUSY; 1728e334d48bSzain wang goto out; 1729e334d48bSzain wang } 173069c34e41SYakir Yang 173169c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1732459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 173369c34e41SYakir Yang 173469c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 173569c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 173669c34e41SYakir Yang vop_line_flag_irq_disable(vop); 173769c34e41SYakir Yang 173869c34e41SYakir Yang if (jiffies_left == 0) { 1739d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1740e334d48bSzain wang ret = -ETIMEDOUT; 1741e334d48bSzain wang goto out; 174269c34e41SYakir Yang } 174369c34e41SYakir Yang 1744e334d48bSzain wang out: 1745e334d48bSzain wang mutex_unlock(&vop->vop_lock); 1746e334d48bSzain wang return ret; 174769c34e41SYakir Yang } 1748459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 174969c34e41SYakir Yang 17502048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 17512048e328SMark Yao { 17522048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 17532048e328SMark Yao const struct vop_data *vop_data; 17542048e328SMark Yao struct drm_device *drm_dev = data; 17552048e328SMark Yao struct vop *vop; 17562048e328SMark Yao struct resource *res; 17573ea68922SHeiko Stuebner int ret, irq; 17582048e328SMark Yao 1759a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 17602048e328SMark Yao if (!vop_data) 17612048e328SMark Yao return -ENODEV; 17622048e328SMark Yao 17632048e328SMark Yao /* Allocate vop struct and its vop_win array */ 176429adeb4fSGustavo A. R. Silva vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 176529adeb4fSGustavo A. R. Silva GFP_KERNEL); 17662048e328SMark Yao if (!vop) 17672048e328SMark Yao return -ENOMEM; 17682048e328SMark Yao 17692048e328SMark Yao vop->dev = dev; 17702048e328SMark Yao vop->data = vop_data; 17712048e328SMark Yao vop->drm_dev = drm_dev; 17722048e328SMark Yao dev_set_drvdata(dev, vop); 17732048e328SMark Yao 17742048e328SMark Yao vop_win_init(vop); 17752048e328SMark Yao 17762048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 17772048e328SMark Yao vop->len = resource_size(res); 17782048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 17792048e328SMark Yao if (IS_ERR(vop->regs)) 17802048e328SMark Yao return PTR_ERR(vop->regs); 17812048e328SMark Yao 17822048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 17832048e328SMark Yao if (!vop->regsbak) 17842048e328SMark Yao return -ENOMEM; 17852048e328SMark Yao 17863ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 17873ea68922SHeiko Stuebner if (irq < 0) { 1788d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 17893ea68922SHeiko Stuebner return irq; 17902048e328SMark Yao } 17913ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 17922048e328SMark Yao 17932048e328SMark Yao spin_lock_init(&vop->reg_lock); 17942048e328SMark Yao spin_lock_init(&vop->irq_lock); 1795e334d48bSzain wang mutex_init(&vop->vop_lock); 17962048e328SMark Yao 17972048e328SMark Yao ret = vop_create_crtc(vop); 17982048e328SMark Yao if (ret) 17995f9e93feSMarc Zyngier return ret; 18002048e328SMark Yao 18012048e328SMark Yao pm_runtime_enable(&pdev->dev); 18025182c1a5SYakir Yang 18035e570373SJeffy Chen ret = vop_initial(vop); 18045e570373SJeffy Chen if (ret < 0) { 1805d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 1806d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 18075e570373SJeffy Chen goto err_disable_pm_runtime; 18085e570373SJeffy Chen } 18095e570373SJeffy Chen 18105f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 18115f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 18125f9e93feSMarc Zyngier if (ret) 18135f9e93feSMarc Zyngier goto err_disable_pm_runtime; 18145f9e93feSMarc Zyngier 18151f0f0151SSandy Huang if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 18161f0f0151SSandy Huang vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 18171f0f0151SSandy Huang if (IS_ERR(vop->rgb)) { 18181f0f0151SSandy Huang ret = PTR_ERR(vop->rgb); 18191f0f0151SSandy Huang goto err_disable_pm_runtime; 18201f0f0151SSandy Huang } 18211f0f0151SSandy Huang } 18221f0f0151SSandy Huang 18232048e328SMark Yao return 0; 18248c763c9bSSean Paul 18255e570373SJeffy Chen err_disable_pm_runtime: 18265e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 18275e570373SJeffy Chen vop_destroy_crtc(vop); 18288c763c9bSSean Paul return ret; 18292048e328SMark Yao } 18302048e328SMark Yao 18312048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 18322048e328SMark Yao { 18332048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 18342048e328SMark Yao 18351f0f0151SSandy Huang if (vop->rgb) 18361f0f0151SSandy Huang rockchip_rgb_fini(vop->rgb); 18371f0f0151SSandy Huang 18382048e328SMark Yao pm_runtime_disable(dev); 18392048e328SMark Yao vop_destroy_crtc(vop); 1840ec6e7767SJeffy Chen 1841ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 1842ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 1843ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 18442048e328SMark Yao } 18452048e328SMark Yao 1846a67719d1SMark Yao const struct component_ops vop_component_ops = { 18472048e328SMark Yao .bind = vop_bind, 18482048e328SMark Yao .unbind = vop_unbind, 18492048e328SMark Yao }; 185054255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1851