12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 2047a7eb45STomasz Figa #include <drm/drm_flip_work.h> 212048e328SMark Yao #include <drm/drm_plane_helper.h> 226cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 233190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 246cca3869SSean Paul #endif 252048e328SMark Yao 262048e328SMark Yao #include <linux/kernel.h> 2700fe6148SPaul Gortmaker #include <linux/module.h> 282048e328SMark Yao #include <linux/platform_device.h> 292048e328SMark Yao #include <linux/clk.h> 307caecdbeSTomasz Figa #include <linux/iopoll.h> 312048e328SMark Yao #include <linux/of.h> 322048e328SMark Yao #include <linux/of_device.h> 332048e328SMark Yao #include <linux/pm_runtime.h> 342048e328SMark Yao #include <linux/component.h> 352048e328SMark Yao 362048e328SMark Yao #include <linux/reset.h> 372048e328SMark Yao #include <linux/delay.h> 382048e328SMark Yao 392048e328SMark Yao #include "rockchip_drm_drv.h" 402048e328SMark Yao #include "rockchip_drm_gem.h" 412048e328SMark Yao #include "rockchip_drm_fb.h" 425182c1a5SYakir Yang #include "rockchip_drm_psr.h" 432048e328SMark Yao #include "rockchip_drm_vop.h" 442048e328SMark Yao 45d49463ecSMark Yao #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ 46d49463ecSMark Yao vop_mask_write(x, off, mask, shift, v, write_mask, true) 47d49463ecSMark Yao 48d49463ecSMark Yao #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ 49d49463ecSMark Yao vop_mask_write(x, off, mask, shift, v, write_mask, false) 502048e328SMark Yao 512048e328SMark Yao #define REG_SET(x, base, reg, v, mode) \ 52d49463ecSMark Yao __REG_SET_##mode(x, base + reg.offset, \ 53d49463ecSMark Yao reg.mask, reg.shift, v, reg.write_mask) 54c7647f86SJohn Keeping #define REG_SET_MASK(x, base, reg, mask, v, mode) \ 55d49463ecSMark Yao __REG_SET_##mode(x, base + reg.offset, \ 56d49463ecSMark Yao mask, reg.shift, v, reg.write_mask) 572048e328SMark Yao 582048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 592048e328SMark Yao REG_SET(x, win->base, win->phy->name, v, RELAXED) 604c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 614c156c21SMark Yao REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 621194fffbSMark Yao #define VOP_SCL_SET_EXT(x, win, name, v) \ 631194fffbSMark Yao REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) 642048e328SMark Yao #define VOP_CTRL_SET(x, name, v) \ 652048e328SMark Yao REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 662048e328SMark Yao 67dbb3d944SMark Yao #define VOP_INTR_GET(vop, name) \ 68dbb3d944SMark Yao vop_read_reg(vop, 0, &vop->data->ctrl->name) 69dbb3d944SMark Yao 70c7647f86SJohn Keeping #define VOP_INTR_SET(vop, name, mask, v) \ 71c7647f86SJohn Keeping REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) 72dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 73dbb3d944SMark Yao do { \ 74c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 75dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 76c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 77dbb3d944SMark Yao reg |= (v) << i; \ 78c7647f86SJohn Keeping mask |= 1 << i; \ 79dbb3d944SMark Yao } \ 80c7647f86SJohn Keeping } \ 81c7647f86SJohn Keeping VOP_INTR_SET(vop, name, mask, reg); \ 82dbb3d944SMark Yao } while (0) 83dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 84dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 85dbb3d944SMark Yao 862048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 872048e328SMark Yao vop_read_reg(x, win->base, &win->phy->name) 882048e328SMark Yao 892048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 902048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 912048e328SMark Yao 922048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 932048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 942048e328SMark Yao 9547a7eb45STomasz Figa enum vop_pending { 9647a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 9747a7eb45STomasz Figa }; 9847a7eb45STomasz Figa 992048e328SMark Yao struct vop_win { 1002048e328SMark Yao struct drm_plane base; 1012048e328SMark Yao const struct vop_win_data *data; 1022048e328SMark Yao struct vop *vop; 1032048e328SMark Yao }; 1042048e328SMark Yao 1052048e328SMark Yao struct vop { 1062048e328SMark Yao struct drm_crtc crtc; 1072048e328SMark Yao struct device *dev; 1082048e328SMark Yao struct drm_device *drm_dev; 10931e980c5SMark Yao bool is_enabled; 1102048e328SMark Yao 1112048e328SMark Yao /* mutex vsync_ work */ 1122048e328SMark Yao struct mutex vsync_mutex; 1132048e328SMark Yao bool vsync_work_pending; 1141067219bSMark Yao struct completion dsp_hold_completion; 1154f9d39a7SDaniel Vetter 1164f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 11763ebb9faSMark Yao struct drm_pending_vblank_event *event; 1182048e328SMark Yao 11947a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 12047a7eb45STomasz Figa unsigned long pending; 12147a7eb45STomasz Figa 12269c34e41SYakir Yang struct completion line_flag_completion; 12369c34e41SYakir Yang 1242048e328SMark Yao const struct vop_data *data; 1252048e328SMark Yao 1262048e328SMark Yao uint32_t *regsbak; 1272048e328SMark Yao void __iomem *regs; 1282048e328SMark Yao 1292048e328SMark Yao /* physical map length of vop register */ 1302048e328SMark Yao uint32_t len; 1312048e328SMark Yao 1322048e328SMark Yao /* one time only one process allowed to config the register */ 1332048e328SMark Yao spinlock_t reg_lock; 1342048e328SMark Yao /* lock vop irq reg */ 1352048e328SMark Yao spinlock_t irq_lock; 1362048e328SMark Yao 1372048e328SMark Yao unsigned int irq; 1382048e328SMark Yao 1392048e328SMark Yao /* vop AHP clk */ 1402048e328SMark Yao struct clk *hclk; 1412048e328SMark Yao /* vop dclk */ 1422048e328SMark Yao struct clk *dclk; 1432048e328SMark Yao /* vop share memory frequency */ 1442048e328SMark Yao struct clk *aclk; 1452048e328SMark Yao 1462048e328SMark Yao /* vop dclk reset */ 1472048e328SMark Yao struct reset_control *dclk_rst; 1482048e328SMark Yao 1492048e328SMark Yao struct vop_win win[]; 1502048e328SMark Yao }; 1512048e328SMark Yao 1522048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1532048e328SMark Yao { 1542048e328SMark Yao writel(v, vop->regs + offset); 1552048e328SMark Yao vop->regsbak[offset >> 2] = v; 1562048e328SMark Yao } 1572048e328SMark Yao 1582048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1592048e328SMark Yao { 1602048e328SMark Yao return readl(vop->regs + offset); 1612048e328SMark Yao } 1622048e328SMark Yao 1632048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1642048e328SMark Yao const struct vop_reg *reg) 1652048e328SMark Yao { 1662048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1672048e328SMark Yao } 1682048e328SMark Yao 1692048e328SMark Yao static inline void vop_mask_write(struct vop *vop, uint32_t offset, 170d49463ecSMark Yao uint32_t mask, uint32_t shift, uint32_t v, 171d49463ecSMark Yao bool write_mask, bool relaxed) 1722048e328SMark Yao { 173d49463ecSMark Yao if (!mask) 174d49463ecSMark Yao return; 175d49463ecSMark Yao 176d49463ecSMark Yao if (write_mask) { 177d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 178d49463ecSMark Yao } else { 1792048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1802048e328SMark Yao 181d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 182d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 1832048e328SMark Yao } 1842048e328SMark Yao 185d49463ecSMark Yao if (relaxed) 186d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 187d49463ecSMark Yao else 188d49463ecSMark Yao writel(v, vop->regs + offset); 1892048e328SMark Yao } 1902048e328SMark Yao 191dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 192dbb3d944SMark Yao const struct vop_reg *reg, int type) 193dbb3d944SMark Yao { 194dbb3d944SMark Yao uint32_t i, ret = 0; 195dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 196dbb3d944SMark Yao 197dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 198dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 199dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 200dbb3d944SMark Yao } 201dbb3d944SMark Yao 202dbb3d944SMark Yao return ret; 203dbb3d944SMark Yao } 204dbb3d944SMark Yao 2050cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2060cf33fe3SMark Yao { 2070cf33fe3SMark Yao VOP_CTRL_SET(vop, cfg_done, 1); 2080cf33fe3SMark Yao } 2090cf33fe3SMark Yao 21085a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 21185a359f2STomasz Figa { 21285a359f2STomasz Figa switch (format) { 21385a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 21485a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 21585a359f2STomasz Figa case DRM_FORMAT_BGR888: 21685a359f2STomasz Figa case DRM_FORMAT_BGR565: 21785a359f2STomasz Figa return true; 21885a359f2STomasz Figa default: 21985a359f2STomasz Figa return false; 22085a359f2STomasz Figa } 22185a359f2STomasz Figa } 22285a359f2STomasz Figa 2232048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2242048e328SMark Yao { 2252048e328SMark Yao switch (format) { 2262048e328SMark Yao case DRM_FORMAT_XRGB8888: 2272048e328SMark Yao case DRM_FORMAT_ARGB8888: 22885a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 22985a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2302048e328SMark Yao return VOP_FMT_ARGB8888; 2312048e328SMark Yao case DRM_FORMAT_RGB888: 23285a359f2STomasz Figa case DRM_FORMAT_BGR888: 2332048e328SMark Yao return VOP_FMT_RGB888; 2342048e328SMark Yao case DRM_FORMAT_RGB565: 23585a359f2STomasz Figa case DRM_FORMAT_BGR565: 2362048e328SMark Yao return VOP_FMT_RGB565; 2372048e328SMark Yao case DRM_FORMAT_NV12: 2382048e328SMark Yao return VOP_FMT_YUV420SP; 2392048e328SMark Yao case DRM_FORMAT_NV16: 2402048e328SMark Yao return VOP_FMT_YUV422SP; 2412048e328SMark Yao case DRM_FORMAT_NV24: 2422048e328SMark Yao return VOP_FMT_YUV444SP; 2432048e328SMark Yao default: 244ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2452048e328SMark Yao return -EINVAL; 2462048e328SMark Yao } 2472048e328SMark Yao } 2482048e328SMark Yao 24984c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 25084c7f8caSMark Yao { 25184c7f8caSMark Yao switch (format) { 25284c7f8caSMark Yao case DRM_FORMAT_NV12: 25384c7f8caSMark Yao case DRM_FORMAT_NV16: 25484c7f8caSMark Yao case DRM_FORMAT_NV24: 25584c7f8caSMark Yao return true; 25684c7f8caSMark Yao default: 25784c7f8caSMark Yao return false; 25884c7f8caSMark Yao } 25984c7f8caSMark Yao } 26084c7f8caSMark Yao 2612048e328SMark Yao static bool is_alpha_support(uint32_t format) 2622048e328SMark Yao { 2632048e328SMark Yao switch (format) { 2642048e328SMark Yao case DRM_FORMAT_ARGB8888: 26585a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2662048e328SMark Yao return true; 2672048e328SMark Yao default: 2682048e328SMark Yao return false; 2692048e328SMark Yao } 2702048e328SMark Yao } 2712048e328SMark Yao 2724c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2734c156c21SMark Yao uint32_t dst, bool is_horizontal, 2744c156c21SMark Yao int vsu_mode, int *vskiplines) 2754c156c21SMark Yao { 2764c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2774c156c21SMark Yao 2784c156c21SMark Yao if (is_horizontal) { 2794c156c21SMark Yao if (mode == SCALE_UP) 2804c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2814c156c21SMark Yao else if (mode == SCALE_DOWN) 2824c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2834c156c21SMark Yao } else { 2844c156c21SMark Yao if (mode == SCALE_UP) { 2854c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2864c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2874c156c21SMark Yao else 2884c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2894c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2904c156c21SMark Yao if (vskiplines) { 2914c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 2924c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 2934c156c21SMark Yao *vskiplines); 2944c156c21SMark Yao } else { 2954c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2964c156c21SMark Yao } 2974c156c21SMark Yao } 2984c156c21SMark Yao } 2994c156c21SMark Yao 3004c156c21SMark Yao return val; 3014c156c21SMark Yao } 3024c156c21SMark Yao 3034c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3044c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3054c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 3064c156c21SMark Yao { 3074c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3084c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3094c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 3104c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 3114c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 3124c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 3134c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 3144c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 3154c156c21SMark Yao uint16_t vsu_mode; 3164c156c21SMark Yao uint16_t lb_mode; 3174c156c21SMark Yao uint32_t val; 3182db00cf5SMark Yao int vskiplines = 0; 3194c156c21SMark Yao 3204c156c21SMark Yao if (dst_w > 3840) { 321ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3224c156c21SMark Yao return; 3234c156c21SMark Yao } 3244c156c21SMark Yao 3251194fffbSMark Yao if (!win->phy->scl->ext) { 3261194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3271194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3281194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3291194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3301194fffbSMark Yao if (is_yuv) { 3311194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 332ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3331194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 334ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3351194fffbSMark Yao } 3361194fffbSMark Yao return; 3371194fffbSMark Yao } 3381194fffbSMark Yao 3394c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3404c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3414c156c21SMark Yao 3424c156c21SMark Yao if (is_yuv) { 3434c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3444c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3454c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3464c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3474c156c21SMark Yao else 3484c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3494c156c21SMark Yao } else { 3504c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3514c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3524c156c21SMark Yao else 3534c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3544c156c21SMark Yao } 3554c156c21SMark Yao 3561194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3574c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3584c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 359ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3604c156c21SMark Yao return; 3614c156c21SMark Yao } 3624c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 363ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3644c156c21SMark Yao return; 3654c156c21SMark Yao } 3664c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3674c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3684c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3694c156c21SMark Yao } else { 3704c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3714c156c21SMark Yao } 3724c156c21SMark Yao 3734c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3744c156c21SMark Yao true, 0, NULL); 3754c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3764c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3774c156c21SMark Yao false, vsu_mode, &vskiplines); 3784c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3794c156c21SMark Yao 3801194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3811194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3824c156c21SMark Yao 3831194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3841194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3851194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3861194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3871194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3884c156c21SMark Yao if (is_yuv) { 3894c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3904c156c21SMark Yao dst_w, true, 0, NULL); 3914c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 3924c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 3934c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 3944c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 3954c156c21SMark Yao 3961194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 3971194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 3981194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 3991194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4001194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4011194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4021194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4034c156c21SMark Yao } 4044c156c21SMark Yao } 4054c156c21SMark Yao 4061067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4071067219bSMark Yao { 4081067219bSMark Yao unsigned long flags; 4091067219bSMark Yao 4101067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4111067219bSMark Yao return; 4121067219bSMark Yao 4131067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4141067219bSMark Yao 415fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 416dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4171067219bSMark Yao 4181067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4191067219bSMark Yao } 4201067219bSMark Yao 4211067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4221067219bSMark Yao { 4231067219bSMark Yao unsigned long flags; 4241067219bSMark Yao 4251067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4261067219bSMark Yao return; 4271067219bSMark Yao 4281067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4291067219bSMark Yao 430dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4311067219bSMark Yao 4321067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4331067219bSMark Yao } 4341067219bSMark Yao 43569c34e41SYakir Yang /* 43669c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 43769c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 43869c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 43969c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 44069c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 44169c34e41SYakir Yang * 44269c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 44369c34e41SYakir Yang * Interrupts 44469c34e41SYakir Yang * LINE_FLAG -------------------------------+ 44569c34e41SYakir Yang * FRAME_SYNC ----+ | 44669c34e41SYakir Yang * | | 44769c34e41SYakir Yang * v v 44869c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 44969c34e41SYakir Yang * ^ ^ ^ ^ 45069c34e41SYakir Yang * | | | | 45169c34e41SYakir Yang * | | | | 45269c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 45369c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 45469c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 45569c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 45669c34e41SYakir Yang */ 45769c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 45869c34e41SYakir Yang { 45969c34e41SYakir Yang uint32_t line_flag_irq; 46069c34e41SYakir Yang unsigned long flags; 46169c34e41SYakir Yang 46269c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 46369c34e41SYakir Yang 46469c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 46569c34e41SYakir Yang 46669c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 46769c34e41SYakir Yang 46869c34e41SYakir Yang return !!line_flag_irq; 46969c34e41SYakir Yang } 47069c34e41SYakir Yang 471459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 47269c34e41SYakir Yang { 47369c34e41SYakir Yang unsigned long flags; 47469c34e41SYakir Yang 47569c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 47669c34e41SYakir Yang return; 47769c34e41SYakir Yang 47869c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 47969c34e41SYakir Yang 480fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 48169c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 48269c34e41SYakir Yang 48369c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 48469c34e41SYakir Yang } 48569c34e41SYakir Yang 48669c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 48769c34e41SYakir Yang { 48869c34e41SYakir Yang unsigned long flags; 48969c34e41SYakir Yang 49069c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 49169c34e41SYakir Yang return; 49269c34e41SYakir Yang 49369c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 49469c34e41SYakir Yang 49569c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 49669c34e41SYakir Yang 49769c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 49869c34e41SYakir Yang } 49969c34e41SYakir Yang 50039a9ad8fSSean Paul static int vop_enable(struct drm_crtc *crtc) 5012048e328SMark Yao { 5022048e328SMark Yao struct vop *vop = to_vop(crtc); 5032048e328SMark Yao int ret; 5042048e328SMark Yao 5055d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5065d82d1a7SMark Yao if (ret < 0) { 5075d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 5085e570373SJeffy Chen return ret; 5095d82d1a7SMark Yao } 5105d82d1a7SMark Yao 5112048e328SMark Yao ret = clk_enable(vop->hclk); 51239a9ad8fSSean Paul if (WARN_ON(ret < 0)) 51339a9ad8fSSean Paul goto err_put_pm_runtime; 5142048e328SMark Yao 5152048e328SMark Yao ret = clk_enable(vop->dclk); 51639a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5172048e328SMark Yao goto err_disable_hclk; 5182048e328SMark Yao 5192048e328SMark Yao ret = clk_enable(vop->aclk); 52039a9ad8fSSean Paul if (WARN_ON(ret < 0)) 5212048e328SMark Yao goto err_disable_dclk; 5222048e328SMark Yao 5232048e328SMark Yao /* 5242048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5252048e328SMark Yao * automatically with this master device via common driver code. 5262048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5272048e328SMark Yao * mapping. 5282048e328SMark Yao */ 5292048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5302048e328SMark Yao if (ret) { 5312048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 5322048e328SMark Yao goto err_disable_aclk; 5332048e328SMark Yao } 5342048e328SMark Yao 53577faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 53617a794d7SChris Zhong vop_cfg_done(vop); 53717a794d7SChris Zhong 53852ab7891SMark Yao /* 53952ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 54052ab7891SMark Yao */ 54152ab7891SMark Yao vop->is_enabled = true; 54252ab7891SMark Yao 5432048e328SMark Yao spin_lock(&vop->reg_lock); 5442048e328SMark Yao 5452048e328SMark Yao VOP_CTRL_SET(vop, standby, 0); 5462048e328SMark Yao 5472048e328SMark Yao spin_unlock(&vop->reg_lock); 5482048e328SMark Yao 5492048e328SMark Yao enable_irq(vop->irq); 5502048e328SMark Yao 551b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 5522048e328SMark Yao 55339a9ad8fSSean Paul return 0; 5542048e328SMark Yao 5552048e328SMark Yao err_disable_aclk: 5562048e328SMark Yao clk_disable(vop->aclk); 5572048e328SMark Yao err_disable_dclk: 5582048e328SMark Yao clk_disable(vop->dclk); 5592048e328SMark Yao err_disable_hclk: 5602048e328SMark Yao clk_disable(vop->hclk); 56139a9ad8fSSean Paul err_put_pm_runtime: 56239a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 56339a9ad8fSSean Paul return ret; 5642048e328SMark Yao } 5652048e328SMark Yao 5660ad3675dSMark Yao static void vop_crtc_disable(struct drm_crtc *crtc) 5672048e328SMark Yao { 5682048e328SMark Yao struct vop *vop = to_vop(crtc); 5693ed6c649STomeu Vizoso int i; 5702048e328SMark Yao 571893b6cadSDaniel Vetter WARN_ON(vop->event); 572893b6cadSDaniel Vetter 573b883c9baSSean Paul rockchip_drm_psr_deactivate(&vop->crtc); 574b883c9baSSean Paul 5753ed6c649STomeu Vizoso /* 5763ed6c649STomeu Vizoso * We need to make sure that all windows are disabled before we 5773ed6c649STomeu Vizoso * disable that crtc. Otherwise we might try to scan from a destroyed 5783ed6c649STomeu Vizoso * buffer later. 5793ed6c649STomeu Vizoso */ 5803ed6c649STomeu Vizoso for (i = 0; i < vop->data->win_size; i++) { 5813ed6c649STomeu Vizoso struct vop_win *vop_win = &vop->win[i]; 5823ed6c649STomeu Vizoso const struct vop_win_data *win = vop_win->data; 5833ed6c649STomeu Vizoso 5843ed6c649STomeu Vizoso spin_lock(&vop->reg_lock); 5853ed6c649STomeu Vizoso VOP_WIN_SET(vop, win, enable, 0); 5863ed6c649STomeu Vizoso spin_unlock(&vop->reg_lock); 5873ed6c649STomeu Vizoso } 5883ed6c649STomeu Vizoso 58917a794d7SChris Zhong vop_cfg_done(vop); 59017a794d7SChris Zhong 591b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 5922048e328SMark Yao 5932048e328SMark Yao /* 5941067219bSMark Yao * Vop standby will take effect at end of current frame, 5951067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5961067219bSMark Yao * 5971067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5981067219bSMark Yao * if not, memory bus maybe dead. 5992048e328SMark Yao */ 6001067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 6011067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 6021067219bSMark Yao 6032048e328SMark Yao spin_lock(&vop->reg_lock); 6042048e328SMark Yao 6052048e328SMark Yao VOP_CTRL_SET(vop, standby, 1); 6062048e328SMark Yao 6072048e328SMark Yao spin_unlock(&vop->reg_lock); 60852ab7891SMark Yao 6091067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 6102048e328SMark Yao 6111067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6121067219bSMark Yao 6131067219bSMark Yao disable_irq(vop->irq); 6141067219bSMark Yao 6151067219bSMark Yao vop->is_enabled = false; 6161067219bSMark Yao 6171067219bSMark Yao /* 6181067219bSMark Yao * vop standby complete, so iommu detach is safe. 6191067219bSMark Yao */ 6202048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6212048e328SMark Yao 6221067219bSMark Yao clk_disable(vop->dclk); 6232048e328SMark Yao clk_disable(vop->aclk); 6242048e328SMark Yao clk_disable(vop->hclk); 6255d82d1a7SMark Yao pm_runtime_put(vop->dev); 626893b6cadSDaniel Vetter 627893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 628893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 629893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 630893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 631893b6cadSDaniel Vetter 632893b6cadSDaniel Vetter crtc->state->event = NULL; 633893b6cadSDaniel Vetter } 6342048e328SMark Yao } 6352048e328SMark Yao 63663ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 6372048e328SMark Yao { 63863ebb9faSMark Yao drm_plane_cleanup(plane); 6392048e328SMark Yao } 6402048e328SMark Yao 64163ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 64263ebb9faSMark Yao struct drm_plane_state *state) 6432048e328SMark Yao { 64463ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 64592915da6SJohn Keeping struct drm_crtc_state *crtc_state; 64663ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 6472048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 6482048e328SMark Yao const struct vop_win_data *win = vop_win->data; 6492048e328SMark Yao int ret; 65063ebb9faSMark Yao struct drm_rect clip; 6514c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 6524c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6534c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 6544c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 6552048e328SMark Yao 65663ebb9faSMark Yao if (!crtc || !fb) 657d47a7246STomasz Figa return 0; 65892915da6SJohn Keeping 65992915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 66092915da6SJohn Keeping if (WARN_ON(!crtc_state)) 66192915da6SJohn Keeping return -EINVAL; 66292915da6SJohn Keeping 66363ebb9faSMark Yao clip.x1 = 0; 66463ebb9faSMark Yao clip.y1 = 0; 66592915da6SJohn Keeping clip.x2 = crtc_state->adjusted_mode.hdisplay; 66692915da6SJohn Keeping clip.y2 = crtc_state->adjusted_mode.vdisplay; 66763ebb9faSMark Yao 668f9b96be0SVille Syrjälä ret = drm_plane_helper_check_state(state, &clip, 669f9b96be0SVille Syrjälä min_scale, max_scale, 670f9b96be0SVille Syrjälä true, true); 6712048e328SMark Yao if (ret) 6722048e328SMark Yao return ret; 6732048e328SMark Yao 674f9b96be0SVille Syrjälä if (!state->visible) 675d47a7246STomasz Figa return 0; 6762048e328SMark Yao 677438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 678d47a7246STomasz Figa if (ret < 0) 679d47a7246STomasz Figa return ret; 68084c7f8caSMark Yao 68184c7f8caSMark Yao /* 68284c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 68384c7f8caSMark Yao * need align with 2 pixel. 68484c7f8caSMark Yao */ 685438b74a5SVille Syrjälä if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) 68663ebb9faSMark Yao return -EINVAL; 68763ebb9faSMark Yao 68863ebb9faSMark Yao return 0; 68984c7f8caSMark Yao } 69084c7f8caSMark Yao 69163ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 69263ebb9faSMark Yao struct drm_plane_state *old_state) 69363ebb9faSMark Yao { 69463ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 69563ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 69663ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 6972048e328SMark Yao 69863ebb9faSMark Yao if (!old_state->crtc) 69963ebb9faSMark Yao return; 7002048e328SMark Yao 70163ebb9faSMark Yao spin_lock(&vop->reg_lock); 7022048e328SMark Yao 70363ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 7042048e328SMark Yao 70563ebb9faSMark Yao spin_unlock(&vop->reg_lock); 70663ebb9faSMark Yao } 70763ebb9faSMark Yao 70863ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 70963ebb9faSMark Yao struct drm_plane_state *old_state) 71063ebb9faSMark Yao { 71163ebb9faSMark Yao struct drm_plane_state *state = plane->state; 71263ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 71363ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 71463ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 71563ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 71663ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 71763ebb9faSMark Yao unsigned int actual_w, actual_h; 71863ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 71963ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 720ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 721ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 72263ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 72363ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 72463ebb9faSMark Yao unsigned long offset; 72563ebb9faSMark Yao dma_addr_t dma_addr; 72663ebb9faSMark Yao uint32_t val; 72763ebb9faSMark Yao bool rb_swap; 728d47a7246STomasz Figa int format; 72963ebb9faSMark Yao 73063ebb9faSMark Yao /* 73163ebb9faSMark Yao * can't update plane when vop is disabled. 73263ebb9faSMark Yao */ 7334f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 73463ebb9faSMark Yao return; 73563ebb9faSMark Yao 73663ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 73763ebb9faSMark Yao return; 73863ebb9faSMark Yao 739d47a7246STomasz Figa if (!state->visible) { 74063ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 74163ebb9faSMark Yao return; 74263ebb9faSMark Yao } 74363ebb9faSMark Yao 74463ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 74563ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 74663ebb9faSMark Yao 74763ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 74863ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 74963ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 75063ebb9faSMark Yao 75163ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 75263ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 75363ebb9faSMark Yao 75463ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 75563ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 75663ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 75763ebb9faSMark Yao 758353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 75963ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 760d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 761d47a7246STomasz Figa 762438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 76363ebb9faSMark Yao 76463ebb9faSMark Yao spin_lock(&vop->reg_lock); 76563ebb9faSMark Yao 766d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 76763ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 768d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 769438b74a5SVille Syrjälä if (is_yuv_support(fb->format->format)) { 770438b74a5SVille Syrjälä int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 771438b74a5SVille Syrjälä int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 772353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 77384c7f8caSMark Yao 77484c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 77584c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 77684c7f8caSMark Yao 77763ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 77863ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 77984c7f8caSMark Yao 78063ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 78163ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 78263ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 78384c7f8caSMark Yao } 7844c156c21SMark Yao 7854c156c21SMark Yao if (win->phy->scl) 7864c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 78763ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 788438b74a5SVille Syrjälä fb->format->format); 7894c156c21SMark Yao 79063ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 79163ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 79263ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 7934c156c21SMark Yao 794438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 79585a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 7962048e328SMark Yao 797438b74a5SVille Syrjälä if (is_alpha_support(fb->format->format)) { 7982048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 7992048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 8002048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 8012048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 8022048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 8032048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 8042048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 8052048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 8062048e328SMark Yao } else { 8072048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 8082048e328SMark Yao } 8092048e328SMark Yao 8102048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 8112048e328SMark Yao spin_unlock(&vop->reg_lock); 8122048e328SMark Yao } 8132048e328SMark Yao 81463ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 81563ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 81663ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 81763ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 81863ebb9faSMark Yao }; 81963ebb9faSMark Yao 8202048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 82163ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 82263ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 8232048e328SMark Yao .destroy = vop_plane_destroy, 824d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 825d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 826d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 8272048e328SMark Yao }; 8282048e328SMark Yao 8292048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 8302048e328SMark Yao { 8312048e328SMark Yao struct vop *vop = to_vop(crtc); 8322048e328SMark Yao unsigned long flags; 8332048e328SMark Yao 83463ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8352048e328SMark Yao return -EPERM; 8362048e328SMark Yao 8372048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 8382048e328SMark Yao 839fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 840dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 8412048e328SMark Yao 8422048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8432048e328SMark Yao 8442048e328SMark Yao return 0; 8452048e328SMark Yao } 8462048e328SMark Yao 8472048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 8482048e328SMark Yao { 8492048e328SMark Yao struct vop *vop = to_vop(crtc); 8502048e328SMark Yao unsigned long flags; 8512048e328SMark Yao 85263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8532048e328SMark Yao return; 85431e980c5SMark Yao 8552048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 856dbb3d944SMark Yao 857dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 858dbb3d944SMark Yao 8592048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8602048e328SMark Yao } 8612048e328SMark Yao 8622048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 8632048e328SMark Yao const struct drm_display_mode *mode, 8642048e328SMark Yao struct drm_display_mode *adjusted_mode) 8652048e328SMark Yao { 866b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 867b59b8de3SChris Zhong 868b59b8de3SChris Zhong adjusted_mode->clock = 869b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 870b59b8de3SChris Zhong 8712048e328SMark Yao return true; 8722048e328SMark Yao } 8732048e328SMark Yao 87463ebb9faSMark Yao static void vop_crtc_enable(struct drm_crtc *crtc) 8752048e328SMark Yao { 8762048e328SMark Yao struct vop *vop = to_vop(crtc); 8774e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 87863ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 8792048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 8802048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 8812048e328SMark Yao u16 htotal = adjusted_mode->htotal; 8822048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 8832048e328SMark Yao u16 hact_end = hact_st + hdisplay; 8842048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 8852048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 8862048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 8872048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 8882048e328SMark Yao u16 vact_end = vact_st + vdisplay; 8890a63bfd0SMark Yao uint32_t pin_pol, val; 89039a9ad8fSSean Paul int ret; 8912048e328SMark Yao 892893b6cadSDaniel Vetter WARN_ON(vop->event); 893893b6cadSDaniel Vetter 89439a9ad8fSSean Paul ret = vop_enable(crtc); 89539a9ad8fSSean Paul if (ret) { 89639a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 89739a9ad8fSSean Paul return; 89839a9ad8fSSean Paul } 89939a9ad8fSSean Paul 9002048e328SMark Yao /* 901ce3887edSMark Yao * If dclk rate is zero, mean that scanout is stop, 902ce3887edSMark Yao * we don't need wait any more. 9032048e328SMark Yao */ 904ce3887edSMark Yao if (clk_get_rate(vop->dclk)) { 905ce3887edSMark Yao /* 906ce3887edSMark Yao * Rk3288 vop timing register is immediately, when configure 907ce3887edSMark Yao * display timing on display time, may cause tearing. 908ce3887edSMark Yao * 909ce3887edSMark Yao * Vop standby will take effect at end of current frame, 910ce3887edSMark Yao * if dsp hold valid irq happen, it means standby complete. 911ce3887edSMark Yao * 912ce3887edSMark Yao * mode set: 913ce3887edSMark Yao * standby and wait complete --> |---- 914ce3887edSMark Yao * | display time 915ce3887edSMark Yao * |---- 916ce3887edSMark Yao * |---> dsp hold irq 917ce3887edSMark Yao * configure display timing --> | 918ce3887edSMark Yao * standby exit | 919ce3887edSMark Yao * | new frame start. 920ce3887edSMark Yao */ 921ce3887edSMark Yao 922ce3887edSMark Yao reinit_completion(&vop->dsp_hold_completion); 923ce3887edSMark Yao vop_dsp_hold_valid_irq_enable(vop); 924ce3887edSMark Yao 925ce3887edSMark Yao spin_lock(&vop->reg_lock); 926ce3887edSMark Yao 927ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 1); 928ce3887edSMark Yao 929ce3887edSMark Yao spin_unlock(&vop->reg_lock); 930ce3887edSMark Yao 931ce3887edSMark Yao wait_for_completion(&vop->dsp_hold_completion); 932ce3887edSMark Yao 933ce3887edSMark Yao vop_dsp_hold_valid_irq_disable(vop); 934ce3887edSMark Yao } 9352048e328SMark Yao 9361a0f7ed3SChris Zhong pin_pol = BIT(DCLK_INVERT); 937d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 938d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 939d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 940d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 9410a63bfd0SMark Yao VOP_CTRL_SET(vop, pin_pol, pin_pol); 9420a63bfd0SMark Yao 9434e257d9eSMark Yao switch (s->output_type) { 9444e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 9454e257d9eSMark Yao VOP_CTRL_SET(vop, rgb_en, 1); 9460a63bfd0SMark Yao VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); 9474e257d9eSMark Yao break; 9484e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 9490a63bfd0SMark Yao VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); 9504e257d9eSMark Yao VOP_CTRL_SET(vop, edp_en, 1); 9514e257d9eSMark Yao break; 9524e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 9530a63bfd0SMark Yao VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); 9544e257d9eSMark Yao VOP_CTRL_SET(vop, hdmi_en, 1); 9554e257d9eSMark Yao break; 9564e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 9570a63bfd0SMark Yao VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); 9584e257d9eSMark Yao VOP_CTRL_SET(vop, mipi_en, 1); 9594e257d9eSMark Yao break; 9601a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 9611a0f7ed3SChris Zhong pin_pol &= ~BIT(DCLK_INVERT); 9621a0f7ed3SChris Zhong VOP_CTRL_SET(vop, dp_pin_pol, pin_pol); 9631a0f7ed3SChris Zhong VOP_CTRL_SET(vop, dp_en, 1); 9641a0f7ed3SChris Zhong break; 9654e257d9eSMark Yao default: 966ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 967ee4d7899SSean Paul s->output_type); 9684e257d9eSMark Yao } 9694e257d9eSMark Yao VOP_CTRL_SET(vop, out_mode, s->output_mode); 9702048e328SMark Yao 9712048e328SMark Yao VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 9722048e328SMark Yao val = hact_st << 16; 9732048e328SMark Yao val |= hact_end; 9742048e328SMark Yao VOP_CTRL_SET(vop, hact_st_end, val); 9752048e328SMark Yao VOP_CTRL_SET(vop, hpost_st_end, val); 9762048e328SMark Yao 9772048e328SMark Yao VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 9782048e328SMark Yao val = vact_st << 16; 9792048e328SMark Yao val |= vact_end; 9802048e328SMark Yao VOP_CTRL_SET(vop, vact_st_end, val); 9812048e328SMark Yao VOP_CTRL_SET(vop, vpost_st_end, val); 9822048e328SMark Yao 983459b086dSJeffy Chen VOP_CTRL_SET(vop, line_flag_num[0], vact_end); 984459b086dSJeffy Chen 9852048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 986ce3887edSMark Yao 987ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 0); 988b883c9baSSean Paul 989b883c9baSSean Paul rockchip_drm_psr_activate(&vop->crtc); 9902048e328SMark Yao } 9912048e328SMark Yao 9927caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 9937caecdbeSTomasz Figa { 9947caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 9957caecdbeSTomasz Figa } 9967caecdbeSTomasz Figa 9977caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 9987caecdbeSTomasz Figa { 9997caecdbeSTomasz Figa bool pending; 10007caecdbeSTomasz Figa int ret; 10017caecdbeSTomasz Figa 10027caecdbeSTomasz Figa /* 10037caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 10047caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 10057caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 10067caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 10077caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 10087caecdbeSTomasz Figa * shouldn't exceed microseconds range. 10097caecdbeSTomasz Figa */ 10107caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 10117caecdbeSTomasz Figa !pending, 0, 10 * 1000); 10127caecdbeSTomasz Figa if (ret) 10137caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 10147caecdbeSTomasz Figa 10157caecdbeSTomasz Figa synchronize_irq(vop->irq); 10167caecdbeSTomasz Figa } 10177caecdbeSTomasz Figa 101863ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 101963ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 102063ebb9faSMark Yao { 102147a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 102247a7eb45STomasz Figa struct drm_plane_state *old_plane_state; 102363ebb9faSMark Yao struct vop *vop = to_vop(crtc); 102447a7eb45STomasz Figa struct drm_plane *plane; 102547a7eb45STomasz Figa int i; 102663ebb9faSMark Yao 102763ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 102863ebb9faSMark Yao return; 102963ebb9faSMark Yao 103063ebb9faSMark Yao spin_lock(&vop->reg_lock); 103163ebb9faSMark Yao 103263ebb9faSMark Yao vop_cfg_done(vop); 103363ebb9faSMark Yao 103463ebb9faSMark Yao spin_unlock(&vop->reg_lock); 10357caecdbeSTomasz Figa 10367caecdbeSTomasz Figa /* 10377caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 10387caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 10397caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 10407caecdbeSTomasz Figa */ 10417caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 104247a7eb45STomasz Figa 104341ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 104441ee4367STomasz Figa if (crtc->state->event) { 104541ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 104641ee4367STomasz Figa WARN_ON(vop->event); 104741ee4367STomasz Figa 104841ee4367STomasz Figa vop->event = crtc->state->event; 104941ee4367STomasz Figa crtc->state->event = NULL; 105041ee4367STomasz Figa } 105141ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 105241ee4367STomasz Figa 105347a7eb45STomasz Figa for_each_plane_in_state(old_state, plane, old_plane_state, i) { 105447a7eb45STomasz Figa if (!old_plane_state->fb) 105547a7eb45STomasz Figa continue; 105647a7eb45STomasz Figa 105747a7eb45STomasz Figa if (old_plane_state->fb == plane->state->fb) 105847a7eb45STomasz Figa continue; 105947a7eb45STomasz Figa 106047a7eb45STomasz Figa drm_framebuffer_reference(old_plane_state->fb); 106147a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 106247a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 106347a7eb45STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 106447a7eb45STomasz Figa } 106563ebb9faSMark Yao } 106663ebb9faSMark Yao 106763ebb9faSMark Yao static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 106863ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 106963ebb9faSMark Yao { 1070b883c9baSSean Paul rockchip_drm_psr_flush(crtc); 10712048e328SMark Yao } 10722048e328SMark Yao 10732048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 10740ad3675dSMark Yao .enable = vop_crtc_enable, 10750ad3675dSMark Yao .disable = vop_crtc_disable, 10762048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 107763ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 107863ebb9faSMark Yao .atomic_begin = vop_crtc_atomic_begin, 10792048e328SMark Yao }; 10802048e328SMark Yao 10812048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 10822048e328SMark Yao { 10832048e328SMark Yao drm_crtc_cleanup(crtc); 10842048e328SMark Yao } 10852048e328SMark Yao 1086dc0b408fSJohn Keeping static void vop_crtc_reset(struct drm_crtc *crtc) 1087dc0b408fSJohn Keeping { 1088dc0b408fSJohn Keeping if (crtc->state) 1089dc0b408fSJohn Keeping __drm_atomic_helper_crtc_destroy_state(crtc->state); 1090dc0b408fSJohn Keeping kfree(crtc->state); 1091dc0b408fSJohn Keeping 1092dc0b408fSJohn Keeping crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1093dc0b408fSJohn Keeping if (crtc->state) 1094dc0b408fSJohn Keeping crtc->state->crtc = crtc; 1095dc0b408fSJohn Keeping } 1096dc0b408fSJohn Keeping 10974e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 10984e257d9eSMark Yao { 10994e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 11004e257d9eSMark Yao 11014e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 11024e257d9eSMark Yao if (!rockchip_state) 11034e257d9eSMark Yao return NULL; 11044e257d9eSMark Yao 11054e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 11064e257d9eSMark Yao return &rockchip_state->base; 11074e257d9eSMark Yao } 11084e257d9eSMark Yao 11094e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 11104e257d9eSMark Yao struct drm_crtc_state *state) 11114e257d9eSMark Yao { 11124e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 11134e257d9eSMark Yao 1114ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 11154e257d9eSMark Yao kfree(s); 11164e257d9eSMark Yao } 11174e257d9eSMark Yao 11186cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 11193190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 11203190e58dSTomeu Vizoso { 11213190e58dSTomeu Vizoso struct drm_crtc *crtc = &vop->crtc; 11223190e58dSTomeu Vizoso struct drm_connector *connector; 11233190e58dSTomeu Vizoso 11243190e58dSTomeu Vizoso mutex_lock(&crtc->dev->mode_config.mutex); 11253190e58dSTomeu Vizoso drm_for_each_connector(connector, crtc->dev) 11263190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 11273190e58dSTomeu Vizoso mutex_unlock(&crtc->dev->mode_config.mutex); 11283190e58dSTomeu Vizoso return connector; 11293190e58dSTomeu Vizoso } 11303190e58dSTomeu Vizoso mutex_unlock(&crtc->dev->mode_config.mutex); 11313190e58dSTomeu Vizoso 11323190e58dSTomeu Vizoso return NULL; 11333190e58dSTomeu Vizoso } 11343190e58dSTomeu Vizoso 11353190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 11363190e58dSTomeu Vizoso const char *source_name, size_t *values_cnt) 11373190e58dSTomeu Vizoso { 11383190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 11393190e58dSTomeu Vizoso struct drm_connector *connector; 11403190e58dSTomeu Vizoso int ret; 11413190e58dSTomeu Vizoso 11423190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 11433190e58dSTomeu Vizoso if (!connector) 11443190e58dSTomeu Vizoso return -EINVAL; 11453190e58dSTomeu Vizoso 11463190e58dSTomeu Vizoso *values_cnt = 3; 11473190e58dSTomeu Vizoso 11483190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 11493190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 11503190e58dSTomeu Vizoso else if (!source_name) 11513190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 11523190e58dSTomeu Vizoso else 11533190e58dSTomeu Vizoso ret = -EINVAL; 11543190e58dSTomeu Vizoso 11553190e58dSTomeu Vizoso return ret; 11563190e58dSTomeu Vizoso } 11576cca3869SSean Paul #else 11586cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 11596cca3869SSean Paul const char *source_name, size_t *values_cnt) 11606cca3869SSean Paul { 11616cca3869SSean Paul return -ENODEV; 11626cca3869SSean Paul } 11636cca3869SSean Paul #endif 11643190e58dSTomeu Vizoso 11652048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 116663ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 116763ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 11682048e328SMark Yao .destroy = vop_crtc_destroy, 1169dc0b408fSJohn Keeping .reset = vop_crtc_reset, 11704e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 11714e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1172c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1173c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 11743190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 11752048e328SMark Yao }; 11762048e328SMark Yao 117747a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 117847a7eb45STomasz Figa { 117947a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 118047a7eb45STomasz Figa struct drm_framebuffer *fb = val; 118147a7eb45STomasz Figa 118247a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 118347a7eb45STomasz Figa drm_framebuffer_unreference(fb); 118447a7eb45STomasz Figa } 118547a7eb45STomasz Figa 118663ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 11872048e328SMark Yao { 118863ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 118963ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 119063ebb9faSMark Yao unsigned long flags; 11912048e328SMark Yao 119263ebb9faSMark Yao spin_lock_irqsave(&drm->event_lock, flags); 1193893b6cadSDaniel Vetter if (vop->event) { 119463ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 11955b680403SSean Paul drm_crtc_vblank_put(crtc); 1196646ec687STomasz Figa vop->event = NULL; 11975b680403SSean Paul } 1198893b6cadSDaniel Vetter spin_unlock_irqrestore(&drm->event_lock, flags); 1199893b6cadSDaniel Vetter 120047a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 120147a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 12022048e328SMark Yao } 12032048e328SMark Yao 12042048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 12052048e328SMark Yao { 12062048e328SMark Yao struct vop *vop = data; 1207b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1208dbb3d944SMark Yao uint32_t active_irqs; 12092048e328SMark Yao unsigned long flags; 12101067219bSMark Yao int ret = IRQ_NONE; 12112048e328SMark Yao 12122048e328SMark Yao /* 1213dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 12142048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 12152048e328SMark Yao */ 12162048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1217dbb3d944SMark Yao 1218dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 12192048e328SMark Yao /* Clear all active interrupt sources */ 12202048e328SMark Yao if (active_irqs) 1221dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1222dbb3d944SMark Yao 12232048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 12242048e328SMark Yao 12252048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 12262048e328SMark Yao if (!active_irqs) 12272048e328SMark Yao return IRQ_NONE; 12282048e328SMark Yao 12291067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 12301067219bSMark Yao complete(&vop->dsp_hold_completion); 12311067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 12321067219bSMark Yao ret = IRQ_HANDLED; 12332048e328SMark Yao } 12342048e328SMark Yao 123569c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 123669c34e41SYakir Yang complete(&vop->line_flag_completion); 123769c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 123869c34e41SYakir Yang ret = IRQ_HANDLED; 123969c34e41SYakir Yang } 124069c34e41SYakir Yang 12411067219bSMark Yao if (active_irqs & FS_INTR) { 1242b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 124363ebb9faSMark Yao vop_handle_vblank(vop); 12441067219bSMark Yao active_irqs &= ~FS_INTR; 124563ebb9faSMark Yao ret = IRQ_HANDLED; 12461067219bSMark Yao } 12472048e328SMark Yao 12481067219bSMark Yao /* Unhandled irqs are spurious. */ 12491067219bSMark Yao if (active_irqs) 1250ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1251ee4d7899SSean Paul active_irqs); 12521067219bSMark Yao 12531067219bSMark Yao return ret; 12542048e328SMark Yao } 12552048e328SMark Yao 12562048e328SMark Yao static int vop_create_crtc(struct vop *vop) 12572048e328SMark Yao { 12582048e328SMark Yao const struct vop_data *vop_data = vop->data; 12592048e328SMark Yao struct device *dev = vop->dev; 12602048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1261328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 12622048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 12632048e328SMark Yao struct device_node *port; 12642048e328SMark Yao int ret; 12652048e328SMark Yao int i; 12662048e328SMark Yao 12672048e328SMark Yao /* 12682048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 12692048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 12702048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 12712048e328SMark Yao */ 12722048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12732048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12742048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12752048e328SMark Yao 12762048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 12772048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 12782048e328SMark Yao continue; 12792048e328SMark Yao 12802048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12812048e328SMark Yao 0, &vop_plane_funcs, 12822048e328SMark Yao win_data->phy->data_formats, 12832048e328SMark Yao win_data->phy->nformats, 1284b0b3b795SVille Syrjälä win_data->type, NULL); 12852048e328SMark Yao if (ret) { 1286ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1287ee4d7899SSean Paul ret); 12882048e328SMark Yao goto err_cleanup_planes; 12892048e328SMark Yao } 12902048e328SMark Yao 12912048e328SMark Yao plane = &vop_win->base; 129263ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 12932048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 12942048e328SMark Yao primary = plane; 12952048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 12962048e328SMark Yao cursor = plane; 12972048e328SMark Yao } 12982048e328SMark Yao 12992048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1300f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 13012048e328SMark Yao if (ret) 1302328b51c0SDouglas Anderson goto err_cleanup_planes; 13032048e328SMark Yao 13042048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 13052048e328SMark Yao 13062048e328SMark Yao /* 13072048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 13082048e328SMark Yao * to the newly created crtc. 13092048e328SMark Yao */ 13102048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13112048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13122048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 13132048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 13142048e328SMark Yao 13152048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 13162048e328SMark Yao continue; 13172048e328SMark Yao 13182048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 13192048e328SMark Yao possible_crtcs, 13202048e328SMark Yao &vop_plane_funcs, 13212048e328SMark Yao win_data->phy->data_formats, 13222048e328SMark Yao win_data->phy->nformats, 1323b0b3b795SVille Syrjälä win_data->type, NULL); 13242048e328SMark Yao if (ret) { 1325ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1326ee4d7899SSean Paul ret); 13272048e328SMark Yao goto err_cleanup_crtc; 13282048e328SMark Yao } 132963ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 13302048e328SMark Yao } 13312048e328SMark Yao 13322048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 13332048e328SMark Yao if (!port) { 1334ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "no port node found in %s\n", 13352048e328SMark Yao dev->of_node->full_name); 1336328b51c0SDouglas Anderson ret = -ENOENT; 13372048e328SMark Yao goto err_cleanup_crtc; 13382048e328SMark Yao } 13392048e328SMark Yao 134047a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 134147a7eb45STomasz Figa vop_fb_unref_worker); 134247a7eb45STomasz Figa 13431067219bSMark Yao init_completion(&vop->dsp_hold_completion); 134469c34e41SYakir Yang init_completion(&vop->line_flag_completion); 13452048e328SMark Yao crtc->port = port; 13462048e328SMark Yao 13472048e328SMark Yao return 0; 13482048e328SMark Yao 13492048e328SMark Yao err_cleanup_crtc: 13502048e328SMark Yao drm_crtc_cleanup(crtc); 13512048e328SMark Yao err_cleanup_planes: 1352328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1353328b51c0SDouglas Anderson head) 13542048e328SMark Yao drm_plane_cleanup(plane); 13552048e328SMark Yao return ret; 13562048e328SMark Yao } 13572048e328SMark Yao 13582048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 13592048e328SMark Yao { 13602048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1361328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1362328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 13632048e328SMark Yao 13642048e328SMark Yao of_node_put(crtc->port); 1365328b51c0SDouglas Anderson 1366328b51c0SDouglas Anderson /* 1367328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1368328b51c0SDouglas Anderson * 1369328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1370328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1371328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1372328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1373328b51c0SDouglas Anderson */ 1374328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1375328b51c0SDouglas Anderson head) 1376328b51c0SDouglas Anderson vop_plane_destroy(plane); 1377328b51c0SDouglas Anderson 1378328b51c0SDouglas Anderson /* 1379328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1380328b51c0SDouglas Anderson * references the CRTC. 1381328b51c0SDouglas Anderson */ 13822048e328SMark Yao drm_crtc_cleanup(crtc); 138347a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 13842048e328SMark Yao } 13852048e328SMark Yao 13862048e328SMark Yao static int vop_initial(struct vop *vop) 13872048e328SMark Yao { 13882048e328SMark Yao const struct vop_data *vop_data = vop->data; 13892048e328SMark Yao const struct vop_reg_data *init_table = vop_data->init_table; 13902048e328SMark Yao struct reset_control *ahb_rst; 13912048e328SMark Yao int i, ret; 13922048e328SMark Yao 13932048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 13942048e328SMark Yao if (IS_ERR(vop->hclk)) { 13952048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 13962048e328SMark Yao return PTR_ERR(vop->hclk); 13972048e328SMark Yao } 13982048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 13992048e328SMark Yao if (IS_ERR(vop->aclk)) { 14002048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 14012048e328SMark Yao return PTR_ERR(vop->aclk); 14022048e328SMark Yao } 14032048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 14042048e328SMark Yao if (IS_ERR(vop->dclk)) { 14052048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 14062048e328SMark Yao return PTR_ERR(vop->dclk); 14072048e328SMark Yao } 14082048e328SMark Yao 14095e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 14105e570373SJeffy Chen if (ret < 0) { 14115e570373SJeffy Chen dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 14125e570373SJeffy Chen return ret; 14135e570373SJeffy Chen } 14145e570373SJeffy Chen 14152048e328SMark Yao ret = clk_prepare(vop->dclk); 14162048e328SMark Yao if (ret < 0) { 14172048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 14185e570373SJeffy Chen goto err_put_pm_runtime; 14192048e328SMark Yao } 14202048e328SMark Yao 1421d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1422d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 14232048e328SMark Yao if (ret < 0) { 1424d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable hclk\n"); 14252048e328SMark Yao goto err_unprepare_dclk; 14262048e328SMark Yao } 14272048e328SMark Yao 1428d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 14292048e328SMark Yao if (ret < 0) { 1430d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1431d7b53fd9SSjoerd Simons goto err_disable_hclk; 14322048e328SMark Yao } 1433d7b53fd9SSjoerd Simons 14342048e328SMark Yao /* 14352048e328SMark Yao * do hclk_reset, reset all vop registers. 14362048e328SMark Yao */ 14372048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 14382048e328SMark Yao if (IS_ERR(ahb_rst)) { 14392048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 14402048e328SMark Yao ret = PTR_ERR(ahb_rst); 1441d7b53fd9SSjoerd Simons goto err_disable_aclk; 14422048e328SMark Yao } 14432048e328SMark Yao reset_control_assert(ahb_rst); 14442048e328SMark Yao usleep_range(10, 20); 14452048e328SMark Yao reset_control_deassert(ahb_rst); 14462048e328SMark Yao 14472048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 14482048e328SMark Yao 14492048e328SMark Yao for (i = 0; i < vop_data->table_size; i++) 14502048e328SMark Yao vop_writel(vop, init_table[i].offset, init_table[i].value); 14512048e328SMark Yao 14522048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 14532048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 14542048e328SMark Yao 14552048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 14562048e328SMark Yao } 14572048e328SMark Yao 14582048e328SMark Yao vop_cfg_done(vop); 14592048e328SMark Yao 14602048e328SMark Yao /* 14612048e328SMark Yao * do dclk_reset, let all config take affect. 14622048e328SMark Yao */ 14632048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 14642048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 14652048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 14662048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1467d7b53fd9SSjoerd Simons goto err_disable_aclk; 14682048e328SMark Yao } 14692048e328SMark Yao reset_control_assert(vop->dclk_rst); 14702048e328SMark Yao usleep_range(10, 20); 14712048e328SMark Yao reset_control_deassert(vop->dclk_rst); 14722048e328SMark Yao 14732048e328SMark Yao clk_disable(vop->hclk); 1474d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 14752048e328SMark Yao 147631e980c5SMark Yao vop->is_enabled = false; 14772048e328SMark Yao 14785e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14795e570373SJeffy Chen 14802048e328SMark Yao return 0; 14812048e328SMark Yao 1482d7b53fd9SSjoerd Simons err_disable_aclk: 1483d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 14842048e328SMark Yao err_disable_hclk: 1485d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 14862048e328SMark Yao err_unprepare_dclk: 14872048e328SMark Yao clk_unprepare(vop->dclk); 14885e570373SJeffy Chen err_put_pm_runtime: 14895e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 14902048e328SMark Yao return ret; 14912048e328SMark Yao } 14922048e328SMark Yao 14932048e328SMark Yao /* 14942048e328SMark Yao * Initialize the vop->win array elements. 14952048e328SMark Yao */ 14962048e328SMark Yao static void vop_win_init(struct vop *vop) 14972048e328SMark Yao { 14982048e328SMark Yao const struct vop_data *vop_data = vop->data; 14992048e328SMark Yao unsigned int i; 15002048e328SMark Yao 15012048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 15022048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 15032048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 15042048e328SMark Yao 15052048e328SMark Yao vop_win->data = win_data; 15062048e328SMark Yao vop_win->vop = vop; 15072048e328SMark Yao } 15082048e328SMark Yao } 15092048e328SMark Yao 151069c34e41SYakir Yang /** 1511459b086dSJeffy Chen * rockchip_drm_wait_vact_end 151269c34e41SYakir Yang * @crtc: CRTC to enable line flag 151369c34e41SYakir Yang * @mstimeout: millisecond for timeout 151469c34e41SYakir Yang * 1515459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 151669c34e41SYakir Yang * 151769c34e41SYakir Yang * Returns: 151869c34e41SYakir Yang * Zero on success, negative errno on failure. 151969c34e41SYakir Yang */ 1520459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 152169c34e41SYakir Yang { 152269c34e41SYakir Yang struct vop *vop = to_vop(crtc); 152369c34e41SYakir Yang unsigned long jiffies_left; 152469c34e41SYakir Yang 152569c34e41SYakir Yang if (!crtc || !vop->is_enabled) 152669c34e41SYakir Yang return -ENODEV; 152769c34e41SYakir Yang 1528459b086dSJeffy Chen if (mstimeout <= 0) 152969c34e41SYakir Yang return -EINVAL; 153069c34e41SYakir Yang 153169c34e41SYakir Yang if (vop_line_flag_irq_is_enabled(vop)) 153269c34e41SYakir Yang return -EBUSY; 153369c34e41SYakir Yang 153469c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1535459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 153669c34e41SYakir Yang 153769c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 153869c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 153969c34e41SYakir Yang vop_line_flag_irq_disable(vop); 154069c34e41SYakir Yang 154169c34e41SYakir Yang if (jiffies_left == 0) { 154269c34e41SYakir Yang dev_err(vop->dev, "Timeout waiting for IRQ\n"); 154369c34e41SYakir Yang return -ETIMEDOUT; 154469c34e41SYakir Yang } 154569c34e41SYakir Yang 154669c34e41SYakir Yang return 0; 154769c34e41SYakir Yang } 1548459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 154969c34e41SYakir Yang 15502048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 15512048e328SMark Yao { 15522048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 15532048e328SMark Yao const struct vop_data *vop_data; 15542048e328SMark Yao struct drm_device *drm_dev = data; 15552048e328SMark Yao struct vop *vop; 15562048e328SMark Yao struct resource *res; 15572048e328SMark Yao size_t alloc_size; 15583ea68922SHeiko Stuebner int ret, irq; 15592048e328SMark Yao 1560a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 15612048e328SMark Yao if (!vop_data) 15622048e328SMark Yao return -ENODEV; 15632048e328SMark Yao 15642048e328SMark Yao /* Allocate vop struct and its vop_win array */ 15652048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 15662048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 15672048e328SMark Yao if (!vop) 15682048e328SMark Yao return -ENOMEM; 15692048e328SMark Yao 15702048e328SMark Yao vop->dev = dev; 15712048e328SMark Yao vop->data = vop_data; 15722048e328SMark Yao vop->drm_dev = drm_dev; 15732048e328SMark Yao dev_set_drvdata(dev, vop); 15742048e328SMark Yao 15752048e328SMark Yao vop_win_init(vop); 15762048e328SMark Yao 15772048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15782048e328SMark Yao vop->len = resource_size(res); 15792048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 15802048e328SMark Yao if (IS_ERR(vop->regs)) 15812048e328SMark Yao return PTR_ERR(vop->regs); 15822048e328SMark Yao 15832048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 15842048e328SMark Yao if (!vop->regsbak) 15852048e328SMark Yao return -ENOMEM; 15862048e328SMark Yao 15873ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 15883ea68922SHeiko Stuebner if (irq < 0) { 15892048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 15903ea68922SHeiko Stuebner return irq; 15912048e328SMark Yao } 15923ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 15932048e328SMark Yao 15942048e328SMark Yao spin_lock_init(&vop->reg_lock); 15952048e328SMark Yao spin_lock_init(&vop->irq_lock); 15962048e328SMark Yao 15972048e328SMark Yao mutex_init(&vop->vsync_mutex); 15982048e328SMark Yao 159963ebb9faSMark Yao ret = devm_request_irq(dev, vop->irq, vop_isr, 16002048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 16012048e328SMark Yao if (ret) 16022048e328SMark Yao return ret; 16032048e328SMark Yao 16042048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 16052048e328SMark Yao disable_irq(vop->irq); 16062048e328SMark Yao 16072048e328SMark Yao ret = vop_create_crtc(vop); 16082048e328SMark Yao if (ret) 16098c763c9bSSean Paul goto err_enable_irq; 16102048e328SMark Yao 16112048e328SMark Yao pm_runtime_enable(&pdev->dev); 16125182c1a5SYakir Yang 16135e570373SJeffy Chen ret = vop_initial(vop); 16145e570373SJeffy Chen if (ret < 0) { 16155e570373SJeffy Chen dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 16165e570373SJeffy Chen goto err_disable_pm_runtime; 16175e570373SJeffy Chen } 16185e570373SJeffy Chen 16192048e328SMark Yao return 0; 16208c763c9bSSean Paul 16215e570373SJeffy Chen err_disable_pm_runtime: 16225e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 16235e570373SJeffy Chen vop_destroy_crtc(vop); 16248c763c9bSSean Paul err_enable_irq: 16258c763c9bSSean Paul enable_irq(vop->irq); /* To balance out the disable_irq above */ 16268c763c9bSSean Paul return ret; 16272048e328SMark Yao } 16282048e328SMark Yao 16292048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 16302048e328SMark Yao { 16312048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 16322048e328SMark Yao 16332048e328SMark Yao pm_runtime_disable(dev); 16342048e328SMark Yao vop_destroy_crtc(vop); 1635ec6e7767SJeffy Chen 1636ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 1637ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 1638ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 16392048e328SMark Yao } 16402048e328SMark Yao 1641a67719d1SMark Yao const struct component_ops vop_component_ops = { 16422048e328SMark Yao .bind = vop_bind, 16432048e328SMark Yao .unbind = vop_unbind, 16442048e328SMark Yao }; 164554255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1646