12048e328SMark Yao /* 22048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 32048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 42048e328SMark Yao * 52048e328SMark Yao * This software is licensed under the terms of the GNU General Public 62048e328SMark Yao * License version 2, as published by the Free Software Foundation, and 72048e328SMark Yao * may be copied, distributed, and modified under those terms. 82048e328SMark Yao * 92048e328SMark Yao * This program is distributed in the hope that it will be useful, 102048e328SMark Yao * but WITHOUT ANY WARRANTY; without even the implied warranty of 112048e328SMark Yao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122048e328SMark Yao * GNU General Public License for more details. 132048e328SMark Yao */ 142048e328SMark Yao 152048e328SMark Yao #include <drm/drm.h> 162048e328SMark Yao #include <drm/drmP.h> 1763ebb9faSMark Yao #include <drm/drm_atomic.h> 182048e328SMark Yao #include <drm/drm_crtc.h> 192048e328SMark Yao #include <drm/drm_crtc_helper.h> 202048e328SMark Yao #include <drm/drm_plane_helper.h> 212048e328SMark Yao 222048e328SMark Yao #include <linux/kernel.h> 2300fe6148SPaul Gortmaker #include <linux/module.h> 242048e328SMark Yao #include <linux/platform_device.h> 252048e328SMark Yao #include <linux/clk.h> 262048e328SMark Yao #include <linux/of.h> 272048e328SMark Yao #include <linux/of_device.h> 282048e328SMark Yao #include <linux/pm_runtime.h> 292048e328SMark Yao #include <linux/component.h> 302048e328SMark Yao 312048e328SMark Yao #include <linux/reset.h> 322048e328SMark Yao #include <linux/delay.h> 332048e328SMark Yao 342048e328SMark Yao #include "rockchip_drm_drv.h" 352048e328SMark Yao #include "rockchip_drm_gem.h" 362048e328SMark Yao #include "rockchip_drm_fb.h" 372048e328SMark Yao #include "rockchip_drm_vop.h" 382048e328SMark Yao 392048e328SMark Yao #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 402048e328SMark Yao vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 412048e328SMark Yao #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 422048e328SMark Yao vop_mask_write(x, off, (mask) << shift, (v) << shift) 432048e328SMark Yao 442048e328SMark Yao #define REG_SET(x, base, reg, v, mode) \ 452048e328SMark Yao __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 46c7647f86SJohn Keeping #define REG_SET_MASK(x, base, reg, mask, v, mode) \ 47c7647f86SJohn Keeping __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) 482048e328SMark Yao 492048e328SMark Yao #define VOP_WIN_SET(x, win, name, v) \ 502048e328SMark Yao REG_SET(x, win->base, win->phy->name, v, RELAXED) 514c156c21SMark Yao #define VOP_SCL_SET(x, win, name, v) \ 524c156c21SMark Yao REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 531194fffbSMark Yao #define VOP_SCL_SET_EXT(x, win, name, v) \ 541194fffbSMark Yao REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) 552048e328SMark Yao #define VOP_CTRL_SET(x, name, v) \ 562048e328SMark Yao REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 572048e328SMark Yao 58dbb3d944SMark Yao #define VOP_INTR_GET(vop, name) \ 59dbb3d944SMark Yao vop_read_reg(vop, 0, &vop->data->ctrl->name) 60dbb3d944SMark Yao 61c7647f86SJohn Keeping #define VOP_INTR_SET(vop, name, mask, v) \ 62c7647f86SJohn Keeping REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) 63dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 64dbb3d944SMark Yao do { \ 65c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 66dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 67c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 68dbb3d944SMark Yao reg |= (v) << i; \ 69c7647f86SJohn Keeping mask |= 1 << i; \ 70dbb3d944SMark Yao } \ 71c7647f86SJohn Keeping } \ 72c7647f86SJohn Keeping VOP_INTR_SET(vop, name, mask, reg); \ 73dbb3d944SMark Yao } while (0) 74dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 75dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 76dbb3d944SMark Yao 772048e328SMark Yao #define VOP_WIN_GET(x, win, name) \ 782048e328SMark Yao vop_read_reg(x, win->base, &win->phy->name) 792048e328SMark Yao 802048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 812048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 822048e328SMark Yao 832048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 842048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 8563ebb9faSMark Yao #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) 862048e328SMark Yao 8763ebb9faSMark Yao struct vop_plane_state { 8863ebb9faSMark Yao struct drm_plane_state base; 8963ebb9faSMark Yao int format; 9063ebb9faSMark Yao struct drm_rect src; 9163ebb9faSMark Yao struct drm_rect dest; 922048e328SMark Yao dma_addr_t yrgb_mst; 9363ebb9faSMark Yao bool enable; 942048e328SMark Yao }; 952048e328SMark Yao 962048e328SMark Yao struct vop_win { 972048e328SMark Yao struct drm_plane base; 982048e328SMark Yao const struct vop_win_data *data; 992048e328SMark Yao struct vop *vop; 1002048e328SMark Yao 10163ebb9faSMark Yao struct vop_plane_state state; 1022048e328SMark Yao }; 1032048e328SMark Yao 1042048e328SMark Yao struct vop { 1052048e328SMark Yao struct drm_crtc crtc; 1062048e328SMark Yao struct device *dev; 1072048e328SMark Yao struct drm_device *drm_dev; 10831e980c5SMark Yao bool is_enabled; 1092048e328SMark Yao 1102048e328SMark Yao /* mutex vsync_ work */ 1112048e328SMark Yao struct mutex vsync_mutex; 1122048e328SMark Yao bool vsync_work_pending; 1131067219bSMark Yao struct completion dsp_hold_completion; 11463ebb9faSMark Yao struct completion wait_update_complete; 11563ebb9faSMark Yao struct drm_pending_vblank_event *event; 1162048e328SMark Yao 1172048e328SMark Yao const struct vop_data *data; 1182048e328SMark Yao 1192048e328SMark Yao uint32_t *regsbak; 1202048e328SMark Yao void __iomem *regs; 1212048e328SMark Yao 1222048e328SMark Yao /* physical map length of vop register */ 1232048e328SMark Yao uint32_t len; 1242048e328SMark Yao 1252048e328SMark Yao /* one time only one process allowed to config the register */ 1262048e328SMark Yao spinlock_t reg_lock; 1272048e328SMark Yao /* lock vop irq reg */ 1282048e328SMark Yao spinlock_t irq_lock; 1292048e328SMark Yao 1302048e328SMark Yao unsigned int irq; 1312048e328SMark Yao 1322048e328SMark Yao /* vop AHP clk */ 1332048e328SMark Yao struct clk *hclk; 1342048e328SMark Yao /* vop dclk */ 1352048e328SMark Yao struct clk *dclk; 1362048e328SMark Yao /* vop share memory frequency */ 1372048e328SMark Yao struct clk *aclk; 1382048e328SMark Yao 1392048e328SMark Yao /* vop dclk reset */ 1402048e328SMark Yao struct reset_control *dclk_rst; 1412048e328SMark Yao 1422048e328SMark Yao struct vop_win win[]; 1432048e328SMark Yao }; 1442048e328SMark Yao 1452048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1462048e328SMark Yao { 1472048e328SMark Yao writel(v, vop->regs + offset); 1482048e328SMark Yao vop->regsbak[offset >> 2] = v; 1492048e328SMark Yao } 1502048e328SMark Yao 1512048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1522048e328SMark Yao { 1532048e328SMark Yao return readl(vop->regs + offset); 1542048e328SMark Yao } 1552048e328SMark Yao 1562048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1572048e328SMark Yao const struct vop_reg *reg) 1582048e328SMark Yao { 1592048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1602048e328SMark Yao } 1612048e328SMark Yao 1622048e328SMark Yao static inline void vop_mask_write(struct vop *vop, uint32_t offset, 1632048e328SMark Yao uint32_t mask, uint32_t v) 1642048e328SMark Yao { 1652048e328SMark Yao if (mask) { 1662048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1672048e328SMark Yao 1682048e328SMark Yao cached_val = (cached_val & ~mask) | v; 1692048e328SMark Yao writel(cached_val, vop->regs + offset); 1702048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 1712048e328SMark Yao } 1722048e328SMark Yao } 1732048e328SMark Yao 1742048e328SMark Yao static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 1752048e328SMark Yao uint32_t mask, uint32_t v) 1762048e328SMark Yao { 1772048e328SMark Yao if (mask) { 1782048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 1792048e328SMark Yao 1802048e328SMark Yao cached_val = (cached_val & ~mask) | v; 1812048e328SMark Yao writel_relaxed(cached_val, vop->regs + offset); 1822048e328SMark Yao vop->regsbak[offset >> 2] = cached_val; 1832048e328SMark Yao } 1842048e328SMark Yao } 1852048e328SMark Yao 186dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 187dbb3d944SMark Yao const struct vop_reg *reg, int type) 188dbb3d944SMark Yao { 189dbb3d944SMark Yao uint32_t i, ret = 0; 190dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 191dbb3d944SMark Yao 192dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 193dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 194dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 195dbb3d944SMark Yao } 196dbb3d944SMark Yao 197dbb3d944SMark Yao return ret; 198dbb3d944SMark Yao } 199dbb3d944SMark Yao 2000cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2010cf33fe3SMark Yao { 2020cf33fe3SMark Yao VOP_CTRL_SET(vop, cfg_done, 1); 2030cf33fe3SMark Yao } 2040cf33fe3SMark Yao 20585a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 20685a359f2STomasz Figa { 20785a359f2STomasz Figa switch (format) { 20885a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 20985a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 21085a359f2STomasz Figa case DRM_FORMAT_BGR888: 21185a359f2STomasz Figa case DRM_FORMAT_BGR565: 21285a359f2STomasz Figa return true; 21385a359f2STomasz Figa default: 21485a359f2STomasz Figa return false; 21585a359f2STomasz Figa } 21685a359f2STomasz Figa } 21785a359f2STomasz Figa 2182048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2192048e328SMark Yao { 2202048e328SMark Yao switch (format) { 2212048e328SMark Yao case DRM_FORMAT_XRGB8888: 2222048e328SMark Yao case DRM_FORMAT_ARGB8888: 22385a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 22485a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2252048e328SMark Yao return VOP_FMT_ARGB8888; 2262048e328SMark Yao case DRM_FORMAT_RGB888: 22785a359f2STomasz Figa case DRM_FORMAT_BGR888: 2282048e328SMark Yao return VOP_FMT_RGB888; 2292048e328SMark Yao case DRM_FORMAT_RGB565: 23085a359f2STomasz Figa case DRM_FORMAT_BGR565: 2312048e328SMark Yao return VOP_FMT_RGB565; 2322048e328SMark Yao case DRM_FORMAT_NV12: 2332048e328SMark Yao return VOP_FMT_YUV420SP; 2342048e328SMark Yao case DRM_FORMAT_NV16: 2352048e328SMark Yao return VOP_FMT_YUV422SP; 2362048e328SMark Yao case DRM_FORMAT_NV24: 2372048e328SMark Yao return VOP_FMT_YUV444SP; 2382048e328SMark Yao default: 2392048e328SMark Yao DRM_ERROR("unsupport format[%08x]\n", format); 2402048e328SMark Yao return -EINVAL; 2412048e328SMark Yao } 2422048e328SMark Yao } 2432048e328SMark Yao 24484c7f8caSMark Yao static bool is_yuv_support(uint32_t format) 24584c7f8caSMark Yao { 24684c7f8caSMark Yao switch (format) { 24784c7f8caSMark Yao case DRM_FORMAT_NV12: 24884c7f8caSMark Yao case DRM_FORMAT_NV16: 24984c7f8caSMark Yao case DRM_FORMAT_NV24: 25084c7f8caSMark Yao return true; 25184c7f8caSMark Yao default: 25284c7f8caSMark Yao return false; 25384c7f8caSMark Yao } 25484c7f8caSMark Yao } 25584c7f8caSMark Yao 2562048e328SMark Yao static bool is_alpha_support(uint32_t format) 2572048e328SMark Yao { 2582048e328SMark Yao switch (format) { 2592048e328SMark Yao case DRM_FORMAT_ARGB8888: 26085a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2612048e328SMark Yao return true; 2622048e328SMark Yao default: 2632048e328SMark Yao return false; 2642048e328SMark Yao } 2652048e328SMark Yao } 2662048e328SMark Yao 2674c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2684c156c21SMark Yao uint32_t dst, bool is_horizontal, 2694c156c21SMark Yao int vsu_mode, int *vskiplines) 2704c156c21SMark Yao { 2714c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2724c156c21SMark Yao 2734c156c21SMark Yao if (is_horizontal) { 2744c156c21SMark Yao if (mode == SCALE_UP) 2754c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2764c156c21SMark Yao else if (mode == SCALE_DOWN) 2774c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2784c156c21SMark Yao } else { 2794c156c21SMark Yao if (mode == SCALE_UP) { 2804c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2814c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2824c156c21SMark Yao else 2834c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2844c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2854c156c21SMark Yao if (vskiplines) { 2864c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 2874c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 2884c156c21SMark Yao *vskiplines); 2894c156c21SMark Yao } else { 2904c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2914c156c21SMark Yao } 2924c156c21SMark Yao } 2934c156c21SMark Yao } 2944c156c21SMark Yao 2954c156c21SMark Yao return val; 2964c156c21SMark Yao } 2974c156c21SMark Yao 2984c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 2994c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3004c156c21SMark Yao uint32_t dst_h, uint32_t pixel_format) 3014c156c21SMark Yao { 3024c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3034c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3044c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 3054c156c21SMark Yao int hsub = drm_format_horz_chroma_subsampling(pixel_format); 3064c156c21SMark Yao int vsub = drm_format_vert_chroma_subsampling(pixel_format); 3074c156c21SMark Yao bool is_yuv = is_yuv_support(pixel_format); 3084c156c21SMark Yao uint16_t cbcr_src_w = src_w / hsub; 3094c156c21SMark Yao uint16_t cbcr_src_h = src_h / vsub; 3104c156c21SMark Yao uint16_t vsu_mode; 3114c156c21SMark Yao uint16_t lb_mode; 3124c156c21SMark Yao uint32_t val; 3134c156c21SMark Yao int vskiplines; 3144c156c21SMark Yao 3154c156c21SMark Yao if (dst_w > 3840) { 3164c156c21SMark Yao DRM_ERROR("Maximum destination width (3840) exceeded\n"); 3174c156c21SMark Yao return; 3184c156c21SMark Yao } 3194c156c21SMark Yao 3201194fffbSMark Yao if (!win->phy->scl->ext) { 3211194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3221194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3231194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3241194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3251194fffbSMark Yao if (is_yuv) { 3261194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 3271194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3281194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 3291194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3301194fffbSMark Yao } 3311194fffbSMark Yao return; 3321194fffbSMark Yao } 3331194fffbSMark Yao 3344c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3354c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3364c156c21SMark Yao 3374c156c21SMark Yao if (is_yuv) { 3384c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3394c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3404c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3414c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3424c156c21SMark Yao else 3434c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3444c156c21SMark Yao } else { 3454c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3464c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3474c156c21SMark Yao else 3484c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3494c156c21SMark Yao } 3504c156c21SMark Yao 3511194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3524c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3534c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 3544c156c21SMark Yao DRM_ERROR("ERROR : not allow yrgb ver scale\n"); 3554c156c21SMark Yao return; 3564c156c21SMark Yao } 3574c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 3584c156c21SMark Yao DRM_ERROR("ERROR : not allow cbcr ver scale\n"); 3594c156c21SMark Yao return; 3604c156c21SMark Yao } 3614c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3624c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3634c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3644c156c21SMark Yao } else { 3654c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3664c156c21SMark Yao } 3674c156c21SMark Yao 3684c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3694c156c21SMark Yao true, 0, NULL); 3704c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3714c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3724c156c21SMark Yao false, vsu_mode, &vskiplines); 3734c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3744c156c21SMark Yao 3751194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3761194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3774c156c21SMark Yao 3781194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3791194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3801194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3811194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3821194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3834c156c21SMark Yao if (is_yuv) { 3844c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3854c156c21SMark Yao dst_w, true, 0, NULL); 3864c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 3874c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 3884c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 3894c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 3904c156c21SMark Yao 3911194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 3921194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 3931194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 3941194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 3951194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 3961194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 3971194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 3984c156c21SMark Yao } 3994c156c21SMark Yao } 4004c156c21SMark Yao 4011067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4021067219bSMark Yao { 4031067219bSMark Yao unsigned long flags; 4041067219bSMark Yao 4051067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4061067219bSMark Yao return; 4071067219bSMark Yao 4081067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4091067219bSMark Yao 410dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4111067219bSMark Yao 4121067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4131067219bSMark Yao } 4141067219bSMark Yao 4151067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4161067219bSMark Yao { 4171067219bSMark Yao unsigned long flags; 4181067219bSMark Yao 4191067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4201067219bSMark Yao return; 4211067219bSMark Yao 4221067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4231067219bSMark Yao 424dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4251067219bSMark Yao 4261067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4271067219bSMark Yao } 4281067219bSMark Yao 42963ebb9faSMark Yao static void vop_enable(struct drm_crtc *crtc) 4302048e328SMark Yao { 4312048e328SMark Yao struct vop *vop = to_vop(crtc); 4322048e328SMark Yao int ret; 4332048e328SMark Yao 43431e980c5SMark Yao if (vop->is_enabled) 43531e980c5SMark Yao return; 43631e980c5SMark Yao 4375d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 4385d82d1a7SMark Yao if (ret < 0) { 4395d82d1a7SMark Yao dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 4405d82d1a7SMark Yao return; 4415d82d1a7SMark Yao } 4425d82d1a7SMark Yao 4432048e328SMark Yao ret = clk_enable(vop->hclk); 4442048e328SMark Yao if (ret < 0) { 4452048e328SMark Yao dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 4462048e328SMark Yao return; 4472048e328SMark Yao } 4482048e328SMark Yao 4492048e328SMark Yao ret = clk_enable(vop->dclk); 4502048e328SMark Yao if (ret < 0) { 4512048e328SMark Yao dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 4522048e328SMark Yao goto err_disable_hclk; 4532048e328SMark Yao } 4542048e328SMark Yao 4552048e328SMark Yao ret = clk_enable(vop->aclk); 4562048e328SMark Yao if (ret < 0) { 4572048e328SMark Yao dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 4582048e328SMark Yao goto err_disable_dclk; 4592048e328SMark Yao } 4602048e328SMark Yao 4612048e328SMark Yao /* 4622048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 4632048e328SMark Yao * automatically with this master device via common driver code. 4642048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 4652048e328SMark Yao * mapping. 4662048e328SMark Yao */ 4672048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 4682048e328SMark Yao if (ret) { 4692048e328SMark Yao dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 4702048e328SMark Yao goto err_disable_aclk; 4712048e328SMark Yao } 4722048e328SMark Yao 47377faa161SMark Yao memcpy(vop->regs, vop->regsbak, vop->len); 47452ab7891SMark Yao /* 47552ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 47652ab7891SMark Yao */ 47752ab7891SMark Yao vop->is_enabled = true; 47852ab7891SMark Yao 4792048e328SMark Yao spin_lock(&vop->reg_lock); 4802048e328SMark Yao 4812048e328SMark Yao VOP_CTRL_SET(vop, standby, 0); 4822048e328SMark Yao 4832048e328SMark Yao spin_unlock(&vop->reg_lock); 4842048e328SMark Yao 4852048e328SMark Yao enable_irq(vop->irq); 4862048e328SMark Yao 487b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 4882048e328SMark Yao 4892048e328SMark Yao return; 4902048e328SMark Yao 4912048e328SMark Yao err_disable_aclk: 4922048e328SMark Yao clk_disable(vop->aclk); 4932048e328SMark Yao err_disable_dclk: 4942048e328SMark Yao clk_disable(vop->dclk); 4952048e328SMark Yao err_disable_hclk: 4962048e328SMark Yao clk_disable(vop->hclk); 4972048e328SMark Yao } 4982048e328SMark Yao 4990ad3675dSMark Yao static void vop_crtc_disable(struct drm_crtc *crtc) 5002048e328SMark Yao { 5012048e328SMark Yao struct vop *vop = to_vop(crtc); 5023ed6c649STomeu Vizoso int i; 5032048e328SMark Yao 50431e980c5SMark Yao if (!vop->is_enabled) 50531e980c5SMark Yao return; 50631e980c5SMark Yao 5073ed6c649STomeu Vizoso /* 5083ed6c649STomeu Vizoso * We need to make sure that all windows are disabled before we 5093ed6c649STomeu Vizoso * disable that crtc. Otherwise we might try to scan from a destroyed 5103ed6c649STomeu Vizoso * buffer later. 5113ed6c649STomeu Vizoso */ 5123ed6c649STomeu Vizoso for (i = 0; i < vop->data->win_size; i++) { 5133ed6c649STomeu Vizoso struct vop_win *vop_win = &vop->win[i]; 5143ed6c649STomeu Vizoso const struct vop_win_data *win = vop_win->data; 5153ed6c649STomeu Vizoso 5163ed6c649STomeu Vizoso spin_lock(&vop->reg_lock); 5173ed6c649STomeu Vizoso VOP_WIN_SET(vop, win, enable, 0); 5183ed6c649STomeu Vizoso spin_unlock(&vop->reg_lock); 5193ed6c649STomeu Vizoso } 5203ed6c649STomeu Vizoso 521b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 5222048e328SMark Yao 5232048e328SMark Yao /* 5241067219bSMark Yao * Vop standby will take effect at end of current frame, 5251067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 5261067219bSMark Yao * 5271067219bSMark Yao * we must wait standby complete when we want to disable aclk, 5281067219bSMark Yao * if not, memory bus maybe dead. 5292048e328SMark Yao */ 5301067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 5311067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 5321067219bSMark Yao 5332048e328SMark Yao spin_lock(&vop->reg_lock); 5342048e328SMark Yao 5352048e328SMark Yao VOP_CTRL_SET(vop, standby, 1); 5362048e328SMark Yao 5372048e328SMark Yao spin_unlock(&vop->reg_lock); 53852ab7891SMark Yao 5391067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 5402048e328SMark Yao 5411067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 5421067219bSMark Yao 5431067219bSMark Yao disable_irq(vop->irq); 5441067219bSMark Yao 5451067219bSMark Yao vop->is_enabled = false; 5461067219bSMark Yao 5471067219bSMark Yao /* 5481067219bSMark Yao * vop standby complete, so iommu detach is safe. 5491067219bSMark Yao */ 5502048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 5512048e328SMark Yao 5521067219bSMark Yao clk_disable(vop->dclk); 5532048e328SMark Yao clk_disable(vop->aclk); 5542048e328SMark Yao clk_disable(vop->hclk); 5555d82d1a7SMark Yao pm_runtime_put(vop->dev); 5562048e328SMark Yao } 5572048e328SMark Yao 55863ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 5592048e328SMark Yao { 56063ebb9faSMark Yao drm_plane_cleanup(plane); 5612048e328SMark Yao } 5622048e328SMark Yao 56344d0237aSMark Yao static int vop_plane_prepare_fb(struct drm_plane *plane, 56444d0237aSMark Yao const struct drm_plane_state *new_state) 56544d0237aSMark Yao { 56644d0237aSMark Yao if (plane->state->fb) 56744d0237aSMark Yao drm_framebuffer_reference(plane->state->fb); 56844d0237aSMark Yao 56944d0237aSMark Yao return 0; 57044d0237aSMark Yao } 57144d0237aSMark Yao 57244d0237aSMark Yao static void vop_plane_cleanup_fb(struct drm_plane *plane, 57344d0237aSMark Yao const struct drm_plane_state *old_state) 57444d0237aSMark Yao { 57544d0237aSMark Yao if (old_state->fb) 57644d0237aSMark Yao drm_framebuffer_unreference(old_state->fb); 57744d0237aSMark Yao } 57844d0237aSMark Yao 57963ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 58063ebb9faSMark Yao struct drm_plane_state *state) 5812048e328SMark Yao { 58263ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 58392915da6SJohn Keeping struct drm_crtc_state *crtc_state; 58463ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 5852048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 58663ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 5872048e328SMark Yao const struct vop_win_data *win = vop_win->data; 5882048e328SMark Yao bool visible; 5892048e328SMark Yao int ret; 59063ebb9faSMark Yao struct drm_rect *dest = &vop_plane_state->dest; 59163ebb9faSMark Yao struct drm_rect *src = &vop_plane_state->src; 59263ebb9faSMark Yao struct drm_rect clip; 5934c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 5944c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 5954c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 5964c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 5972048e328SMark Yao 59863ebb9faSMark Yao if (!crtc || !fb) 59963ebb9faSMark Yao goto out_disable; 60092915da6SJohn Keeping 60192915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 60292915da6SJohn Keeping if (WARN_ON(!crtc_state)) 60392915da6SJohn Keeping return -EINVAL; 60492915da6SJohn Keeping 60563ebb9faSMark Yao src->x1 = state->src_x; 60663ebb9faSMark Yao src->y1 = state->src_y; 60763ebb9faSMark Yao src->x2 = state->src_x + state->src_w; 60863ebb9faSMark Yao src->y2 = state->src_y + state->src_h; 60963ebb9faSMark Yao dest->x1 = state->crtc_x; 61063ebb9faSMark Yao dest->y1 = state->crtc_y; 61163ebb9faSMark Yao dest->x2 = state->crtc_x + state->crtc_w; 61263ebb9faSMark Yao dest->y2 = state->crtc_y + state->crtc_h; 61363ebb9faSMark Yao 61463ebb9faSMark Yao clip.x1 = 0; 61563ebb9faSMark Yao clip.y1 = 0; 61692915da6SJohn Keeping clip.x2 = crtc_state->adjusted_mode.hdisplay; 61792915da6SJohn Keeping clip.y2 = crtc_state->adjusted_mode.vdisplay; 61863ebb9faSMark Yao 61963ebb9faSMark Yao ret = drm_plane_helper_check_update(plane, crtc, state->fb, 62063ebb9faSMark Yao src, dest, &clip, 6214c156c21SMark Yao min_scale, 6224c156c21SMark Yao max_scale, 62363ebb9faSMark Yao true, true, &visible); 6242048e328SMark Yao if (ret) 6252048e328SMark Yao return ret; 6262048e328SMark Yao 6272048e328SMark Yao if (!visible) 62863ebb9faSMark Yao goto out_disable; 6292048e328SMark Yao 63063ebb9faSMark Yao vop_plane_state->format = vop_convert_format(fb->pixel_format); 63163ebb9faSMark Yao if (vop_plane_state->format < 0) 63263ebb9faSMark Yao return vop_plane_state->format; 63384c7f8caSMark Yao 63484c7f8caSMark Yao /* 63584c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 63684c7f8caSMark Yao * need align with 2 pixel. 63784c7f8caSMark Yao */ 63863ebb9faSMark Yao if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) 63963ebb9faSMark Yao return -EINVAL; 64063ebb9faSMark Yao 64163ebb9faSMark Yao vop_plane_state->enable = true; 64263ebb9faSMark Yao 64363ebb9faSMark Yao return 0; 64463ebb9faSMark Yao 64563ebb9faSMark Yao out_disable: 64663ebb9faSMark Yao vop_plane_state->enable = false; 64763ebb9faSMark Yao return 0; 64884c7f8caSMark Yao } 64984c7f8caSMark Yao 65063ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 65163ebb9faSMark Yao struct drm_plane_state *old_state) 65263ebb9faSMark Yao { 65363ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); 65463ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 65563ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 65663ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 6572048e328SMark Yao 65863ebb9faSMark Yao if (!old_state->crtc) 65963ebb9faSMark Yao return; 6602048e328SMark Yao 66163ebb9faSMark Yao spin_lock(&vop->reg_lock); 6622048e328SMark Yao 66363ebb9faSMark Yao VOP_WIN_SET(vop, win, enable, 0); 6642048e328SMark Yao 66563ebb9faSMark Yao spin_unlock(&vop->reg_lock); 66663ebb9faSMark Yao 66763ebb9faSMark Yao vop_plane_state->enable = false; 66863ebb9faSMark Yao } 66963ebb9faSMark Yao 67063ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 67163ebb9faSMark Yao struct drm_plane_state *old_state) 67263ebb9faSMark Yao { 67363ebb9faSMark Yao struct drm_plane_state *state = plane->state; 67463ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 67563ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 67663ebb9faSMark Yao struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 67763ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 67863ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 67963ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 68063ebb9faSMark Yao unsigned int actual_w, actual_h; 68163ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 68263ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 68363ebb9faSMark Yao struct drm_rect *src = &vop_plane_state->src; 68463ebb9faSMark Yao struct drm_rect *dest = &vop_plane_state->dest; 68563ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 68663ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 68763ebb9faSMark Yao unsigned long offset; 68863ebb9faSMark Yao dma_addr_t dma_addr; 68963ebb9faSMark Yao uint32_t val; 69063ebb9faSMark Yao bool rb_swap; 69163ebb9faSMark Yao 69263ebb9faSMark Yao /* 69363ebb9faSMark Yao * can't update plane when vop is disabled. 69463ebb9faSMark Yao */ 69563ebb9faSMark Yao if (!crtc) 69663ebb9faSMark Yao return; 69763ebb9faSMark Yao 69863ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 69963ebb9faSMark Yao return; 70063ebb9faSMark Yao 70163ebb9faSMark Yao if (!vop_plane_state->enable) { 70263ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 70363ebb9faSMark Yao return; 70463ebb9faSMark Yao } 70563ebb9faSMark Yao 70663ebb9faSMark Yao obj = rockchip_fb_get_gem_obj(fb, 0); 70763ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 70863ebb9faSMark Yao 70963ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 71063ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 71163ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 71263ebb9faSMark Yao 71363ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 71463ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 71563ebb9faSMark Yao 71663ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 71763ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 71863ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 71963ebb9faSMark Yao 72063ebb9faSMark Yao offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 72163ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 72263ebb9faSMark Yao vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 72363ebb9faSMark Yao 72463ebb9faSMark Yao spin_lock(&vop->reg_lock); 72563ebb9faSMark Yao 72663ebb9faSMark Yao VOP_WIN_SET(vop, win, format, vop_plane_state->format); 72763ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 72863ebb9faSMark Yao VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); 72963ebb9faSMark Yao if (is_yuv_support(fb->pixel_format)) { 73084c7f8caSMark Yao int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 73184c7f8caSMark Yao int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 73284c7f8caSMark Yao int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 73384c7f8caSMark Yao 73484c7f8caSMark Yao uv_obj = rockchip_fb_get_gem_obj(fb, 1); 73584c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 73684c7f8caSMark Yao 73763ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 73863ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 73984c7f8caSMark Yao 74063ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 74163ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 74263ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 74384c7f8caSMark Yao } 7444c156c21SMark Yao 7454c156c21SMark Yao if (win->phy->scl) 7464c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 74763ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 7484c156c21SMark Yao fb->pixel_format); 7494c156c21SMark Yao 75063ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 75163ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 75263ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 7534c156c21SMark Yao 75463ebb9faSMark Yao rb_swap = has_rb_swapped(fb->pixel_format); 75585a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 7562048e328SMark Yao 75763ebb9faSMark Yao if (is_alpha_support(fb->pixel_format)) { 7582048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 7592048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 7602048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 7612048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 7622048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 7632048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 7642048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 7652048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 7662048e328SMark Yao } else { 7672048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 7682048e328SMark Yao } 7692048e328SMark Yao 7702048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 7712048e328SMark Yao spin_unlock(&vop->reg_lock); 7722048e328SMark Yao } 7732048e328SMark Yao 77463ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 77544d0237aSMark Yao .prepare_fb = vop_plane_prepare_fb, 77644d0237aSMark Yao .cleanup_fb = vop_plane_cleanup_fb, 77763ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 77863ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 77963ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 78063ebb9faSMark Yao }; 78163ebb9faSMark Yao 78263ebb9faSMark Yao void vop_atomic_plane_reset(struct drm_plane *plane) 7832048e328SMark Yao { 78463ebb9faSMark Yao struct vop_plane_state *vop_plane_state = 78563ebb9faSMark Yao to_vop_plane_state(plane->state); 78663ebb9faSMark Yao 78763ebb9faSMark Yao if (plane->state && plane->state->fb) 78863ebb9faSMark Yao drm_framebuffer_unreference(plane->state->fb); 78963ebb9faSMark Yao 79063ebb9faSMark Yao kfree(vop_plane_state); 79163ebb9faSMark Yao vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); 79263ebb9faSMark Yao if (!vop_plane_state) 79363ebb9faSMark Yao return; 79463ebb9faSMark Yao 79563ebb9faSMark Yao plane->state = &vop_plane_state->base; 79663ebb9faSMark Yao plane->state->plane = plane; 7972048e328SMark Yao } 7982048e328SMark Yao 79963ebb9faSMark Yao struct drm_plane_state * 80063ebb9faSMark Yao vop_atomic_plane_duplicate_state(struct drm_plane *plane) 8012048e328SMark Yao { 80263ebb9faSMark Yao struct vop_plane_state *old_vop_plane_state; 80363ebb9faSMark Yao struct vop_plane_state *vop_plane_state; 8042048e328SMark Yao 80563ebb9faSMark Yao if (WARN_ON(!plane->state)) 80663ebb9faSMark Yao return NULL; 8072048e328SMark Yao 80863ebb9faSMark Yao old_vop_plane_state = to_vop_plane_state(plane->state); 80963ebb9faSMark Yao vop_plane_state = kmemdup(old_vop_plane_state, 81063ebb9faSMark Yao sizeof(*vop_plane_state), GFP_KERNEL); 81163ebb9faSMark Yao if (!vop_plane_state) 81263ebb9faSMark Yao return NULL; 81363ebb9faSMark Yao 81463ebb9faSMark Yao __drm_atomic_helper_plane_duplicate_state(plane, 81563ebb9faSMark Yao &vop_plane_state->base); 81663ebb9faSMark Yao 81763ebb9faSMark Yao return &vop_plane_state->base; 8182048e328SMark Yao } 8192048e328SMark Yao 82063ebb9faSMark Yao static void vop_atomic_plane_destroy_state(struct drm_plane *plane, 82163ebb9faSMark Yao struct drm_plane_state *state) 8222048e328SMark Yao { 82363ebb9faSMark Yao struct vop_plane_state *vop_state = to_vop_plane_state(state); 8242048e328SMark Yao 82563ebb9faSMark Yao __drm_atomic_helper_plane_destroy_state(plane, state); 8262048e328SMark Yao 82763ebb9faSMark Yao kfree(vop_state); 8282048e328SMark Yao } 8292048e328SMark Yao 8302048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 83163ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 83263ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 8332048e328SMark Yao .destroy = vop_plane_destroy, 83463ebb9faSMark Yao .reset = vop_atomic_plane_reset, 83563ebb9faSMark Yao .atomic_duplicate_state = vop_atomic_plane_duplicate_state, 83663ebb9faSMark Yao .atomic_destroy_state = vop_atomic_plane_destroy_state, 8372048e328SMark Yao }; 8382048e328SMark Yao 8392048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 8402048e328SMark Yao { 8412048e328SMark Yao struct vop *vop = to_vop(crtc); 8422048e328SMark Yao unsigned long flags; 8432048e328SMark Yao 84463ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8452048e328SMark Yao return -EPERM; 8462048e328SMark Yao 8472048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 8482048e328SMark Yao 849dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 8502048e328SMark Yao 8512048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8522048e328SMark Yao 8532048e328SMark Yao return 0; 8542048e328SMark Yao } 8552048e328SMark Yao 8562048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 8572048e328SMark Yao { 8582048e328SMark Yao struct vop *vop = to_vop(crtc); 8592048e328SMark Yao unsigned long flags; 8602048e328SMark Yao 86163ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 8622048e328SMark Yao return; 86331e980c5SMark Yao 8642048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 865dbb3d944SMark Yao 866dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 867dbb3d944SMark Yao 8682048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 8692048e328SMark Yao } 8702048e328SMark Yao 87163ebb9faSMark Yao static void vop_crtc_wait_for_update(struct drm_crtc *crtc) 87263ebb9faSMark Yao { 87363ebb9faSMark Yao struct vop *vop = to_vop(crtc); 87463ebb9faSMark Yao 87563ebb9faSMark Yao reinit_completion(&vop->wait_update_complete); 87663ebb9faSMark Yao WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); 87763ebb9faSMark Yao } 87863ebb9faSMark Yao 879f135046eSJohn Keeping static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc, 880f135046eSJohn Keeping struct drm_file *file_priv) 881f135046eSJohn Keeping { 882f135046eSJohn Keeping struct drm_device *drm = crtc->dev; 883f135046eSJohn Keeping struct vop *vop = to_vop(crtc); 884f135046eSJohn Keeping struct drm_pending_vblank_event *e; 885f135046eSJohn Keeping unsigned long flags; 886f135046eSJohn Keeping 887f135046eSJohn Keeping spin_lock_irqsave(&drm->event_lock, flags); 888f135046eSJohn Keeping e = vop->event; 889f135046eSJohn Keeping if (e && e->base.file_priv == file_priv) { 890f135046eSJohn Keeping vop->event = NULL; 891f135046eSJohn Keeping 892f135046eSJohn Keeping e->base.destroy(&e->base); 893f135046eSJohn Keeping file_priv->event_space += sizeof(e->event); 894f135046eSJohn Keeping } 895f135046eSJohn Keeping spin_unlock_irqrestore(&drm->event_lock, flags); 896f135046eSJohn Keeping } 897f135046eSJohn Keeping 8982048e328SMark Yao static const struct rockchip_crtc_funcs private_crtc_funcs = { 8992048e328SMark Yao .enable_vblank = vop_crtc_enable_vblank, 9002048e328SMark Yao .disable_vblank = vop_crtc_disable_vblank, 90163ebb9faSMark Yao .wait_for_update = vop_crtc_wait_for_update, 902f135046eSJohn Keeping .cancel_pending_vblank = vop_crtc_cancel_pending_vblank, 9032048e328SMark Yao }; 9042048e328SMark Yao 9052048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 9062048e328SMark Yao const struct drm_display_mode *mode, 9072048e328SMark Yao struct drm_display_mode *adjusted_mode) 9082048e328SMark Yao { 909b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 910b59b8de3SChris Zhong 911b59b8de3SChris Zhong adjusted_mode->clock = 912b59b8de3SChris Zhong clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 913b59b8de3SChris Zhong 9142048e328SMark Yao return true; 9152048e328SMark Yao } 9162048e328SMark Yao 91763ebb9faSMark Yao static void vop_crtc_enable(struct drm_crtc *crtc) 9182048e328SMark Yao { 9192048e328SMark Yao struct vop *vop = to_vop(crtc); 9204e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 92163ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 9222048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 9232048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 9242048e328SMark Yao u16 htotal = adjusted_mode->htotal; 9252048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 9262048e328SMark Yao u16 hact_end = hact_st + hdisplay; 9272048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 9282048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 9292048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 9302048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 9312048e328SMark Yao u16 vact_end = vact_st + vdisplay; 9322048e328SMark Yao uint32_t val; 9332048e328SMark Yao 93463ebb9faSMark Yao vop_enable(crtc); 9352048e328SMark Yao /* 936ce3887edSMark Yao * If dclk rate is zero, mean that scanout is stop, 937ce3887edSMark Yao * we don't need wait any more. 9382048e328SMark Yao */ 939ce3887edSMark Yao if (clk_get_rate(vop->dclk)) { 940ce3887edSMark Yao /* 941ce3887edSMark Yao * Rk3288 vop timing register is immediately, when configure 942ce3887edSMark Yao * display timing on display time, may cause tearing. 943ce3887edSMark Yao * 944ce3887edSMark Yao * Vop standby will take effect at end of current frame, 945ce3887edSMark Yao * if dsp hold valid irq happen, it means standby complete. 946ce3887edSMark Yao * 947ce3887edSMark Yao * mode set: 948ce3887edSMark Yao * standby and wait complete --> |---- 949ce3887edSMark Yao * | display time 950ce3887edSMark Yao * |---- 951ce3887edSMark Yao * |---> dsp hold irq 952ce3887edSMark Yao * configure display timing --> | 953ce3887edSMark Yao * standby exit | 954ce3887edSMark Yao * | new frame start. 955ce3887edSMark Yao */ 956ce3887edSMark Yao 957ce3887edSMark Yao reinit_completion(&vop->dsp_hold_completion); 958ce3887edSMark Yao vop_dsp_hold_valid_irq_enable(vop); 959ce3887edSMark Yao 960ce3887edSMark Yao spin_lock(&vop->reg_lock); 961ce3887edSMark Yao 962ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 1); 963ce3887edSMark Yao 964ce3887edSMark Yao spin_unlock(&vop->reg_lock); 965ce3887edSMark Yao 966ce3887edSMark Yao wait_for_completion(&vop->dsp_hold_completion); 967ce3887edSMark Yao 968ce3887edSMark Yao vop_dsp_hold_valid_irq_disable(vop); 969ce3887edSMark Yao } 9702048e328SMark Yao 9712048e328SMark Yao val = 0x8; 97244ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 97344ddb7efSMark Yao val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 9742048e328SMark Yao VOP_CTRL_SET(vop, pin_pol, val); 9754e257d9eSMark Yao switch (s->output_type) { 9764e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 9774e257d9eSMark Yao VOP_CTRL_SET(vop, rgb_en, 1); 9784e257d9eSMark Yao break; 9794e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 9804e257d9eSMark Yao VOP_CTRL_SET(vop, edp_en, 1); 9814e257d9eSMark Yao break; 9824e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 9834e257d9eSMark Yao VOP_CTRL_SET(vop, hdmi_en, 1); 9844e257d9eSMark Yao break; 9854e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 9864e257d9eSMark Yao VOP_CTRL_SET(vop, mipi_en, 1); 9874e257d9eSMark Yao break; 9884e257d9eSMark Yao default: 9894e257d9eSMark Yao DRM_ERROR("unsupport connector_type[%d]\n", s->output_type); 9904e257d9eSMark Yao } 9914e257d9eSMark Yao VOP_CTRL_SET(vop, out_mode, s->output_mode); 9922048e328SMark Yao 9932048e328SMark Yao VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 9942048e328SMark Yao val = hact_st << 16; 9952048e328SMark Yao val |= hact_end; 9962048e328SMark Yao VOP_CTRL_SET(vop, hact_st_end, val); 9972048e328SMark Yao VOP_CTRL_SET(vop, hpost_st_end, val); 9982048e328SMark Yao 9992048e328SMark Yao VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 10002048e328SMark Yao val = vact_st << 16; 10012048e328SMark Yao val |= vact_end; 10022048e328SMark Yao VOP_CTRL_SET(vop, vact_st_end, val); 10032048e328SMark Yao VOP_CTRL_SET(vop, vpost_st_end, val); 10042048e328SMark Yao 10052048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1006ce3887edSMark Yao 1007ce3887edSMark Yao VOP_CTRL_SET(vop, standby, 0); 10082048e328SMark Yao } 10092048e328SMark Yao 101063ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 101163ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 101263ebb9faSMark Yao { 101363ebb9faSMark Yao struct vop *vop = to_vop(crtc); 101463ebb9faSMark Yao 101563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 101663ebb9faSMark Yao return; 101763ebb9faSMark Yao 101863ebb9faSMark Yao spin_lock(&vop->reg_lock); 101963ebb9faSMark Yao 102063ebb9faSMark Yao vop_cfg_done(vop); 102163ebb9faSMark Yao 102263ebb9faSMark Yao spin_unlock(&vop->reg_lock); 102363ebb9faSMark Yao } 102463ebb9faSMark Yao 102563ebb9faSMark Yao static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 102663ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 102763ebb9faSMark Yao { 102863ebb9faSMark Yao struct vop *vop = to_vop(crtc); 102963ebb9faSMark Yao 103063ebb9faSMark Yao if (crtc->state->event) { 103163ebb9faSMark Yao WARN_ON(drm_crtc_vblank_get(crtc) != 0); 103263ebb9faSMark Yao 103363ebb9faSMark Yao vop->event = crtc->state->event; 103463ebb9faSMark Yao crtc->state->event = NULL; 103563ebb9faSMark Yao } 10362048e328SMark Yao } 10372048e328SMark Yao 10382048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 10390ad3675dSMark Yao .enable = vop_crtc_enable, 10400ad3675dSMark Yao .disable = vop_crtc_disable, 10412048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 104263ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 104363ebb9faSMark Yao .atomic_begin = vop_crtc_atomic_begin, 10442048e328SMark Yao }; 10452048e328SMark Yao 10462048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 10472048e328SMark Yao { 10482048e328SMark Yao drm_crtc_cleanup(crtc); 10492048e328SMark Yao } 10502048e328SMark Yao 10514e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 10524e257d9eSMark Yao { 10534e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 10544e257d9eSMark Yao 10554e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 10564e257d9eSMark Yao if (!rockchip_state) 10574e257d9eSMark Yao return NULL; 10584e257d9eSMark Yao 10594e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 10604e257d9eSMark Yao return &rockchip_state->base; 10614e257d9eSMark Yao } 10624e257d9eSMark Yao 10634e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 10644e257d9eSMark Yao struct drm_crtc_state *state) 10654e257d9eSMark Yao { 10664e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 10674e257d9eSMark Yao 10684e257d9eSMark Yao __drm_atomic_helper_crtc_destroy_state(crtc, &s->base); 10694e257d9eSMark Yao kfree(s); 10704e257d9eSMark Yao } 10714e257d9eSMark Yao 10722048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 107363ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 107463ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 10752048e328SMark Yao .destroy = vop_crtc_destroy, 107663ebb9faSMark Yao .reset = drm_atomic_helper_crtc_reset, 10774e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 10784e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 10792048e328SMark Yao }; 10802048e328SMark Yao 108163ebb9faSMark Yao static bool vop_win_pending_is_complete(struct vop_win *vop_win) 10822048e328SMark Yao { 108363ebb9faSMark Yao struct drm_plane *plane = &vop_win->base; 108463ebb9faSMark Yao struct vop_plane_state *state = to_vop_plane_state(plane->state); 10852048e328SMark Yao dma_addr_t yrgb_mst; 10862048e328SMark Yao 108763ebb9faSMark Yao if (!state->enable) 108863ebb9faSMark Yao return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; 108963ebb9faSMark Yao 10902048e328SMark Yao yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 10912048e328SMark Yao 109263ebb9faSMark Yao return yrgb_mst == state->yrgb_mst; 10932048e328SMark Yao } 10942048e328SMark Yao 109563ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 10962048e328SMark Yao { 109763ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 109863ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 109963ebb9faSMark Yao unsigned long flags; 110063ebb9faSMark Yao int i; 11012048e328SMark Yao 110263ebb9faSMark Yao for (i = 0; i < vop->data->win_size; i++) { 110363ebb9faSMark Yao if (!vop_win_pending_is_complete(&vop->win[i])) 11042048e328SMark Yao return; 11052048e328SMark Yao } 11062048e328SMark Yao 110763ebb9faSMark Yao if (vop->event) { 110863ebb9faSMark Yao spin_lock_irqsave(&drm->event_lock, flags); 11092048e328SMark Yao 111063ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 111163ebb9faSMark Yao drm_crtc_vblank_put(crtc); 111263ebb9faSMark Yao vop->event = NULL; 111363ebb9faSMark Yao 111463ebb9faSMark Yao spin_unlock_irqrestore(&drm->event_lock, flags); 11152048e328SMark Yao } 111663ebb9faSMark Yao if (!completion_done(&vop->wait_update_complete)) 111763ebb9faSMark Yao complete(&vop->wait_update_complete); 11182048e328SMark Yao } 11192048e328SMark Yao 11202048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 11212048e328SMark Yao { 11222048e328SMark Yao struct vop *vop = data; 1123b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1124dbb3d944SMark Yao uint32_t active_irqs; 11252048e328SMark Yao unsigned long flags; 11261067219bSMark Yao int ret = IRQ_NONE; 11272048e328SMark Yao 11282048e328SMark Yao /* 1129dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 11302048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 11312048e328SMark Yao */ 11322048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1133dbb3d944SMark Yao 1134dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 11352048e328SMark Yao /* Clear all active interrupt sources */ 11362048e328SMark Yao if (active_irqs) 1137dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1138dbb3d944SMark Yao 11392048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11402048e328SMark Yao 11412048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 11422048e328SMark Yao if (!active_irqs) 11432048e328SMark Yao return IRQ_NONE; 11442048e328SMark Yao 11451067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 11461067219bSMark Yao complete(&vop->dsp_hold_completion); 11471067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 11481067219bSMark Yao ret = IRQ_HANDLED; 11492048e328SMark Yao } 11502048e328SMark Yao 11511067219bSMark Yao if (active_irqs & FS_INTR) { 1152b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 115363ebb9faSMark Yao vop_handle_vblank(vop); 11541067219bSMark Yao active_irqs &= ~FS_INTR; 115563ebb9faSMark Yao ret = IRQ_HANDLED; 11561067219bSMark Yao } 11572048e328SMark Yao 11581067219bSMark Yao /* Unhandled irqs are spurious. */ 11591067219bSMark Yao if (active_irqs) 11601067219bSMark Yao DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 11611067219bSMark Yao 11621067219bSMark Yao return ret; 11632048e328SMark Yao } 11642048e328SMark Yao 11652048e328SMark Yao static int vop_create_crtc(struct vop *vop) 11662048e328SMark Yao { 11672048e328SMark Yao const struct vop_data *vop_data = vop->data; 11682048e328SMark Yao struct device *dev = vop->dev; 11692048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1170328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 11712048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 11722048e328SMark Yao struct device_node *port; 11732048e328SMark Yao int ret; 11742048e328SMark Yao int i; 11752048e328SMark Yao 11762048e328SMark Yao /* 11772048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 11782048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 11792048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 11802048e328SMark Yao */ 11812048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 11822048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 11832048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 11842048e328SMark Yao 11852048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 11862048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 11872048e328SMark Yao continue; 11882048e328SMark Yao 11892048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 11902048e328SMark Yao 0, &vop_plane_funcs, 11912048e328SMark Yao win_data->phy->data_formats, 11922048e328SMark Yao win_data->phy->nformats, 1193b0b3b795SVille Syrjälä win_data->type, NULL); 11942048e328SMark Yao if (ret) { 11952048e328SMark Yao DRM_ERROR("failed to initialize plane\n"); 11962048e328SMark Yao goto err_cleanup_planes; 11972048e328SMark Yao } 11982048e328SMark Yao 11992048e328SMark Yao plane = &vop_win->base; 120063ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 12012048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 12022048e328SMark Yao primary = plane; 12032048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 12042048e328SMark Yao cursor = plane; 12052048e328SMark Yao } 12062048e328SMark Yao 12072048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1208f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 12092048e328SMark Yao if (ret) 1210328b51c0SDouglas Anderson goto err_cleanup_planes; 12112048e328SMark Yao 12122048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 12132048e328SMark Yao 12142048e328SMark Yao /* 12152048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 12162048e328SMark Yao * to the newly created crtc. 12172048e328SMark Yao */ 12182048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 12192048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 12202048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 12212048e328SMark Yao unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 12222048e328SMark Yao 12232048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 12242048e328SMark Yao continue; 12252048e328SMark Yao 12262048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 12272048e328SMark Yao possible_crtcs, 12282048e328SMark Yao &vop_plane_funcs, 12292048e328SMark Yao win_data->phy->data_formats, 12302048e328SMark Yao win_data->phy->nformats, 1231b0b3b795SVille Syrjälä win_data->type, NULL); 12322048e328SMark Yao if (ret) { 12332048e328SMark Yao DRM_ERROR("failed to initialize overlay plane\n"); 12342048e328SMark Yao goto err_cleanup_crtc; 12352048e328SMark Yao } 123663ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 12372048e328SMark Yao } 12382048e328SMark Yao 12392048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 12402048e328SMark Yao if (!port) { 12412048e328SMark Yao DRM_ERROR("no port node found in %s\n", 12422048e328SMark Yao dev->of_node->full_name); 1243328b51c0SDouglas Anderson ret = -ENOENT; 12442048e328SMark Yao goto err_cleanup_crtc; 12452048e328SMark Yao } 12462048e328SMark Yao 12471067219bSMark Yao init_completion(&vop->dsp_hold_completion); 124863ebb9faSMark Yao init_completion(&vop->wait_update_complete); 12492048e328SMark Yao crtc->port = port; 1250b5f7b755SMark Yao rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); 12512048e328SMark Yao 12522048e328SMark Yao return 0; 12532048e328SMark Yao 12542048e328SMark Yao err_cleanup_crtc: 12552048e328SMark Yao drm_crtc_cleanup(crtc); 12562048e328SMark Yao err_cleanup_planes: 1257328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1258328b51c0SDouglas Anderson head) 12592048e328SMark Yao drm_plane_cleanup(plane); 12602048e328SMark Yao return ret; 12612048e328SMark Yao } 12622048e328SMark Yao 12632048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 12642048e328SMark Yao { 12652048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1266328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1267328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 12682048e328SMark Yao 1269b5f7b755SMark Yao rockchip_unregister_crtc_funcs(crtc); 12702048e328SMark Yao of_node_put(crtc->port); 1271328b51c0SDouglas Anderson 1272328b51c0SDouglas Anderson /* 1273328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1274328b51c0SDouglas Anderson * 1275328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1276328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1277328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1278328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1279328b51c0SDouglas Anderson */ 1280328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1281328b51c0SDouglas Anderson head) 1282328b51c0SDouglas Anderson vop_plane_destroy(plane); 1283328b51c0SDouglas Anderson 1284328b51c0SDouglas Anderson /* 1285328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1286328b51c0SDouglas Anderson * references the CRTC. 1287328b51c0SDouglas Anderson */ 12882048e328SMark Yao drm_crtc_cleanup(crtc); 12892048e328SMark Yao } 12902048e328SMark Yao 12912048e328SMark Yao static int vop_initial(struct vop *vop) 12922048e328SMark Yao { 12932048e328SMark Yao const struct vop_data *vop_data = vop->data; 12942048e328SMark Yao const struct vop_reg_data *init_table = vop_data->init_table; 12952048e328SMark Yao struct reset_control *ahb_rst; 12962048e328SMark Yao int i, ret; 12972048e328SMark Yao 12982048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 12992048e328SMark Yao if (IS_ERR(vop->hclk)) { 13002048e328SMark Yao dev_err(vop->dev, "failed to get hclk source\n"); 13012048e328SMark Yao return PTR_ERR(vop->hclk); 13022048e328SMark Yao } 13032048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 13042048e328SMark Yao if (IS_ERR(vop->aclk)) { 13052048e328SMark Yao dev_err(vop->dev, "failed to get aclk source\n"); 13062048e328SMark Yao return PTR_ERR(vop->aclk); 13072048e328SMark Yao } 13082048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 13092048e328SMark Yao if (IS_ERR(vop->dclk)) { 13102048e328SMark Yao dev_err(vop->dev, "failed to get dclk source\n"); 13112048e328SMark Yao return PTR_ERR(vop->dclk); 13122048e328SMark Yao } 13132048e328SMark Yao 13142048e328SMark Yao ret = clk_prepare(vop->dclk); 13152048e328SMark Yao if (ret < 0) { 13162048e328SMark Yao dev_err(vop->dev, "failed to prepare dclk\n"); 1317d7b53fd9SSjoerd Simons return ret; 13182048e328SMark Yao } 13192048e328SMark Yao 1320d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1321d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 13222048e328SMark Yao if (ret < 0) { 1323d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable hclk\n"); 13242048e328SMark Yao goto err_unprepare_dclk; 13252048e328SMark Yao } 13262048e328SMark Yao 1327d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 13282048e328SMark Yao if (ret < 0) { 1329d7b53fd9SSjoerd Simons dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1330d7b53fd9SSjoerd Simons goto err_disable_hclk; 13312048e328SMark Yao } 1332d7b53fd9SSjoerd Simons 13332048e328SMark Yao /* 13342048e328SMark Yao * do hclk_reset, reset all vop registers. 13352048e328SMark Yao */ 13362048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 13372048e328SMark Yao if (IS_ERR(ahb_rst)) { 13382048e328SMark Yao dev_err(vop->dev, "failed to get ahb reset\n"); 13392048e328SMark Yao ret = PTR_ERR(ahb_rst); 1340d7b53fd9SSjoerd Simons goto err_disable_aclk; 13412048e328SMark Yao } 13422048e328SMark Yao reset_control_assert(ahb_rst); 13432048e328SMark Yao usleep_range(10, 20); 13442048e328SMark Yao reset_control_deassert(ahb_rst); 13452048e328SMark Yao 13462048e328SMark Yao memcpy(vop->regsbak, vop->regs, vop->len); 13472048e328SMark Yao 13482048e328SMark Yao for (i = 0; i < vop_data->table_size; i++) 13492048e328SMark Yao vop_writel(vop, init_table[i].offset, init_table[i].value); 13502048e328SMark Yao 13512048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13522048e328SMark Yao const struct vop_win_data *win = &vop_data->win[i]; 13532048e328SMark Yao 13542048e328SMark Yao VOP_WIN_SET(vop, win, enable, 0); 13552048e328SMark Yao } 13562048e328SMark Yao 13572048e328SMark Yao vop_cfg_done(vop); 13582048e328SMark Yao 13592048e328SMark Yao /* 13602048e328SMark Yao * do dclk_reset, let all config take affect. 13612048e328SMark Yao */ 13622048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 13632048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 13642048e328SMark Yao dev_err(vop->dev, "failed to get dclk reset\n"); 13652048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1366d7b53fd9SSjoerd Simons goto err_disable_aclk; 13672048e328SMark Yao } 13682048e328SMark Yao reset_control_assert(vop->dclk_rst); 13692048e328SMark Yao usleep_range(10, 20); 13702048e328SMark Yao reset_control_deassert(vop->dclk_rst); 13712048e328SMark Yao 13722048e328SMark Yao clk_disable(vop->hclk); 1373d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 13742048e328SMark Yao 137531e980c5SMark Yao vop->is_enabled = false; 13762048e328SMark Yao 13772048e328SMark Yao return 0; 13782048e328SMark Yao 1379d7b53fd9SSjoerd Simons err_disable_aclk: 1380d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 13812048e328SMark Yao err_disable_hclk: 1382d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 13832048e328SMark Yao err_unprepare_dclk: 13842048e328SMark Yao clk_unprepare(vop->dclk); 13852048e328SMark Yao return ret; 13862048e328SMark Yao } 13872048e328SMark Yao 13882048e328SMark Yao /* 13892048e328SMark Yao * Initialize the vop->win array elements. 13902048e328SMark Yao */ 13912048e328SMark Yao static void vop_win_init(struct vop *vop) 13922048e328SMark Yao { 13932048e328SMark Yao const struct vop_data *vop_data = vop->data; 13942048e328SMark Yao unsigned int i; 13952048e328SMark Yao 13962048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 13972048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 13982048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 13992048e328SMark Yao 14002048e328SMark Yao vop_win->data = win_data; 14012048e328SMark Yao vop_win->vop = vop; 14022048e328SMark Yao } 14032048e328SMark Yao } 14042048e328SMark Yao 14052048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 14062048e328SMark Yao { 14072048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 14082048e328SMark Yao const struct vop_data *vop_data; 14092048e328SMark Yao struct drm_device *drm_dev = data; 14102048e328SMark Yao struct vop *vop; 14112048e328SMark Yao struct resource *res; 14122048e328SMark Yao size_t alloc_size; 14133ea68922SHeiko Stuebner int ret, irq; 14142048e328SMark Yao 1415a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 14162048e328SMark Yao if (!vop_data) 14172048e328SMark Yao return -ENODEV; 14182048e328SMark Yao 14192048e328SMark Yao /* Allocate vop struct and its vop_win array */ 14202048e328SMark Yao alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 14212048e328SMark Yao vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 14222048e328SMark Yao if (!vop) 14232048e328SMark Yao return -ENOMEM; 14242048e328SMark Yao 14252048e328SMark Yao vop->dev = dev; 14262048e328SMark Yao vop->data = vop_data; 14272048e328SMark Yao vop->drm_dev = drm_dev; 14282048e328SMark Yao dev_set_drvdata(dev, vop); 14292048e328SMark Yao 14302048e328SMark Yao vop_win_init(vop); 14312048e328SMark Yao 14322048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 14332048e328SMark Yao vop->len = resource_size(res); 14342048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 14352048e328SMark Yao if (IS_ERR(vop->regs)) 14362048e328SMark Yao return PTR_ERR(vop->regs); 14372048e328SMark Yao 14382048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 14392048e328SMark Yao if (!vop->regsbak) 14402048e328SMark Yao return -ENOMEM; 14412048e328SMark Yao 14422048e328SMark Yao ret = vop_initial(vop); 14432048e328SMark Yao if (ret < 0) { 14442048e328SMark Yao dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 14452048e328SMark Yao return ret; 14462048e328SMark Yao } 14472048e328SMark Yao 14483ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 14493ea68922SHeiko Stuebner if (irq < 0) { 14502048e328SMark Yao dev_err(dev, "cannot find irq for vop\n"); 14513ea68922SHeiko Stuebner return irq; 14522048e328SMark Yao } 14533ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 14542048e328SMark Yao 14552048e328SMark Yao spin_lock_init(&vop->reg_lock); 14562048e328SMark Yao spin_lock_init(&vop->irq_lock); 14572048e328SMark Yao 14582048e328SMark Yao mutex_init(&vop->vsync_mutex); 14592048e328SMark Yao 146063ebb9faSMark Yao ret = devm_request_irq(dev, vop->irq, vop_isr, 14612048e328SMark Yao IRQF_SHARED, dev_name(dev), vop); 14622048e328SMark Yao if (ret) 14632048e328SMark Yao return ret; 14642048e328SMark Yao 14652048e328SMark Yao /* IRQ is initially disabled; it gets enabled in power_on */ 14662048e328SMark Yao disable_irq(vop->irq); 14672048e328SMark Yao 14682048e328SMark Yao ret = vop_create_crtc(vop); 14692048e328SMark Yao if (ret) 14702048e328SMark Yao return ret; 14712048e328SMark Yao 14722048e328SMark Yao pm_runtime_enable(&pdev->dev); 14732048e328SMark Yao return 0; 14742048e328SMark Yao } 14752048e328SMark Yao 14762048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 14772048e328SMark Yao { 14782048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 14792048e328SMark Yao 14802048e328SMark Yao pm_runtime_disable(dev); 14812048e328SMark Yao vop_destroy_crtc(vop); 14822048e328SMark Yao } 14832048e328SMark Yao 1484a67719d1SMark Yao const struct component_ops vop_component_ops = { 14852048e328SMark Yao .bind = vop_bind, 14862048e328SMark Yao .unbind = vop_unbind, 14872048e328SMark Yao }; 148854255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 1489