19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22048e328SMark Yao /* 32048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 42048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 52048e328SMark Yao */ 62048e328SMark Yao 7c2156ccdSSam Ravnborg #include <linux/clk.h> 8c2156ccdSSam Ravnborg #include <linux/component.h> 9c2156ccdSSam Ravnborg #include <linux/delay.h> 10c2156ccdSSam Ravnborg #include <linux/iopoll.h> 11c2156ccdSSam Ravnborg #include <linux/kernel.h> 12c2156ccdSSam Ravnborg #include <linux/module.h> 13c2156ccdSSam Ravnborg #include <linux/of.h> 14c2156ccdSSam Ravnborg #include <linux/of_device.h> 15c2156ccdSSam Ravnborg #include <linux/overflow.h> 16c2156ccdSSam Ravnborg #include <linux/platform_device.h> 17c2156ccdSSam Ravnborg #include <linux/pm_runtime.h> 18c2156ccdSSam Ravnborg #include <linux/reset.h> 19c2156ccdSSam Ravnborg 202048e328SMark Yao #include <drm/drm.h> 2163ebb9faSMark Yao #include <drm/drm_atomic.h> 2215609559SEnric Balletbo i Serra #include <drm/drm_atomic_uapi.h> 232048e328SMark Yao #include <drm/drm_crtc.h> 2447a7eb45STomasz Figa #include <drm/drm_flip_work.h> 25c2156ccdSSam Ravnborg #include <drm/drm_fourcc.h> 2663d5e06aSHeiko Stuebner #include <drm/drm_gem_framebuffer_helper.h> 272048e328SMark Yao #include <drm/drm_plane_helper.h> 28fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 296c836d96SSean Paul #include <drm/drm_self_refresh_helper.h> 30c2156ccdSSam Ravnborg #include <drm/drm_vblank.h> 31c2156ccdSSam Ravnborg 326cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 333190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 346cca3869SSean Paul #endif 352048e328SMark Yao 362048e328SMark Yao #include "rockchip_drm_drv.h" 372048e328SMark Yao #include "rockchip_drm_gem.h" 382048e328SMark Yao #include "rockchip_drm_fb.h" 392048e328SMark Yao #include "rockchip_drm_vop.h" 401f0f0151SSandy Huang #include "rockchip_rgb.h" 412048e328SMark Yao 422996fb75SEzequiel Garcia #define VOP_WIN_SET(vop, win, name, v) \ 439a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 442996fb75SEzequiel Garcia #define VOP_SCL_SET(vop, win, name, v) \ 459a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 462996fb75SEzequiel Garcia #define VOP_SCL_SET_EXT(vop, win, name, v) \ 479a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 489a61c54bSMark yao win->base, ~0, v, #name) 49ac6560dfSMark yao 502996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 511c21aa8fSDaniele Castagna do { \ 521c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 531c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 541c21aa8fSDaniele Castagna } while (0) 551c21aa8fSDaniele Castagna 562996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 571c21aa8fSDaniele Castagna do { \ 581c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 591c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 601c21aa8fSDaniele Castagna } while (0) 611c21aa8fSDaniele Castagna 62ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 639a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 649a61c54bSMark yao 659a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 669a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 67ac6560dfSMark yao 68dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 69dbb3d944SMark Yao do { \ 70c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 71dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 72c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 73dbb3d944SMark Yao reg |= (v) << i; \ 74c7647f86SJohn Keeping mask |= 1 << i; \ 75dbb3d944SMark Yao } \ 76c7647f86SJohn Keeping } \ 77ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 78dbb3d944SMark Yao } while (0) 79dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 80dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 81dbb3d944SMark Yao 822996fb75SEzequiel Garcia #define VOP_WIN_GET(vop, win, name) \ 83cc8f1299SJohn Keeping vop_read_reg(vop, win->base, &win->phy->name) 842048e328SMark Yao 85677e8bbcSDaniele Castagna #define VOP_WIN_HAS_REG(win, name) \ 86677e8bbcSDaniele Castagna (!!(win->phy->name.mask)) 87677e8bbcSDaniele Castagna 882048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 892048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 902048e328SMark Yao 9158badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 9258badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 9358badaa7SKristian H. Kristensen 947707f722SAndrzej Pietrasiewicz #define VOP_AFBC_SET(vop, name, v) \ 957707f722SAndrzej Pietrasiewicz do { \ 967707f722SAndrzej Pietrasiewicz if ((vop)->data->afbc) \ 977707f722SAndrzej Pietrasiewicz vop_reg_set((vop), &(vop)->data->afbc->name, \ 987707f722SAndrzej Pietrasiewicz 0, ~0, v, #name); \ 997707f722SAndrzej Pietrasiewicz } while (0) 1007707f722SAndrzej Pietrasiewicz 1012048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 1022048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 1032048e328SMark Yao 1047707f722SAndrzej Pietrasiewicz #define AFBC_FMT_RGB565 0x0 1057707f722SAndrzej Pietrasiewicz #define AFBC_FMT_U8U8U8U8 0x5 1067707f722SAndrzej Pietrasiewicz #define AFBC_FMT_U8U8U8 0x4 1077707f722SAndrzej Pietrasiewicz 1087707f722SAndrzej Pietrasiewicz #define AFBC_TILE_16x16 BIT(4) 1097707f722SAndrzej Pietrasiewicz 1101c21aa8fSDaniele Castagna /* 1111c21aa8fSDaniele Castagna * The coefficients of the following matrix are all fixed points. 1121c21aa8fSDaniele Castagna * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 1131c21aa8fSDaniele Castagna * They are all represented in two's complement. 1141c21aa8fSDaniele Castagna */ 1151c21aa8fSDaniele Castagna static const uint32_t bt601_yuv2rgb[] = { 1161c21aa8fSDaniele Castagna 0x4A8, 0x0, 0x662, 1171c21aa8fSDaniele Castagna 0x4A8, 0x1E6F, 0x1CBF, 1181c21aa8fSDaniele Castagna 0x4A8, 0x812, 0x0, 1191c21aa8fSDaniele Castagna 0x321168, 0x0877CF, 0x2EB127 1201c21aa8fSDaniele Castagna }; 1211c21aa8fSDaniele Castagna 12247a7eb45STomasz Figa enum vop_pending { 12347a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 12447a7eb45STomasz Figa }; 12547a7eb45STomasz Figa 1262048e328SMark Yao struct vop_win { 1272048e328SMark Yao struct drm_plane base; 1282048e328SMark Yao const struct vop_win_data *data; 1291c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *yuv2yuv_data; 1302048e328SMark Yao struct vop *vop; 1312048e328SMark Yao }; 1322048e328SMark Yao 1331f0f0151SSandy Huang struct rockchip_rgb; 1342048e328SMark Yao struct vop { 1352048e328SMark Yao struct drm_crtc crtc; 1362048e328SMark Yao struct device *dev; 1372048e328SMark Yao struct drm_device *drm_dev; 13831e980c5SMark Yao bool is_enabled; 1392048e328SMark Yao 1401067219bSMark Yao struct completion dsp_hold_completion; 141bed030a4SSean Paul unsigned int win_enabled; 1424f9d39a7SDaniel Vetter 1434f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 14463ebb9faSMark Yao struct drm_pending_vblank_event *event; 1452048e328SMark Yao 14647a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 14747a7eb45STomasz Figa unsigned long pending; 14847a7eb45STomasz Figa 14969c34e41SYakir Yang struct completion line_flag_completion; 15069c34e41SYakir Yang 1512048e328SMark Yao const struct vop_data *data; 1522048e328SMark Yao 1532048e328SMark Yao uint32_t *regsbak; 1542048e328SMark Yao void __iomem *regs; 155b23ab6acSEzequiel Garcia void __iomem *lut_regs; 1562048e328SMark Yao 1572048e328SMark Yao /* physical map length of vop register */ 1582048e328SMark Yao uint32_t len; 1592048e328SMark Yao 1602048e328SMark Yao /* one time only one process allowed to config the register */ 1612048e328SMark Yao spinlock_t reg_lock; 1622048e328SMark Yao /* lock vop irq reg */ 1632048e328SMark Yao spinlock_t irq_lock; 164e334d48bSzain wang /* protects crtc enable/disable */ 165e334d48bSzain wang struct mutex vop_lock; 1662048e328SMark Yao 1672048e328SMark Yao unsigned int irq; 1682048e328SMark Yao 1692048e328SMark Yao /* vop AHP clk */ 1702048e328SMark Yao struct clk *hclk; 1712048e328SMark Yao /* vop dclk */ 1722048e328SMark Yao struct clk *dclk; 1732048e328SMark Yao /* vop share memory frequency */ 1742048e328SMark Yao struct clk *aclk; 1752048e328SMark Yao 1762048e328SMark Yao /* vop dclk reset */ 1772048e328SMark Yao struct reset_control *dclk_rst; 1782048e328SMark Yao 1791f0f0151SSandy Huang /* optional internal rgb encoder */ 1801f0f0151SSandy Huang struct rockchip_rgb *rgb; 1811f0f0151SSandy Huang 1822048e328SMark Yao struct vop_win win[]; 1832048e328SMark Yao }; 1842048e328SMark Yao 1852048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1862048e328SMark Yao { 1872048e328SMark Yao writel(v, vop->regs + offset); 1882048e328SMark Yao vop->regsbak[offset >> 2] = v; 1892048e328SMark Yao } 1902048e328SMark Yao 1912048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1922048e328SMark Yao { 1932048e328SMark Yao return readl(vop->regs + offset); 1942048e328SMark Yao } 1952048e328SMark Yao 1962048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1972048e328SMark Yao const struct vop_reg *reg) 1982048e328SMark Yao { 1992048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 2002048e328SMark Yao } 2012048e328SMark Yao 2029a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 2039a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 2049a61c54bSMark yao const char *reg_name) 2052048e328SMark Yao { 2069a61c54bSMark yao int offset, mask, shift; 207d49463ecSMark Yao 2089a61c54bSMark yao if (!reg || !reg->mask) { 209d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 2109a61c54bSMark yao return; 2119a61c54bSMark yao } 2129a61c54bSMark yao 2139a61c54bSMark yao offset = reg->offset + _offset; 2149a61c54bSMark yao mask = reg->mask & _mask; 2159a61c54bSMark yao shift = reg->shift; 2169a61c54bSMark yao 2179a61c54bSMark yao if (reg->write_mask) { 218d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 219d49463ecSMark Yao } else { 2202048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 2212048e328SMark Yao 222d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 223d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 2242048e328SMark Yao } 2252048e328SMark Yao 2269a61c54bSMark yao if (reg->relaxed) 227d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 228d49463ecSMark Yao else 229d49463ecSMark Yao writel(v, vop->regs + offset); 2302048e328SMark Yao } 2312048e328SMark Yao 232dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 233dbb3d944SMark Yao const struct vop_reg *reg, int type) 234dbb3d944SMark Yao { 235dbb3d944SMark Yao uint32_t i, ret = 0; 236dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 237dbb3d944SMark Yao 238dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 239dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 240dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 241dbb3d944SMark Yao } 242dbb3d944SMark Yao 243dbb3d944SMark Yao return ret; 244dbb3d944SMark Yao } 245dbb3d944SMark Yao 2460cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2470cf33fe3SMark Yao { 2489a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2490cf33fe3SMark Yao } 2500cf33fe3SMark Yao 25185a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 25285a359f2STomasz Figa { 25385a359f2STomasz Figa switch (format) { 25485a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 25585a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 25685a359f2STomasz Figa case DRM_FORMAT_BGR888: 25785a359f2STomasz Figa case DRM_FORMAT_BGR565: 25885a359f2STomasz Figa return true; 25985a359f2STomasz Figa default: 26085a359f2STomasz Figa return false; 26185a359f2STomasz Figa } 26285a359f2STomasz Figa } 26385a359f2STomasz Figa 2642048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2652048e328SMark Yao { 2662048e328SMark Yao switch (format) { 2672048e328SMark Yao case DRM_FORMAT_XRGB8888: 2682048e328SMark Yao case DRM_FORMAT_ARGB8888: 26985a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 27085a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2712048e328SMark Yao return VOP_FMT_ARGB8888; 2722048e328SMark Yao case DRM_FORMAT_RGB888: 27385a359f2STomasz Figa case DRM_FORMAT_BGR888: 2742048e328SMark Yao return VOP_FMT_RGB888; 2752048e328SMark Yao case DRM_FORMAT_RGB565: 27685a359f2STomasz Figa case DRM_FORMAT_BGR565: 2772048e328SMark Yao return VOP_FMT_RGB565; 2782048e328SMark Yao case DRM_FORMAT_NV12: 2792048e328SMark Yao return VOP_FMT_YUV420SP; 2802048e328SMark Yao case DRM_FORMAT_NV16: 2812048e328SMark Yao return VOP_FMT_YUV422SP; 2822048e328SMark Yao case DRM_FORMAT_NV24: 2832048e328SMark Yao return VOP_FMT_YUV444SP; 2842048e328SMark Yao default: 285ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2862048e328SMark Yao return -EINVAL; 2872048e328SMark Yao } 2882048e328SMark Yao } 2892048e328SMark Yao 2907707f722SAndrzej Pietrasiewicz static int vop_convert_afbc_format(uint32_t format) 2917707f722SAndrzej Pietrasiewicz { 2927707f722SAndrzej Pietrasiewicz switch (format) { 2937707f722SAndrzej Pietrasiewicz case DRM_FORMAT_XRGB8888: 2947707f722SAndrzej Pietrasiewicz case DRM_FORMAT_ARGB8888: 2957707f722SAndrzej Pietrasiewicz case DRM_FORMAT_XBGR8888: 2967707f722SAndrzej Pietrasiewicz case DRM_FORMAT_ABGR8888: 2977707f722SAndrzej Pietrasiewicz return AFBC_FMT_U8U8U8U8; 2987707f722SAndrzej Pietrasiewicz case DRM_FORMAT_RGB888: 2997707f722SAndrzej Pietrasiewicz case DRM_FORMAT_BGR888: 3007707f722SAndrzej Pietrasiewicz return AFBC_FMT_U8U8U8; 3017707f722SAndrzej Pietrasiewicz case DRM_FORMAT_RGB565: 3027707f722SAndrzej Pietrasiewicz case DRM_FORMAT_BGR565: 3037707f722SAndrzej Pietrasiewicz return AFBC_FMT_RGB565; 3047707f722SAndrzej Pietrasiewicz /* either of the below should not be reachable */ 3057707f722SAndrzej Pietrasiewicz default: 3067707f722SAndrzej Pietrasiewicz DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); 3077707f722SAndrzej Pietrasiewicz return -EINVAL; 3087707f722SAndrzej Pietrasiewicz } 3097707f722SAndrzej Pietrasiewicz 3107707f722SAndrzej Pietrasiewicz return -EINVAL; 3117707f722SAndrzej Pietrasiewicz } 3127707f722SAndrzej Pietrasiewicz 3134c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 3144c156c21SMark Yao uint32_t dst, bool is_horizontal, 3154c156c21SMark Yao int vsu_mode, int *vskiplines) 3164c156c21SMark Yao { 3174c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 3184c156c21SMark Yao 319ce91d373SJeffy Chen if (vskiplines) 320ce91d373SJeffy Chen *vskiplines = 0; 321ce91d373SJeffy Chen 3224c156c21SMark Yao if (is_horizontal) { 3234c156c21SMark Yao if (mode == SCALE_UP) 3244c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3254c156c21SMark Yao else if (mode == SCALE_DOWN) 3264c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3274c156c21SMark Yao } else { 3284c156c21SMark Yao if (mode == SCALE_UP) { 3294c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 3304c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 3314c156c21SMark Yao else 3324c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3334c156c21SMark Yao } else if (mode == SCALE_DOWN) { 3344c156c21SMark Yao if (vskiplines) { 3354c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 3364c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 3374c156c21SMark Yao *vskiplines); 3384c156c21SMark Yao } else { 3394c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3404c156c21SMark Yao } 3414c156c21SMark Yao } 3424c156c21SMark Yao } 3434c156c21SMark Yao 3444c156c21SMark Yao return val; 3454c156c21SMark Yao } 3464c156c21SMark Yao 3474c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3484c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 34945babef0SMaxime Ripard uint32_t dst_h, const struct drm_format_info *info) 3504c156c21SMark Yao { 3514c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3524c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3534c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 354d8bd23d9SAyan Kumar Halder bool is_yuv = false; 355f3e9632cSMaxime Ripard uint16_t cbcr_src_w = src_w / info->hsub; 356f3e9632cSMaxime Ripard uint16_t cbcr_src_h = src_h / info->vsub; 3574c156c21SMark Yao uint16_t vsu_mode; 3584c156c21SMark Yao uint16_t lb_mode; 3594c156c21SMark Yao uint32_t val; 360ce91d373SJeffy Chen int vskiplines; 3614c156c21SMark Yao 362d8bd23d9SAyan Kumar Halder if (info->is_yuv) 363d8bd23d9SAyan Kumar Halder is_yuv = true; 364d8bd23d9SAyan Kumar Halder 3654c156c21SMark Yao if (dst_w > 3840) { 366ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3674c156c21SMark Yao return; 3684c156c21SMark Yao } 3694c156c21SMark Yao 3701194fffbSMark Yao if (!win->phy->scl->ext) { 3711194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3721194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3731194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3741194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3751194fffbSMark Yao if (is_yuv) { 3761194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 377ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3781194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 379ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3801194fffbSMark Yao } 3811194fffbSMark Yao return; 3821194fffbSMark Yao } 3831194fffbSMark Yao 3844c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3854c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3864c156c21SMark Yao 3874c156c21SMark Yao if (is_yuv) { 3884c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3894c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3904c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3914c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3924c156c21SMark Yao else 3934c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3944c156c21SMark Yao } else { 3954c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3964c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3974c156c21SMark Yao else 3984c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3994c156c21SMark Yao } 4004c156c21SMark Yao 4011194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 4024c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 4034c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 404ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 4054c156c21SMark Yao return; 4064c156c21SMark Yao } 4074c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 408ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 4094c156c21SMark Yao return; 4104c156c21SMark Yao } 4114c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 4124c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 4134c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 4144c156c21SMark Yao } else { 4154c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 4164c156c21SMark Yao } 4174c156c21SMark Yao 4184c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 4194c156c21SMark Yao true, 0, NULL); 4204c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 4214c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 4224c156c21SMark Yao false, vsu_mode, &vskiplines); 4234c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 4244c156c21SMark Yao 4251194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 4261194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 4274c156c21SMark Yao 4281194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 4291194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 4301194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 4311194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 4321194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 4334c156c21SMark Yao if (is_yuv) { 4344c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 4354c156c21SMark Yao dst_w, true, 0, NULL); 4364c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 4374c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 4384c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 4394c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 4404c156c21SMark Yao 4411194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 4421194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4431194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4441194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4451194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4461194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4471194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4484c156c21SMark Yao } 4494c156c21SMark Yao } 4504c156c21SMark Yao 4511067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4521067219bSMark Yao { 4531067219bSMark Yao unsigned long flags; 4541067219bSMark Yao 4551067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4561067219bSMark Yao return; 4571067219bSMark Yao 4581067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4591067219bSMark Yao 460fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 461dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4621067219bSMark Yao 4631067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4641067219bSMark Yao } 4651067219bSMark Yao 4661067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4671067219bSMark Yao { 4681067219bSMark Yao unsigned long flags; 4691067219bSMark Yao 4701067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4711067219bSMark Yao return; 4721067219bSMark Yao 4731067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4741067219bSMark Yao 475dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4761067219bSMark Yao 4771067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4781067219bSMark Yao } 4791067219bSMark Yao 48069c34e41SYakir Yang /* 48169c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 48269c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 48369c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 48469c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 48569c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 48669c34e41SYakir Yang * 48769c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 48869c34e41SYakir Yang * Interrupts 48969c34e41SYakir Yang * LINE_FLAG -------------------------------+ 49069c34e41SYakir Yang * FRAME_SYNC ----+ | 49169c34e41SYakir Yang * | | 49269c34e41SYakir Yang * v v 49369c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 49469c34e41SYakir Yang * ^ ^ ^ ^ 49569c34e41SYakir Yang * | | | | 49669c34e41SYakir Yang * | | | | 49769c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 49869c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 49969c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 50069c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 50169c34e41SYakir Yang */ 50269c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 50369c34e41SYakir Yang { 50469c34e41SYakir Yang uint32_t line_flag_irq; 50569c34e41SYakir Yang unsigned long flags; 50669c34e41SYakir Yang 50769c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 50869c34e41SYakir Yang 50969c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 51069c34e41SYakir Yang 51169c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 51269c34e41SYakir Yang 51369c34e41SYakir Yang return !!line_flag_irq; 51469c34e41SYakir Yang } 51569c34e41SYakir Yang 516459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 51769c34e41SYakir Yang { 51869c34e41SYakir Yang unsigned long flags; 51969c34e41SYakir Yang 52069c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 52169c34e41SYakir Yang return; 52269c34e41SYakir Yang 52369c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 52469c34e41SYakir Yang 525fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 52669c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 52769c34e41SYakir Yang 52869c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 52969c34e41SYakir Yang } 53069c34e41SYakir Yang 53169c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 53269c34e41SYakir Yang { 53369c34e41SYakir Yang unsigned long flags; 53469c34e41SYakir Yang 53569c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 53669c34e41SYakir Yang return; 53769c34e41SYakir Yang 53869c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 53969c34e41SYakir Yang 54069c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 54169c34e41SYakir Yang 54269c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 54369c34e41SYakir Yang } 54469c34e41SYakir Yang 545e2810a71SHeiko Stuebner static int vop_core_clks_enable(struct vop *vop) 546e2810a71SHeiko Stuebner { 547e2810a71SHeiko Stuebner int ret; 548e2810a71SHeiko Stuebner 549e2810a71SHeiko Stuebner ret = clk_enable(vop->hclk); 550e2810a71SHeiko Stuebner if (ret < 0) 551e2810a71SHeiko Stuebner return ret; 552e2810a71SHeiko Stuebner 553e2810a71SHeiko Stuebner ret = clk_enable(vop->aclk); 554e2810a71SHeiko Stuebner if (ret < 0) 555e2810a71SHeiko Stuebner goto err_disable_hclk; 556e2810a71SHeiko Stuebner 557e2810a71SHeiko Stuebner return 0; 558e2810a71SHeiko Stuebner 559e2810a71SHeiko Stuebner err_disable_hclk: 560e2810a71SHeiko Stuebner clk_disable(vop->hclk); 561e2810a71SHeiko Stuebner return ret; 562e2810a71SHeiko Stuebner } 563e2810a71SHeiko Stuebner 564e2810a71SHeiko Stuebner static void vop_core_clks_disable(struct vop *vop) 565e2810a71SHeiko Stuebner { 566e2810a71SHeiko Stuebner clk_disable(vop->aclk); 567e2810a71SHeiko Stuebner clk_disable(vop->hclk); 568e2810a71SHeiko Stuebner } 569e2810a71SHeiko Stuebner 5702b60e11dSSean Paul static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 571e9abc611SJonas Karlman { 5722b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 5732b60e11dSSean Paul 574e9abc611SJonas Karlman if (win->phy->scl && win->phy->scl->ext) { 575e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 576e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 577e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 578e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 579e9abc611SJonas Karlman } 580e9abc611SJonas Karlman 581e9abc611SJonas Karlman VOP_WIN_SET(vop, win, enable, 0); 582bed030a4SSean Paul vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 583e9abc611SJonas Karlman } 584e9abc611SJonas Karlman 5856c836d96SSean Paul static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 5862048e328SMark Yao { 5872048e328SMark Yao struct vop *vop = to_vop(crtc); 58864d77564SMark yao int ret, i; 5892048e328SMark Yao 5905d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5915d82d1a7SMark Yao if (ret < 0) { 592d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 5935e570373SJeffy Chen return ret; 5945d82d1a7SMark Yao } 5955d82d1a7SMark Yao 596e2810a71SHeiko Stuebner ret = vop_core_clks_enable(vop); 59739a9ad8fSSean Paul if (WARN_ON(ret < 0)) 59839a9ad8fSSean Paul goto err_put_pm_runtime; 5992048e328SMark Yao 6002048e328SMark Yao ret = clk_enable(vop->dclk); 60139a9ad8fSSean Paul if (WARN_ON(ret < 0)) 602e2810a71SHeiko Stuebner goto err_disable_core; 6032048e328SMark Yao 6042048e328SMark Yao /* 6052048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 6062048e328SMark Yao * automatically with this master device via common driver code. 6072048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 6082048e328SMark Yao * mapping. 6092048e328SMark Yao */ 6102048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 6112048e328SMark Yao if (ret) { 612d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 613d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 614e2810a71SHeiko Stuebner goto err_disable_dclk; 6152048e328SMark Yao } 6162048e328SMark Yao 61776f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 61876f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 61976f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 62076f1416eSMarc Zyngier 62164d77564SMark yao /* 62264d77564SMark yao * We need to make sure that all windows are disabled before we 62364d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 62464d77564SMark yao * buffer later. 6256c836d96SSean Paul * 6266c836d96SSean Paul * In the case of enable-after-PSR, we don't need to worry about this 6276c836d96SSean Paul * case since the buffer is guaranteed to be valid and disabling the 6286c836d96SSean Paul * window will result in screen glitches on PSR exit. 62964d77564SMark yao */ 6306c836d96SSean Paul if (!old_state || !old_state->self_refresh_active) { 63164d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 63264d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 63364d77564SMark yao 6342b60e11dSSean Paul vop_win_disable(vop, vop_win); 63564d77564SMark yao } 6366c836d96SSean Paul } 6377707f722SAndrzej Pietrasiewicz 6387707f722SAndrzej Pietrasiewicz if (vop->data->afbc) { 6397707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 6407707f722SAndrzej Pietrasiewicz /* 6417707f722SAndrzej Pietrasiewicz * Disable AFBC and forget there was a vop window with AFBC 6427707f722SAndrzej Pietrasiewicz */ 6437707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, enable, 0); 6447707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc->state); 6457707f722SAndrzej Pietrasiewicz s->enable_afbc = false; 6467707f722SAndrzej Pietrasiewicz } 6477707f722SAndrzej Pietrasiewicz 64817a794d7SChris Zhong vop_cfg_done(vop); 64917a794d7SChris Zhong 6505fa63f07SEmil Velikov spin_unlock(&vop->reg_lock); 6515fa63f07SEmil Velikov 65252ab7891SMark Yao /* 65352ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 65452ab7891SMark Yao */ 65552ab7891SMark Yao vop->is_enabled = true; 65652ab7891SMark Yao 6572048e328SMark Yao spin_lock(&vop->reg_lock); 6582048e328SMark Yao 6599a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6602048e328SMark Yao 6612048e328SMark Yao spin_unlock(&vop->reg_lock); 6622048e328SMark Yao 663b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6642048e328SMark Yao 66539a9ad8fSSean Paul return 0; 6662048e328SMark Yao 6672048e328SMark Yao err_disable_dclk: 6682048e328SMark Yao clk_disable(vop->dclk); 669e2810a71SHeiko Stuebner err_disable_core: 670e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 67139a9ad8fSSean Paul err_put_pm_runtime: 67239a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 67339a9ad8fSSean Paul return ret; 6742048e328SMark Yao } 6752048e328SMark Yao 676bed030a4SSean Paul static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 677bed030a4SSean Paul { 678bed030a4SSean Paul struct vop *vop = to_vop(crtc); 679bed030a4SSean Paul int i; 680bed030a4SSean Paul 681bed030a4SSean Paul spin_lock(&vop->reg_lock); 682bed030a4SSean Paul 683bed030a4SSean Paul for (i = 0; i < vop->data->win_size; i++) { 684bed030a4SSean Paul struct vop_win *vop_win = &vop->win[i]; 685bed030a4SSean Paul const struct vop_win_data *win = vop_win->data; 686bed030a4SSean Paul 687bed030a4SSean Paul VOP_WIN_SET(vop, win, enable, 688bed030a4SSean Paul enabled && (vop->win_enabled & BIT(i))); 689bed030a4SSean Paul } 690bed030a4SSean Paul vop_cfg_done(vop); 691bed030a4SSean Paul 692bed030a4SSean Paul spin_unlock(&vop->reg_lock); 693bed030a4SSean Paul } 694bed030a4SSean Paul 69564581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 69664581714SLaurent Pinchart struct drm_crtc_state *old_state) 6972048e328SMark Yao { 6982048e328SMark Yao struct vop *vop = to_vop(crtc); 6992048e328SMark Yao 700893b6cadSDaniel Vetter WARN_ON(vop->event); 701893b6cadSDaniel Vetter 702bed030a4SSean Paul if (crtc->state->self_refresh_active) 703bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, false); 704bed030a4SSean Paul 705e334d48bSzain wang mutex_lock(&vop->vop_lock); 7066c836d96SSean Paul 707b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 7082048e328SMark Yao 709bed030a4SSean Paul if (crtc->state->self_refresh_active) 710bed030a4SSean Paul goto out; 711bed030a4SSean Paul 7122048e328SMark Yao /* 7131067219bSMark Yao * Vop standby will take effect at end of current frame, 7141067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 7151067219bSMark Yao * 7161067219bSMark Yao * we must wait standby complete when we want to disable aclk, 7171067219bSMark Yao * if not, memory bus maybe dead. 7182048e328SMark Yao */ 7191067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 7201067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 7211067219bSMark Yao 7222048e328SMark Yao spin_lock(&vop->reg_lock); 7232048e328SMark Yao 7249a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 7252048e328SMark Yao 7262048e328SMark Yao spin_unlock(&vop->reg_lock); 72752ab7891SMark Yao 7281067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 7292048e328SMark Yao 7301067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 7311067219bSMark Yao 7321067219bSMark Yao vop->is_enabled = false; 7331067219bSMark Yao 7341067219bSMark Yao /* 7351067219bSMark Yao * vop standby complete, so iommu detach is safe. 7361067219bSMark Yao */ 7372048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 7382048e328SMark Yao 7391067219bSMark Yao clk_disable(vop->dclk); 740e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 7415d82d1a7SMark Yao pm_runtime_put(vop->dev); 742bed030a4SSean Paul 743bed030a4SSean Paul out: 744e334d48bSzain wang mutex_unlock(&vop->vop_lock); 745893b6cadSDaniel Vetter 746893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 747893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 748893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 749893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 750893b6cadSDaniel Vetter 751893b6cadSDaniel Vetter crtc->state->event = NULL; 752893b6cadSDaniel Vetter } 7532048e328SMark Yao } 7542048e328SMark Yao 75563ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 7562048e328SMark Yao { 75763ebb9faSMark Yao drm_plane_cleanup(plane); 7582048e328SMark Yao } 7592048e328SMark Yao 7607707f722SAndrzej Pietrasiewicz static inline bool rockchip_afbc(u64 modifier) 7617707f722SAndrzej Pietrasiewicz { 7627707f722SAndrzej Pietrasiewicz return modifier == ROCKCHIP_AFBC_MOD; 7637707f722SAndrzej Pietrasiewicz } 7647707f722SAndrzej Pietrasiewicz 7657707f722SAndrzej Pietrasiewicz static bool rockchip_mod_supported(struct drm_plane *plane, 7667707f722SAndrzej Pietrasiewicz u32 format, u64 modifier) 7677707f722SAndrzej Pietrasiewicz { 7687707f722SAndrzej Pietrasiewicz if (modifier == DRM_FORMAT_MOD_LINEAR) 7697707f722SAndrzej Pietrasiewicz return true; 7707707f722SAndrzej Pietrasiewicz 7717707f722SAndrzej Pietrasiewicz if (!rockchip_afbc(modifier)) { 7726472e4e2SColin Ian King DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 7737707f722SAndrzej Pietrasiewicz 7747707f722SAndrzej Pietrasiewicz return false; 7757707f722SAndrzej Pietrasiewicz } 7767707f722SAndrzej Pietrasiewicz 7777707f722SAndrzej Pietrasiewicz return vop_convert_afbc_format(format) >= 0; 7787707f722SAndrzej Pietrasiewicz } 7797707f722SAndrzej Pietrasiewicz 78063ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 78163ebb9faSMark Yao struct drm_plane_state *state) 7822048e328SMark Yao { 78363ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 78492915da6SJohn Keeping struct drm_crtc_state *crtc_state; 78563ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 7862048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 7872048e328SMark Yao const struct vop_win_data *win = vop_win->data; 7882048e328SMark Yao int ret; 7894c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 7904c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7914c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 7924c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7932048e328SMark Yao 794fd907adeSDaniel Vetter if (!crtc || WARN_ON(!fb)) 795d47a7246STomasz Figa return 0; 79692915da6SJohn Keeping 79792915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 79892915da6SJohn Keeping if (WARN_ON(!crtc_state)) 79992915da6SJohn Keeping return -EINVAL; 80092915da6SJohn Keeping 80181af63a4SVille Syrjälä ret = drm_atomic_helper_check_plane_state(state, crtc_state, 802f9b96be0SVille Syrjälä min_scale, max_scale, 803f9b96be0SVille Syrjälä true, true); 8042048e328SMark Yao if (ret) 8052048e328SMark Yao return ret; 8062048e328SMark Yao 807f9b96be0SVille Syrjälä if (!state->visible) 808d47a7246STomasz Figa return 0; 8092048e328SMark Yao 810438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 811d47a7246STomasz Figa if (ret < 0) 812d47a7246STomasz Figa return ret; 81384c7f8caSMark Yao 81484c7f8caSMark Yao /* 81584c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 81684c7f8caSMark Yao * need align with 2 pixel. 81784c7f8caSMark Yao */ 818d8bd23d9SAyan Kumar Halder if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 819d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 82063ebb9faSMark Yao return -EINVAL; 821d415fb87SMark yao } 82263ebb9faSMark Yao 823677e8bbcSDaniele Castagna if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 824677e8bbcSDaniele Castagna DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 825677e8bbcSDaniele Castagna return -EINVAL; 826677e8bbcSDaniele Castagna } 827677e8bbcSDaniele Castagna 8287707f722SAndrzej Pietrasiewicz if (rockchip_afbc(fb->modifier)) { 8297707f722SAndrzej Pietrasiewicz struct vop *vop = to_vop(crtc); 8307707f722SAndrzej Pietrasiewicz 8317707f722SAndrzej Pietrasiewicz if (!vop->data->afbc) { 8327707f722SAndrzej Pietrasiewicz DRM_ERROR("vop does not support AFBC\n"); 8337707f722SAndrzej Pietrasiewicz return -EINVAL; 8347707f722SAndrzej Pietrasiewicz } 8357707f722SAndrzej Pietrasiewicz 8367707f722SAndrzej Pietrasiewicz ret = vop_convert_afbc_format(fb->format->format); 8377707f722SAndrzej Pietrasiewicz if (ret < 0) 8387707f722SAndrzej Pietrasiewicz return ret; 8397707f722SAndrzej Pietrasiewicz 8407707f722SAndrzej Pietrasiewicz if (state->src.x1 || state->src.y1) { 8417707f722SAndrzej Pietrasiewicz DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", state->src.x1, state->src.y1, fb->offsets[0]); 8427707f722SAndrzej Pietrasiewicz return -EINVAL; 8437707f722SAndrzej Pietrasiewicz } 8447707f722SAndrzej Pietrasiewicz 8457707f722SAndrzej Pietrasiewicz if (state->rotation && state->rotation != DRM_MODE_ROTATE_0) { 8467707f722SAndrzej Pietrasiewicz DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 8477707f722SAndrzej Pietrasiewicz state->rotation); 8487707f722SAndrzej Pietrasiewicz return -EINVAL; 8497707f722SAndrzej Pietrasiewicz } 8507707f722SAndrzej Pietrasiewicz } 8517707f722SAndrzej Pietrasiewicz 85263ebb9faSMark Yao return 0; 85384c7f8caSMark Yao } 85484c7f8caSMark Yao 85563ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 85663ebb9faSMark Yao struct drm_plane_state *old_state) 85763ebb9faSMark Yao { 85863ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 85963ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 8602048e328SMark Yao 86163ebb9faSMark Yao if (!old_state->crtc) 86263ebb9faSMark Yao return; 8632048e328SMark Yao 86463ebb9faSMark Yao spin_lock(&vop->reg_lock); 8652048e328SMark Yao 8662b60e11dSSean Paul vop_win_disable(vop, vop_win); 8672048e328SMark Yao 86863ebb9faSMark Yao spin_unlock(&vop->reg_lock); 86963ebb9faSMark Yao } 87063ebb9faSMark Yao 87163ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 87263ebb9faSMark Yao struct drm_plane_state *old_state) 87363ebb9faSMark Yao { 87463ebb9faSMark Yao struct drm_plane_state *state = plane->state; 87563ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 87663ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 87763ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 8781c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 87963ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 88063ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 88163ebb9faSMark Yao unsigned int actual_w, actual_h; 88263ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 88363ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 884ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 885ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 88663ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 88763ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 88863ebb9faSMark Yao unsigned long offset; 88963ebb9faSMark Yao dma_addr_t dma_addr; 89063ebb9faSMark Yao uint32_t val; 89163ebb9faSMark Yao bool rb_swap; 89258badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 893d47a7246STomasz Figa int format; 8941c21aa8fSDaniele Castagna int is_yuv = fb->format->is_yuv; 8951c21aa8fSDaniele Castagna int i; 89663ebb9faSMark Yao 89763ebb9faSMark Yao /* 89863ebb9faSMark Yao * can't update plane when vop is disabled. 89963ebb9faSMark Yao */ 9004f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 90163ebb9faSMark Yao return; 90263ebb9faSMark Yao 90363ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 90463ebb9faSMark Yao return; 90563ebb9faSMark Yao 906d47a7246STomasz Figa if (!state->visible) { 90763ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 90863ebb9faSMark Yao return; 90963ebb9faSMark Yao } 91063ebb9faSMark Yao 911957428f9SDaniel Stone obj = fb->obj[0]; 91263ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 91363ebb9faSMark Yao 91463ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 91563ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 91663ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 91763ebb9faSMark Yao 91863ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 91963ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 92063ebb9faSMark Yao 92163ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 92263ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 92363ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 92463ebb9faSMark Yao 925353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 92663ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 927d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 928d47a7246STomasz Figa 929677e8bbcSDaniele Castagna /* 930677e8bbcSDaniele Castagna * For y-mirroring we need to move address 931677e8bbcSDaniele Castagna * to the beginning of the last line. 932677e8bbcSDaniele Castagna */ 933677e8bbcSDaniele Castagna if (state->rotation & DRM_MODE_REFLECT_Y) 934677e8bbcSDaniele Castagna dma_addr += (actual_h - 1) * fb->pitches[0]; 935677e8bbcSDaniele Castagna 936438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 93763ebb9faSMark Yao 93863ebb9faSMark Yao spin_lock(&vop->reg_lock); 93963ebb9faSMark Yao 9407707f722SAndrzej Pietrasiewicz if (rockchip_afbc(fb->modifier)) { 9417707f722SAndrzej Pietrasiewicz int afbc_format = vop_convert_afbc_format(fb->format->format); 9427707f722SAndrzej Pietrasiewicz 9437707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 9447707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, hreg_block_split, 0); 9457707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 9467707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 9477707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, pic_size, act_info); 9487707f722SAndrzej Pietrasiewicz } 9497707f722SAndrzej Pietrasiewicz 950d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 951da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 952d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 9531c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 954677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, y_mir_en, 955677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 956677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, x_mir_en, 957677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 9581c21aa8fSDaniele Castagna 9591c21aa8fSDaniele Castagna if (is_yuv) { 960f3e9632cSMaxime Ripard int hsub = fb->format->hsub; 961f3e9632cSMaxime Ripard int vsub = fb->format->vsub; 962353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 96384c7f8caSMark Yao 964957428f9SDaniel Stone uv_obj = fb->obj[1]; 96584c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 96684c7f8caSMark Yao 96763ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 96863ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 96984c7f8caSMark Yao 97063ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 971da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 97263ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 9731c21aa8fSDaniele Castagna 9741c21aa8fSDaniele Castagna for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 9751c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 9761c21aa8fSDaniele Castagna win_yuv2yuv, 9771c21aa8fSDaniele Castagna y2r_coefficients[i], 9781c21aa8fSDaniele Castagna bt601_yuv2rgb[i]); 9791c21aa8fSDaniele Castagna } 98084c7f8caSMark Yao } 9814c156c21SMark Yao 9824c156c21SMark Yao if (win->phy->scl) 9834c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 98463ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 98545babef0SMaxime Ripard fb->format); 9864c156c21SMark Yao 98763ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 98863ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 98963ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 9904c156c21SMark Yao 991438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 99285a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 9932048e328SMark Yao 99458badaa7SKristian H. Kristensen /* 99558badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 99658badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 99758badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 99858badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 99958badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 100058badaa7SKristian H. Kristensen */ 100158badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 10022048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 10032048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 10042048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 10052048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 10062048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 10072048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 10082048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 10092048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 10102aae8ed1SPaul Kocialkowski 10112aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 10122aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 10132aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_en, 1); 10142048e328SMark Yao } else { 10152048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 10162048e328SMark Yao } 10172048e328SMark Yao 10182048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 1019bed030a4SSean Paul vop->win_enabled |= BIT(win_index); 10202048e328SMark Yao spin_unlock(&vop->reg_lock); 10212048e328SMark Yao } 10222048e328SMark Yao 102315609559SEnric Balletbo i Serra static int vop_plane_atomic_async_check(struct drm_plane *plane, 102415609559SEnric Balletbo i Serra struct drm_plane_state *state) 102515609559SEnric Balletbo i Serra { 102615609559SEnric Balletbo i Serra struct vop_win *vop_win = to_vop_win(plane); 102715609559SEnric Balletbo i Serra const struct vop_win_data *win = vop_win->data; 102815609559SEnric Balletbo i Serra int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 102915609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 103015609559SEnric Balletbo i Serra int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 103115609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 103215609559SEnric Balletbo i Serra struct drm_crtc_state *crtc_state; 103315609559SEnric Balletbo i Serra 103415609559SEnric Balletbo i Serra if (plane != state->crtc->cursor) 103515609559SEnric Balletbo i Serra return -EINVAL; 103615609559SEnric Balletbo i Serra 103715609559SEnric Balletbo i Serra if (!plane->state) 103815609559SEnric Balletbo i Serra return -EINVAL; 103915609559SEnric Balletbo i Serra 104015609559SEnric Balletbo i Serra if (!plane->state->fb) 104115609559SEnric Balletbo i Serra return -EINVAL; 104215609559SEnric Balletbo i Serra 104315609559SEnric Balletbo i Serra if (state->state) 104415609559SEnric Balletbo i Serra crtc_state = drm_atomic_get_existing_crtc_state(state->state, 104515609559SEnric Balletbo i Serra state->crtc); 104615609559SEnric Balletbo i Serra else /* Special case for asynchronous cursor updates. */ 104715609559SEnric Balletbo i Serra crtc_state = plane->crtc->state; 104815609559SEnric Balletbo i Serra 104915609559SEnric Balletbo i Serra return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 105015609559SEnric Balletbo i Serra min_scale, max_scale, 105115609559SEnric Balletbo i Serra true, true); 105215609559SEnric Balletbo i Serra } 105315609559SEnric Balletbo i Serra 105415609559SEnric Balletbo i Serra static void vop_plane_atomic_async_update(struct drm_plane *plane, 105515609559SEnric Balletbo i Serra struct drm_plane_state *new_state) 105615609559SEnric Balletbo i Serra { 105715609559SEnric Balletbo i Serra struct vop *vop = to_vop(plane->state->crtc); 1058d985a353SHelen Koike struct drm_framebuffer *old_fb = plane->state->fb; 105915609559SEnric Balletbo i Serra 1060d985a353SHelen Koike plane->state->crtc_x = new_state->crtc_x; 1061d985a353SHelen Koike plane->state->crtc_y = new_state->crtc_y; 1062d985a353SHelen Koike plane->state->crtc_h = new_state->crtc_h; 1063d985a353SHelen Koike plane->state->crtc_w = new_state->crtc_w; 1064d985a353SHelen Koike plane->state->src_x = new_state->src_x; 1065d985a353SHelen Koike plane->state->src_y = new_state->src_y; 1066d985a353SHelen Koike plane->state->src_h = new_state->src_h; 1067d985a353SHelen Koike plane->state->src_w = new_state->src_w; 1068d985a353SHelen Koike swap(plane->state->fb, new_state->fb); 106915609559SEnric Balletbo i Serra 107015609559SEnric Balletbo i Serra if (vop->is_enabled) { 107115609559SEnric Balletbo i Serra vop_plane_atomic_update(plane, plane->state); 107215609559SEnric Balletbo i Serra spin_lock(&vop->reg_lock); 107315609559SEnric Balletbo i Serra vop_cfg_done(vop); 107415609559SEnric Balletbo i Serra spin_unlock(&vop->reg_lock); 107515609559SEnric Balletbo i Serra 1076d985a353SHelen Koike /* 1077d985a353SHelen Koike * A scanout can still be occurring, so we can't drop the 1078d985a353SHelen Koike * reference to the old framebuffer. To solve this we get a 1079d985a353SHelen Koike * reference to old_fb and set a worker to release it later. 1080d985a353SHelen Koike * FIXME: if we perform 500 async_update calls before the 1081d985a353SHelen Koike * vblank, then we can have 500 different framebuffers waiting 1082d985a353SHelen Koike * to be released. 1083d985a353SHelen Koike */ 1084d985a353SHelen Koike if (old_fb && plane->state->fb != old_fb) { 1085d985a353SHelen Koike drm_framebuffer_get(old_fb); 1086d985a353SHelen Koike WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1087d985a353SHelen Koike drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1088d985a353SHelen Koike set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1089d985a353SHelen Koike } 1090d985a353SHelen Koike } 109115609559SEnric Balletbo i Serra } 109215609559SEnric Balletbo i Serra 109363ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 109463ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 109563ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 109663ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 109715609559SEnric Balletbo i Serra .atomic_async_check = vop_plane_atomic_async_check, 109815609559SEnric Balletbo i Serra .atomic_async_update = vop_plane_atomic_async_update, 109963d5e06aSHeiko Stuebner .prepare_fb = drm_gem_fb_prepare_fb, 110063ebb9faSMark Yao }; 110163ebb9faSMark Yao 11022048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 110363ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 110463ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 11052048e328SMark Yao .destroy = vop_plane_destroy, 1106d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 1107d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1108d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 11097707f722SAndrzej Pietrasiewicz .format_mod_supported = rockchip_mod_supported, 11102048e328SMark Yao }; 11112048e328SMark Yao 11122048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 11132048e328SMark Yao { 11142048e328SMark Yao struct vop *vop = to_vop(crtc); 11152048e328SMark Yao unsigned long flags; 11162048e328SMark Yao 111763ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 11182048e328SMark Yao return -EPERM; 11192048e328SMark Yao 11202048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 11212048e328SMark Yao 1122fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1123dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 11242048e328SMark Yao 11252048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11262048e328SMark Yao 11272048e328SMark Yao return 0; 11282048e328SMark Yao } 11292048e328SMark Yao 11302048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 11312048e328SMark Yao { 11322048e328SMark Yao struct vop *vop = to_vop(crtc); 11332048e328SMark Yao unsigned long flags; 11342048e328SMark Yao 113563ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 11362048e328SMark Yao return; 113731e980c5SMark Yao 11382048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1139dbb3d944SMark Yao 1140dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1141dbb3d944SMark Yao 11422048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11432048e328SMark Yao } 11442048e328SMark Yao 11452048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 11462048e328SMark Yao const struct drm_display_mode *mode, 11472048e328SMark Yao struct drm_display_mode *adjusted_mode) 11482048e328SMark Yao { 1149b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 1150287422a9SDouglas Anderson unsigned long rate; 1151b59b8de3SChris Zhong 1152287422a9SDouglas Anderson /* 1153287422a9SDouglas Anderson * Clock craziness. 1154287422a9SDouglas Anderson * 1155287422a9SDouglas Anderson * Key points: 1156287422a9SDouglas Anderson * 1157287422a9SDouglas Anderson * - DRM works in in kHz. 1158287422a9SDouglas Anderson * - Clock framework works in Hz. 1159287422a9SDouglas Anderson * - Rockchip's clock driver picks the clock rate that is the 1160287422a9SDouglas Anderson * same _OR LOWER_ than the one requested. 1161287422a9SDouglas Anderson * 1162287422a9SDouglas Anderson * Action plan: 1163287422a9SDouglas Anderson * 1164287422a9SDouglas Anderson * 1. When DRM gives us a mode, we should add 999 Hz to it. That way 1165287422a9SDouglas Anderson * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to 1166287422a9SDouglas Anderson * make 60000 kHz then the clock framework will actually give us 1167287422a9SDouglas Anderson * the right clock. 1168287422a9SDouglas Anderson * 1169287422a9SDouglas Anderson * NOTE: if the PLL (maybe through a divider) could actually make 1170287422a9SDouglas Anderson * a clock rate 999 Hz higher instead of the one we want then this 1171287422a9SDouglas Anderson * could be a problem. Unfortunately there's not much we can do 1172287422a9SDouglas Anderson * since it's baked into DRM to use kHz. It shouldn't matter in 1173287422a9SDouglas Anderson * practice since Rockchip PLLs are controlled by tables and 1174287422a9SDouglas Anderson * even if there is a divider in the middle I wouldn't expect PLL 1175287422a9SDouglas Anderson * rates in the table that are just a few kHz different. 1176287422a9SDouglas Anderson * 1177287422a9SDouglas Anderson * 2. Get the clock framework to round the rate for us to tell us 1178287422a9SDouglas Anderson * what it will actually make. 1179287422a9SDouglas Anderson * 1180287422a9SDouglas Anderson * 3. Store the rounded up rate so that we don't need to worry about 1181287422a9SDouglas Anderson * this in the actual clk_set_rate(). 1182287422a9SDouglas Anderson */ 1183287422a9SDouglas Anderson rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); 1184287422a9SDouglas Anderson adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1185b59b8de3SChris Zhong 11862048e328SMark Yao return true; 11872048e328SMark Yao } 11882048e328SMark Yao 1189b23ab6acSEzequiel Garcia static bool vop_dsp_lut_is_enabled(struct vop *vop) 1190b23ab6acSEzequiel Garcia { 1191b23ab6acSEzequiel Garcia return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1192b23ab6acSEzequiel Garcia } 1193b23ab6acSEzequiel Garcia 1194b23ab6acSEzequiel Garcia static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1195b23ab6acSEzequiel Garcia { 1196b23ab6acSEzequiel Garcia struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1197b23ab6acSEzequiel Garcia unsigned int i; 1198b23ab6acSEzequiel Garcia 1199b23ab6acSEzequiel Garcia for (i = 0; i < crtc->gamma_size; i++) { 1200b23ab6acSEzequiel Garcia u32 word; 1201b23ab6acSEzequiel Garcia 1202b23ab6acSEzequiel Garcia word = (drm_color_lut_extract(lut[i].red, 10) << 20) | 1203b23ab6acSEzequiel Garcia (drm_color_lut_extract(lut[i].green, 10) << 10) | 1204b23ab6acSEzequiel Garcia drm_color_lut_extract(lut[i].blue, 10); 1205b23ab6acSEzequiel Garcia writel(word, vop->lut_regs + i * 4); 1206b23ab6acSEzequiel Garcia } 1207b23ab6acSEzequiel Garcia } 1208b23ab6acSEzequiel Garcia 1209b23ab6acSEzequiel Garcia static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1210b23ab6acSEzequiel Garcia struct drm_crtc_state *old_state) 1211b23ab6acSEzequiel Garcia { 1212b23ab6acSEzequiel Garcia struct drm_crtc_state *state = crtc->state; 1213b23ab6acSEzequiel Garcia unsigned int idle; 1214b23ab6acSEzequiel Garcia int ret; 1215b23ab6acSEzequiel Garcia 1216b23ab6acSEzequiel Garcia if (!vop->lut_regs) 1217b23ab6acSEzequiel Garcia return; 1218b23ab6acSEzequiel Garcia /* 1219b23ab6acSEzequiel Garcia * To disable gamma (gamma_lut is null) or to write 1220b23ab6acSEzequiel Garcia * an update to the LUT, clear dsp_lut_en. 1221b23ab6acSEzequiel Garcia */ 1222b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1223b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 0); 1224b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1225b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1226b23ab6acSEzequiel Garcia 1227b23ab6acSEzequiel Garcia /* 1228b23ab6acSEzequiel Garcia * In order to write the LUT to the internal memory, 1229b23ab6acSEzequiel Garcia * we need to first make sure the dsp_lut_en bit is cleared. 1230b23ab6acSEzequiel Garcia */ 1231b23ab6acSEzequiel Garcia ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1232b23ab6acSEzequiel Garcia idle, !idle, 5, 30 * 1000); 1233b23ab6acSEzequiel Garcia if (ret) { 1234b23ab6acSEzequiel Garcia DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1235b23ab6acSEzequiel Garcia return; 1236b23ab6acSEzequiel Garcia } 1237b23ab6acSEzequiel Garcia 1238b23ab6acSEzequiel Garcia if (!state->gamma_lut) 1239b23ab6acSEzequiel Garcia return; 1240b23ab6acSEzequiel Garcia 1241b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1242b23ab6acSEzequiel Garcia vop_crtc_write_gamma_lut(vop, crtc); 1243b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 1); 1244b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1245b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1246b23ab6acSEzequiel Garcia } 1247b23ab6acSEzequiel Garcia 1248b23ab6acSEzequiel Garcia static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1249b23ab6acSEzequiel Garcia struct drm_crtc_state *old_crtc_state) 1250b23ab6acSEzequiel Garcia { 1251b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 1252b23ab6acSEzequiel Garcia 1253b23ab6acSEzequiel Garcia /* 1254b23ab6acSEzequiel Garcia * Only update GAMMA if the 'active' flag is not changed, 1255b23ab6acSEzequiel Garcia * otherwise it's updated by .atomic_enable. 1256b23ab6acSEzequiel Garcia */ 1257b23ab6acSEzequiel Garcia if (crtc->state->color_mgmt_changed && 1258b23ab6acSEzequiel Garcia !crtc->state->active_changed) 1259b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1260b23ab6acSEzequiel Garcia } 1261b23ab6acSEzequiel Garcia 12620b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 12630b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 12642048e328SMark Yao { 12652048e328SMark Yao struct vop *vop = to_vop(crtc); 1266efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 12674e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 126863ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 12692048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 12702048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 12712048e328SMark Yao u16 htotal = adjusted_mode->htotal; 12722048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 12732048e328SMark Yao u16 hact_end = hact_st + hdisplay; 12742048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 12752048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 12762048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 12772048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 12782048e328SMark Yao u16 vact_end = vact_st + vdisplay; 12790a63bfd0SMark Yao uint32_t pin_pol, val; 1280a5c0fa44SUrja Rannikko int dither_bpc = s->output_bpc ? s->output_bpc : 10; 128139a9ad8fSSean Paul int ret; 12822048e328SMark Yao 1283bed030a4SSean Paul if (old_state && old_state->self_refresh_active) { 1284bed030a4SSean Paul drm_crtc_vblank_on(crtc); 1285bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, true); 1286bed030a4SSean Paul return; 1287bed030a4SSean Paul } 1288bed030a4SSean Paul 1289b23ab6acSEzequiel Garcia /* 1290b23ab6acSEzequiel Garcia * If we have a GAMMA LUT in the state, then let's make sure 1291b23ab6acSEzequiel Garcia * it's updated. We might be coming out of suspend, 1292b23ab6acSEzequiel Garcia * which means the LUT internal memory needs to be re-written. 1293b23ab6acSEzequiel Garcia */ 1294b23ab6acSEzequiel Garcia if (crtc->state->gamma_lut) 1295b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_state); 1296b23ab6acSEzequiel Garcia 1297e334d48bSzain wang mutex_lock(&vop->vop_lock); 1298e334d48bSzain wang 1299893b6cadSDaniel Vetter WARN_ON(vop->event); 1300893b6cadSDaniel Vetter 13016c836d96SSean Paul ret = vop_enable(crtc, old_state); 130239a9ad8fSSean Paul if (ret) { 1303e334d48bSzain wang mutex_unlock(&vop->vop_lock); 130439a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 130539a9ad8fSSean Paul return; 130639a9ad8fSSean Paul } 13071f6c62caSNickey Yang pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1308d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 1309d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1310d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 13119a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 1312cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 13130a63bfd0SMark Yao 13144e257d9eSMark Yao switch (s->output_type) { 13154e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 13161f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 13179a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 13181f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_en, 1); 13194e257d9eSMark Yao break; 13204e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 13211f6c62caSNickey Yang VOP_REG_SET(vop, output, edp_dclk_pol, 1); 13229a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 13239a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 13244e257d9eSMark Yao break; 13254e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 13261f6c62caSNickey Yang VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 13279a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 13289a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 13294e257d9eSMark Yao break; 13304e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 13311f6c62caSNickey Yang VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 13329a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 13339a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 1334cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 1335cf6d100dSHeiko Stuebner !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 13364e257d9eSMark Yao break; 13371a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 13381f6c62caSNickey Yang VOP_REG_SET(vop, output, dp_dclk_pol, 0); 13399a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 13409a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 13411a0f7ed3SChris Zhong break; 13424e257d9eSMark Yao default: 1343ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1344ee4d7899SSean Paul s->output_type); 13454e257d9eSMark Yao } 1346efd11cc8SMark yao 1347efd11cc8SMark yao /* 1348efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 1349efd11cc8SMark yao */ 1350efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1351efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1352efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 13536bda8112SMark Yao 1354a5c0fa44SUrja Rannikko if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 13556bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 13566bda8112SMark Yao else 13576bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 13586bda8112SMark Yao 1359a5c0fa44SUrja Rannikko if (dither_bpc == 6) { 1360a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1361a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1362a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 1); 1363a5c0fa44SUrja Rannikko } else { 1364a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 0); 1365a5c0fa44SUrja Rannikko } 1366a5c0fa44SUrja Rannikko 13679a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 13682048e328SMark Yao 13699a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 13702048e328SMark Yao val = hact_st << 16; 13712048e328SMark Yao val |= hact_end; 13729a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 13739a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 13742048e328SMark Yao 13759a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 13762048e328SMark Yao val = vact_st << 16; 13772048e328SMark Yao val |= vact_end; 13789a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 13799a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 13802048e328SMark Yao 13819a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1382459b086dSJeffy Chen 13832048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1384ce3887edSMark Yao 13859a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 1386e334d48bSzain wang mutex_unlock(&vop->vop_lock); 13872048e328SMark Yao } 13882048e328SMark Yao 13897caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 13907caecdbeSTomasz Figa { 13917caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 13927caecdbeSTomasz Figa } 13937caecdbeSTomasz Figa 13947caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 13957caecdbeSTomasz Figa { 13967caecdbeSTomasz Figa bool pending; 13977caecdbeSTomasz Figa int ret; 13987caecdbeSTomasz Figa 13997caecdbeSTomasz Figa /* 14007caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 14017caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 14027caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 14037caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 14047caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 14057caecdbeSTomasz Figa * shouldn't exceed microseconds range. 14067caecdbeSTomasz Figa */ 14077caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 14087caecdbeSTomasz Figa !pending, 0, 10 * 1000); 14097caecdbeSTomasz Figa if (ret) 14107caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 14117caecdbeSTomasz Figa 14127caecdbeSTomasz Figa synchronize_irq(vop->irq); 14137caecdbeSTomasz Figa } 14147caecdbeSTomasz Figa 1415b23ab6acSEzequiel Garcia static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1416b23ab6acSEzequiel Garcia struct drm_crtc_state *crtc_state) 1417b23ab6acSEzequiel Garcia { 1418b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 14197707f722SAndrzej Pietrasiewicz struct drm_plane *plane; 14207707f722SAndrzej Pietrasiewicz struct drm_plane_state *plane_state; 14217707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 14227707f722SAndrzej Pietrasiewicz int afbc_planes = 0; 1423b23ab6acSEzequiel Garcia 1424b23ab6acSEzequiel Garcia if (vop->lut_regs && crtc_state->color_mgmt_changed && 1425b23ab6acSEzequiel Garcia crtc_state->gamma_lut) { 1426b23ab6acSEzequiel Garcia unsigned int len; 1427b23ab6acSEzequiel Garcia 1428b23ab6acSEzequiel Garcia len = drm_color_lut_size(crtc_state->gamma_lut); 1429b23ab6acSEzequiel Garcia if (len != crtc->gamma_size) { 1430b23ab6acSEzequiel Garcia DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1431b23ab6acSEzequiel Garcia len, crtc->gamma_size); 1432b23ab6acSEzequiel Garcia return -EINVAL; 1433b23ab6acSEzequiel Garcia } 1434b23ab6acSEzequiel Garcia } 1435b23ab6acSEzequiel Garcia 14367707f722SAndrzej Pietrasiewicz drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 14377707f722SAndrzej Pietrasiewicz plane_state = 14387707f722SAndrzej Pietrasiewicz drm_atomic_get_plane_state(crtc_state->state, plane); 14397707f722SAndrzej Pietrasiewicz if (IS_ERR(plane_state)) { 14407707f722SAndrzej Pietrasiewicz DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 14417707f722SAndrzej Pietrasiewicz plane->name); 14427707f722SAndrzej Pietrasiewicz return PTR_ERR(plane_state); 14437707f722SAndrzej Pietrasiewicz } 14447707f722SAndrzej Pietrasiewicz 14457707f722SAndrzej Pietrasiewicz if (drm_is_afbc(plane_state->fb->modifier)) 14467707f722SAndrzej Pietrasiewicz ++afbc_planes; 14477707f722SAndrzej Pietrasiewicz } 14487707f722SAndrzej Pietrasiewicz 14497707f722SAndrzej Pietrasiewicz if (afbc_planes > 1) { 14507707f722SAndrzej Pietrasiewicz DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 14517707f722SAndrzej Pietrasiewicz return -EINVAL; 14527707f722SAndrzej Pietrasiewicz } 14537707f722SAndrzej Pietrasiewicz 14547707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc_state); 14557707f722SAndrzej Pietrasiewicz s->enable_afbc = afbc_planes > 0; 14567707f722SAndrzej Pietrasiewicz 1457b23ab6acSEzequiel Garcia return 0; 1458b23ab6acSEzequiel Garcia } 1459b23ab6acSEzequiel Garcia 146063ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 146163ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 146263ebb9faSMark Yao { 146347a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1464e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 146563ebb9faSMark Yao struct vop *vop = to_vop(crtc); 146647a7eb45STomasz Figa struct drm_plane *plane; 14677707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 146847a7eb45STomasz Figa int i; 146963ebb9faSMark Yao 147063ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 147163ebb9faSMark Yao return; 147263ebb9faSMark Yao 147363ebb9faSMark Yao spin_lock(&vop->reg_lock); 147463ebb9faSMark Yao 14757707f722SAndrzej Pietrasiewicz /* Enable AFBC if there is some AFBC window, disable otherwise. */ 14767707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc->state); 14777707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, enable, s->enable_afbc); 147863ebb9faSMark Yao vop_cfg_done(vop); 147963ebb9faSMark Yao 148063ebb9faSMark Yao spin_unlock(&vop->reg_lock); 14817caecdbeSTomasz Figa 14827caecdbeSTomasz Figa /* 14837caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 14847caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 14857caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 14867caecdbeSTomasz Figa */ 14877caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 148847a7eb45STomasz Figa 148941ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 149041ee4367STomasz Figa if (crtc->state->event) { 149141ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 149241ee4367STomasz Figa WARN_ON(vop->event); 149341ee4367STomasz Figa 149441ee4367STomasz Figa vop->event = crtc->state->event; 149541ee4367STomasz Figa crtc->state->event = NULL; 149641ee4367STomasz Figa } 149741ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 149841ee4367STomasz Figa 1499e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1500e741f2b1SMaarten Lankhorst new_plane_state, i) { 150147a7eb45STomasz Figa if (!old_plane_state->fb) 150247a7eb45STomasz Figa continue; 150347a7eb45STomasz Figa 1504e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 150547a7eb45STomasz Figa continue; 150647a7eb45STomasz Figa 1507adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 15082d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 150947a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 151047a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 151147a7eb45STomasz Figa } 151263ebb9faSMark Yao } 151363ebb9faSMark Yao 15142048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 15152048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 1516b23ab6acSEzequiel Garcia .atomic_check = vop_crtc_atomic_check, 1517b23ab6acSEzequiel Garcia .atomic_begin = vop_crtc_atomic_begin, 151863ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 15190b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 152064581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 15212048e328SMark Yao }; 15222048e328SMark Yao 15232048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 15242048e328SMark Yao { 15252048e328SMark Yao drm_crtc_cleanup(crtc); 15262048e328SMark Yao } 15272048e328SMark Yao 15284e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 15294e257d9eSMark Yao { 15304e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 15314e257d9eSMark Yao 15324e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 15334e257d9eSMark Yao if (!rockchip_state) 15344e257d9eSMark Yao return NULL; 15354e257d9eSMark Yao 15364e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 15374e257d9eSMark Yao return &rockchip_state->base; 15384e257d9eSMark Yao } 15394e257d9eSMark Yao 15404e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 15414e257d9eSMark Yao struct drm_crtc_state *state) 15424e257d9eSMark Yao { 15434e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 15444e257d9eSMark Yao 1545ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 15464e257d9eSMark Yao kfree(s); 15474e257d9eSMark Yao } 15484e257d9eSMark Yao 154901e2eaf4SMaarten Lankhorst static void vop_crtc_reset(struct drm_crtc *crtc) 155001e2eaf4SMaarten Lankhorst { 155101e2eaf4SMaarten Lankhorst struct rockchip_crtc_state *crtc_state = 155201e2eaf4SMaarten Lankhorst kzalloc(sizeof(*crtc_state), GFP_KERNEL); 155301e2eaf4SMaarten Lankhorst 155401e2eaf4SMaarten Lankhorst if (crtc->state) 155501e2eaf4SMaarten Lankhorst vop_crtc_destroy_state(crtc, crtc->state); 155601e2eaf4SMaarten Lankhorst 155701e2eaf4SMaarten Lankhorst __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 155801e2eaf4SMaarten Lankhorst } 155901e2eaf4SMaarten Lankhorst 15606cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 15613190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 15623190e58dSTomeu Vizoso { 15633190e58dSTomeu Vizoso struct drm_connector *connector; 15642cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 15653190e58dSTomeu Vizoso 15662cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 15672cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 15683190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 15692cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 15703190e58dSTomeu Vizoso return connector; 15713190e58dSTomeu Vizoso } 15722cbeb64fSGustavo Padovan } 15732cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 15743190e58dSTomeu Vizoso 15753190e58dSTomeu Vizoso return NULL; 15763190e58dSTomeu Vizoso } 15773190e58dSTomeu Vizoso 15783190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1579c0811a7dSMahesh Kumar const char *source_name) 15803190e58dSTomeu Vizoso { 15813190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 15823190e58dSTomeu Vizoso struct drm_connector *connector; 15833190e58dSTomeu Vizoso int ret; 15843190e58dSTomeu Vizoso 15853190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 15863190e58dSTomeu Vizoso if (!connector) 15873190e58dSTomeu Vizoso return -EINVAL; 15883190e58dSTomeu Vizoso 15893190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 15903190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 15913190e58dSTomeu Vizoso else if (!source_name) 15923190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 15933190e58dSTomeu Vizoso else 15943190e58dSTomeu Vizoso ret = -EINVAL; 15953190e58dSTomeu Vizoso 15963190e58dSTomeu Vizoso return ret; 15973190e58dSTomeu Vizoso } 1598b8d913c0SMahesh Kumar 1599b8d913c0SMahesh Kumar static int 1600b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1601b8d913c0SMahesh Kumar size_t *values_cnt) 1602b8d913c0SMahesh Kumar { 1603b8d913c0SMahesh Kumar if (source_name && strcmp(source_name, "auto") != 0) 1604b8d913c0SMahesh Kumar return -EINVAL; 1605b8d913c0SMahesh Kumar 1606b8d913c0SMahesh Kumar *values_cnt = 3; 1607b8d913c0SMahesh Kumar return 0; 1608b8d913c0SMahesh Kumar } 1609b8d913c0SMahesh Kumar 16106cca3869SSean Paul #else 16116cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1612c0811a7dSMahesh Kumar const char *source_name) 16136cca3869SSean Paul { 16146cca3869SSean Paul return -ENODEV; 16156cca3869SSean Paul } 1616b8d913c0SMahesh Kumar 1617b8d913c0SMahesh Kumar static int 1618b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1619b8d913c0SMahesh Kumar size_t *values_cnt) 1620b8d913c0SMahesh Kumar { 1621b8d913c0SMahesh Kumar return -ENODEV; 1622b8d913c0SMahesh Kumar } 16236cca3869SSean Paul #endif 16243190e58dSTomeu Vizoso 16252048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 162663ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 162763ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 16282048e328SMark Yao .destroy = vop_crtc_destroy, 1629dc0b408fSJohn Keeping .reset = vop_crtc_reset, 16304e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 16314e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1632c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1633c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 16343190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 1635b8d913c0SMahesh Kumar .verify_crc_source = vop_crtc_verify_crc_source, 1636b23ab6acSEzequiel Garcia .gamma_set = drm_atomic_helper_legacy_gamma_set, 16372048e328SMark Yao }; 16382048e328SMark Yao 163947a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 164047a7eb45STomasz Figa { 164147a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 164247a7eb45STomasz Figa struct drm_framebuffer *fb = val; 164347a7eb45STomasz Figa 164447a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1645adedbf03SCihangir Akturk drm_framebuffer_put(fb); 164647a7eb45STomasz Figa } 164747a7eb45STomasz Figa 164863ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 16492048e328SMark Yao { 165063ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 165163ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 16522048e328SMark Yao 16531c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1654893b6cadSDaniel Vetter if (vop->event) { 165563ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 16565b680403SSean Paul drm_crtc_vblank_put(crtc); 1657646ec687STomasz Figa vop->event = NULL; 16585b680403SSean Paul } 16591c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1660893b6cadSDaniel Vetter 166147a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 166247a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 16632048e328SMark Yao } 16642048e328SMark Yao 16652048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 16662048e328SMark Yao { 16672048e328SMark Yao struct vop *vop = data; 1668b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1669dbb3d944SMark Yao uint32_t active_irqs; 16701067219bSMark Yao int ret = IRQ_NONE; 16712048e328SMark Yao 16722048e328SMark Yao /* 16736456314fSSandy Huang * The irq is shared with the iommu. If the runtime-pm state of the 16746456314fSSandy Huang * vop-device is disabled the irq has to be targeted at the iommu. 16756456314fSSandy Huang */ 16766456314fSSandy Huang if (!pm_runtime_get_if_in_use(vop->dev)) 16776456314fSSandy Huang return IRQ_NONE; 16786456314fSSandy Huang 16796456314fSSandy Huang if (vop_core_clks_enable(vop)) { 16806456314fSSandy Huang DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 16816456314fSSandy Huang goto out; 16826456314fSSandy Huang } 16836456314fSSandy Huang 16846456314fSSandy Huang /* 1685dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 16862048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 16872048e328SMark Yao */ 16881c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1689dbb3d944SMark Yao 1690dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 16912048e328SMark Yao /* Clear all active interrupt sources */ 16922048e328SMark Yao if (active_irqs) 1693dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1694dbb3d944SMark Yao 16951c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 16962048e328SMark Yao 16972048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 16982048e328SMark Yao if (!active_irqs) 16996456314fSSandy Huang goto out_disable; 17002048e328SMark Yao 17011067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 17021067219bSMark Yao complete(&vop->dsp_hold_completion); 17031067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 17041067219bSMark Yao ret = IRQ_HANDLED; 17052048e328SMark Yao } 17062048e328SMark Yao 170769c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 170869c34e41SYakir Yang complete(&vop->line_flag_completion); 170969c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 171069c34e41SYakir Yang ret = IRQ_HANDLED; 171169c34e41SYakir Yang } 171269c34e41SYakir Yang 17131067219bSMark Yao if (active_irqs & FS_INTR) { 1714b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 171563ebb9faSMark Yao vop_handle_vblank(vop); 17161067219bSMark Yao active_irqs &= ~FS_INTR; 171763ebb9faSMark Yao ret = IRQ_HANDLED; 17181067219bSMark Yao } 17192048e328SMark Yao 17201067219bSMark Yao /* Unhandled irqs are spurious. */ 17211067219bSMark Yao if (active_irqs) 1722ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1723ee4d7899SSean Paul active_irqs); 17241067219bSMark Yao 17256456314fSSandy Huang out_disable: 17266456314fSSandy Huang vop_core_clks_disable(vop); 17276456314fSSandy Huang out: 17286456314fSSandy Huang pm_runtime_put(vop->dev); 17291067219bSMark Yao return ret; 17302048e328SMark Yao } 17312048e328SMark Yao 1732677e8bbcSDaniele Castagna static void vop_plane_add_properties(struct drm_plane *plane, 1733677e8bbcSDaniele Castagna const struct vop_win_data *win_data) 1734677e8bbcSDaniele Castagna { 1735677e8bbcSDaniele Castagna unsigned int flags = 0; 1736677e8bbcSDaniele Castagna 1737677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1738677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1739677e8bbcSDaniele Castagna if (flags) 1740677e8bbcSDaniele Castagna drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1741677e8bbcSDaniele Castagna DRM_MODE_ROTATE_0 | flags); 1742677e8bbcSDaniele Castagna } 1743677e8bbcSDaniele Castagna 17442048e328SMark Yao static int vop_create_crtc(struct vop *vop) 17452048e328SMark Yao { 17462048e328SMark Yao const struct vop_data *vop_data = vop->data; 17472048e328SMark Yao struct device *dev = vop->dev; 17482048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1749328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 17502048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 17512048e328SMark Yao struct device_node *port; 17522048e328SMark Yao int ret; 17532048e328SMark Yao int i; 17542048e328SMark Yao 17552048e328SMark Yao /* 17562048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 17572048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 17582048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 17592048e328SMark Yao */ 17602048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 17612048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 17622048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 17632048e328SMark Yao 17642048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 17652048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 17662048e328SMark Yao continue; 17672048e328SMark Yao 17682048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 17692048e328SMark Yao 0, &vop_plane_funcs, 17702048e328SMark Yao win_data->phy->data_formats, 17712048e328SMark Yao win_data->phy->nformats, 17727707f722SAndrzej Pietrasiewicz win_data->phy->format_modifiers, 17737707f722SAndrzej Pietrasiewicz win_data->type, NULL); 17742048e328SMark Yao if (ret) { 1775ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1776ee4d7899SSean Paul ret); 17772048e328SMark Yao goto err_cleanup_planes; 17782048e328SMark Yao } 17792048e328SMark Yao 17802048e328SMark Yao plane = &vop_win->base; 178163ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 1782677e8bbcSDaniele Castagna vop_plane_add_properties(plane, win_data); 17832048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 17842048e328SMark Yao primary = plane; 17852048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 17862048e328SMark Yao cursor = plane; 17872048e328SMark Yao } 17882048e328SMark Yao 17892048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1790f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 17912048e328SMark Yao if (ret) 1792328b51c0SDouglas Anderson goto err_cleanup_planes; 17932048e328SMark Yao 17942048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1795b23ab6acSEzequiel Garcia if (vop->lut_regs) { 1796b23ab6acSEzequiel Garcia drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1797b23ab6acSEzequiel Garcia drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1798b23ab6acSEzequiel Garcia } 17992048e328SMark Yao 18002048e328SMark Yao /* 18012048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 18022048e328SMark Yao * to the newly created crtc. 18032048e328SMark Yao */ 18042048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 18052048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 18062048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 1807a3e77e16SVille Syrjälä unsigned long possible_crtcs = drm_crtc_mask(crtc); 18082048e328SMark Yao 18092048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 18102048e328SMark Yao continue; 18112048e328SMark Yao 18122048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 18132048e328SMark Yao possible_crtcs, 18142048e328SMark Yao &vop_plane_funcs, 18152048e328SMark Yao win_data->phy->data_formats, 18162048e328SMark Yao win_data->phy->nformats, 18177707f722SAndrzej Pietrasiewicz win_data->phy->format_modifiers, 18187707f722SAndrzej Pietrasiewicz win_data->type, NULL); 18192048e328SMark Yao if (ret) { 1820ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1821ee4d7899SSean Paul ret); 18222048e328SMark Yao goto err_cleanup_crtc; 18232048e328SMark Yao } 182463ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1825677e8bbcSDaniele Castagna vop_plane_add_properties(&vop_win->base, win_data); 18262048e328SMark Yao } 18272048e328SMark Yao 18282048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 18292048e328SMark Yao if (!port) { 18304bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 18314bf99144SRob Herring dev->of_node); 1832328b51c0SDouglas Anderson ret = -ENOENT; 18332048e328SMark Yao goto err_cleanup_crtc; 18342048e328SMark Yao } 18352048e328SMark Yao 183647a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 183747a7eb45STomasz Figa vop_fb_unref_worker); 183847a7eb45STomasz Figa 18391067219bSMark Yao init_completion(&vop->dsp_hold_completion); 184069c34e41SYakir Yang init_completion(&vop->line_flag_completion); 18412048e328SMark Yao crtc->port = port; 18422048e328SMark Yao 1843d4da4e33SSean Paul ret = drm_self_refresh_helper_init(crtc); 18446c836d96SSean Paul if (ret) 18456c836d96SSean Paul DRM_DEV_DEBUG_KMS(vop->dev, 18466c836d96SSean Paul "Failed to init %s with SR helpers %d, ignoring\n", 18476c836d96SSean Paul crtc->name, ret); 18486c836d96SSean Paul 18492048e328SMark Yao return 0; 18502048e328SMark Yao 18512048e328SMark Yao err_cleanup_crtc: 18522048e328SMark Yao drm_crtc_cleanup(crtc); 18532048e328SMark Yao err_cleanup_planes: 1854328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1855328b51c0SDouglas Anderson head) 18562048e328SMark Yao drm_plane_cleanup(plane); 18572048e328SMark Yao return ret; 18582048e328SMark Yao } 18592048e328SMark Yao 18602048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 18612048e328SMark Yao { 18622048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1863328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1864328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 18652048e328SMark Yao 18666c836d96SSean Paul drm_self_refresh_helper_cleanup(crtc); 18676c836d96SSean Paul 18682048e328SMark Yao of_node_put(crtc->port); 1869328b51c0SDouglas Anderson 1870328b51c0SDouglas Anderson /* 1871328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1872328b51c0SDouglas Anderson * 1873328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1874328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1875328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1876328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1877328b51c0SDouglas Anderson */ 1878328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1879328b51c0SDouglas Anderson head) 1880328b51c0SDouglas Anderson vop_plane_destroy(plane); 1881328b51c0SDouglas Anderson 1882328b51c0SDouglas Anderson /* 1883328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1884328b51c0SDouglas Anderson * references the CRTC. 1885328b51c0SDouglas Anderson */ 18862048e328SMark Yao drm_crtc_cleanup(crtc); 188747a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 18882048e328SMark Yao } 18892048e328SMark Yao 18902048e328SMark Yao static int vop_initial(struct vop *vop) 18912048e328SMark Yao { 18922048e328SMark Yao struct reset_control *ahb_rst; 18932048e328SMark Yao int i, ret; 18942048e328SMark Yao 18952048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 18962048e328SMark Yao if (IS_ERR(vop->hclk)) { 1897d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 18982048e328SMark Yao return PTR_ERR(vop->hclk); 18992048e328SMark Yao } 19002048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 19012048e328SMark Yao if (IS_ERR(vop->aclk)) { 1902d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 19032048e328SMark Yao return PTR_ERR(vop->aclk); 19042048e328SMark Yao } 19052048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 19062048e328SMark Yao if (IS_ERR(vop->dclk)) { 1907d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 19082048e328SMark Yao return PTR_ERR(vop->dclk); 19092048e328SMark Yao } 19102048e328SMark Yao 19115e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 19125e570373SJeffy Chen if (ret < 0) { 1913d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 19145e570373SJeffy Chen return ret; 19155e570373SJeffy Chen } 19165e570373SJeffy Chen 19172048e328SMark Yao ret = clk_prepare(vop->dclk); 19182048e328SMark Yao if (ret < 0) { 1919d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 19205e570373SJeffy Chen goto err_put_pm_runtime; 19212048e328SMark Yao } 19222048e328SMark Yao 1923d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1924d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 19252048e328SMark Yao if (ret < 0) { 1926d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 19272048e328SMark Yao goto err_unprepare_dclk; 19282048e328SMark Yao } 19292048e328SMark Yao 1930d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 19312048e328SMark Yao if (ret < 0) { 1932d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1933d7b53fd9SSjoerd Simons goto err_disable_hclk; 19342048e328SMark Yao } 1935d7b53fd9SSjoerd Simons 19362048e328SMark Yao /* 19372048e328SMark Yao * do hclk_reset, reset all vop registers. 19382048e328SMark Yao */ 19392048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 19402048e328SMark Yao if (IS_ERR(ahb_rst)) { 1941d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 19422048e328SMark Yao ret = PTR_ERR(ahb_rst); 1943d7b53fd9SSjoerd Simons goto err_disable_aclk; 19442048e328SMark Yao } 19452048e328SMark Yao reset_control_assert(ahb_rst); 19462048e328SMark Yao usleep_range(10, 20); 19472048e328SMark Yao reset_control_deassert(ahb_rst); 19482048e328SMark Yao 19495f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 19505f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 19515f9e93feSMarc Zyngier 195276f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 195376f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 19542048e328SMark Yao 19559a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 19569a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 19572048e328SMark Yao 19582b60e11dSSean Paul for (i = 0; i < vop->data->win_size; i++) { 19592b60e11dSSean Paul struct vop_win *vop_win = &vop->win[i]; 19602b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 19619dd2aca4SMark yao int channel = i * 2 + 1; 19622048e328SMark Yao 19639dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 19642b60e11dSSean Paul vop_win_disable(vop, vop_win); 196560b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 19662048e328SMark Yao } 19672048e328SMark Yao 19682048e328SMark Yao vop_cfg_done(vop); 19692048e328SMark Yao 19702048e328SMark Yao /* 19712048e328SMark Yao * do dclk_reset, let all config take affect. 19722048e328SMark Yao */ 19732048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 19742048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1975d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 19762048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1977d7b53fd9SSjoerd Simons goto err_disable_aclk; 19782048e328SMark Yao } 19792048e328SMark Yao reset_control_assert(vop->dclk_rst); 19802048e328SMark Yao usleep_range(10, 20); 19812048e328SMark Yao reset_control_deassert(vop->dclk_rst); 19822048e328SMark Yao 19832048e328SMark Yao clk_disable(vop->hclk); 1984d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 19852048e328SMark Yao 198631e980c5SMark Yao vop->is_enabled = false; 19872048e328SMark Yao 19885e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 19895e570373SJeffy Chen 19902048e328SMark Yao return 0; 19912048e328SMark Yao 1992d7b53fd9SSjoerd Simons err_disable_aclk: 1993d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 19942048e328SMark Yao err_disable_hclk: 1995d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 19962048e328SMark Yao err_unprepare_dclk: 19972048e328SMark Yao clk_unprepare(vop->dclk); 19985e570373SJeffy Chen err_put_pm_runtime: 19995e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 20002048e328SMark Yao return ret; 20012048e328SMark Yao } 20022048e328SMark Yao 20032048e328SMark Yao /* 20042048e328SMark Yao * Initialize the vop->win array elements. 20052048e328SMark Yao */ 20062048e328SMark Yao static void vop_win_init(struct vop *vop) 20072048e328SMark Yao { 20082048e328SMark Yao const struct vop_data *vop_data = vop->data; 20092048e328SMark Yao unsigned int i; 20102048e328SMark Yao 20112048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 20122048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 20132048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 20142048e328SMark Yao 20152048e328SMark Yao vop_win->data = win_data; 20162048e328SMark Yao vop_win->vop = vop; 2017ce6912b4SHeiko Stuebner 2018ce6912b4SHeiko Stuebner if (vop_data->win_yuv2yuv) 20191c21aa8fSDaniele Castagna vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 20202048e328SMark Yao } 20212048e328SMark Yao } 20222048e328SMark Yao 202369c34e41SYakir Yang /** 2024459b086dSJeffy Chen * rockchip_drm_wait_vact_end 202569c34e41SYakir Yang * @crtc: CRTC to enable line flag 202669c34e41SYakir Yang * @mstimeout: millisecond for timeout 202769c34e41SYakir Yang * 2028459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 202969c34e41SYakir Yang * 203069c34e41SYakir Yang * Returns: 203169c34e41SYakir Yang * Zero on success, negative errno on failure. 203269c34e41SYakir Yang */ 2033459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 203469c34e41SYakir Yang { 203569c34e41SYakir Yang struct vop *vop = to_vop(crtc); 203669c34e41SYakir Yang unsigned long jiffies_left; 2037e334d48bSzain wang int ret = 0; 203869c34e41SYakir Yang 203969c34e41SYakir Yang if (!crtc || !vop->is_enabled) 204069c34e41SYakir Yang return -ENODEV; 204169c34e41SYakir Yang 2042e334d48bSzain wang mutex_lock(&vop->vop_lock); 2043e334d48bSzain wang if (mstimeout <= 0) { 2044e334d48bSzain wang ret = -EINVAL; 2045e334d48bSzain wang goto out; 2046e334d48bSzain wang } 204769c34e41SYakir Yang 2048e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 2049e334d48bSzain wang ret = -EBUSY; 2050e334d48bSzain wang goto out; 2051e334d48bSzain wang } 205269c34e41SYakir Yang 205369c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 2054459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 205569c34e41SYakir Yang 205669c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 205769c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 205869c34e41SYakir Yang vop_line_flag_irq_disable(vop); 205969c34e41SYakir Yang 206069c34e41SYakir Yang if (jiffies_left == 0) { 2061d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2062e334d48bSzain wang ret = -ETIMEDOUT; 2063e334d48bSzain wang goto out; 206469c34e41SYakir Yang } 206569c34e41SYakir Yang 2066e334d48bSzain wang out: 2067e334d48bSzain wang mutex_unlock(&vop->vop_lock); 2068e334d48bSzain wang return ret; 206969c34e41SYakir Yang } 2070459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 207169c34e41SYakir Yang 20722048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 20732048e328SMark Yao { 20742048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 20752048e328SMark Yao const struct vop_data *vop_data; 20762048e328SMark Yao struct drm_device *drm_dev = data; 20772048e328SMark Yao struct vop *vop; 20782048e328SMark Yao struct resource *res; 20793ea68922SHeiko Stuebner int ret, irq; 20802048e328SMark Yao 2081a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 20822048e328SMark Yao if (!vop_data) 20832048e328SMark Yao return -ENODEV; 20842048e328SMark Yao 20852048e328SMark Yao /* Allocate vop struct and its vop_win array */ 208629adeb4fSGustavo A. R. Silva vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 208729adeb4fSGustavo A. R. Silva GFP_KERNEL); 20882048e328SMark Yao if (!vop) 20892048e328SMark Yao return -ENOMEM; 20902048e328SMark Yao 20912048e328SMark Yao vop->dev = dev; 20922048e328SMark Yao vop->data = vop_data; 20932048e328SMark Yao vop->drm_dev = drm_dev; 20942048e328SMark Yao dev_set_drvdata(dev, vop); 20952048e328SMark Yao 20962048e328SMark Yao vop_win_init(vop); 20972048e328SMark Yao 20982048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 20992048e328SMark Yao vop->len = resource_size(res); 21002048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 21012048e328SMark Yao if (IS_ERR(vop->regs)) 21022048e328SMark Yao return PTR_ERR(vop->regs); 21032048e328SMark Yao 2104b23ab6acSEzequiel Garcia res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2105b23ab6acSEzequiel Garcia if (res) { 2106b23ab6acSEzequiel Garcia if (!vop_data->lut_size) { 2107b23ab6acSEzequiel Garcia DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); 2108b23ab6acSEzequiel Garcia return -EINVAL; 2109b23ab6acSEzequiel Garcia } 2110b23ab6acSEzequiel Garcia vop->lut_regs = devm_ioremap_resource(dev, res); 2111b23ab6acSEzequiel Garcia if (IS_ERR(vop->lut_regs)) 2112b23ab6acSEzequiel Garcia return PTR_ERR(vop->lut_regs); 2113b23ab6acSEzequiel Garcia } 2114b23ab6acSEzequiel Garcia 21152048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 21162048e328SMark Yao if (!vop->regsbak) 21172048e328SMark Yao return -ENOMEM; 21182048e328SMark Yao 21193ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 21203ea68922SHeiko Stuebner if (irq < 0) { 2121d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 21223ea68922SHeiko Stuebner return irq; 21232048e328SMark Yao } 21243ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 21252048e328SMark Yao 21262048e328SMark Yao spin_lock_init(&vop->reg_lock); 21272048e328SMark Yao spin_lock_init(&vop->irq_lock); 2128e334d48bSzain wang mutex_init(&vop->vop_lock); 21292048e328SMark Yao 21302048e328SMark Yao ret = vop_create_crtc(vop); 21312048e328SMark Yao if (ret) 21325f9e93feSMarc Zyngier return ret; 21332048e328SMark Yao 21342048e328SMark Yao pm_runtime_enable(&pdev->dev); 21355182c1a5SYakir Yang 21365e570373SJeffy Chen ret = vop_initial(vop); 21375e570373SJeffy Chen if (ret < 0) { 2138d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 2139d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 21405e570373SJeffy Chen goto err_disable_pm_runtime; 21415e570373SJeffy Chen } 21425e570373SJeffy Chen 21435f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 21445f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 21455f9e93feSMarc Zyngier if (ret) 21465f9e93feSMarc Zyngier goto err_disable_pm_runtime; 21475f9e93feSMarc Zyngier 21481f0f0151SSandy Huang if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 21491f0f0151SSandy Huang vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 21501f0f0151SSandy Huang if (IS_ERR(vop->rgb)) { 21511f0f0151SSandy Huang ret = PTR_ERR(vop->rgb); 21521f0f0151SSandy Huang goto err_disable_pm_runtime; 21531f0f0151SSandy Huang } 21541f0f0151SSandy Huang } 21551f0f0151SSandy Huang 21562048e328SMark Yao return 0; 21578c763c9bSSean Paul 21585e570373SJeffy Chen err_disable_pm_runtime: 21595e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 21605e570373SJeffy Chen vop_destroy_crtc(vop); 21618c763c9bSSean Paul return ret; 21622048e328SMark Yao } 21632048e328SMark Yao 21642048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 21652048e328SMark Yao { 21662048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 21672048e328SMark Yao 21681f0f0151SSandy Huang if (vop->rgb) 21691f0f0151SSandy Huang rockchip_rgb_fini(vop->rgb); 21701f0f0151SSandy Huang 21712048e328SMark Yao pm_runtime_disable(dev); 21722048e328SMark Yao vop_destroy_crtc(vop); 2173ec6e7767SJeffy Chen 2174ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 2175ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 2176ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 21772048e328SMark Yao } 21782048e328SMark Yao 2179a67719d1SMark Yao const struct component_ops vop_component_ops = { 21802048e328SMark Yao .bind = vop_bind, 21812048e328SMark Yao .unbind = vop_unbind, 21822048e328SMark Yao }; 218354255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 2184