19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22048e328SMark Yao /* 32048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 42048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 52048e328SMark Yao */ 62048e328SMark Yao 7c2156ccdSSam Ravnborg #include <linux/clk.h> 8c2156ccdSSam Ravnborg #include <linux/component.h> 9c2156ccdSSam Ravnborg #include <linux/delay.h> 10c2156ccdSSam Ravnborg #include <linux/iopoll.h> 11c2156ccdSSam Ravnborg #include <linux/kernel.h> 12c2156ccdSSam Ravnborg #include <linux/module.h> 13c2156ccdSSam Ravnborg #include <linux/of.h> 14c2156ccdSSam Ravnborg #include <linux/of_device.h> 15c2156ccdSSam Ravnborg #include <linux/overflow.h> 16c2156ccdSSam Ravnborg #include <linux/platform_device.h> 17c2156ccdSSam Ravnborg #include <linux/pm_runtime.h> 18c2156ccdSSam Ravnborg #include <linux/reset.h> 19c2156ccdSSam Ravnborg 202048e328SMark Yao #include <drm/drm.h> 2163ebb9faSMark Yao #include <drm/drm_atomic.h> 2215609559SEnric Balletbo i Serra #include <drm/drm_atomic_uapi.h> 232048e328SMark Yao #include <drm/drm_crtc.h> 2447a7eb45STomasz Figa #include <drm/drm_flip_work.h> 25c2156ccdSSam Ravnborg #include <drm/drm_fourcc.h> 2663d5e06aSHeiko Stuebner #include <drm/drm_gem_framebuffer_helper.h> 272048e328SMark Yao #include <drm/drm_plane_helper.h> 28fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 296c836d96SSean Paul #include <drm/drm_self_refresh_helper.h> 30c2156ccdSSam Ravnborg #include <drm/drm_vblank.h> 31c2156ccdSSam Ravnborg 326cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 333190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 346cca3869SSean Paul #endif 352048e328SMark Yao 362048e328SMark Yao #include "rockchip_drm_drv.h" 372048e328SMark Yao #include "rockchip_drm_gem.h" 382048e328SMark Yao #include "rockchip_drm_fb.h" 392048e328SMark Yao #include "rockchip_drm_vop.h" 401f0f0151SSandy Huang #include "rockchip_rgb.h" 412048e328SMark Yao 422996fb75SEzequiel Garcia #define VOP_WIN_SET(vop, win, name, v) \ 439a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 442996fb75SEzequiel Garcia #define VOP_SCL_SET(vop, win, name, v) \ 459a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 462996fb75SEzequiel Garcia #define VOP_SCL_SET_EXT(vop, win, name, v) \ 479a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 489a61c54bSMark yao win->base, ~0, v, #name) 49ac6560dfSMark yao 502996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 511c21aa8fSDaniele Castagna do { \ 521c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 531c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 541c21aa8fSDaniele Castagna } while (0) 551c21aa8fSDaniele Castagna 562996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 571c21aa8fSDaniele Castagna do { \ 581c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 591c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 601c21aa8fSDaniele Castagna } while (0) 611c21aa8fSDaniele Castagna 62ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 639a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 649a61c54bSMark yao 659a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 669a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 67ac6560dfSMark yao 68dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 69dbb3d944SMark Yao do { \ 70c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 71dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 72c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 73dbb3d944SMark Yao reg |= (v) << i; \ 74c7647f86SJohn Keeping mask |= 1 << i; \ 75dbb3d944SMark Yao } \ 76c7647f86SJohn Keeping } \ 77ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 78dbb3d944SMark Yao } while (0) 79dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 80dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 81dbb3d944SMark Yao 822996fb75SEzequiel Garcia #define VOP_WIN_GET(vop, win, name) \ 83cc8f1299SJohn Keeping vop_read_reg(vop, win->base, &win->phy->name) 842048e328SMark Yao 85677e8bbcSDaniele Castagna #define VOP_WIN_HAS_REG(win, name) \ 86677e8bbcSDaniele Castagna (!!(win->phy->name.mask)) 87677e8bbcSDaniele Castagna 882048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 892048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 902048e328SMark Yao 9158badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 9258badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 9358badaa7SKristian H. Kristensen 942048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 952048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 962048e328SMark Yao 971c21aa8fSDaniele Castagna /* 981c21aa8fSDaniele Castagna * The coefficients of the following matrix are all fixed points. 991c21aa8fSDaniele Castagna * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 1001c21aa8fSDaniele Castagna * They are all represented in two's complement. 1011c21aa8fSDaniele Castagna */ 1021c21aa8fSDaniele Castagna static const uint32_t bt601_yuv2rgb[] = { 1031c21aa8fSDaniele Castagna 0x4A8, 0x0, 0x662, 1041c21aa8fSDaniele Castagna 0x4A8, 0x1E6F, 0x1CBF, 1051c21aa8fSDaniele Castagna 0x4A8, 0x812, 0x0, 1061c21aa8fSDaniele Castagna 0x321168, 0x0877CF, 0x2EB127 1071c21aa8fSDaniele Castagna }; 1081c21aa8fSDaniele Castagna 10947a7eb45STomasz Figa enum vop_pending { 11047a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 11147a7eb45STomasz Figa }; 11247a7eb45STomasz Figa 1132048e328SMark Yao struct vop_win { 1142048e328SMark Yao struct drm_plane base; 1152048e328SMark Yao const struct vop_win_data *data; 1161c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *yuv2yuv_data; 1172048e328SMark Yao struct vop *vop; 1182048e328SMark Yao }; 1192048e328SMark Yao 1201f0f0151SSandy Huang struct rockchip_rgb; 1212048e328SMark Yao struct vop { 1222048e328SMark Yao struct drm_crtc crtc; 1232048e328SMark Yao struct device *dev; 1242048e328SMark Yao struct drm_device *drm_dev; 12531e980c5SMark Yao bool is_enabled; 1262048e328SMark Yao 1271067219bSMark Yao struct completion dsp_hold_completion; 128bed030a4SSean Paul unsigned int win_enabled; 1294f9d39a7SDaniel Vetter 1304f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 13163ebb9faSMark Yao struct drm_pending_vblank_event *event; 1322048e328SMark Yao 13347a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 13447a7eb45STomasz Figa unsigned long pending; 13547a7eb45STomasz Figa 13669c34e41SYakir Yang struct completion line_flag_completion; 13769c34e41SYakir Yang 1382048e328SMark Yao const struct vop_data *data; 1392048e328SMark Yao 1402048e328SMark Yao uint32_t *regsbak; 1412048e328SMark Yao void __iomem *regs; 142b23ab6acSEzequiel Garcia void __iomem *lut_regs; 1432048e328SMark Yao 1442048e328SMark Yao /* physical map length of vop register */ 1452048e328SMark Yao uint32_t len; 1462048e328SMark Yao 1472048e328SMark Yao /* one time only one process allowed to config the register */ 1482048e328SMark Yao spinlock_t reg_lock; 1492048e328SMark Yao /* lock vop irq reg */ 1502048e328SMark Yao spinlock_t irq_lock; 151e334d48bSzain wang /* protects crtc enable/disable */ 152e334d48bSzain wang struct mutex vop_lock; 1532048e328SMark Yao 1542048e328SMark Yao unsigned int irq; 1552048e328SMark Yao 1562048e328SMark Yao /* vop AHP clk */ 1572048e328SMark Yao struct clk *hclk; 1582048e328SMark Yao /* vop dclk */ 1592048e328SMark Yao struct clk *dclk; 1602048e328SMark Yao /* vop share memory frequency */ 1612048e328SMark Yao struct clk *aclk; 1622048e328SMark Yao 1632048e328SMark Yao /* vop dclk reset */ 1642048e328SMark Yao struct reset_control *dclk_rst; 1652048e328SMark Yao 1661f0f0151SSandy Huang /* optional internal rgb encoder */ 1671f0f0151SSandy Huang struct rockchip_rgb *rgb; 1681f0f0151SSandy Huang 1692048e328SMark Yao struct vop_win win[]; 1702048e328SMark Yao }; 1712048e328SMark Yao 1722048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1732048e328SMark Yao { 1742048e328SMark Yao writel(v, vop->regs + offset); 1752048e328SMark Yao vop->regsbak[offset >> 2] = v; 1762048e328SMark Yao } 1772048e328SMark Yao 1782048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1792048e328SMark Yao { 1802048e328SMark Yao return readl(vop->regs + offset); 1812048e328SMark Yao } 1822048e328SMark Yao 1832048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1842048e328SMark Yao const struct vop_reg *reg) 1852048e328SMark Yao { 1862048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 1872048e328SMark Yao } 1882048e328SMark Yao 1899a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 1909a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 1919a61c54bSMark yao const char *reg_name) 1922048e328SMark Yao { 1939a61c54bSMark yao int offset, mask, shift; 194d49463ecSMark Yao 1959a61c54bSMark yao if (!reg || !reg->mask) { 196d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 1979a61c54bSMark yao return; 1989a61c54bSMark yao } 1999a61c54bSMark yao 2009a61c54bSMark yao offset = reg->offset + _offset; 2019a61c54bSMark yao mask = reg->mask & _mask; 2029a61c54bSMark yao shift = reg->shift; 2039a61c54bSMark yao 2049a61c54bSMark yao if (reg->write_mask) { 205d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 206d49463ecSMark Yao } else { 2072048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 2082048e328SMark Yao 209d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 210d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 2112048e328SMark Yao } 2122048e328SMark Yao 2139a61c54bSMark yao if (reg->relaxed) 214d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 215d49463ecSMark Yao else 216d49463ecSMark Yao writel(v, vop->regs + offset); 2172048e328SMark Yao } 2182048e328SMark Yao 219dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 220dbb3d944SMark Yao const struct vop_reg *reg, int type) 221dbb3d944SMark Yao { 222dbb3d944SMark Yao uint32_t i, ret = 0; 223dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 224dbb3d944SMark Yao 225dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 226dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 227dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 228dbb3d944SMark Yao } 229dbb3d944SMark Yao 230dbb3d944SMark Yao return ret; 231dbb3d944SMark Yao } 232dbb3d944SMark Yao 2330cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2340cf33fe3SMark Yao { 2359a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2360cf33fe3SMark Yao } 2370cf33fe3SMark Yao 23885a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 23985a359f2STomasz Figa { 24085a359f2STomasz Figa switch (format) { 24185a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 24285a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 24385a359f2STomasz Figa case DRM_FORMAT_BGR888: 24485a359f2STomasz Figa case DRM_FORMAT_BGR565: 24585a359f2STomasz Figa return true; 24685a359f2STomasz Figa default: 24785a359f2STomasz Figa return false; 24885a359f2STomasz Figa } 24985a359f2STomasz Figa } 25085a359f2STomasz Figa 2512048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2522048e328SMark Yao { 2532048e328SMark Yao switch (format) { 2542048e328SMark Yao case DRM_FORMAT_XRGB8888: 2552048e328SMark Yao case DRM_FORMAT_ARGB8888: 25685a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 25785a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2582048e328SMark Yao return VOP_FMT_ARGB8888; 2592048e328SMark Yao case DRM_FORMAT_RGB888: 26085a359f2STomasz Figa case DRM_FORMAT_BGR888: 2612048e328SMark Yao return VOP_FMT_RGB888; 2622048e328SMark Yao case DRM_FORMAT_RGB565: 26385a359f2STomasz Figa case DRM_FORMAT_BGR565: 2642048e328SMark Yao return VOP_FMT_RGB565; 2652048e328SMark Yao case DRM_FORMAT_NV12: 2662048e328SMark Yao return VOP_FMT_YUV420SP; 2672048e328SMark Yao case DRM_FORMAT_NV16: 2682048e328SMark Yao return VOP_FMT_YUV422SP; 2692048e328SMark Yao case DRM_FORMAT_NV24: 2702048e328SMark Yao return VOP_FMT_YUV444SP; 2712048e328SMark Yao default: 272ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2732048e328SMark Yao return -EINVAL; 2742048e328SMark Yao } 2752048e328SMark Yao } 2762048e328SMark Yao 2774c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 2784c156c21SMark Yao uint32_t dst, bool is_horizontal, 2794c156c21SMark Yao int vsu_mode, int *vskiplines) 2804c156c21SMark Yao { 2814c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 2824c156c21SMark Yao 283ce91d373SJeffy Chen if (vskiplines) 284ce91d373SJeffy Chen *vskiplines = 0; 285ce91d373SJeffy Chen 2864c156c21SMark Yao if (is_horizontal) { 2874c156c21SMark Yao if (mode == SCALE_UP) 2884c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2894c156c21SMark Yao else if (mode == SCALE_DOWN) 2904c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 2914c156c21SMark Yao } else { 2924c156c21SMark Yao if (mode == SCALE_UP) { 2934c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 2944c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 2954c156c21SMark Yao else 2964c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 2974c156c21SMark Yao } else if (mode == SCALE_DOWN) { 2984c156c21SMark Yao if (vskiplines) { 2994c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 3004c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 3014c156c21SMark Yao *vskiplines); 3024c156c21SMark Yao } else { 3034c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3044c156c21SMark Yao } 3054c156c21SMark Yao } 3064c156c21SMark Yao } 3074c156c21SMark Yao 3084c156c21SMark Yao return val; 3094c156c21SMark Yao } 3104c156c21SMark Yao 3114c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3124c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 31345babef0SMaxime Ripard uint32_t dst_h, const struct drm_format_info *info) 3144c156c21SMark Yao { 3154c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3164c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3174c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 318d8bd23d9SAyan Kumar Halder bool is_yuv = false; 319f3e9632cSMaxime Ripard uint16_t cbcr_src_w = src_w / info->hsub; 320f3e9632cSMaxime Ripard uint16_t cbcr_src_h = src_h / info->vsub; 3214c156c21SMark Yao uint16_t vsu_mode; 3224c156c21SMark Yao uint16_t lb_mode; 3234c156c21SMark Yao uint32_t val; 324ce91d373SJeffy Chen int vskiplines; 3254c156c21SMark Yao 326d8bd23d9SAyan Kumar Halder if (info->is_yuv) 327d8bd23d9SAyan Kumar Halder is_yuv = true; 328d8bd23d9SAyan Kumar Halder 3294c156c21SMark Yao if (dst_w > 3840) { 330ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3314c156c21SMark Yao return; 3324c156c21SMark Yao } 3334c156c21SMark Yao 3341194fffbSMark Yao if (!win->phy->scl->ext) { 3351194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3361194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3371194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3381194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3391194fffbSMark Yao if (is_yuv) { 3401194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 341ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3421194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 343ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3441194fffbSMark Yao } 3451194fffbSMark Yao return; 3461194fffbSMark Yao } 3471194fffbSMark Yao 3484c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3494c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3504c156c21SMark Yao 3514c156c21SMark Yao if (is_yuv) { 3524c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3534c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3544c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3554c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3564c156c21SMark Yao else 3574c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3584c156c21SMark Yao } else { 3594c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3604c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3614c156c21SMark Yao else 3624c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 3634c156c21SMark Yao } 3644c156c21SMark Yao 3651194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 3664c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 3674c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 368ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 3694c156c21SMark Yao return; 3704c156c21SMark Yao } 3714c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 372ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 3734c156c21SMark Yao return; 3744c156c21SMark Yao } 3754c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3764c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 3774c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 3784c156c21SMark Yao } else { 3794c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 3804c156c21SMark Yao } 3814c156c21SMark Yao 3824c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 3834c156c21SMark Yao true, 0, NULL); 3844c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 3854c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 3864c156c21SMark Yao false, vsu_mode, &vskiplines); 3874c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 3884c156c21SMark Yao 3891194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 3901194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 3914c156c21SMark Yao 3921194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 3931194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 3941194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 3951194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 3961194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 3974c156c21SMark Yao if (is_yuv) { 3984c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 3994c156c21SMark Yao dst_w, true, 0, NULL); 4004c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 4014c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 4024c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 4034c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 4044c156c21SMark Yao 4051194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 4061194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4071194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4081194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4091194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4101194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4111194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4124c156c21SMark Yao } 4134c156c21SMark Yao } 4144c156c21SMark Yao 4151067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4161067219bSMark Yao { 4171067219bSMark Yao unsigned long flags; 4181067219bSMark Yao 4191067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4201067219bSMark Yao return; 4211067219bSMark Yao 4221067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4231067219bSMark Yao 424fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 425dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4261067219bSMark Yao 4271067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4281067219bSMark Yao } 4291067219bSMark Yao 4301067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4311067219bSMark Yao { 4321067219bSMark Yao unsigned long flags; 4331067219bSMark Yao 4341067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4351067219bSMark Yao return; 4361067219bSMark Yao 4371067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4381067219bSMark Yao 439dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4401067219bSMark Yao 4411067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4421067219bSMark Yao } 4431067219bSMark Yao 44469c34e41SYakir Yang /* 44569c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 44669c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 44769c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 44869c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 44969c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 45069c34e41SYakir Yang * 45169c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 45269c34e41SYakir Yang * Interrupts 45369c34e41SYakir Yang * LINE_FLAG -------------------------------+ 45469c34e41SYakir Yang * FRAME_SYNC ----+ | 45569c34e41SYakir Yang * | | 45669c34e41SYakir Yang * v v 45769c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 45869c34e41SYakir Yang * ^ ^ ^ ^ 45969c34e41SYakir Yang * | | | | 46069c34e41SYakir Yang * | | | | 46169c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 46269c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 46369c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 46469c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 46569c34e41SYakir Yang */ 46669c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 46769c34e41SYakir Yang { 46869c34e41SYakir Yang uint32_t line_flag_irq; 46969c34e41SYakir Yang unsigned long flags; 47069c34e41SYakir Yang 47169c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 47269c34e41SYakir Yang 47369c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 47469c34e41SYakir Yang 47569c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 47669c34e41SYakir Yang 47769c34e41SYakir Yang return !!line_flag_irq; 47869c34e41SYakir Yang } 47969c34e41SYakir Yang 480459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 48169c34e41SYakir Yang { 48269c34e41SYakir Yang unsigned long flags; 48369c34e41SYakir Yang 48469c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 48569c34e41SYakir Yang return; 48669c34e41SYakir Yang 48769c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 48869c34e41SYakir Yang 489fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 49069c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 49169c34e41SYakir Yang 49269c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 49369c34e41SYakir Yang } 49469c34e41SYakir Yang 49569c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 49669c34e41SYakir Yang { 49769c34e41SYakir Yang unsigned long flags; 49869c34e41SYakir Yang 49969c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 50069c34e41SYakir Yang return; 50169c34e41SYakir Yang 50269c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 50369c34e41SYakir Yang 50469c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 50569c34e41SYakir Yang 50669c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 50769c34e41SYakir Yang } 50869c34e41SYakir Yang 509e2810a71SHeiko Stuebner static int vop_core_clks_enable(struct vop *vop) 510e2810a71SHeiko Stuebner { 511e2810a71SHeiko Stuebner int ret; 512e2810a71SHeiko Stuebner 513e2810a71SHeiko Stuebner ret = clk_enable(vop->hclk); 514e2810a71SHeiko Stuebner if (ret < 0) 515e2810a71SHeiko Stuebner return ret; 516e2810a71SHeiko Stuebner 517e2810a71SHeiko Stuebner ret = clk_enable(vop->aclk); 518e2810a71SHeiko Stuebner if (ret < 0) 519e2810a71SHeiko Stuebner goto err_disable_hclk; 520e2810a71SHeiko Stuebner 521e2810a71SHeiko Stuebner return 0; 522e2810a71SHeiko Stuebner 523e2810a71SHeiko Stuebner err_disable_hclk: 524e2810a71SHeiko Stuebner clk_disable(vop->hclk); 525e2810a71SHeiko Stuebner return ret; 526e2810a71SHeiko Stuebner } 527e2810a71SHeiko Stuebner 528e2810a71SHeiko Stuebner static void vop_core_clks_disable(struct vop *vop) 529e2810a71SHeiko Stuebner { 530e2810a71SHeiko Stuebner clk_disable(vop->aclk); 531e2810a71SHeiko Stuebner clk_disable(vop->hclk); 532e2810a71SHeiko Stuebner } 533e2810a71SHeiko Stuebner 5342b60e11dSSean Paul static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 535e9abc611SJonas Karlman { 5362b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 5372b60e11dSSean Paul 538e9abc611SJonas Karlman if (win->phy->scl && win->phy->scl->ext) { 539e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 540e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 541e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 542e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 543e9abc611SJonas Karlman } 544e9abc611SJonas Karlman 545e9abc611SJonas Karlman VOP_WIN_SET(vop, win, enable, 0); 546bed030a4SSean Paul vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 547e9abc611SJonas Karlman } 548e9abc611SJonas Karlman 5496c836d96SSean Paul static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 5502048e328SMark Yao { 5512048e328SMark Yao struct vop *vop = to_vop(crtc); 55264d77564SMark yao int ret, i; 5532048e328SMark Yao 5545d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5555d82d1a7SMark Yao if (ret < 0) { 556d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 5575e570373SJeffy Chen return ret; 5585d82d1a7SMark Yao } 5595d82d1a7SMark Yao 560e2810a71SHeiko Stuebner ret = vop_core_clks_enable(vop); 56139a9ad8fSSean Paul if (WARN_ON(ret < 0)) 56239a9ad8fSSean Paul goto err_put_pm_runtime; 5632048e328SMark Yao 5642048e328SMark Yao ret = clk_enable(vop->dclk); 56539a9ad8fSSean Paul if (WARN_ON(ret < 0)) 566e2810a71SHeiko Stuebner goto err_disable_core; 5672048e328SMark Yao 5682048e328SMark Yao /* 5692048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 5702048e328SMark Yao * automatically with this master device via common driver code. 5712048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 5722048e328SMark Yao * mapping. 5732048e328SMark Yao */ 5742048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 5752048e328SMark Yao if (ret) { 576d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 577d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 578e2810a71SHeiko Stuebner goto err_disable_dclk; 5792048e328SMark Yao } 5802048e328SMark Yao 58176f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 58276f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 58376f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 58476f1416eSMarc Zyngier 58564d77564SMark yao /* 58664d77564SMark yao * We need to make sure that all windows are disabled before we 58764d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 58864d77564SMark yao * buffer later. 5896c836d96SSean Paul * 5906c836d96SSean Paul * In the case of enable-after-PSR, we don't need to worry about this 5916c836d96SSean Paul * case since the buffer is guaranteed to be valid and disabling the 5926c836d96SSean Paul * window will result in screen glitches on PSR exit. 59364d77564SMark yao */ 5946c836d96SSean Paul if (!old_state || !old_state->self_refresh_active) { 59564d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 59664d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 59764d77564SMark yao 5982b60e11dSSean Paul vop_win_disable(vop, vop_win); 59964d77564SMark yao } 6006c836d96SSean Paul } 60176f1416eSMarc Zyngier spin_unlock(&vop->reg_lock); 60264d77564SMark yao 60317a794d7SChris Zhong vop_cfg_done(vop); 60417a794d7SChris Zhong 60552ab7891SMark Yao /* 60652ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 60752ab7891SMark Yao */ 60852ab7891SMark Yao vop->is_enabled = true; 60952ab7891SMark Yao 6102048e328SMark Yao spin_lock(&vop->reg_lock); 6112048e328SMark Yao 6129a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6132048e328SMark Yao 6142048e328SMark Yao spin_unlock(&vop->reg_lock); 6152048e328SMark Yao 616b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6172048e328SMark Yao 61839a9ad8fSSean Paul return 0; 6192048e328SMark Yao 6202048e328SMark Yao err_disable_dclk: 6212048e328SMark Yao clk_disable(vop->dclk); 622e2810a71SHeiko Stuebner err_disable_core: 623e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 62439a9ad8fSSean Paul err_put_pm_runtime: 62539a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 62639a9ad8fSSean Paul return ret; 6272048e328SMark Yao } 6282048e328SMark Yao 629bed030a4SSean Paul static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 630bed030a4SSean Paul { 631bed030a4SSean Paul struct vop *vop = to_vop(crtc); 632bed030a4SSean Paul int i; 633bed030a4SSean Paul 634bed030a4SSean Paul spin_lock(&vop->reg_lock); 635bed030a4SSean Paul 636bed030a4SSean Paul for (i = 0; i < vop->data->win_size; i++) { 637bed030a4SSean Paul struct vop_win *vop_win = &vop->win[i]; 638bed030a4SSean Paul const struct vop_win_data *win = vop_win->data; 639bed030a4SSean Paul 640bed030a4SSean Paul VOP_WIN_SET(vop, win, enable, 641bed030a4SSean Paul enabled && (vop->win_enabled & BIT(i))); 642bed030a4SSean Paul } 643bed030a4SSean Paul vop_cfg_done(vop); 644bed030a4SSean Paul 645bed030a4SSean Paul spin_unlock(&vop->reg_lock); 646bed030a4SSean Paul } 647bed030a4SSean Paul 64864581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 64964581714SLaurent Pinchart struct drm_crtc_state *old_state) 6502048e328SMark Yao { 6512048e328SMark Yao struct vop *vop = to_vop(crtc); 6522048e328SMark Yao 653893b6cadSDaniel Vetter WARN_ON(vop->event); 654893b6cadSDaniel Vetter 655bed030a4SSean Paul if (crtc->state->self_refresh_active) 656bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, false); 657bed030a4SSean Paul 658e334d48bSzain wang mutex_lock(&vop->vop_lock); 6596c836d96SSean Paul 660b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 6612048e328SMark Yao 662bed030a4SSean Paul if (crtc->state->self_refresh_active) 663bed030a4SSean Paul goto out; 664bed030a4SSean Paul 6652048e328SMark Yao /* 6661067219bSMark Yao * Vop standby will take effect at end of current frame, 6671067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 6681067219bSMark Yao * 6691067219bSMark Yao * we must wait standby complete when we want to disable aclk, 6701067219bSMark Yao * if not, memory bus maybe dead. 6712048e328SMark Yao */ 6721067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 6731067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 6741067219bSMark Yao 6752048e328SMark Yao spin_lock(&vop->reg_lock); 6762048e328SMark Yao 6779a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6782048e328SMark Yao 6792048e328SMark Yao spin_unlock(&vop->reg_lock); 68052ab7891SMark Yao 6811067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 6822048e328SMark Yao 6831067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 6841067219bSMark Yao 6851067219bSMark Yao vop->is_enabled = false; 6861067219bSMark Yao 6871067219bSMark Yao /* 6881067219bSMark Yao * vop standby complete, so iommu detach is safe. 6891067219bSMark Yao */ 6902048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 6912048e328SMark Yao 6921067219bSMark Yao clk_disable(vop->dclk); 693e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 6945d82d1a7SMark Yao pm_runtime_put(vop->dev); 695bed030a4SSean Paul 696bed030a4SSean Paul out: 697e334d48bSzain wang mutex_unlock(&vop->vop_lock); 698893b6cadSDaniel Vetter 699893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 700893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 701893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 702893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 703893b6cadSDaniel Vetter 704893b6cadSDaniel Vetter crtc->state->event = NULL; 705893b6cadSDaniel Vetter } 7062048e328SMark Yao } 7072048e328SMark Yao 70863ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 7092048e328SMark Yao { 71063ebb9faSMark Yao drm_plane_cleanup(plane); 7112048e328SMark Yao } 7122048e328SMark Yao 71363ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 71463ebb9faSMark Yao struct drm_plane_state *state) 7152048e328SMark Yao { 71663ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 71792915da6SJohn Keeping struct drm_crtc_state *crtc_state; 71863ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 7192048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 7202048e328SMark Yao const struct vop_win_data *win = vop_win->data; 7212048e328SMark Yao int ret; 7224c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 7234c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7244c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 7254c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7262048e328SMark Yao 72763ebb9faSMark Yao if (!crtc || !fb) 728d47a7246STomasz Figa return 0; 72992915da6SJohn Keeping 73092915da6SJohn Keeping crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 73192915da6SJohn Keeping if (WARN_ON(!crtc_state)) 73292915da6SJohn Keeping return -EINVAL; 73392915da6SJohn Keeping 73481af63a4SVille Syrjälä ret = drm_atomic_helper_check_plane_state(state, crtc_state, 735f9b96be0SVille Syrjälä min_scale, max_scale, 736f9b96be0SVille Syrjälä true, true); 7372048e328SMark Yao if (ret) 7382048e328SMark Yao return ret; 7392048e328SMark Yao 740f9b96be0SVille Syrjälä if (!state->visible) 741d47a7246STomasz Figa return 0; 7422048e328SMark Yao 743438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 744d47a7246STomasz Figa if (ret < 0) 745d47a7246STomasz Figa return ret; 74684c7f8caSMark Yao 74784c7f8caSMark Yao /* 74884c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 74984c7f8caSMark Yao * need align with 2 pixel. 75084c7f8caSMark Yao */ 751d8bd23d9SAyan Kumar Halder if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 752d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 75363ebb9faSMark Yao return -EINVAL; 754d415fb87SMark yao } 75563ebb9faSMark Yao 756677e8bbcSDaniele Castagna if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 757677e8bbcSDaniele Castagna DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 758677e8bbcSDaniele Castagna return -EINVAL; 759677e8bbcSDaniele Castagna } 760677e8bbcSDaniele Castagna 76163ebb9faSMark Yao return 0; 76284c7f8caSMark Yao } 76384c7f8caSMark Yao 76463ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 76563ebb9faSMark Yao struct drm_plane_state *old_state) 76663ebb9faSMark Yao { 76763ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 76863ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 7692048e328SMark Yao 77063ebb9faSMark Yao if (!old_state->crtc) 77163ebb9faSMark Yao return; 7722048e328SMark Yao 77363ebb9faSMark Yao spin_lock(&vop->reg_lock); 7742048e328SMark Yao 7752b60e11dSSean Paul vop_win_disable(vop, vop_win); 7762048e328SMark Yao 77763ebb9faSMark Yao spin_unlock(&vop->reg_lock); 77863ebb9faSMark Yao } 77963ebb9faSMark Yao 78063ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 78163ebb9faSMark Yao struct drm_plane_state *old_state) 78263ebb9faSMark Yao { 78363ebb9faSMark Yao struct drm_plane_state *state = plane->state; 78463ebb9faSMark Yao struct drm_crtc *crtc = state->crtc; 78563ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 78663ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 7871c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 78863ebb9faSMark Yao struct vop *vop = to_vop(state->crtc); 78963ebb9faSMark Yao struct drm_framebuffer *fb = state->fb; 79063ebb9faSMark Yao unsigned int actual_w, actual_h; 79163ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 79263ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 793ac92028eSVille Syrjälä struct drm_rect *src = &state->src; 794ac92028eSVille Syrjälä struct drm_rect *dest = &state->dst; 79563ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 79663ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 79763ebb9faSMark Yao unsigned long offset; 79863ebb9faSMark Yao dma_addr_t dma_addr; 79963ebb9faSMark Yao uint32_t val; 80063ebb9faSMark Yao bool rb_swap; 80158badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 802d47a7246STomasz Figa int format; 8031c21aa8fSDaniele Castagna int is_yuv = fb->format->is_yuv; 8041c21aa8fSDaniele Castagna int i; 80563ebb9faSMark Yao 80663ebb9faSMark Yao /* 80763ebb9faSMark Yao * can't update plane when vop is disabled. 80863ebb9faSMark Yao */ 8094f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 81063ebb9faSMark Yao return; 81163ebb9faSMark Yao 81263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 81363ebb9faSMark Yao return; 81463ebb9faSMark Yao 815d47a7246STomasz Figa if (!state->visible) { 81663ebb9faSMark Yao vop_plane_atomic_disable(plane, old_state); 81763ebb9faSMark Yao return; 81863ebb9faSMark Yao } 81963ebb9faSMark Yao 820957428f9SDaniel Stone obj = fb->obj[0]; 82163ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 82263ebb9faSMark Yao 82363ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 82463ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 82563ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 82663ebb9faSMark Yao 82763ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 82863ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 82963ebb9faSMark Yao 83063ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 83163ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 83263ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 83363ebb9faSMark Yao 834353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 83563ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 836d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 837d47a7246STomasz Figa 838677e8bbcSDaniele Castagna /* 839677e8bbcSDaniele Castagna * For y-mirroring we need to move address 840677e8bbcSDaniele Castagna * to the beginning of the last line. 841677e8bbcSDaniele Castagna */ 842677e8bbcSDaniele Castagna if (state->rotation & DRM_MODE_REFLECT_Y) 843677e8bbcSDaniele Castagna dma_addr += (actual_h - 1) * fb->pitches[0]; 844677e8bbcSDaniele Castagna 845438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 84663ebb9faSMark Yao 84763ebb9faSMark Yao spin_lock(&vop->reg_lock); 84863ebb9faSMark Yao 849d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 850da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 851d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 8521c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 853677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, y_mir_en, 854677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 855677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, x_mir_en, 856677e8bbcSDaniele Castagna (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 8571c21aa8fSDaniele Castagna 8581c21aa8fSDaniele Castagna if (is_yuv) { 859f3e9632cSMaxime Ripard int hsub = fb->format->hsub; 860f3e9632cSMaxime Ripard int vsub = fb->format->vsub; 861353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 86284c7f8caSMark Yao 863957428f9SDaniel Stone uv_obj = fb->obj[1]; 86484c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 86584c7f8caSMark Yao 86663ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 86763ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 86884c7f8caSMark Yao 86963ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 870da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 87163ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 8721c21aa8fSDaniele Castagna 8731c21aa8fSDaniele Castagna for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 8741c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 8751c21aa8fSDaniele Castagna win_yuv2yuv, 8761c21aa8fSDaniele Castagna y2r_coefficients[i], 8771c21aa8fSDaniele Castagna bt601_yuv2rgb[i]); 8781c21aa8fSDaniele Castagna } 87984c7f8caSMark Yao } 8804c156c21SMark Yao 8814c156c21SMark Yao if (win->phy->scl) 8824c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 88363ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 88445babef0SMaxime Ripard fb->format); 8854c156c21SMark Yao 88663ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 88763ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 88863ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 8894c156c21SMark Yao 890438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 89185a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 8922048e328SMark Yao 89358badaa7SKristian H. Kristensen /* 89458badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 89558badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 89658badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 89758badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 89858badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 89958badaa7SKristian H. Kristensen */ 90058badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 9012048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 9022048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 9032048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 9042048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 9052048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 9062048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 9072048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 9082048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 9092048e328SMark Yao } else { 9102048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 9112048e328SMark Yao } 9122048e328SMark Yao 9132048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 914bed030a4SSean Paul vop->win_enabled |= BIT(win_index); 9152048e328SMark Yao spin_unlock(&vop->reg_lock); 9162048e328SMark Yao } 9172048e328SMark Yao 91815609559SEnric Balletbo i Serra static int vop_plane_atomic_async_check(struct drm_plane *plane, 91915609559SEnric Balletbo i Serra struct drm_plane_state *state) 92015609559SEnric Balletbo i Serra { 92115609559SEnric Balletbo i Serra struct vop_win *vop_win = to_vop_win(plane); 92215609559SEnric Balletbo i Serra const struct vop_win_data *win = vop_win->data; 92315609559SEnric Balletbo i Serra int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 92415609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 92515609559SEnric Balletbo i Serra int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 92615609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 92715609559SEnric Balletbo i Serra struct drm_crtc_state *crtc_state; 92815609559SEnric Balletbo i Serra 92915609559SEnric Balletbo i Serra if (plane != state->crtc->cursor) 93015609559SEnric Balletbo i Serra return -EINVAL; 93115609559SEnric Balletbo i Serra 93215609559SEnric Balletbo i Serra if (!plane->state) 93315609559SEnric Balletbo i Serra return -EINVAL; 93415609559SEnric Balletbo i Serra 93515609559SEnric Balletbo i Serra if (!plane->state->fb) 93615609559SEnric Balletbo i Serra return -EINVAL; 93715609559SEnric Balletbo i Serra 93815609559SEnric Balletbo i Serra if (state->state) 93915609559SEnric Balletbo i Serra crtc_state = drm_atomic_get_existing_crtc_state(state->state, 94015609559SEnric Balletbo i Serra state->crtc); 94115609559SEnric Balletbo i Serra else /* Special case for asynchronous cursor updates. */ 94215609559SEnric Balletbo i Serra crtc_state = plane->crtc->state; 94315609559SEnric Balletbo i Serra 94415609559SEnric Balletbo i Serra return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 94515609559SEnric Balletbo i Serra min_scale, max_scale, 94615609559SEnric Balletbo i Serra true, true); 94715609559SEnric Balletbo i Serra } 94815609559SEnric Balletbo i Serra 94915609559SEnric Balletbo i Serra static void vop_plane_atomic_async_update(struct drm_plane *plane, 95015609559SEnric Balletbo i Serra struct drm_plane_state *new_state) 95115609559SEnric Balletbo i Serra { 95215609559SEnric Balletbo i Serra struct vop *vop = to_vop(plane->state->crtc); 953d985a353SHelen Koike struct drm_framebuffer *old_fb = plane->state->fb; 95415609559SEnric Balletbo i Serra 955d985a353SHelen Koike plane->state->crtc_x = new_state->crtc_x; 956d985a353SHelen Koike plane->state->crtc_y = new_state->crtc_y; 957d985a353SHelen Koike plane->state->crtc_h = new_state->crtc_h; 958d985a353SHelen Koike plane->state->crtc_w = new_state->crtc_w; 959d985a353SHelen Koike plane->state->src_x = new_state->src_x; 960d985a353SHelen Koike plane->state->src_y = new_state->src_y; 961d985a353SHelen Koike plane->state->src_h = new_state->src_h; 962d985a353SHelen Koike plane->state->src_w = new_state->src_w; 963d985a353SHelen Koike swap(plane->state->fb, new_state->fb); 96415609559SEnric Balletbo i Serra 96515609559SEnric Balletbo i Serra if (vop->is_enabled) { 96615609559SEnric Balletbo i Serra vop_plane_atomic_update(plane, plane->state); 96715609559SEnric Balletbo i Serra spin_lock(&vop->reg_lock); 96815609559SEnric Balletbo i Serra vop_cfg_done(vop); 96915609559SEnric Balletbo i Serra spin_unlock(&vop->reg_lock); 97015609559SEnric Balletbo i Serra 971d985a353SHelen Koike /* 972d985a353SHelen Koike * A scanout can still be occurring, so we can't drop the 973d985a353SHelen Koike * reference to the old framebuffer. To solve this we get a 974d985a353SHelen Koike * reference to old_fb and set a worker to release it later. 975d985a353SHelen Koike * FIXME: if we perform 500 async_update calls before the 976d985a353SHelen Koike * vblank, then we can have 500 different framebuffers waiting 977d985a353SHelen Koike * to be released. 978d985a353SHelen Koike */ 979d985a353SHelen Koike if (old_fb && plane->state->fb != old_fb) { 980d985a353SHelen Koike drm_framebuffer_get(old_fb); 981d985a353SHelen Koike WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 982d985a353SHelen Koike drm_flip_work_queue(&vop->fb_unref_work, old_fb); 983d985a353SHelen Koike set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 984d985a353SHelen Koike } 985d985a353SHelen Koike } 98615609559SEnric Balletbo i Serra } 98715609559SEnric Balletbo i Serra 98863ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 98963ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 99063ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 99163ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 99215609559SEnric Balletbo i Serra .atomic_async_check = vop_plane_atomic_async_check, 99315609559SEnric Balletbo i Serra .atomic_async_update = vop_plane_atomic_async_update, 99463d5e06aSHeiko Stuebner .prepare_fb = drm_gem_fb_prepare_fb, 99563ebb9faSMark Yao }; 99663ebb9faSMark Yao 9972048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 99863ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 99963ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 10002048e328SMark Yao .destroy = vop_plane_destroy, 1001d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 1002d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1003d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 10042048e328SMark Yao }; 10052048e328SMark Yao 10062048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 10072048e328SMark Yao { 10082048e328SMark Yao struct vop *vop = to_vop(crtc); 10092048e328SMark Yao unsigned long flags; 10102048e328SMark Yao 101163ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10122048e328SMark Yao return -EPERM; 10132048e328SMark Yao 10142048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 10152048e328SMark Yao 1016fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1017dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 10182048e328SMark Yao 10192048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10202048e328SMark Yao 10212048e328SMark Yao return 0; 10222048e328SMark Yao } 10232048e328SMark Yao 10242048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 10252048e328SMark Yao { 10262048e328SMark Yao struct vop *vop = to_vop(crtc); 10272048e328SMark Yao unsigned long flags; 10282048e328SMark Yao 102963ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 10302048e328SMark Yao return; 103131e980c5SMark Yao 10322048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1033dbb3d944SMark Yao 1034dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1035dbb3d944SMark Yao 10362048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 10372048e328SMark Yao } 10382048e328SMark Yao 10392048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 10402048e328SMark Yao const struct drm_display_mode *mode, 10412048e328SMark Yao struct drm_display_mode *adjusted_mode) 10422048e328SMark Yao { 1043b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 1044287422a9SDouglas Anderson unsigned long rate; 1045b59b8de3SChris Zhong 1046287422a9SDouglas Anderson /* 1047287422a9SDouglas Anderson * Clock craziness. 1048287422a9SDouglas Anderson * 1049287422a9SDouglas Anderson * Key points: 1050287422a9SDouglas Anderson * 1051287422a9SDouglas Anderson * - DRM works in in kHz. 1052287422a9SDouglas Anderson * - Clock framework works in Hz. 1053287422a9SDouglas Anderson * - Rockchip's clock driver picks the clock rate that is the 1054287422a9SDouglas Anderson * same _OR LOWER_ than the one requested. 1055287422a9SDouglas Anderson * 1056287422a9SDouglas Anderson * Action plan: 1057287422a9SDouglas Anderson * 1058287422a9SDouglas Anderson * 1. When DRM gives us a mode, we should add 999 Hz to it. That way 1059287422a9SDouglas Anderson * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to 1060287422a9SDouglas Anderson * make 60000 kHz then the clock framework will actually give us 1061287422a9SDouglas Anderson * the right clock. 1062287422a9SDouglas Anderson * 1063287422a9SDouglas Anderson * NOTE: if the PLL (maybe through a divider) could actually make 1064287422a9SDouglas Anderson * a clock rate 999 Hz higher instead of the one we want then this 1065287422a9SDouglas Anderson * could be a problem. Unfortunately there's not much we can do 1066287422a9SDouglas Anderson * since it's baked into DRM to use kHz. It shouldn't matter in 1067287422a9SDouglas Anderson * practice since Rockchip PLLs are controlled by tables and 1068287422a9SDouglas Anderson * even if there is a divider in the middle I wouldn't expect PLL 1069287422a9SDouglas Anderson * rates in the table that are just a few kHz different. 1070287422a9SDouglas Anderson * 1071287422a9SDouglas Anderson * 2. Get the clock framework to round the rate for us to tell us 1072287422a9SDouglas Anderson * what it will actually make. 1073287422a9SDouglas Anderson * 1074287422a9SDouglas Anderson * 3. Store the rounded up rate so that we don't need to worry about 1075287422a9SDouglas Anderson * this in the actual clk_set_rate(). 1076287422a9SDouglas Anderson */ 1077287422a9SDouglas Anderson rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); 1078287422a9SDouglas Anderson adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1079b59b8de3SChris Zhong 10802048e328SMark Yao return true; 10812048e328SMark Yao } 10822048e328SMark Yao 1083b23ab6acSEzequiel Garcia static bool vop_dsp_lut_is_enabled(struct vop *vop) 1084b23ab6acSEzequiel Garcia { 1085b23ab6acSEzequiel Garcia return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1086b23ab6acSEzequiel Garcia } 1087b23ab6acSEzequiel Garcia 1088b23ab6acSEzequiel Garcia static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1089b23ab6acSEzequiel Garcia { 1090b23ab6acSEzequiel Garcia struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1091b23ab6acSEzequiel Garcia unsigned int i; 1092b23ab6acSEzequiel Garcia 1093b23ab6acSEzequiel Garcia for (i = 0; i < crtc->gamma_size; i++) { 1094b23ab6acSEzequiel Garcia u32 word; 1095b23ab6acSEzequiel Garcia 1096b23ab6acSEzequiel Garcia word = (drm_color_lut_extract(lut[i].red, 10) << 20) | 1097b23ab6acSEzequiel Garcia (drm_color_lut_extract(lut[i].green, 10) << 10) | 1098b23ab6acSEzequiel Garcia drm_color_lut_extract(lut[i].blue, 10); 1099b23ab6acSEzequiel Garcia writel(word, vop->lut_regs + i * 4); 1100b23ab6acSEzequiel Garcia } 1101b23ab6acSEzequiel Garcia } 1102b23ab6acSEzequiel Garcia 1103b23ab6acSEzequiel Garcia static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1104b23ab6acSEzequiel Garcia struct drm_crtc_state *old_state) 1105b23ab6acSEzequiel Garcia { 1106b23ab6acSEzequiel Garcia struct drm_crtc_state *state = crtc->state; 1107b23ab6acSEzequiel Garcia unsigned int idle; 1108b23ab6acSEzequiel Garcia int ret; 1109b23ab6acSEzequiel Garcia 1110b23ab6acSEzequiel Garcia if (!vop->lut_regs) 1111b23ab6acSEzequiel Garcia return; 1112b23ab6acSEzequiel Garcia /* 1113b23ab6acSEzequiel Garcia * To disable gamma (gamma_lut is null) or to write 1114b23ab6acSEzequiel Garcia * an update to the LUT, clear dsp_lut_en. 1115b23ab6acSEzequiel Garcia */ 1116b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1117b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 0); 1118b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1119b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1120b23ab6acSEzequiel Garcia 1121b23ab6acSEzequiel Garcia /* 1122b23ab6acSEzequiel Garcia * In order to write the LUT to the internal memory, 1123b23ab6acSEzequiel Garcia * we need to first make sure the dsp_lut_en bit is cleared. 1124b23ab6acSEzequiel Garcia */ 1125b23ab6acSEzequiel Garcia ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1126b23ab6acSEzequiel Garcia idle, !idle, 5, 30 * 1000); 1127b23ab6acSEzequiel Garcia if (ret) { 1128b23ab6acSEzequiel Garcia DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1129b23ab6acSEzequiel Garcia return; 1130b23ab6acSEzequiel Garcia } 1131b23ab6acSEzequiel Garcia 1132b23ab6acSEzequiel Garcia if (!state->gamma_lut) 1133b23ab6acSEzequiel Garcia return; 1134b23ab6acSEzequiel Garcia 1135b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1136b23ab6acSEzequiel Garcia vop_crtc_write_gamma_lut(vop, crtc); 1137b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 1); 1138b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1139b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1140b23ab6acSEzequiel Garcia } 1141b23ab6acSEzequiel Garcia 1142b23ab6acSEzequiel Garcia static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1143b23ab6acSEzequiel Garcia struct drm_crtc_state *old_crtc_state) 1144b23ab6acSEzequiel Garcia { 1145b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 1146b23ab6acSEzequiel Garcia 1147b23ab6acSEzequiel Garcia /* 1148b23ab6acSEzequiel Garcia * Only update GAMMA if the 'active' flag is not changed, 1149b23ab6acSEzequiel Garcia * otherwise it's updated by .atomic_enable. 1150b23ab6acSEzequiel Garcia */ 1151b23ab6acSEzequiel Garcia if (crtc->state->color_mgmt_changed && 1152b23ab6acSEzequiel Garcia !crtc->state->active_changed) 1153b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1154b23ab6acSEzequiel Garcia } 1155b23ab6acSEzequiel Garcia 11560b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 11570b20a0f8SLaurent Pinchart struct drm_crtc_state *old_state) 11582048e328SMark Yao { 11592048e328SMark Yao struct vop *vop = to_vop(crtc); 1160efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 11614e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 116263ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 11632048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 11642048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 11652048e328SMark Yao u16 htotal = adjusted_mode->htotal; 11662048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 11672048e328SMark Yao u16 hact_end = hact_st + hdisplay; 11682048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 11692048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 11702048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 11712048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 11722048e328SMark Yao u16 vact_end = vact_st + vdisplay; 11730a63bfd0SMark Yao uint32_t pin_pol, val; 1174a5c0fa44SUrja Rannikko int dither_bpc = s->output_bpc ? s->output_bpc : 10; 117539a9ad8fSSean Paul int ret; 11762048e328SMark Yao 1177bed030a4SSean Paul if (old_state && old_state->self_refresh_active) { 1178bed030a4SSean Paul drm_crtc_vblank_on(crtc); 1179bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, true); 1180bed030a4SSean Paul return; 1181bed030a4SSean Paul } 1182bed030a4SSean Paul 1183b23ab6acSEzequiel Garcia /* 1184b23ab6acSEzequiel Garcia * If we have a GAMMA LUT in the state, then let's make sure 1185b23ab6acSEzequiel Garcia * it's updated. We might be coming out of suspend, 1186b23ab6acSEzequiel Garcia * which means the LUT internal memory needs to be re-written. 1187b23ab6acSEzequiel Garcia */ 1188b23ab6acSEzequiel Garcia if (crtc->state->gamma_lut) 1189b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_state); 1190b23ab6acSEzequiel Garcia 1191e334d48bSzain wang mutex_lock(&vop->vop_lock); 1192e334d48bSzain wang 1193893b6cadSDaniel Vetter WARN_ON(vop->event); 1194893b6cadSDaniel Vetter 11956c836d96SSean Paul ret = vop_enable(crtc, old_state); 119639a9ad8fSSean Paul if (ret) { 1197e334d48bSzain wang mutex_unlock(&vop->vop_lock); 119839a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 119939a9ad8fSSean Paul return; 120039a9ad8fSSean Paul } 12011f6c62caSNickey Yang pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1202d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 1203d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1204d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 12059a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 1206cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 12070a63bfd0SMark Yao 12084e257d9eSMark Yao switch (s->output_type) { 12094e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 12101f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 12119a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 12121f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_en, 1); 12134e257d9eSMark Yao break; 12144e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 12151f6c62caSNickey Yang VOP_REG_SET(vop, output, edp_dclk_pol, 1); 12169a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 12179a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 12184e257d9eSMark Yao break; 12194e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 12201f6c62caSNickey Yang VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 12219a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 12229a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 12234e257d9eSMark Yao break; 12244e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 12251f6c62caSNickey Yang VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 12269a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 12279a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 1228cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 1229cf6d100dSHeiko Stuebner !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 12304e257d9eSMark Yao break; 12311a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 12321f6c62caSNickey Yang VOP_REG_SET(vop, output, dp_dclk_pol, 0); 12339a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 12349a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 12351a0f7ed3SChris Zhong break; 12364e257d9eSMark Yao default: 1237ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1238ee4d7899SSean Paul s->output_type); 12394e257d9eSMark Yao } 1240efd11cc8SMark yao 1241efd11cc8SMark yao /* 1242efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 1243efd11cc8SMark yao */ 1244efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1245efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1246efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 12476bda8112SMark Yao 1248a5c0fa44SUrja Rannikko if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 12496bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 12506bda8112SMark Yao else 12516bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 12526bda8112SMark Yao 1253a5c0fa44SUrja Rannikko if (dither_bpc == 6) { 1254a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1255a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1256a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 1); 1257a5c0fa44SUrja Rannikko } else { 1258a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 0); 1259a5c0fa44SUrja Rannikko } 1260a5c0fa44SUrja Rannikko 12619a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 12622048e328SMark Yao 12639a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 12642048e328SMark Yao val = hact_st << 16; 12652048e328SMark Yao val |= hact_end; 12669a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 12679a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 12682048e328SMark Yao 12699a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 12702048e328SMark Yao val = vact_st << 16; 12712048e328SMark Yao val |= vact_end; 12729a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 12739a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 12742048e328SMark Yao 12759a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1276459b086dSJeffy Chen 12772048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1278ce3887edSMark Yao 12799a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 1280e334d48bSzain wang mutex_unlock(&vop->vop_lock); 12812048e328SMark Yao } 12822048e328SMark Yao 12837caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 12847caecdbeSTomasz Figa { 12857caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 12867caecdbeSTomasz Figa } 12877caecdbeSTomasz Figa 12887caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 12897caecdbeSTomasz Figa { 12907caecdbeSTomasz Figa bool pending; 12917caecdbeSTomasz Figa int ret; 12927caecdbeSTomasz Figa 12937caecdbeSTomasz Figa /* 12947caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 12957caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 12967caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 12977caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 12987caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 12997caecdbeSTomasz Figa * shouldn't exceed microseconds range. 13007caecdbeSTomasz Figa */ 13017caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 13027caecdbeSTomasz Figa !pending, 0, 10 * 1000); 13037caecdbeSTomasz Figa if (ret) 13047caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 13057caecdbeSTomasz Figa 13067caecdbeSTomasz Figa synchronize_irq(vop->irq); 13077caecdbeSTomasz Figa } 13087caecdbeSTomasz Figa 1309b23ab6acSEzequiel Garcia static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1310b23ab6acSEzequiel Garcia struct drm_crtc_state *crtc_state) 1311b23ab6acSEzequiel Garcia { 1312b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 1313b23ab6acSEzequiel Garcia 1314b23ab6acSEzequiel Garcia if (vop->lut_regs && crtc_state->color_mgmt_changed && 1315b23ab6acSEzequiel Garcia crtc_state->gamma_lut) { 1316b23ab6acSEzequiel Garcia unsigned int len; 1317b23ab6acSEzequiel Garcia 1318b23ab6acSEzequiel Garcia len = drm_color_lut_size(crtc_state->gamma_lut); 1319b23ab6acSEzequiel Garcia if (len != crtc->gamma_size) { 1320b23ab6acSEzequiel Garcia DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1321b23ab6acSEzequiel Garcia len, crtc->gamma_size); 1322b23ab6acSEzequiel Garcia return -EINVAL; 1323b23ab6acSEzequiel Garcia } 1324b23ab6acSEzequiel Garcia } 1325b23ab6acSEzequiel Garcia 1326b23ab6acSEzequiel Garcia return 0; 1327b23ab6acSEzequiel Garcia } 1328b23ab6acSEzequiel Garcia 132963ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 133063ebb9faSMark Yao struct drm_crtc_state *old_crtc_state) 133163ebb9faSMark Yao { 133247a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1333e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 133463ebb9faSMark Yao struct vop *vop = to_vop(crtc); 133547a7eb45STomasz Figa struct drm_plane *plane; 133647a7eb45STomasz Figa int i; 133763ebb9faSMark Yao 133863ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 133963ebb9faSMark Yao return; 134063ebb9faSMark Yao 134163ebb9faSMark Yao spin_lock(&vop->reg_lock); 134263ebb9faSMark Yao 134363ebb9faSMark Yao vop_cfg_done(vop); 134463ebb9faSMark Yao 134563ebb9faSMark Yao spin_unlock(&vop->reg_lock); 13467caecdbeSTomasz Figa 13477caecdbeSTomasz Figa /* 13487caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 13497caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 13507caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 13517caecdbeSTomasz Figa */ 13527caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 135347a7eb45STomasz Figa 135441ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 135541ee4367STomasz Figa if (crtc->state->event) { 135641ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 135741ee4367STomasz Figa WARN_ON(vop->event); 135841ee4367STomasz Figa 135941ee4367STomasz Figa vop->event = crtc->state->event; 136041ee4367STomasz Figa crtc->state->event = NULL; 136141ee4367STomasz Figa } 136241ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 136341ee4367STomasz Figa 1364e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1365e741f2b1SMaarten Lankhorst new_plane_state, i) { 136647a7eb45STomasz Figa if (!old_plane_state->fb) 136747a7eb45STomasz Figa continue; 136847a7eb45STomasz Figa 1369e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 137047a7eb45STomasz Figa continue; 137147a7eb45STomasz Figa 1372adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 13732d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 137447a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 137547a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 137647a7eb45STomasz Figa } 137763ebb9faSMark Yao } 137863ebb9faSMark Yao 13792048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 13802048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 1381b23ab6acSEzequiel Garcia .atomic_check = vop_crtc_atomic_check, 1382b23ab6acSEzequiel Garcia .atomic_begin = vop_crtc_atomic_begin, 138363ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 13840b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 138564581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 13862048e328SMark Yao }; 13872048e328SMark Yao 13882048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 13892048e328SMark Yao { 13902048e328SMark Yao drm_crtc_cleanup(crtc); 13912048e328SMark Yao } 13922048e328SMark Yao 13934e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 13944e257d9eSMark Yao { 13954e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 13964e257d9eSMark Yao 13974e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 13984e257d9eSMark Yao if (!rockchip_state) 13994e257d9eSMark Yao return NULL; 14004e257d9eSMark Yao 14014e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 14024e257d9eSMark Yao return &rockchip_state->base; 14034e257d9eSMark Yao } 14044e257d9eSMark Yao 14054e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 14064e257d9eSMark Yao struct drm_crtc_state *state) 14074e257d9eSMark Yao { 14084e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 14094e257d9eSMark Yao 1410ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 14114e257d9eSMark Yao kfree(s); 14124e257d9eSMark Yao } 14134e257d9eSMark Yao 141401e2eaf4SMaarten Lankhorst static void vop_crtc_reset(struct drm_crtc *crtc) 141501e2eaf4SMaarten Lankhorst { 141601e2eaf4SMaarten Lankhorst struct rockchip_crtc_state *crtc_state = 141701e2eaf4SMaarten Lankhorst kzalloc(sizeof(*crtc_state), GFP_KERNEL); 141801e2eaf4SMaarten Lankhorst 141901e2eaf4SMaarten Lankhorst if (crtc->state) 142001e2eaf4SMaarten Lankhorst vop_crtc_destroy_state(crtc, crtc->state); 142101e2eaf4SMaarten Lankhorst 142201e2eaf4SMaarten Lankhorst __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 142301e2eaf4SMaarten Lankhorst } 142401e2eaf4SMaarten Lankhorst 14256cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 14263190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 14273190e58dSTomeu Vizoso { 14283190e58dSTomeu Vizoso struct drm_connector *connector; 14292cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 14303190e58dSTomeu Vizoso 14312cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 14322cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 14333190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 14342cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 14353190e58dSTomeu Vizoso return connector; 14363190e58dSTomeu Vizoso } 14372cbeb64fSGustavo Padovan } 14382cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 14393190e58dSTomeu Vizoso 14403190e58dSTomeu Vizoso return NULL; 14413190e58dSTomeu Vizoso } 14423190e58dSTomeu Vizoso 14433190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1444c0811a7dSMahesh Kumar const char *source_name) 14453190e58dSTomeu Vizoso { 14463190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 14473190e58dSTomeu Vizoso struct drm_connector *connector; 14483190e58dSTomeu Vizoso int ret; 14493190e58dSTomeu Vizoso 14503190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 14513190e58dSTomeu Vizoso if (!connector) 14523190e58dSTomeu Vizoso return -EINVAL; 14533190e58dSTomeu Vizoso 14543190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 14553190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 14563190e58dSTomeu Vizoso else if (!source_name) 14573190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 14583190e58dSTomeu Vizoso else 14593190e58dSTomeu Vizoso ret = -EINVAL; 14603190e58dSTomeu Vizoso 14613190e58dSTomeu Vizoso return ret; 14623190e58dSTomeu Vizoso } 1463b8d913c0SMahesh Kumar 1464b8d913c0SMahesh Kumar static int 1465b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1466b8d913c0SMahesh Kumar size_t *values_cnt) 1467b8d913c0SMahesh Kumar { 1468b8d913c0SMahesh Kumar if (source_name && strcmp(source_name, "auto") != 0) 1469b8d913c0SMahesh Kumar return -EINVAL; 1470b8d913c0SMahesh Kumar 1471b8d913c0SMahesh Kumar *values_cnt = 3; 1472b8d913c0SMahesh Kumar return 0; 1473b8d913c0SMahesh Kumar } 1474b8d913c0SMahesh Kumar 14756cca3869SSean Paul #else 14766cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1477c0811a7dSMahesh Kumar const char *source_name) 14786cca3869SSean Paul { 14796cca3869SSean Paul return -ENODEV; 14806cca3869SSean Paul } 1481b8d913c0SMahesh Kumar 1482b8d913c0SMahesh Kumar static int 1483b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1484b8d913c0SMahesh Kumar size_t *values_cnt) 1485b8d913c0SMahesh Kumar { 1486b8d913c0SMahesh Kumar return -ENODEV; 1487b8d913c0SMahesh Kumar } 14886cca3869SSean Paul #endif 14893190e58dSTomeu Vizoso 14902048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 149163ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 149263ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 14932048e328SMark Yao .destroy = vop_crtc_destroy, 1494dc0b408fSJohn Keeping .reset = vop_crtc_reset, 14954e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 14964e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1497c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1498c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 14993190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 1500b8d913c0SMahesh Kumar .verify_crc_source = vop_crtc_verify_crc_source, 1501b23ab6acSEzequiel Garcia .gamma_set = drm_atomic_helper_legacy_gamma_set, 15022048e328SMark Yao }; 15032048e328SMark Yao 150447a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 150547a7eb45STomasz Figa { 150647a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 150747a7eb45STomasz Figa struct drm_framebuffer *fb = val; 150847a7eb45STomasz Figa 150947a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1510adedbf03SCihangir Akturk drm_framebuffer_put(fb); 151147a7eb45STomasz Figa } 151247a7eb45STomasz Figa 151363ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 15142048e328SMark Yao { 151563ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 151663ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 15172048e328SMark Yao 15181c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1519893b6cadSDaniel Vetter if (vop->event) { 152063ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 15215b680403SSean Paul drm_crtc_vblank_put(crtc); 1522646ec687STomasz Figa vop->event = NULL; 15235b680403SSean Paul } 15241c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1525893b6cadSDaniel Vetter 152647a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 152747a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 15282048e328SMark Yao } 15292048e328SMark Yao 15302048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 15312048e328SMark Yao { 15322048e328SMark Yao struct vop *vop = data; 1533b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1534dbb3d944SMark Yao uint32_t active_irqs; 15351067219bSMark Yao int ret = IRQ_NONE; 15362048e328SMark Yao 15372048e328SMark Yao /* 15386456314fSSandy Huang * The irq is shared with the iommu. If the runtime-pm state of the 15396456314fSSandy Huang * vop-device is disabled the irq has to be targeted at the iommu. 15406456314fSSandy Huang */ 15416456314fSSandy Huang if (!pm_runtime_get_if_in_use(vop->dev)) 15426456314fSSandy Huang return IRQ_NONE; 15436456314fSSandy Huang 15446456314fSSandy Huang if (vop_core_clks_enable(vop)) { 15456456314fSSandy Huang DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 15466456314fSSandy Huang goto out; 15476456314fSSandy Huang } 15486456314fSSandy Huang 15496456314fSSandy Huang /* 1550dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 15512048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 15522048e328SMark Yao */ 15531c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1554dbb3d944SMark Yao 1555dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 15562048e328SMark Yao /* Clear all active interrupt sources */ 15572048e328SMark Yao if (active_irqs) 1558dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1559dbb3d944SMark Yao 15601c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 15612048e328SMark Yao 15622048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 15632048e328SMark Yao if (!active_irqs) 15646456314fSSandy Huang goto out_disable; 15652048e328SMark Yao 15661067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 15671067219bSMark Yao complete(&vop->dsp_hold_completion); 15681067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 15691067219bSMark Yao ret = IRQ_HANDLED; 15702048e328SMark Yao } 15712048e328SMark Yao 157269c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 157369c34e41SYakir Yang complete(&vop->line_flag_completion); 157469c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 157569c34e41SYakir Yang ret = IRQ_HANDLED; 157669c34e41SYakir Yang } 157769c34e41SYakir Yang 15781067219bSMark Yao if (active_irqs & FS_INTR) { 1579b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 158063ebb9faSMark Yao vop_handle_vblank(vop); 15811067219bSMark Yao active_irqs &= ~FS_INTR; 158263ebb9faSMark Yao ret = IRQ_HANDLED; 15831067219bSMark Yao } 15842048e328SMark Yao 15851067219bSMark Yao /* Unhandled irqs are spurious. */ 15861067219bSMark Yao if (active_irqs) 1587ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1588ee4d7899SSean Paul active_irqs); 15891067219bSMark Yao 15906456314fSSandy Huang out_disable: 15916456314fSSandy Huang vop_core_clks_disable(vop); 15926456314fSSandy Huang out: 15936456314fSSandy Huang pm_runtime_put(vop->dev); 15941067219bSMark Yao return ret; 15952048e328SMark Yao } 15962048e328SMark Yao 1597677e8bbcSDaniele Castagna static void vop_plane_add_properties(struct drm_plane *plane, 1598677e8bbcSDaniele Castagna const struct vop_win_data *win_data) 1599677e8bbcSDaniele Castagna { 1600677e8bbcSDaniele Castagna unsigned int flags = 0; 1601677e8bbcSDaniele Castagna 1602677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1603677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1604677e8bbcSDaniele Castagna if (flags) 1605677e8bbcSDaniele Castagna drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1606677e8bbcSDaniele Castagna DRM_MODE_ROTATE_0 | flags); 1607677e8bbcSDaniele Castagna } 1608677e8bbcSDaniele Castagna 16092048e328SMark Yao static int vop_create_crtc(struct vop *vop) 16102048e328SMark Yao { 16112048e328SMark Yao const struct vop_data *vop_data = vop->data; 16122048e328SMark Yao struct device *dev = vop->dev; 16132048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1614328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 16152048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 16162048e328SMark Yao struct device_node *port; 16172048e328SMark Yao int ret; 16182048e328SMark Yao int i; 16192048e328SMark Yao 16202048e328SMark Yao /* 16212048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 16222048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 16232048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 16242048e328SMark Yao */ 16252048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16262048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 16272048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 16282048e328SMark Yao 16292048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 16302048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 16312048e328SMark Yao continue; 16322048e328SMark Yao 16332048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 16342048e328SMark Yao 0, &vop_plane_funcs, 16352048e328SMark Yao win_data->phy->data_formats, 16362048e328SMark Yao win_data->phy->nformats, 1637e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 16382048e328SMark Yao if (ret) { 1639ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1640ee4d7899SSean Paul ret); 16412048e328SMark Yao goto err_cleanup_planes; 16422048e328SMark Yao } 16432048e328SMark Yao 16442048e328SMark Yao plane = &vop_win->base; 164563ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 1646677e8bbcSDaniele Castagna vop_plane_add_properties(plane, win_data); 16472048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 16482048e328SMark Yao primary = plane; 16492048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 16502048e328SMark Yao cursor = plane; 16512048e328SMark Yao } 16522048e328SMark Yao 16532048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1654f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 16552048e328SMark Yao if (ret) 1656328b51c0SDouglas Anderson goto err_cleanup_planes; 16572048e328SMark Yao 16582048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1659b23ab6acSEzequiel Garcia if (vop->lut_regs) { 1660b23ab6acSEzequiel Garcia drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1661b23ab6acSEzequiel Garcia drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1662b23ab6acSEzequiel Garcia } 16632048e328SMark Yao 16642048e328SMark Yao /* 16652048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 16662048e328SMark Yao * to the newly created crtc. 16672048e328SMark Yao */ 16682048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 16692048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 16702048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 1671a3e77e16SVille Syrjälä unsigned long possible_crtcs = drm_crtc_mask(crtc); 16722048e328SMark Yao 16732048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 16742048e328SMark Yao continue; 16752048e328SMark Yao 16762048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 16772048e328SMark Yao possible_crtcs, 16782048e328SMark Yao &vop_plane_funcs, 16792048e328SMark Yao win_data->phy->data_formats, 16802048e328SMark Yao win_data->phy->nformats, 1681e6fc3b68SBen Widawsky NULL, win_data->type, NULL); 16822048e328SMark Yao if (ret) { 1683ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1684ee4d7899SSean Paul ret); 16852048e328SMark Yao goto err_cleanup_crtc; 16862048e328SMark Yao } 168763ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1688677e8bbcSDaniele Castagna vop_plane_add_properties(&vop_win->base, win_data); 16892048e328SMark Yao } 16902048e328SMark Yao 16912048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 16922048e328SMark Yao if (!port) { 16934bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 16944bf99144SRob Herring dev->of_node); 1695328b51c0SDouglas Anderson ret = -ENOENT; 16962048e328SMark Yao goto err_cleanup_crtc; 16972048e328SMark Yao } 16982048e328SMark Yao 169947a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 170047a7eb45STomasz Figa vop_fb_unref_worker); 170147a7eb45STomasz Figa 17021067219bSMark Yao init_completion(&vop->dsp_hold_completion); 170369c34e41SYakir Yang init_completion(&vop->line_flag_completion); 17042048e328SMark Yao crtc->port = port; 17052048e328SMark Yao 1706d4da4e33SSean Paul ret = drm_self_refresh_helper_init(crtc); 17076c836d96SSean Paul if (ret) 17086c836d96SSean Paul DRM_DEV_DEBUG_KMS(vop->dev, 17096c836d96SSean Paul "Failed to init %s with SR helpers %d, ignoring\n", 17106c836d96SSean Paul crtc->name, ret); 17116c836d96SSean Paul 17122048e328SMark Yao return 0; 17132048e328SMark Yao 17142048e328SMark Yao err_cleanup_crtc: 17152048e328SMark Yao drm_crtc_cleanup(crtc); 17162048e328SMark Yao err_cleanup_planes: 1717328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1718328b51c0SDouglas Anderson head) 17192048e328SMark Yao drm_plane_cleanup(plane); 17202048e328SMark Yao return ret; 17212048e328SMark Yao } 17222048e328SMark Yao 17232048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 17242048e328SMark Yao { 17252048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1726328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1727328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 17282048e328SMark Yao 17296c836d96SSean Paul drm_self_refresh_helper_cleanup(crtc); 17306c836d96SSean Paul 17312048e328SMark Yao of_node_put(crtc->port); 1732328b51c0SDouglas Anderson 1733328b51c0SDouglas Anderson /* 1734328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1735328b51c0SDouglas Anderson * 1736328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1737328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1738328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1739328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1740328b51c0SDouglas Anderson */ 1741328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1742328b51c0SDouglas Anderson head) 1743328b51c0SDouglas Anderson vop_plane_destroy(plane); 1744328b51c0SDouglas Anderson 1745328b51c0SDouglas Anderson /* 1746328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1747328b51c0SDouglas Anderson * references the CRTC. 1748328b51c0SDouglas Anderson */ 17492048e328SMark Yao drm_crtc_cleanup(crtc); 175047a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 17512048e328SMark Yao } 17522048e328SMark Yao 17532048e328SMark Yao static int vop_initial(struct vop *vop) 17542048e328SMark Yao { 17552048e328SMark Yao struct reset_control *ahb_rst; 17562048e328SMark Yao int i, ret; 17572048e328SMark Yao 17582048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 17592048e328SMark Yao if (IS_ERR(vop->hclk)) { 1760d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 17612048e328SMark Yao return PTR_ERR(vop->hclk); 17622048e328SMark Yao } 17632048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 17642048e328SMark Yao if (IS_ERR(vop->aclk)) { 1765d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 17662048e328SMark Yao return PTR_ERR(vop->aclk); 17672048e328SMark Yao } 17682048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 17692048e328SMark Yao if (IS_ERR(vop->dclk)) { 1770d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 17712048e328SMark Yao return PTR_ERR(vop->dclk); 17722048e328SMark Yao } 17732048e328SMark Yao 17745e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 17755e570373SJeffy Chen if (ret < 0) { 1776d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 17775e570373SJeffy Chen return ret; 17785e570373SJeffy Chen } 17795e570373SJeffy Chen 17802048e328SMark Yao ret = clk_prepare(vop->dclk); 17812048e328SMark Yao if (ret < 0) { 1782d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 17835e570373SJeffy Chen goto err_put_pm_runtime; 17842048e328SMark Yao } 17852048e328SMark Yao 1786d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1787d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 17882048e328SMark Yao if (ret < 0) { 1789d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 17902048e328SMark Yao goto err_unprepare_dclk; 17912048e328SMark Yao } 17922048e328SMark Yao 1793d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 17942048e328SMark Yao if (ret < 0) { 1795d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1796d7b53fd9SSjoerd Simons goto err_disable_hclk; 17972048e328SMark Yao } 1798d7b53fd9SSjoerd Simons 17992048e328SMark Yao /* 18002048e328SMark Yao * do hclk_reset, reset all vop registers. 18012048e328SMark Yao */ 18022048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 18032048e328SMark Yao if (IS_ERR(ahb_rst)) { 1804d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 18052048e328SMark Yao ret = PTR_ERR(ahb_rst); 1806d7b53fd9SSjoerd Simons goto err_disable_aclk; 18072048e328SMark Yao } 18082048e328SMark Yao reset_control_assert(ahb_rst); 18092048e328SMark Yao usleep_range(10, 20); 18102048e328SMark Yao reset_control_deassert(ahb_rst); 18112048e328SMark Yao 18125f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 18135f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 18145f9e93feSMarc Zyngier 181576f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 181676f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 18172048e328SMark Yao 18189a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 18199a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 18202048e328SMark Yao 18212b60e11dSSean Paul for (i = 0; i < vop->data->win_size; i++) { 18222b60e11dSSean Paul struct vop_win *vop_win = &vop->win[i]; 18232b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 18249dd2aca4SMark yao int channel = i * 2 + 1; 18252048e328SMark Yao 18269dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 18272b60e11dSSean Paul vop_win_disable(vop, vop_win); 182860b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 18292048e328SMark Yao } 18302048e328SMark Yao 18312048e328SMark Yao vop_cfg_done(vop); 18322048e328SMark Yao 18332048e328SMark Yao /* 18342048e328SMark Yao * do dclk_reset, let all config take affect. 18352048e328SMark Yao */ 18362048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 18372048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1838d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 18392048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 1840d7b53fd9SSjoerd Simons goto err_disable_aclk; 18412048e328SMark Yao } 18422048e328SMark Yao reset_control_assert(vop->dclk_rst); 18432048e328SMark Yao usleep_range(10, 20); 18442048e328SMark Yao reset_control_deassert(vop->dclk_rst); 18452048e328SMark Yao 18462048e328SMark Yao clk_disable(vop->hclk); 1847d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 18482048e328SMark Yao 184931e980c5SMark Yao vop->is_enabled = false; 18502048e328SMark Yao 18515e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 18525e570373SJeffy Chen 18532048e328SMark Yao return 0; 18542048e328SMark Yao 1855d7b53fd9SSjoerd Simons err_disable_aclk: 1856d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 18572048e328SMark Yao err_disable_hclk: 1858d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 18592048e328SMark Yao err_unprepare_dclk: 18602048e328SMark Yao clk_unprepare(vop->dclk); 18615e570373SJeffy Chen err_put_pm_runtime: 18625e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 18632048e328SMark Yao return ret; 18642048e328SMark Yao } 18652048e328SMark Yao 18662048e328SMark Yao /* 18672048e328SMark Yao * Initialize the vop->win array elements. 18682048e328SMark Yao */ 18692048e328SMark Yao static void vop_win_init(struct vop *vop) 18702048e328SMark Yao { 18712048e328SMark Yao const struct vop_data *vop_data = vop->data; 18722048e328SMark Yao unsigned int i; 18732048e328SMark Yao 18742048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 18752048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 18762048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 18772048e328SMark Yao 18782048e328SMark Yao vop_win->data = win_data; 18792048e328SMark Yao vop_win->vop = vop; 1880ce6912b4SHeiko Stuebner 1881ce6912b4SHeiko Stuebner if (vop_data->win_yuv2yuv) 18821c21aa8fSDaniele Castagna vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 18832048e328SMark Yao } 18842048e328SMark Yao } 18852048e328SMark Yao 188669c34e41SYakir Yang /** 1887459b086dSJeffy Chen * rockchip_drm_wait_vact_end 188869c34e41SYakir Yang * @crtc: CRTC to enable line flag 188969c34e41SYakir Yang * @mstimeout: millisecond for timeout 189069c34e41SYakir Yang * 1891459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 189269c34e41SYakir Yang * 189369c34e41SYakir Yang * Returns: 189469c34e41SYakir Yang * Zero on success, negative errno on failure. 189569c34e41SYakir Yang */ 1896459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 189769c34e41SYakir Yang { 189869c34e41SYakir Yang struct vop *vop = to_vop(crtc); 189969c34e41SYakir Yang unsigned long jiffies_left; 1900e334d48bSzain wang int ret = 0; 190169c34e41SYakir Yang 190269c34e41SYakir Yang if (!crtc || !vop->is_enabled) 190369c34e41SYakir Yang return -ENODEV; 190469c34e41SYakir Yang 1905e334d48bSzain wang mutex_lock(&vop->vop_lock); 1906e334d48bSzain wang if (mstimeout <= 0) { 1907e334d48bSzain wang ret = -EINVAL; 1908e334d48bSzain wang goto out; 1909e334d48bSzain wang } 191069c34e41SYakir Yang 1911e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 1912e334d48bSzain wang ret = -EBUSY; 1913e334d48bSzain wang goto out; 1914e334d48bSzain wang } 191569c34e41SYakir Yang 191669c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 1917459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 191869c34e41SYakir Yang 191969c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 192069c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 192169c34e41SYakir Yang vop_line_flag_irq_disable(vop); 192269c34e41SYakir Yang 192369c34e41SYakir Yang if (jiffies_left == 0) { 1924d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1925e334d48bSzain wang ret = -ETIMEDOUT; 1926e334d48bSzain wang goto out; 192769c34e41SYakir Yang } 192869c34e41SYakir Yang 1929e334d48bSzain wang out: 1930e334d48bSzain wang mutex_unlock(&vop->vop_lock); 1931e334d48bSzain wang return ret; 193269c34e41SYakir Yang } 1933459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 193469c34e41SYakir Yang 19352048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 19362048e328SMark Yao { 19372048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 19382048e328SMark Yao const struct vop_data *vop_data; 19392048e328SMark Yao struct drm_device *drm_dev = data; 19402048e328SMark Yao struct vop *vop; 19412048e328SMark Yao struct resource *res; 19423ea68922SHeiko Stuebner int ret, irq; 19432048e328SMark Yao 1944a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 19452048e328SMark Yao if (!vop_data) 19462048e328SMark Yao return -ENODEV; 19472048e328SMark Yao 19482048e328SMark Yao /* Allocate vop struct and its vop_win array */ 194929adeb4fSGustavo A. R. Silva vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 195029adeb4fSGustavo A. R. Silva GFP_KERNEL); 19512048e328SMark Yao if (!vop) 19522048e328SMark Yao return -ENOMEM; 19532048e328SMark Yao 19542048e328SMark Yao vop->dev = dev; 19552048e328SMark Yao vop->data = vop_data; 19562048e328SMark Yao vop->drm_dev = drm_dev; 19572048e328SMark Yao dev_set_drvdata(dev, vop); 19582048e328SMark Yao 19592048e328SMark Yao vop_win_init(vop); 19602048e328SMark Yao 19612048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 19622048e328SMark Yao vop->len = resource_size(res); 19632048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 19642048e328SMark Yao if (IS_ERR(vop->regs)) 19652048e328SMark Yao return PTR_ERR(vop->regs); 19662048e328SMark Yao 1967b23ab6acSEzequiel Garcia res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1968b23ab6acSEzequiel Garcia if (res) { 1969b23ab6acSEzequiel Garcia if (!vop_data->lut_size) { 1970b23ab6acSEzequiel Garcia DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); 1971b23ab6acSEzequiel Garcia return -EINVAL; 1972b23ab6acSEzequiel Garcia } 1973b23ab6acSEzequiel Garcia vop->lut_regs = devm_ioremap_resource(dev, res); 1974b23ab6acSEzequiel Garcia if (IS_ERR(vop->lut_regs)) 1975b23ab6acSEzequiel Garcia return PTR_ERR(vop->lut_regs); 1976b23ab6acSEzequiel Garcia } 1977b23ab6acSEzequiel Garcia 19782048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 19792048e328SMark Yao if (!vop->regsbak) 19802048e328SMark Yao return -ENOMEM; 19812048e328SMark Yao 19823ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 19833ea68922SHeiko Stuebner if (irq < 0) { 1984d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 19853ea68922SHeiko Stuebner return irq; 19862048e328SMark Yao } 19873ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 19882048e328SMark Yao 19892048e328SMark Yao spin_lock_init(&vop->reg_lock); 19902048e328SMark Yao spin_lock_init(&vop->irq_lock); 1991e334d48bSzain wang mutex_init(&vop->vop_lock); 19922048e328SMark Yao 19932048e328SMark Yao ret = vop_create_crtc(vop); 19942048e328SMark Yao if (ret) 19955f9e93feSMarc Zyngier return ret; 19962048e328SMark Yao 19972048e328SMark Yao pm_runtime_enable(&pdev->dev); 19985182c1a5SYakir Yang 19995e570373SJeffy Chen ret = vop_initial(vop); 20005e570373SJeffy Chen if (ret < 0) { 2001d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 2002d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 20035e570373SJeffy Chen goto err_disable_pm_runtime; 20045e570373SJeffy Chen } 20055e570373SJeffy Chen 20065f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 20075f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 20085f9e93feSMarc Zyngier if (ret) 20095f9e93feSMarc Zyngier goto err_disable_pm_runtime; 20105f9e93feSMarc Zyngier 20111f0f0151SSandy Huang if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 20121f0f0151SSandy Huang vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 20131f0f0151SSandy Huang if (IS_ERR(vop->rgb)) { 20141f0f0151SSandy Huang ret = PTR_ERR(vop->rgb); 20151f0f0151SSandy Huang goto err_disable_pm_runtime; 20161f0f0151SSandy Huang } 20171f0f0151SSandy Huang } 20181f0f0151SSandy Huang 20192048e328SMark Yao return 0; 20208c763c9bSSean Paul 20215e570373SJeffy Chen err_disable_pm_runtime: 20225e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 20235e570373SJeffy Chen vop_destroy_crtc(vop); 20248c763c9bSSean Paul return ret; 20252048e328SMark Yao } 20262048e328SMark Yao 20272048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 20282048e328SMark Yao { 20292048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 20302048e328SMark Yao 20311f0f0151SSandy Huang if (vop->rgb) 20321f0f0151SSandy Huang rockchip_rgb_fini(vop->rgb); 20331f0f0151SSandy Huang 20342048e328SMark Yao pm_runtime_disable(dev); 20352048e328SMark Yao vop_destroy_crtc(vop); 2036ec6e7767SJeffy Chen 2037ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 2038ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 2039ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 20402048e328SMark Yao } 20412048e328SMark Yao 2042a67719d1SMark Yao const struct component_ops vop_component_ops = { 20432048e328SMark Yao .bind = vop_bind, 20442048e328SMark Yao .unbind = vop_unbind, 20452048e328SMark Yao }; 204654255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 2047