19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22048e328SMark Yao /* 32048e328SMark Yao * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 42048e328SMark Yao * Author:Mark Yao <mark.yao@rock-chips.com> 52048e328SMark Yao */ 62048e328SMark Yao 7c2156ccdSSam Ravnborg #include <linux/clk.h> 8c2156ccdSSam Ravnborg #include <linux/component.h> 9c2156ccdSSam Ravnborg #include <linux/delay.h> 10c2156ccdSSam Ravnborg #include <linux/iopoll.h> 11c2156ccdSSam Ravnborg #include <linux/kernel.h> 12c2156ccdSSam Ravnborg #include <linux/module.h> 13c2156ccdSSam Ravnborg #include <linux/of.h> 14c2156ccdSSam Ravnborg #include <linux/of_device.h> 15c2156ccdSSam Ravnborg #include <linux/overflow.h> 16c2156ccdSSam Ravnborg #include <linux/platform_device.h> 17c2156ccdSSam Ravnborg #include <linux/pm_runtime.h> 18c2156ccdSSam Ravnborg #include <linux/reset.h> 19c2156ccdSSam Ravnborg 202048e328SMark Yao #include <drm/drm.h> 2163ebb9faSMark Yao #include <drm/drm_atomic.h> 2215609559SEnric Balletbo i Serra #include <drm/drm_atomic_uapi.h> 232048e328SMark Yao #include <drm/drm_crtc.h> 2447a7eb45STomasz Figa #include <drm/drm_flip_work.h> 25c2156ccdSSam Ravnborg #include <drm/drm_fourcc.h> 26820c1707SThomas Zimmermann #include <drm/drm_gem_atomic_helper.h> 2763d5e06aSHeiko Stuebner #include <drm/drm_gem_framebuffer_helper.h> 282048e328SMark Yao #include <drm/drm_plane_helper.h> 29fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 306c836d96SSean Paul #include <drm/drm_self_refresh_helper.h> 31c2156ccdSSam Ravnborg #include <drm/drm_vblank.h> 32c2156ccdSSam Ravnborg 336cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 343190e58dSTomeu Vizoso #include <drm/bridge/analogix_dp.h> 356cca3869SSean Paul #endif 362048e328SMark Yao 372048e328SMark Yao #include "rockchip_drm_drv.h" 382048e328SMark Yao #include "rockchip_drm_gem.h" 392048e328SMark Yao #include "rockchip_drm_fb.h" 402048e328SMark Yao #include "rockchip_drm_vop.h" 411f0f0151SSandy Huang #include "rockchip_rgb.h" 422048e328SMark Yao 432996fb75SEzequiel Garcia #define VOP_WIN_SET(vop, win, name, v) \ 449a61c54bSMark yao vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 452996fb75SEzequiel Garcia #define VOP_SCL_SET(vop, win, name, v) \ 469a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 472996fb75SEzequiel Garcia #define VOP_SCL_SET_EXT(vop, win, name, v) \ 489a61c54bSMark yao vop_reg_set(vop, &win->phy->scl->ext->name, \ 499a61c54bSMark yao win->base, ~0, v, #name) 50ac6560dfSMark yao 512996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 521c21aa8fSDaniele Castagna do { \ 531c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 541c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 551c21aa8fSDaniele Castagna } while (0) 561c21aa8fSDaniele Castagna 572996fb75SEzequiel Garcia #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 581c21aa8fSDaniele Castagna do { \ 591c21aa8fSDaniele Castagna if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 601c21aa8fSDaniele Castagna vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 611c21aa8fSDaniele Castagna } while (0) 621c21aa8fSDaniele Castagna 63ac6560dfSMark yao #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 649a61c54bSMark yao vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 659a61c54bSMark yao 669a61c54bSMark yao #define VOP_REG_SET(vop, group, name, v) \ 679a61c54bSMark yao vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 68ac6560dfSMark yao 69dbb3d944SMark Yao #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 70dbb3d944SMark Yao do { \ 71c7647f86SJohn Keeping int i, reg = 0, mask = 0; \ 72dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { \ 73c7647f86SJohn Keeping if (vop->data->intr->intrs[i] & type) { \ 74dbb3d944SMark Yao reg |= (v) << i; \ 75c7647f86SJohn Keeping mask |= 1 << i; \ 76dbb3d944SMark Yao } \ 77c7647f86SJohn Keeping } \ 78ac6560dfSMark yao VOP_INTR_SET_MASK(vop, name, mask, reg); \ 79dbb3d944SMark Yao } while (0) 80dbb3d944SMark Yao #define VOP_INTR_GET_TYPE(vop, name, type) \ 81dbb3d944SMark Yao vop_get_intr_type(vop, &vop->data->intr->name, type) 82dbb3d944SMark Yao 832996fb75SEzequiel Garcia #define VOP_WIN_GET(vop, win, name) \ 84cc8f1299SJohn Keeping vop_read_reg(vop, win->base, &win->phy->name) 852048e328SMark Yao 86677e8bbcSDaniele Castagna #define VOP_WIN_HAS_REG(win, name) \ 87677e8bbcSDaniele Castagna (!!(win->phy->name.mask)) 88677e8bbcSDaniele Castagna 892048e328SMark Yao #define VOP_WIN_GET_YRGBADDR(vop, win) \ 902048e328SMark Yao vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 912048e328SMark Yao 9258badaa7SKristian H. Kristensen #define VOP_WIN_TO_INDEX(vop_win) \ 9358badaa7SKristian H. Kristensen ((vop_win) - (vop_win)->vop->win) 9458badaa7SKristian H. Kristensen 957707f722SAndrzej Pietrasiewicz #define VOP_AFBC_SET(vop, name, v) \ 967707f722SAndrzej Pietrasiewicz do { \ 977707f722SAndrzej Pietrasiewicz if ((vop)->data->afbc) \ 987707f722SAndrzej Pietrasiewicz vop_reg_set((vop), &(vop)->data->afbc->name, \ 997707f722SAndrzej Pietrasiewicz 0, ~0, v, #name); \ 1007707f722SAndrzej Pietrasiewicz } while (0) 1017707f722SAndrzej Pietrasiewicz 1022048e328SMark Yao #define to_vop(x) container_of(x, struct vop, crtc) 1032048e328SMark Yao #define to_vop_win(x) container_of(x, struct vop_win, base) 1042048e328SMark Yao 1057707f722SAndrzej Pietrasiewicz #define AFBC_FMT_RGB565 0x0 1067707f722SAndrzej Pietrasiewicz #define AFBC_FMT_U8U8U8U8 0x5 1077707f722SAndrzej Pietrasiewicz #define AFBC_FMT_U8U8U8 0x4 1087707f722SAndrzej Pietrasiewicz 1097707f722SAndrzej Pietrasiewicz #define AFBC_TILE_16x16 BIT(4) 1107707f722SAndrzej Pietrasiewicz 1111c21aa8fSDaniele Castagna /* 1121c21aa8fSDaniele Castagna * The coefficients of the following matrix are all fixed points. 1131c21aa8fSDaniele Castagna * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 1141c21aa8fSDaniele Castagna * They are all represented in two's complement. 1151c21aa8fSDaniele Castagna */ 1161c21aa8fSDaniele Castagna static const uint32_t bt601_yuv2rgb[] = { 1171c21aa8fSDaniele Castagna 0x4A8, 0x0, 0x662, 1181c21aa8fSDaniele Castagna 0x4A8, 0x1E6F, 0x1CBF, 1191c21aa8fSDaniele Castagna 0x4A8, 0x812, 0x0, 1201c21aa8fSDaniele Castagna 0x321168, 0x0877CF, 0x2EB127 1211c21aa8fSDaniele Castagna }; 1221c21aa8fSDaniele Castagna 12347a7eb45STomasz Figa enum vop_pending { 12447a7eb45STomasz Figa VOP_PENDING_FB_UNREF, 12547a7eb45STomasz Figa }; 12647a7eb45STomasz Figa 1272048e328SMark Yao struct vop_win { 1282048e328SMark Yao struct drm_plane base; 1292048e328SMark Yao const struct vop_win_data *data; 1301c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *yuv2yuv_data; 1312048e328SMark Yao struct vop *vop; 1322048e328SMark Yao }; 1332048e328SMark Yao 1341f0f0151SSandy Huang struct rockchip_rgb; 1352048e328SMark Yao struct vop { 1362048e328SMark Yao struct drm_crtc crtc; 1372048e328SMark Yao struct device *dev; 1382048e328SMark Yao struct drm_device *drm_dev; 13931e980c5SMark Yao bool is_enabled; 1402048e328SMark Yao 1411067219bSMark Yao struct completion dsp_hold_completion; 142bed030a4SSean Paul unsigned int win_enabled; 1434f9d39a7SDaniel Vetter 1444f9d39a7SDaniel Vetter /* protected by dev->event_lock */ 14563ebb9faSMark Yao struct drm_pending_vblank_event *event; 1462048e328SMark Yao 14747a7eb45STomasz Figa struct drm_flip_work fb_unref_work; 14847a7eb45STomasz Figa unsigned long pending; 14947a7eb45STomasz Figa 15069c34e41SYakir Yang struct completion line_flag_completion; 15169c34e41SYakir Yang 1522048e328SMark Yao const struct vop_data *data; 1532048e328SMark Yao 1542048e328SMark Yao uint32_t *regsbak; 1552048e328SMark Yao void __iomem *regs; 156b23ab6acSEzequiel Garcia void __iomem *lut_regs; 1572048e328SMark Yao 1582048e328SMark Yao /* physical map length of vop register */ 1592048e328SMark Yao uint32_t len; 1602048e328SMark Yao 1612048e328SMark Yao /* one time only one process allowed to config the register */ 1622048e328SMark Yao spinlock_t reg_lock; 1632048e328SMark Yao /* lock vop irq reg */ 1642048e328SMark Yao spinlock_t irq_lock; 165e334d48bSzain wang /* protects crtc enable/disable */ 166e334d48bSzain wang struct mutex vop_lock; 1672048e328SMark Yao 1682048e328SMark Yao unsigned int irq; 1692048e328SMark Yao 1702048e328SMark Yao /* vop AHP clk */ 1712048e328SMark Yao struct clk *hclk; 1722048e328SMark Yao /* vop dclk */ 1732048e328SMark Yao struct clk *dclk; 1742048e328SMark Yao /* vop share memory frequency */ 1752048e328SMark Yao struct clk *aclk; 1762048e328SMark Yao 1772048e328SMark Yao /* vop dclk reset */ 1782048e328SMark Yao struct reset_control *dclk_rst; 1792048e328SMark Yao 1801f0f0151SSandy Huang /* optional internal rgb encoder */ 1811f0f0151SSandy Huang struct rockchip_rgb *rgb; 1821f0f0151SSandy Huang 1832048e328SMark Yao struct vop_win win[]; 1842048e328SMark Yao }; 1852048e328SMark Yao 1862048e328SMark Yao static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 1872048e328SMark Yao { 1882048e328SMark Yao writel(v, vop->regs + offset); 1892048e328SMark Yao vop->regsbak[offset >> 2] = v; 1902048e328SMark Yao } 1912048e328SMark Yao 1922048e328SMark Yao static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 1932048e328SMark Yao { 1942048e328SMark Yao return readl(vop->regs + offset); 1952048e328SMark Yao } 1962048e328SMark Yao 1972048e328SMark Yao static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 1982048e328SMark Yao const struct vop_reg *reg) 1992048e328SMark Yao { 2002048e328SMark Yao return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 2012048e328SMark Yao } 2022048e328SMark Yao 2039a61c54bSMark yao static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 2049a61c54bSMark yao uint32_t _offset, uint32_t _mask, uint32_t v, 2059a61c54bSMark yao const char *reg_name) 2062048e328SMark Yao { 2079a61c54bSMark yao int offset, mask, shift; 208d49463ecSMark Yao 2099a61c54bSMark yao if (!reg || !reg->mask) { 210d8dd6804SHaneen Mohammed DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 2119a61c54bSMark yao return; 2129a61c54bSMark yao } 2139a61c54bSMark yao 2149a61c54bSMark yao offset = reg->offset + _offset; 2159a61c54bSMark yao mask = reg->mask & _mask; 2169a61c54bSMark yao shift = reg->shift; 2179a61c54bSMark yao 2189a61c54bSMark yao if (reg->write_mask) { 219d49463ecSMark Yao v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 220d49463ecSMark Yao } else { 2212048e328SMark Yao uint32_t cached_val = vop->regsbak[offset >> 2]; 2222048e328SMark Yao 223d49463ecSMark Yao v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 224d49463ecSMark Yao vop->regsbak[offset >> 2] = v; 2252048e328SMark Yao } 2262048e328SMark Yao 2279a61c54bSMark yao if (reg->relaxed) 228d49463ecSMark Yao writel_relaxed(v, vop->regs + offset); 229d49463ecSMark Yao else 230d49463ecSMark Yao writel(v, vop->regs + offset); 2312048e328SMark Yao } 2322048e328SMark Yao 233dbb3d944SMark Yao static inline uint32_t vop_get_intr_type(struct vop *vop, 234dbb3d944SMark Yao const struct vop_reg *reg, int type) 235dbb3d944SMark Yao { 236dbb3d944SMark Yao uint32_t i, ret = 0; 237dbb3d944SMark Yao uint32_t regs = vop_read_reg(vop, 0, reg); 238dbb3d944SMark Yao 239dbb3d944SMark Yao for (i = 0; i < vop->data->intr->nintrs; i++) { 240dbb3d944SMark Yao if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 241dbb3d944SMark Yao ret |= vop->data->intr->intrs[i]; 242dbb3d944SMark Yao } 243dbb3d944SMark Yao 244dbb3d944SMark Yao return ret; 245dbb3d944SMark Yao } 246dbb3d944SMark Yao 2470cf33fe3SMark Yao static inline void vop_cfg_done(struct vop *vop) 2480cf33fe3SMark Yao { 2499a61c54bSMark yao VOP_REG_SET(vop, common, cfg_done, 1); 2500cf33fe3SMark Yao } 2510cf33fe3SMark Yao 25285a359f2STomasz Figa static bool has_rb_swapped(uint32_t format) 25385a359f2STomasz Figa { 25485a359f2STomasz Figa switch (format) { 25585a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 25685a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 25785a359f2STomasz Figa case DRM_FORMAT_BGR888: 25885a359f2STomasz Figa case DRM_FORMAT_BGR565: 25985a359f2STomasz Figa return true; 26085a359f2STomasz Figa default: 26185a359f2STomasz Figa return false; 26285a359f2STomasz Figa } 26385a359f2STomasz Figa } 26485a359f2STomasz Figa 2652048e328SMark Yao static enum vop_data_format vop_convert_format(uint32_t format) 2662048e328SMark Yao { 2672048e328SMark Yao switch (format) { 2682048e328SMark Yao case DRM_FORMAT_XRGB8888: 2692048e328SMark Yao case DRM_FORMAT_ARGB8888: 27085a359f2STomasz Figa case DRM_FORMAT_XBGR8888: 27185a359f2STomasz Figa case DRM_FORMAT_ABGR8888: 2722048e328SMark Yao return VOP_FMT_ARGB8888; 2732048e328SMark Yao case DRM_FORMAT_RGB888: 27485a359f2STomasz Figa case DRM_FORMAT_BGR888: 2752048e328SMark Yao return VOP_FMT_RGB888; 2762048e328SMark Yao case DRM_FORMAT_RGB565: 27785a359f2STomasz Figa case DRM_FORMAT_BGR565: 2782048e328SMark Yao return VOP_FMT_RGB565; 2792048e328SMark Yao case DRM_FORMAT_NV12: 2802048e328SMark Yao return VOP_FMT_YUV420SP; 2812048e328SMark Yao case DRM_FORMAT_NV16: 2822048e328SMark Yao return VOP_FMT_YUV422SP; 2832048e328SMark Yao case DRM_FORMAT_NV24: 2842048e328SMark Yao return VOP_FMT_YUV444SP; 2852048e328SMark Yao default: 286ee4d7899SSean Paul DRM_ERROR("unsupported format[%08x]\n", format); 2872048e328SMark Yao return -EINVAL; 2882048e328SMark Yao } 2892048e328SMark Yao } 2902048e328SMark Yao 2917707f722SAndrzej Pietrasiewicz static int vop_convert_afbc_format(uint32_t format) 2927707f722SAndrzej Pietrasiewicz { 2937707f722SAndrzej Pietrasiewicz switch (format) { 2947707f722SAndrzej Pietrasiewicz case DRM_FORMAT_XRGB8888: 2957707f722SAndrzej Pietrasiewicz case DRM_FORMAT_ARGB8888: 2967707f722SAndrzej Pietrasiewicz case DRM_FORMAT_XBGR8888: 2977707f722SAndrzej Pietrasiewicz case DRM_FORMAT_ABGR8888: 2987707f722SAndrzej Pietrasiewicz return AFBC_FMT_U8U8U8U8; 2997707f722SAndrzej Pietrasiewicz case DRM_FORMAT_RGB888: 3007707f722SAndrzej Pietrasiewicz case DRM_FORMAT_BGR888: 3017707f722SAndrzej Pietrasiewicz return AFBC_FMT_U8U8U8; 3027707f722SAndrzej Pietrasiewicz case DRM_FORMAT_RGB565: 3037707f722SAndrzej Pietrasiewicz case DRM_FORMAT_BGR565: 3047707f722SAndrzej Pietrasiewicz return AFBC_FMT_RGB565; 3057707f722SAndrzej Pietrasiewicz /* either of the below should not be reachable */ 3067707f722SAndrzej Pietrasiewicz default: 3077707f722SAndrzej Pietrasiewicz DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); 3087707f722SAndrzej Pietrasiewicz return -EINVAL; 3097707f722SAndrzej Pietrasiewicz } 3107707f722SAndrzej Pietrasiewicz 3117707f722SAndrzej Pietrasiewicz return -EINVAL; 3127707f722SAndrzej Pietrasiewicz } 3137707f722SAndrzej Pietrasiewicz 3144c156c21SMark Yao static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 3154c156c21SMark Yao uint32_t dst, bool is_horizontal, 3164c156c21SMark Yao int vsu_mode, int *vskiplines) 3174c156c21SMark Yao { 3184c156c21SMark Yao uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 3194c156c21SMark Yao 320ce91d373SJeffy Chen if (vskiplines) 321ce91d373SJeffy Chen *vskiplines = 0; 322ce91d373SJeffy Chen 3234c156c21SMark Yao if (is_horizontal) { 3244c156c21SMark Yao if (mode == SCALE_UP) 3254c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3264c156c21SMark Yao else if (mode == SCALE_DOWN) 3274c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3284c156c21SMark Yao } else { 3294c156c21SMark Yao if (mode == SCALE_UP) { 3304c156c21SMark Yao if (vsu_mode == SCALE_UP_BIL) 3314c156c21SMark Yao val = GET_SCL_FT_BILI_UP(src, dst); 3324c156c21SMark Yao else 3334c156c21SMark Yao val = GET_SCL_FT_BIC(src, dst); 3344c156c21SMark Yao } else if (mode == SCALE_DOWN) { 3354c156c21SMark Yao if (vskiplines) { 3364c156c21SMark Yao *vskiplines = scl_get_vskiplines(src, dst); 3374c156c21SMark Yao val = scl_get_bili_dn_vskip(src, dst, 3384c156c21SMark Yao *vskiplines); 3394c156c21SMark Yao } else { 3404c156c21SMark Yao val = GET_SCL_FT_BILI_DN(src, dst); 3414c156c21SMark Yao } 3424c156c21SMark Yao } 3434c156c21SMark Yao } 3444c156c21SMark Yao 3454c156c21SMark Yao return val; 3464c156c21SMark Yao } 3474c156c21SMark Yao 3484c156c21SMark Yao static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 3494c156c21SMark Yao uint32_t src_w, uint32_t src_h, uint32_t dst_w, 35045babef0SMaxime Ripard uint32_t dst_h, const struct drm_format_info *info) 3514c156c21SMark Yao { 3524c156c21SMark Yao uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3534c156c21SMark Yao uint16_t cbcr_hor_scl_mode = SCALE_NONE; 3544c156c21SMark Yao uint16_t cbcr_ver_scl_mode = SCALE_NONE; 355d8bd23d9SAyan Kumar Halder bool is_yuv = false; 356f3e9632cSMaxime Ripard uint16_t cbcr_src_w = src_w / info->hsub; 357f3e9632cSMaxime Ripard uint16_t cbcr_src_h = src_h / info->vsub; 3584c156c21SMark Yao uint16_t vsu_mode; 3594c156c21SMark Yao uint16_t lb_mode; 3604c156c21SMark Yao uint32_t val; 361ce91d373SJeffy Chen int vskiplines; 3624c156c21SMark Yao 363d8bd23d9SAyan Kumar Halder if (info->is_yuv) 364d8bd23d9SAyan Kumar Halder is_yuv = true; 365d8bd23d9SAyan Kumar Halder 3664c156c21SMark Yao if (dst_w > 3840) { 367ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 3684c156c21SMark Yao return; 3694c156c21SMark Yao } 3704c156c21SMark Yao 3711194fffbSMark Yao if (!win->phy->scl->ext) { 3721194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, 3731194fffbSMark Yao scl_cal_scale2(src_w, dst_w)); 3741194fffbSMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, 3751194fffbSMark Yao scl_cal_scale2(src_h, dst_h)); 3761194fffbSMark Yao if (is_yuv) { 3771194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, 378ee8662fcSMark Yao scl_cal_scale2(cbcr_src_w, dst_w)); 3791194fffbSMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, 380ee8662fcSMark Yao scl_cal_scale2(cbcr_src_h, dst_h)); 3811194fffbSMark Yao } 3821194fffbSMark Yao return; 3831194fffbSMark Yao } 3841194fffbSMark Yao 3854c156c21SMark Yao yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3864c156c21SMark Yao yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3874c156c21SMark Yao 3884c156c21SMark Yao if (is_yuv) { 3894c156c21SMark Yao cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 3904c156c21SMark Yao cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 3914c156c21SMark Yao if (cbcr_hor_scl_mode == SCALE_DOWN) 3924c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, true); 3934c156c21SMark Yao else 3944c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 3954c156c21SMark Yao } else { 3964c156c21SMark Yao if (yrgb_hor_scl_mode == SCALE_DOWN) 3974c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(dst_w, false); 3984c156c21SMark Yao else 3994c156c21SMark Yao lb_mode = scl_vop_cal_lb_mode(src_w, false); 4004c156c21SMark Yao } 4014c156c21SMark Yao 4021194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 4034c156c21SMark Yao if (lb_mode == LB_RGB_3840X2) { 4044c156c21SMark Yao if (yrgb_ver_scl_mode != SCALE_NONE) { 405ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 4064c156c21SMark Yao return; 4074c156c21SMark Yao } 4084c156c21SMark Yao if (cbcr_ver_scl_mode != SCALE_NONE) { 409ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 4104c156c21SMark Yao return; 4114c156c21SMark Yao } 4124c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 4134c156c21SMark Yao } else if (lb_mode == LB_RGB_2560X4) { 4144c156c21SMark Yao vsu_mode = SCALE_UP_BIL; 4154c156c21SMark Yao } else { 4164c156c21SMark Yao vsu_mode = SCALE_UP_BIC; 4174c156c21SMark Yao } 4184c156c21SMark Yao 4194c156c21SMark Yao val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 4204c156c21SMark Yao true, 0, NULL); 4214c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_x, val); 4224c156c21SMark Yao val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 4234c156c21SMark Yao false, vsu_mode, &vskiplines); 4244c156c21SMark Yao VOP_SCL_SET(vop, win, scale_yrgb_y, val); 4254c156c21SMark Yao 4261194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 4271194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 4284c156c21SMark Yao 4291194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 4301194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 4311194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 4321194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 4331194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 4344c156c21SMark Yao if (is_yuv) { 4354c156c21SMark Yao val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 4364c156c21SMark Yao dst_w, true, 0, NULL); 4374c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_x, val); 4384c156c21SMark Yao val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 4394c156c21SMark Yao dst_h, false, vsu_mode, &vskiplines); 4404c156c21SMark Yao VOP_SCL_SET(vop, win, scale_cbcr_y, val); 4414c156c21SMark Yao 4421194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 4431194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 4441194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 4451194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 4461194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 4471194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 4481194fffbSMark Yao VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 4494c156c21SMark Yao } 4504c156c21SMark Yao } 4514c156c21SMark Yao 4521067219bSMark Yao static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 4531067219bSMark Yao { 4541067219bSMark Yao unsigned long flags; 4551067219bSMark Yao 4561067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4571067219bSMark Yao return; 4581067219bSMark Yao 4591067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4601067219bSMark Yao 461fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 462dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 4631067219bSMark Yao 4641067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4651067219bSMark Yao } 4661067219bSMark Yao 4671067219bSMark Yao static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 4681067219bSMark Yao { 4691067219bSMark Yao unsigned long flags; 4701067219bSMark Yao 4711067219bSMark Yao if (WARN_ON(!vop->is_enabled)) 4721067219bSMark Yao return; 4731067219bSMark Yao 4741067219bSMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 4751067219bSMark Yao 476dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 4771067219bSMark Yao 4781067219bSMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 4791067219bSMark Yao } 4801067219bSMark Yao 48169c34e41SYakir Yang /* 48269c34e41SYakir Yang * (1) each frame starts at the start of the Vsync pulse which is signaled by 48369c34e41SYakir Yang * the "FRAME_SYNC" interrupt. 48469c34e41SYakir Yang * (2) the active data region of each frame ends at dsp_vact_end 48569c34e41SYakir Yang * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 48669c34e41SYakir Yang * to get "LINE_FLAG" interrupt at the end of the active on screen data. 48769c34e41SYakir Yang * 48869c34e41SYakir Yang * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 48969c34e41SYakir Yang * Interrupts 49069c34e41SYakir Yang * LINE_FLAG -------------------------------+ 49169c34e41SYakir Yang * FRAME_SYNC ----+ | 49269c34e41SYakir Yang * | | 49369c34e41SYakir Yang * v v 49469c34e41SYakir Yang * | Vsync | Vbp | Vactive | Vfp | 49569c34e41SYakir Yang * ^ ^ ^ ^ 49669c34e41SYakir Yang * | | | | 49769c34e41SYakir Yang * | | | | 49869c34e41SYakir Yang * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 49969c34e41SYakir Yang * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 50069c34e41SYakir Yang * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 50169c34e41SYakir Yang * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 50269c34e41SYakir Yang */ 50369c34e41SYakir Yang static bool vop_line_flag_irq_is_enabled(struct vop *vop) 50469c34e41SYakir Yang { 50569c34e41SYakir Yang uint32_t line_flag_irq; 50669c34e41SYakir Yang unsigned long flags; 50769c34e41SYakir Yang 50869c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 50969c34e41SYakir Yang 51069c34e41SYakir Yang line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 51169c34e41SYakir Yang 51269c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 51369c34e41SYakir Yang 51469c34e41SYakir Yang return !!line_flag_irq; 51569c34e41SYakir Yang } 51669c34e41SYakir Yang 517459b086dSJeffy Chen static void vop_line_flag_irq_enable(struct vop *vop) 51869c34e41SYakir Yang { 51969c34e41SYakir Yang unsigned long flags; 52069c34e41SYakir Yang 52169c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 52269c34e41SYakir Yang return; 52369c34e41SYakir Yang 52469c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 52569c34e41SYakir Yang 526fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 52769c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 52869c34e41SYakir Yang 52969c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 53069c34e41SYakir Yang } 53169c34e41SYakir Yang 53269c34e41SYakir Yang static void vop_line_flag_irq_disable(struct vop *vop) 53369c34e41SYakir Yang { 53469c34e41SYakir Yang unsigned long flags; 53569c34e41SYakir Yang 53669c34e41SYakir Yang if (WARN_ON(!vop->is_enabled)) 53769c34e41SYakir Yang return; 53869c34e41SYakir Yang 53969c34e41SYakir Yang spin_lock_irqsave(&vop->irq_lock, flags); 54069c34e41SYakir Yang 54169c34e41SYakir Yang VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 54269c34e41SYakir Yang 54369c34e41SYakir Yang spin_unlock_irqrestore(&vop->irq_lock, flags); 54469c34e41SYakir Yang } 54569c34e41SYakir Yang 546e2810a71SHeiko Stuebner static int vop_core_clks_enable(struct vop *vop) 547e2810a71SHeiko Stuebner { 548e2810a71SHeiko Stuebner int ret; 549e2810a71SHeiko Stuebner 550e2810a71SHeiko Stuebner ret = clk_enable(vop->hclk); 551e2810a71SHeiko Stuebner if (ret < 0) 552e2810a71SHeiko Stuebner return ret; 553e2810a71SHeiko Stuebner 554e2810a71SHeiko Stuebner ret = clk_enable(vop->aclk); 555e2810a71SHeiko Stuebner if (ret < 0) 556e2810a71SHeiko Stuebner goto err_disable_hclk; 557e2810a71SHeiko Stuebner 558e2810a71SHeiko Stuebner return 0; 559e2810a71SHeiko Stuebner 560e2810a71SHeiko Stuebner err_disable_hclk: 561e2810a71SHeiko Stuebner clk_disable(vop->hclk); 562e2810a71SHeiko Stuebner return ret; 563e2810a71SHeiko Stuebner } 564e2810a71SHeiko Stuebner 565e2810a71SHeiko Stuebner static void vop_core_clks_disable(struct vop *vop) 566e2810a71SHeiko Stuebner { 567e2810a71SHeiko Stuebner clk_disable(vop->aclk); 568e2810a71SHeiko Stuebner clk_disable(vop->hclk); 569e2810a71SHeiko Stuebner } 570e2810a71SHeiko Stuebner 5712b60e11dSSean Paul static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 572e9abc611SJonas Karlman { 5732b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 5742b60e11dSSean Paul 575e9abc611SJonas Karlman if (win->phy->scl && win->phy->scl->ext) { 576e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 577e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 578e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 579e9abc611SJonas Karlman VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 580e9abc611SJonas Karlman } 581e9abc611SJonas Karlman 582e9abc611SJonas Karlman VOP_WIN_SET(vop, win, enable, 0); 583bed030a4SSean Paul vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 584e9abc611SJonas Karlman } 585e9abc611SJonas Karlman 5866c836d96SSean Paul static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 5872048e328SMark Yao { 5882048e328SMark Yao struct vop *vop = to_vop(crtc); 58964d77564SMark yao int ret, i; 5902048e328SMark Yao 5915d82d1a7SMark Yao ret = pm_runtime_get_sync(vop->dev); 5925d82d1a7SMark Yao if (ret < 0) { 593d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 5945e570373SJeffy Chen return ret; 5955d82d1a7SMark Yao } 5965d82d1a7SMark Yao 597e2810a71SHeiko Stuebner ret = vop_core_clks_enable(vop); 59839a9ad8fSSean Paul if (WARN_ON(ret < 0)) 59939a9ad8fSSean Paul goto err_put_pm_runtime; 6002048e328SMark Yao 6012048e328SMark Yao ret = clk_enable(vop->dclk); 60239a9ad8fSSean Paul if (WARN_ON(ret < 0)) 603e2810a71SHeiko Stuebner goto err_disable_core; 6042048e328SMark Yao 6052048e328SMark Yao /* 6062048e328SMark Yao * Slave iommu shares power, irq and clock with vop. It was associated 6072048e328SMark Yao * automatically with this master device via common driver code. 6082048e328SMark Yao * Now that we have enabled the clock we attach it to the shared drm 6092048e328SMark Yao * mapping. 6102048e328SMark Yao */ 6112048e328SMark Yao ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 6122048e328SMark Yao if (ret) { 613d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, 614d8dd6804SHaneen Mohammed "failed to attach dma mapping, %d\n", ret); 615e2810a71SHeiko Stuebner goto err_disable_dclk; 6162048e328SMark Yao } 6172048e328SMark Yao 61876f1416eSMarc Zyngier spin_lock(&vop->reg_lock); 61976f1416eSMarc Zyngier for (i = 0; i < vop->len; i += 4) 62076f1416eSMarc Zyngier writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 62176f1416eSMarc Zyngier 62264d77564SMark yao /* 62364d77564SMark yao * We need to make sure that all windows are disabled before we 62464d77564SMark yao * enable the crtc. Otherwise we might try to scan from a destroyed 62564d77564SMark yao * buffer later. 6266c836d96SSean Paul * 6276c836d96SSean Paul * In the case of enable-after-PSR, we don't need to worry about this 6286c836d96SSean Paul * case since the buffer is guaranteed to be valid and disabling the 6296c836d96SSean Paul * window will result in screen glitches on PSR exit. 63064d77564SMark yao */ 6316c836d96SSean Paul if (!old_state || !old_state->self_refresh_active) { 63264d77564SMark yao for (i = 0; i < vop->data->win_size; i++) { 63364d77564SMark yao struct vop_win *vop_win = &vop->win[i]; 63464d77564SMark yao 6352b60e11dSSean Paul vop_win_disable(vop, vop_win); 63664d77564SMark yao } 6376c836d96SSean Paul } 6387707f722SAndrzej Pietrasiewicz 6397707f722SAndrzej Pietrasiewicz if (vop->data->afbc) { 6407707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 6417707f722SAndrzej Pietrasiewicz /* 6427707f722SAndrzej Pietrasiewicz * Disable AFBC and forget there was a vop window with AFBC 6437707f722SAndrzej Pietrasiewicz */ 6447707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, enable, 0); 6457707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc->state); 6467707f722SAndrzej Pietrasiewicz s->enable_afbc = false; 6477707f722SAndrzej Pietrasiewicz } 6487707f722SAndrzej Pietrasiewicz 64917a794d7SChris Zhong vop_cfg_done(vop); 65017a794d7SChris Zhong 6515fa63f07SEmil Velikov spin_unlock(&vop->reg_lock); 6525fa63f07SEmil Velikov 65352ab7891SMark Yao /* 65452ab7891SMark Yao * At here, vop clock & iommu is enable, R/W vop regs would be safe. 65552ab7891SMark Yao */ 65652ab7891SMark Yao vop->is_enabled = true; 65752ab7891SMark Yao 6582048e328SMark Yao spin_lock(&vop->reg_lock); 6592048e328SMark Yao 6609a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 6612048e328SMark Yao 6622048e328SMark Yao spin_unlock(&vop->reg_lock); 6632048e328SMark Yao 664b5f7b755SMark Yao drm_crtc_vblank_on(crtc); 6652048e328SMark Yao 66639a9ad8fSSean Paul return 0; 6672048e328SMark Yao 6682048e328SMark Yao err_disable_dclk: 6692048e328SMark Yao clk_disable(vop->dclk); 670e2810a71SHeiko Stuebner err_disable_core: 671e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 67239a9ad8fSSean Paul err_put_pm_runtime: 67339a9ad8fSSean Paul pm_runtime_put_sync(vop->dev); 67439a9ad8fSSean Paul return ret; 6752048e328SMark Yao } 6762048e328SMark Yao 677bed030a4SSean Paul static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 678bed030a4SSean Paul { 679bed030a4SSean Paul struct vop *vop = to_vop(crtc); 680bed030a4SSean Paul int i; 681bed030a4SSean Paul 682bed030a4SSean Paul spin_lock(&vop->reg_lock); 683bed030a4SSean Paul 684bed030a4SSean Paul for (i = 0; i < vop->data->win_size; i++) { 685bed030a4SSean Paul struct vop_win *vop_win = &vop->win[i]; 686bed030a4SSean Paul const struct vop_win_data *win = vop_win->data; 687bed030a4SSean Paul 688bed030a4SSean Paul VOP_WIN_SET(vop, win, enable, 689bed030a4SSean Paul enabled && (vop->win_enabled & BIT(i))); 690bed030a4SSean Paul } 691bed030a4SSean Paul vop_cfg_done(vop); 692bed030a4SSean Paul 693bed030a4SSean Paul spin_unlock(&vop->reg_lock); 694bed030a4SSean Paul } 695bed030a4SSean Paul 69664581714SLaurent Pinchart static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 697351f950dSMaxime Ripard struct drm_atomic_state *state) 6982048e328SMark Yao { 6992048e328SMark Yao struct vop *vop = to_vop(crtc); 7002048e328SMark Yao 701893b6cadSDaniel Vetter WARN_ON(vop->event); 702893b6cadSDaniel Vetter 703bed030a4SSean Paul if (crtc->state->self_refresh_active) 704bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, false); 705bed030a4SSean Paul 706e334d48bSzain wang mutex_lock(&vop->vop_lock); 7076c836d96SSean Paul 708b5f7b755SMark Yao drm_crtc_vblank_off(crtc); 7092048e328SMark Yao 710bed030a4SSean Paul if (crtc->state->self_refresh_active) 711bed030a4SSean Paul goto out; 712bed030a4SSean Paul 7132048e328SMark Yao /* 7141067219bSMark Yao * Vop standby will take effect at end of current frame, 7151067219bSMark Yao * if dsp hold valid irq happen, it means standby complete. 7161067219bSMark Yao * 7171067219bSMark Yao * we must wait standby complete when we want to disable aclk, 7181067219bSMark Yao * if not, memory bus maybe dead. 7192048e328SMark Yao */ 7201067219bSMark Yao reinit_completion(&vop->dsp_hold_completion); 7211067219bSMark Yao vop_dsp_hold_valid_irq_enable(vop); 7221067219bSMark Yao 7232048e328SMark Yao spin_lock(&vop->reg_lock); 7242048e328SMark Yao 7259a61c54bSMark yao VOP_REG_SET(vop, common, standby, 1); 7262048e328SMark Yao 7272048e328SMark Yao spin_unlock(&vop->reg_lock); 72852ab7891SMark Yao 7291067219bSMark Yao wait_for_completion(&vop->dsp_hold_completion); 7302048e328SMark Yao 7311067219bSMark Yao vop_dsp_hold_valid_irq_disable(vop); 7321067219bSMark Yao 7331067219bSMark Yao vop->is_enabled = false; 7341067219bSMark Yao 7351067219bSMark Yao /* 7361067219bSMark Yao * vop standby complete, so iommu detach is safe. 7371067219bSMark Yao */ 7382048e328SMark Yao rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 7392048e328SMark Yao 7401067219bSMark Yao clk_disable(vop->dclk); 741e2810a71SHeiko Stuebner vop_core_clks_disable(vop); 7425d82d1a7SMark Yao pm_runtime_put(vop->dev); 743bed030a4SSean Paul 744bed030a4SSean Paul out: 745e334d48bSzain wang mutex_unlock(&vop->vop_lock); 746893b6cadSDaniel Vetter 747893b6cadSDaniel Vetter if (crtc->state->event && !crtc->state->active) { 748893b6cadSDaniel Vetter spin_lock_irq(&crtc->dev->event_lock); 749893b6cadSDaniel Vetter drm_crtc_send_vblank_event(crtc, crtc->state->event); 750893b6cadSDaniel Vetter spin_unlock_irq(&crtc->dev->event_lock); 751893b6cadSDaniel Vetter 752893b6cadSDaniel Vetter crtc->state->event = NULL; 753893b6cadSDaniel Vetter } 7542048e328SMark Yao } 7552048e328SMark Yao 75663ebb9faSMark Yao static void vop_plane_destroy(struct drm_plane *plane) 7572048e328SMark Yao { 75863ebb9faSMark Yao drm_plane_cleanup(plane); 7592048e328SMark Yao } 7602048e328SMark Yao 7617707f722SAndrzej Pietrasiewicz static inline bool rockchip_afbc(u64 modifier) 7627707f722SAndrzej Pietrasiewicz { 7637707f722SAndrzej Pietrasiewicz return modifier == ROCKCHIP_AFBC_MOD; 7647707f722SAndrzej Pietrasiewicz } 7657707f722SAndrzej Pietrasiewicz 7667707f722SAndrzej Pietrasiewicz static bool rockchip_mod_supported(struct drm_plane *plane, 7677707f722SAndrzej Pietrasiewicz u32 format, u64 modifier) 7687707f722SAndrzej Pietrasiewicz { 7697707f722SAndrzej Pietrasiewicz if (modifier == DRM_FORMAT_MOD_LINEAR) 7707707f722SAndrzej Pietrasiewicz return true; 7717707f722SAndrzej Pietrasiewicz 7727707f722SAndrzej Pietrasiewicz if (!rockchip_afbc(modifier)) { 7736472e4e2SColin Ian King DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 7747707f722SAndrzej Pietrasiewicz 7757707f722SAndrzej Pietrasiewicz return false; 7767707f722SAndrzej Pietrasiewicz } 7777707f722SAndrzej Pietrasiewicz 7787707f722SAndrzej Pietrasiewicz return vop_convert_afbc_format(format) >= 0; 7797707f722SAndrzej Pietrasiewicz } 7807707f722SAndrzej Pietrasiewicz 78163ebb9faSMark Yao static int vop_plane_atomic_check(struct drm_plane *plane, 7827c11b99aSMaxime Ripard struct drm_atomic_state *state) 7832048e328SMark Yao { 7847c11b99aSMaxime Ripard struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 7857c11b99aSMaxime Ripard plane); 786ba5c1649SMaxime Ripard struct drm_crtc *crtc = new_plane_state->crtc; 78792915da6SJohn Keeping struct drm_crtc_state *crtc_state; 788ba5c1649SMaxime Ripard struct drm_framebuffer *fb = new_plane_state->fb; 7892048e328SMark Yao struct vop_win *vop_win = to_vop_win(plane); 7902048e328SMark Yao const struct vop_win_data *win = vop_win->data; 7912048e328SMark Yao int ret; 7924c156c21SMark Yao int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 7934c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7944c156c21SMark Yao int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 7954c156c21SMark Yao DRM_PLANE_HELPER_NO_SCALING; 7962048e328SMark Yao 797fd907adeSDaniel Vetter if (!crtc || WARN_ON(!fb)) 798d47a7246STomasz Figa return 0; 79992915da6SJohn Keeping 800dec92020SMaxime Ripard crtc_state = drm_atomic_get_existing_crtc_state(state, 801ba5c1649SMaxime Ripard crtc); 80292915da6SJohn Keeping if (WARN_ON(!crtc_state)) 80392915da6SJohn Keeping return -EINVAL; 80492915da6SJohn Keeping 805ba5c1649SMaxime Ripard ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 806f9b96be0SVille Syrjälä min_scale, max_scale, 807f9b96be0SVille Syrjälä true, true); 8082048e328SMark Yao if (ret) 8092048e328SMark Yao return ret; 8102048e328SMark Yao 811ba5c1649SMaxime Ripard if (!new_plane_state->visible) 812d47a7246STomasz Figa return 0; 8132048e328SMark Yao 814438b74a5SVille Syrjälä ret = vop_convert_format(fb->format->format); 815d47a7246STomasz Figa if (ret < 0) 816d47a7246STomasz Figa return ret; 81784c7f8caSMark Yao 81884c7f8caSMark Yao /* 81984c7f8caSMark Yao * Src.x1 can be odd when do clip, but yuv plane start point 82084c7f8caSMark Yao * need align with 2 pixel. 82184c7f8caSMark Yao */ 822ba5c1649SMaxime Ripard if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 823d415fb87SMark yao DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 82463ebb9faSMark Yao return -EINVAL; 825d415fb87SMark yao } 82663ebb9faSMark Yao 827ba5c1649SMaxime Ripard if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 828677e8bbcSDaniele Castagna DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 829677e8bbcSDaniele Castagna return -EINVAL; 830677e8bbcSDaniele Castagna } 831677e8bbcSDaniele Castagna 8327707f722SAndrzej Pietrasiewicz if (rockchip_afbc(fb->modifier)) { 8337707f722SAndrzej Pietrasiewicz struct vop *vop = to_vop(crtc); 8347707f722SAndrzej Pietrasiewicz 8357707f722SAndrzej Pietrasiewicz if (!vop->data->afbc) { 8367707f722SAndrzej Pietrasiewicz DRM_ERROR("vop does not support AFBC\n"); 8377707f722SAndrzej Pietrasiewicz return -EINVAL; 8387707f722SAndrzej Pietrasiewicz } 8397707f722SAndrzej Pietrasiewicz 8407707f722SAndrzej Pietrasiewicz ret = vop_convert_afbc_format(fb->format->format); 8417707f722SAndrzej Pietrasiewicz if (ret < 0) 8427707f722SAndrzej Pietrasiewicz return ret; 8437707f722SAndrzej Pietrasiewicz 844ba5c1649SMaxime Ripard if (new_plane_state->src.x1 || new_plane_state->src.y1) { 845ba5c1649SMaxime Ripard DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", 846ba5c1649SMaxime Ripard new_plane_state->src.x1, 847ba5c1649SMaxime Ripard new_plane_state->src.y1, fb->offsets[0]); 8487707f722SAndrzej Pietrasiewicz return -EINVAL; 8497707f722SAndrzej Pietrasiewicz } 8507707f722SAndrzej Pietrasiewicz 851ba5c1649SMaxime Ripard if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 8527707f722SAndrzej Pietrasiewicz DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 853ba5c1649SMaxime Ripard new_plane_state->rotation); 8547707f722SAndrzej Pietrasiewicz return -EINVAL; 8557707f722SAndrzej Pietrasiewicz } 8567707f722SAndrzej Pietrasiewicz } 8577707f722SAndrzej Pietrasiewicz 85863ebb9faSMark Yao return 0; 85984c7f8caSMark Yao } 86084c7f8caSMark Yao 86163ebb9faSMark Yao static void vop_plane_atomic_disable(struct drm_plane *plane, 862977697e2SMaxime Ripard struct drm_atomic_state *state) 86363ebb9faSMark Yao { 864977697e2SMaxime Ripard struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 865977697e2SMaxime Ripard plane); 86663ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 86763ebb9faSMark Yao struct vop *vop = to_vop(old_state->crtc); 8682048e328SMark Yao 86963ebb9faSMark Yao if (!old_state->crtc) 87063ebb9faSMark Yao return; 8712048e328SMark Yao 87263ebb9faSMark Yao spin_lock(&vop->reg_lock); 8732048e328SMark Yao 8742b60e11dSSean Paul vop_win_disable(vop, vop_win); 8752048e328SMark Yao 87663ebb9faSMark Yao spin_unlock(&vop->reg_lock); 87763ebb9faSMark Yao } 87863ebb9faSMark Yao 87963ebb9faSMark Yao static void vop_plane_atomic_update(struct drm_plane *plane, 880977697e2SMaxime Ripard struct drm_atomic_state *state) 88163ebb9faSMark Yao { 88237418bf1SMaxime Ripard struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 88337418bf1SMaxime Ripard plane); 88441016fe1SMaxime Ripard struct drm_crtc *crtc = new_state->crtc; 88563ebb9faSMark Yao struct vop_win *vop_win = to_vop_win(plane); 88663ebb9faSMark Yao const struct vop_win_data *win = vop_win->data; 8871c21aa8fSDaniele Castagna const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 88841016fe1SMaxime Ripard struct vop *vop = to_vop(new_state->crtc); 88941016fe1SMaxime Ripard struct drm_framebuffer *fb = new_state->fb; 89063ebb9faSMark Yao unsigned int actual_w, actual_h; 89163ebb9faSMark Yao unsigned int dsp_stx, dsp_sty; 89263ebb9faSMark Yao uint32_t act_info, dsp_info, dsp_st; 89341016fe1SMaxime Ripard struct drm_rect *src = &new_state->src; 89441016fe1SMaxime Ripard struct drm_rect *dest = &new_state->dst; 89563ebb9faSMark Yao struct drm_gem_object *obj, *uv_obj; 89663ebb9faSMark Yao struct rockchip_gem_object *rk_obj, *rk_uv_obj; 89763ebb9faSMark Yao unsigned long offset; 89863ebb9faSMark Yao dma_addr_t dma_addr; 89963ebb9faSMark Yao uint32_t val; 90063ebb9faSMark Yao bool rb_swap; 90158badaa7SKristian H. Kristensen int win_index = VOP_WIN_TO_INDEX(vop_win); 902d47a7246STomasz Figa int format; 9031c21aa8fSDaniele Castagna int is_yuv = fb->format->is_yuv; 9041c21aa8fSDaniele Castagna int i; 90563ebb9faSMark Yao 90663ebb9faSMark Yao /* 90763ebb9faSMark Yao * can't update plane when vop is disabled. 90863ebb9faSMark Yao */ 9094f9d39a7SDaniel Vetter if (WARN_ON(!crtc)) 91063ebb9faSMark Yao return; 91163ebb9faSMark Yao 91263ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 91363ebb9faSMark Yao return; 91463ebb9faSMark Yao 91541016fe1SMaxime Ripard if (!new_state->visible) { 916977697e2SMaxime Ripard vop_plane_atomic_disable(plane, state); 91763ebb9faSMark Yao return; 91863ebb9faSMark Yao } 91963ebb9faSMark Yao 920957428f9SDaniel Stone obj = fb->obj[0]; 92163ebb9faSMark Yao rk_obj = to_rockchip_obj(obj); 92263ebb9faSMark Yao 92363ebb9faSMark Yao actual_w = drm_rect_width(src) >> 16; 92463ebb9faSMark Yao actual_h = drm_rect_height(src) >> 16; 92563ebb9faSMark Yao act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 92663ebb9faSMark Yao 92763ebb9faSMark Yao dsp_info = (drm_rect_height(dest) - 1) << 16; 92863ebb9faSMark Yao dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 92963ebb9faSMark Yao 93063ebb9faSMark Yao dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 93163ebb9faSMark Yao dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 93263ebb9faSMark Yao dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 93363ebb9faSMark Yao 934353c8598SVille Syrjälä offset = (src->x1 >> 16) * fb->format->cpp[0]; 93563ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[0]; 936d47a7246STomasz Figa dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 937d47a7246STomasz Figa 938677e8bbcSDaniele Castagna /* 939677e8bbcSDaniele Castagna * For y-mirroring we need to move address 940677e8bbcSDaniele Castagna * to the beginning of the last line. 941677e8bbcSDaniele Castagna */ 94241016fe1SMaxime Ripard if (new_state->rotation & DRM_MODE_REFLECT_Y) 943677e8bbcSDaniele Castagna dma_addr += (actual_h - 1) * fb->pitches[0]; 944677e8bbcSDaniele Castagna 945438b74a5SVille Syrjälä format = vop_convert_format(fb->format->format); 94663ebb9faSMark Yao 94763ebb9faSMark Yao spin_lock(&vop->reg_lock); 94863ebb9faSMark Yao 9497707f722SAndrzej Pietrasiewicz if (rockchip_afbc(fb->modifier)) { 9507707f722SAndrzej Pietrasiewicz int afbc_format = vop_convert_afbc_format(fb->format->format); 9517707f722SAndrzej Pietrasiewicz 9527707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 9537707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, hreg_block_split, 0); 9547707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 9557707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 9567707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, pic_size, act_info); 9577707f722SAndrzej Pietrasiewicz } 9587707f722SAndrzej Pietrasiewicz 959d47a7246STomasz Figa VOP_WIN_SET(vop, win, format, format); 960da709a7bSMark yao VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 961d47a7246STomasz Figa VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 9621c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 963677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, y_mir_en, 96441016fe1SMaxime Ripard (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 965677e8bbcSDaniele Castagna VOP_WIN_SET(vop, win, x_mir_en, 96641016fe1SMaxime Ripard (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 9671c21aa8fSDaniele Castagna 9681c21aa8fSDaniele Castagna if (is_yuv) { 969f3e9632cSMaxime Ripard int hsub = fb->format->hsub; 970f3e9632cSMaxime Ripard int vsub = fb->format->vsub; 971353c8598SVille Syrjälä int bpp = fb->format->cpp[1]; 97284c7f8caSMark Yao 973957428f9SDaniel Stone uv_obj = fb->obj[1]; 97484c7f8caSMark Yao rk_uv_obj = to_rockchip_obj(uv_obj); 97584c7f8caSMark Yao 97663ebb9faSMark Yao offset = (src->x1 >> 16) * bpp / hsub; 97763ebb9faSMark Yao offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 97884c7f8caSMark Yao 97963ebb9faSMark Yao dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 980da709a7bSMark yao VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 98163ebb9faSMark Yao VOP_WIN_SET(vop, win, uv_mst, dma_addr); 9821c21aa8fSDaniele Castagna 9831c21aa8fSDaniele Castagna for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 9841c21aa8fSDaniele Castagna VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 9851c21aa8fSDaniele Castagna win_yuv2yuv, 9861c21aa8fSDaniele Castagna y2r_coefficients[i], 9871c21aa8fSDaniele Castagna bt601_yuv2rgb[i]); 9881c21aa8fSDaniele Castagna } 98984c7f8caSMark Yao } 9904c156c21SMark Yao 9914c156c21SMark Yao if (win->phy->scl) 9924c156c21SMark Yao scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 99363ebb9faSMark Yao drm_rect_width(dest), drm_rect_height(dest), 99445babef0SMaxime Ripard fb->format); 9954c156c21SMark Yao 99663ebb9faSMark Yao VOP_WIN_SET(vop, win, act_info, act_info); 99763ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_info, dsp_info); 99863ebb9faSMark Yao VOP_WIN_SET(vop, win, dsp_st, dsp_st); 9994c156c21SMark Yao 1000438b74a5SVille Syrjälä rb_swap = has_rb_swapped(fb->format->format); 100185a359f2STomasz Figa VOP_WIN_SET(vop, win, rb_swap, rb_swap); 10022048e328SMark Yao 100358badaa7SKristian H. Kristensen /* 100458badaa7SKristian H. Kristensen * Blending win0 with the background color doesn't seem to work 100558badaa7SKristian H. Kristensen * correctly. We only get the background color, no matter the contents 100658badaa7SKristian H. Kristensen * of the win0 framebuffer. However, blending pre-multiplied color 100758badaa7SKristian H. Kristensen * with the default opaque black default background color is a no-op, 100858badaa7SKristian H. Kristensen * so we can just disable blending to get the correct result. 100958badaa7SKristian H. Kristensen */ 101058badaa7SKristian H. Kristensen if (fb->format->has_alpha && win_index > 0) { 10112048e328SMark Yao VOP_WIN_SET(vop, win, dst_alpha_ctl, 10122048e328SMark Yao DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 10132048e328SMark Yao val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 10142048e328SMark Yao SRC_ALPHA_M0(ALPHA_STRAIGHT) | 10152048e328SMark Yao SRC_BLEND_M0(ALPHA_PER_PIX) | 10162048e328SMark Yao SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 10172048e328SMark Yao SRC_FACTOR_M0(ALPHA_ONE); 10182048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, val); 10192aae8ed1SPaul Kocialkowski 10202aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 10212aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 10222aae8ed1SPaul Kocialkowski VOP_WIN_SET(vop, win, alpha_en, 1); 10232048e328SMark Yao } else { 10242048e328SMark Yao VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1025*046e0db9SAlex Bee VOP_WIN_SET(vop, win, alpha_en, 0); 10262048e328SMark Yao } 10272048e328SMark Yao 10282048e328SMark Yao VOP_WIN_SET(vop, win, enable, 1); 1029bed030a4SSean Paul vop->win_enabled |= BIT(win_index); 10302048e328SMark Yao spin_unlock(&vop->reg_lock); 10312048e328SMark Yao } 10322048e328SMark Yao 103315609559SEnric Balletbo i Serra static int vop_plane_atomic_async_check(struct drm_plane *plane, 10345ddb0bd4SMaxime Ripard struct drm_atomic_state *state) 103515609559SEnric Balletbo i Serra { 10365ddb0bd4SMaxime Ripard struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 10375ddb0bd4SMaxime Ripard plane); 103815609559SEnric Balletbo i Serra struct vop_win *vop_win = to_vop_win(plane); 103915609559SEnric Balletbo i Serra const struct vop_win_data *win = vop_win->data; 104015609559SEnric Balletbo i Serra int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 104115609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 104215609559SEnric Balletbo i Serra int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 104315609559SEnric Balletbo i Serra DRM_PLANE_HELPER_NO_SCALING; 104415609559SEnric Balletbo i Serra struct drm_crtc_state *crtc_state; 104515609559SEnric Balletbo i Serra 10465ddb0bd4SMaxime Ripard if (plane != new_plane_state->crtc->cursor) 104715609559SEnric Balletbo i Serra return -EINVAL; 104815609559SEnric Balletbo i Serra 104915609559SEnric Balletbo i Serra if (!plane->state) 105015609559SEnric Balletbo i Serra return -EINVAL; 105115609559SEnric Balletbo i Serra 105215609559SEnric Balletbo i Serra if (!plane->state->fb) 105315609559SEnric Balletbo i Serra return -EINVAL; 105415609559SEnric Balletbo i Serra 10555ddb0bd4SMaxime Ripard if (state) 10565ddb0bd4SMaxime Ripard crtc_state = drm_atomic_get_existing_crtc_state(state, 10575ddb0bd4SMaxime Ripard new_plane_state->crtc); 105815609559SEnric Balletbo i Serra else /* Special case for asynchronous cursor updates. */ 105915609559SEnric Balletbo i Serra crtc_state = plane->crtc->state; 106015609559SEnric Balletbo i Serra 106115609559SEnric Balletbo i Serra return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 106215609559SEnric Balletbo i Serra min_scale, max_scale, 106315609559SEnric Balletbo i Serra true, true); 106415609559SEnric Balletbo i Serra } 106515609559SEnric Balletbo i Serra 106615609559SEnric Balletbo i Serra static void vop_plane_atomic_async_update(struct drm_plane *plane, 10675ddb0bd4SMaxime Ripard struct drm_atomic_state *state) 106815609559SEnric Balletbo i Serra { 10695ddb0bd4SMaxime Ripard struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 10705ddb0bd4SMaxime Ripard plane); 107115609559SEnric Balletbo i Serra struct vop *vop = to_vop(plane->state->crtc); 1072d985a353SHelen Koike struct drm_framebuffer *old_fb = plane->state->fb; 107315609559SEnric Balletbo i Serra 1074d985a353SHelen Koike plane->state->crtc_x = new_state->crtc_x; 1075d985a353SHelen Koike plane->state->crtc_y = new_state->crtc_y; 1076d985a353SHelen Koike plane->state->crtc_h = new_state->crtc_h; 1077d985a353SHelen Koike plane->state->crtc_w = new_state->crtc_w; 1078d985a353SHelen Koike plane->state->src_x = new_state->src_x; 1079d985a353SHelen Koike plane->state->src_y = new_state->src_y; 1080d985a353SHelen Koike plane->state->src_h = new_state->src_h; 1081d985a353SHelen Koike plane->state->src_w = new_state->src_w; 1082d985a353SHelen Koike swap(plane->state->fb, new_state->fb); 108315609559SEnric Balletbo i Serra 108415609559SEnric Balletbo i Serra if (vop->is_enabled) { 1085977697e2SMaxime Ripard vop_plane_atomic_update(plane, state); 108615609559SEnric Balletbo i Serra spin_lock(&vop->reg_lock); 108715609559SEnric Balletbo i Serra vop_cfg_done(vop); 108815609559SEnric Balletbo i Serra spin_unlock(&vop->reg_lock); 108915609559SEnric Balletbo i Serra 1090d985a353SHelen Koike /* 1091d985a353SHelen Koike * A scanout can still be occurring, so we can't drop the 1092d985a353SHelen Koike * reference to the old framebuffer. To solve this we get a 1093d985a353SHelen Koike * reference to old_fb and set a worker to release it later. 1094d985a353SHelen Koike * FIXME: if we perform 500 async_update calls before the 1095d985a353SHelen Koike * vblank, then we can have 500 different framebuffers waiting 1096d985a353SHelen Koike * to be released. 1097d985a353SHelen Koike */ 1098d985a353SHelen Koike if (old_fb && plane->state->fb != old_fb) { 1099d985a353SHelen Koike drm_framebuffer_get(old_fb); 1100d985a353SHelen Koike WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1101d985a353SHelen Koike drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1102d985a353SHelen Koike set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1103d985a353SHelen Koike } 1104d985a353SHelen Koike } 110515609559SEnric Balletbo i Serra } 110615609559SEnric Balletbo i Serra 110763ebb9faSMark Yao static const struct drm_plane_helper_funcs plane_helper_funcs = { 110863ebb9faSMark Yao .atomic_check = vop_plane_atomic_check, 110963ebb9faSMark Yao .atomic_update = vop_plane_atomic_update, 111063ebb9faSMark Yao .atomic_disable = vop_plane_atomic_disable, 111115609559SEnric Balletbo i Serra .atomic_async_check = vop_plane_atomic_async_check, 111215609559SEnric Balletbo i Serra .atomic_async_update = vop_plane_atomic_async_update, 1113820c1707SThomas Zimmermann .prepare_fb = drm_gem_plane_helper_prepare_fb, 111463ebb9faSMark Yao }; 111563ebb9faSMark Yao 11162048e328SMark Yao static const struct drm_plane_funcs vop_plane_funcs = { 111763ebb9faSMark Yao .update_plane = drm_atomic_helper_update_plane, 111863ebb9faSMark Yao .disable_plane = drm_atomic_helper_disable_plane, 11192048e328SMark Yao .destroy = vop_plane_destroy, 1120d47a7246STomasz Figa .reset = drm_atomic_helper_plane_reset, 1121d47a7246STomasz Figa .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1122d47a7246STomasz Figa .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 11237707f722SAndrzej Pietrasiewicz .format_mod_supported = rockchip_mod_supported, 11242048e328SMark Yao }; 11252048e328SMark Yao 11262048e328SMark Yao static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 11272048e328SMark Yao { 11282048e328SMark Yao struct vop *vop = to_vop(crtc); 11292048e328SMark Yao unsigned long flags; 11302048e328SMark Yao 113163ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 11322048e328SMark Yao return -EPERM; 11332048e328SMark Yao 11342048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 11352048e328SMark Yao 1136fa374107STomasz Figa VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1137dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 11382048e328SMark Yao 11392048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11402048e328SMark Yao 11412048e328SMark Yao return 0; 11422048e328SMark Yao } 11432048e328SMark Yao 11442048e328SMark Yao static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 11452048e328SMark Yao { 11462048e328SMark Yao struct vop *vop = to_vop(crtc); 11472048e328SMark Yao unsigned long flags; 11482048e328SMark Yao 114963ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 11502048e328SMark Yao return; 115131e980c5SMark Yao 11522048e328SMark Yao spin_lock_irqsave(&vop->irq_lock, flags); 1153dbb3d944SMark Yao 1154dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1155dbb3d944SMark Yao 11562048e328SMark Yao spin_unlock_irqrestore(&vop->irq_lock, flags); 11572048e328SMark Yao } 11582048e328SMark Yao 11592048e328SMark Yao static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 11602048e328SMark Yao const struct drm_display_mode *mode, 11612048e328SMark Yao struct drm_display_mode *adjusted_mode) 11622048e328SMark Yao { 1163b59b8de3SChris Zhong struct vop *vop = to_vop(crtc); 1164287422a9SDouglas Anderson unsigned long rate; 1165b59b8de3SChris Zhong 1166287422a9SDouglas Anderson /* 1167287422a9SDouglas Anderson * Clock craziness. 1168287422a9SDouglas Anderson * 1169287422a9SDouglas Anderson * Key points: 1170287422a9SDouglas Anderson * 1171287422a9SDouglas Anderson * - DRM works in in kHz. 1172287422a9SDouglas Anderson * - Clock framework works in Hz. 1173287422a9SDouglas Anderson * - Rockchip's clock driver picks the clock rate that is the 1174287422a9SDouglas Anderson * same _OR LOWER_ than the one requested. 1175287422a9SDouglas Anderson * 1176287422a9SDouglas Anderson * Action plan: 1177287422a9SDouglas Anderson * 1178287422a9SDouglas Anderson * 1. When DRM gives us a mode, we should add 999 Hz to it. That way 1179287422a9SDouglas Anderson * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to 1180287422a9SDouglas Anderson * make 60000 kHz then the clock framework will actually give us 1181287422a9SDouglas Anderson * the right clock. 1182287422a9SDouglas Anderson * 1183287422a9SDouglas Anderson * NOTE: if the PLL (maybe through a divider) could actually make 1184287422a9SDouglas Anderson * a clock rate 999 Hz higher instead of the one we want then this 1185287422a9SDouglas Anderson * could be a problem. Unfortunately there's not much we can do 1186287422a9SDouglas Anderson * since it's baked into DRM to use kHz. It shouldn't matter in 1187287422a9SDouglas Anderson * practice since Rockchip PLLs are controlled by tables and 1188287422a9SDouglas Anderson * even if there is a divider in the middle I wouldn't expect PLL 1189287422a9SDouglas Anderson * rates in the table that are just a few kHz different. 1190287422a9SDouglas Anderson * 1191287422a9SDouglas Anderson * 2. Get the clock framework to round the rate for us to tell us 1192287422a9SDouglas Anderson * what it will actually make. 1193287422a9SDouglas Anderson * 1194287422a9SDouglas Anderson * 3. Store the rounded up rate so that we don't need to worry about 1195287422a9SDouglas Anderson * this in the actual clk_set_rate(). 1196287422a9SDouglas Anderson */ 1197287422a9SDouglas Anderson rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); 1198287422a9SDouglas Anderson adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1199b59b8de3SChris Zhong 12002048e328SMark Yao return true; 12012048e328SMark Yao } 12022048e328SMark Yao 1203b23ab6acSEzequiel Garcia static bool vop_dsp_lut_is_enabled(struct vop *vop) 1204b23ab6acSEzequiel Garcia { 1205b23ab6acSEzequiel Garcia return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1206b23ab6acSEzequiel Garcia } 1207b23ab6acSEzequiel Garcia 1208b23ab6acSEzequiel Garcia static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1209b23ab6acSEzequiel Garcia { 1210b23ab6acSEzequiel Garcia struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1211b23ab6acSEzequiel Garcia unsigned int i; 1212b23ab6acSEzequiel Garcia 1213b23ab6acSEzequiel Garcia for (i = 0; i < crtc->gamma_size; i++) { 1214b23ab6acSEzequiel Garcia u32 word; 1215b23ab6acSEzequiel Garcia 1216b23ab6acSEzequiel Garcia word = (drm_color_lut_extract(lut[i].red, 10) << 20) | 1217b23ab6acSEzequiel Garcia (drm_color_lut_extract(lut[i].green, 10) << 10) | 1218b23ab6acSEzequiel Garcia drm_color_lut_extract(lut[i].blue, 10); 1219b23ab6acSEzequiel Garcia writel(word, vop->lut_regs + i * 4); 1220b23ab6acSEzequiel Garcia } 1221b23ab6acSEzequiel Garcia } 1222b23ab6acSEzequiel Garcia 1223b23ab6acSEzequiel Garcia static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1224b23ab6acSEzequiel Garcia struct drm_crtc_state *old_state) 1225b23ab6acSEzequiel Garcia { 1226b23ab6acSEzequiel Garcia struct drm_crtc_state *state = crtc->state; 1227b23ab6acSEzequiel Garcia unsigned int idle; 1228b23ab6acSEzequiel Garcia int ret; 1229b23ab6acSEzequiel Garcia 1230b23ab6acSEzequiel Garcia if (!vop->lut_regs) 1231b23ab6acSEzequiel Garcia return; 1232b23ab6acSEzequiel Garcia /* 1233b23ab6acSEzequiel Garcia * To disable gamma (gamma_lut is null) or to write 1234b23ab6acSEzequiel Garcia * an update to the LUT, clear dsp_lut_en. 1235b23ab6acSEzequiel Garcia */ 1236b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1237b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 0); 1238b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1239b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1240b23ab6acSEzequiel Garcia 1241b23ab6acSEzequiel Garcia /* 1242b23ab6acSEzequiel Garcia * In order to write the LUT to the internal memory, 1243b23ab6acSEzequiel Garcia * we need to first make sure the dsp_lut_en bit is cleared. 1244b23ab6acSEzequiel Garcia */ 1245b23ab6acSEzequiel Garcia ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1246b23ab6acSEzequiel Garcia idle, !idle, 5, 30 * 1000); 1247b23ab6acSEzequiel Garcia if (ret) { 1248b23ab6acSEzequiel Garcia DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1249b23ab6acSEzequiel Garcia return; 1250b23ab6acSEzequiel Garcia } 1251b23ab6acSEzequiel Garcia 1252b23ab6acSEzequiel Garcia if (!state->gamma_lut) 1253b23ab6acSEzequiel Garcia return; 1254b23ab6acSEzequiel Garcia 1255b23ab6acSEzequiel Garcia spin_lock(&vop->reg_lock); 1256b23ab6acSEzequiel Garcia vop_crtc_write_gamma_lut(vop, crtc); 1257b23ab6acSEzequiel Garcia VOP_REG_SET(vop, common, dsp_lut_en, 1); 1258b23ab6acSEzequiel Garcia vop_cfg_done(vop); 1259b23ab6acSEzequiel Garcia spin_unlock(&vop->reg_lock); 1260b23ab6acSEzequiel Garcia } 1261b23ab6acSEzequiel Garcia 1262b23ab6acSEzequiel Garcia static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1263f6ebe9f9SMaxime Ripard struct drm_atomic_state *state) 1264b23ab6acSEzequiel Garcia { 1265253f28b6SMaxime Ripard struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1266253f28b6SMaxime Ripard crtc); 1267f6ebe9f9SMaxime Ripard struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1268f6ebe9f9SMaxime Ripard crtc); 1269b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 1270b23ab6acSEzequiel Garcia 1271b23ab6acSEzequiel Garcia /* 1272b23ab6acSEzequiel Garcia * Only update GAMMA if the 'active' flag is not changed, 1273b23ab6acSEzequiel Garcia * otherwise it's updated by .atomic_enable. 1274b23ab6acSEzequiel Garcia */ 1275253f28b6SMaxime Ripard if (crtc_state->color_mgmt_changed && 1276253f28b6SMaxime Ripard !crtc_state->active_changed) 1277b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1278b23ab6acSEzequiel Garcia } 1279b23ab6acSEzequiel Garcia 12800b20a0f8SLaurent Pinchart static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1281351f950dSMaxime Ripard struct drm_atomic_state *state) 12822048e328SMark Yao { 1283351f950dSMaxime Ripard struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1284351f950dSMaxime Ripard crtc); 12852048e328SMark Yao struct vop *vop = to_vop(crtc); 1286efd11cc8SMark yao const struct vop_data *vop_data = vop->data; 12874e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 128863ebb9faSMark Yao struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 12892048e328SMark Yao u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 12902048e328SMark Yao u16 hdisplay = adjusted_mode->hdisplay; 12912048e328SMark Yao u16 htotal = adjusted_mode->htotal; 12922048e328SMark Yao u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 12932048e328SMark Yao u16 hact_end = hact_st + hdisplay; 12942048e328SMark Yao u16 vdisplay = adjusted_mode->vdisplay; 12952048e328SMark Yao u16 vtotal = adjusted_mode->vtotal; 12962048e328SMark Yao u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 12972048e328SMark Yao u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 12982048e328SMark Yao u16 vact_end = vact_st + vdisplay; 12990a63bfd0SMark Yao uint32_t pin_pol, val; 1300a5c0fa44SUrja Rannikko int dither_bpc = s->output_bpc ? s->output_bpc : 10; 130139a9ad8fSSean Paul int ret; 13022048e328SMark Yao 1303bed030a4SSean Paul if (old_state && old_state->self_refresh_active) { 1304bed030a4SSean Paul drm_crtc_vblank_on(crtc); 1305bed030a4SSean Paul rockchip_drm_set_win_enabled(crtc, true); 1306bed030a4SSean Paul return; 1307bed030a4SSean Paul } 1308bed030a4SSean Paul 1309b23ab6acSEzequiel Garcia /* 1310b23ab6acSEzequiel Garcia * If we have a GAMMA LUT in the state, then let's make sure 1311b23ab6acSEzequiel Garcia * it's updated. We might be coming out of suspend, 1312b23ab6acSEzequiel Garcia * which means the LUT internal memory needs to be re-written. 1313b23ab6acSEzequiel Garcia */ 1314b23ab6acSEzequiel Garcia if (crtc->state->gamma_lut) 1315b23ab6acSEzequiel Garcia vop_crtc_gamma_set(vop, crtc, old_state); 1316b23ab6acSEzequiel Garcia 1317e334d48bSzain wang mutex_lock(&vop->vop_lock); 1318e334d48bSzain wang 1319893b6cadSDaniel Vetter WARN_ON(vop->event); 1320893b6cadSDaniel Vetter 13216c836d96SSean Paul ret = vop_enable(crtc, old_state); 132239a9ad8fSSean Paul if (ret) { 1323e334d48bSzain wang mutex_unlock(&vop->vop_lock); 132439a9ad8fSSean Paul DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 132539a9ad8fSSean Paul return; 132639a9ad8fSSean Paul } 13271f6c62caSNickey Yang pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1328d790ad03SJohn Keeping BIT(HSYNC_POSITIVE) : 0; 1329d790ad03SJohn Keeping pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1330d790ad03SJohn Keeping BIT(VSYNC_POSITIVE) : 0; 13319a61c54bSMark yao VOP_REG_SET(vop, output, pin_pol, pin_pol); 1332cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 13330a63bfd0SMark Yao 13344e257d9eSMark Yao switch (s->output_type) { 13354e257d9eSMark Yao case DRM_MODE_CONNECTOR_LVDS: 13361f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 13379a61c54bSMark yao VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 13381f6c62caSNickey Yang VOP_REG_SET(vop, output, rgb_en, 1); 13394e257d9eSMark Yao break; 13404e257d9eSMark Yao case DRM_MODE_CONNECTOR_eDP: 13411f6c62caSNickey Yang VOP_REG_SET(vop, output, edp_dclk_pol, 1); 13429a61c54bSMark yao VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 13439a61c54bSMark yao VOP_REG_SET(vop, output, edp_en, 1); 13444e257d9eSMark Yao break; 13454e257d9eSMark Yao case DRM_MODE_CONNECTOR_HDMIA: 13461f6c62caSNickey Yang VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 13479a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 13489a61c54bSMark yao VOP_REG_SET(vop, output, hdmi_en, 1); 13494e257d9eSMark Yao break; 13504e257d9eSMark Yao case DRM_MODE_CONNECTOR_DSI: 13511f6c62caSNickey Yang VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 13529a61c54bSMark yao VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 13539a61c54bSMark yao VOP_REG_SET(vop, output, mipi_en, 1); 1354cf6d100dSHeiko Stuebner VOP_REG_SET(vop, output, mipi_dual_channel_en, 1355cf6d100dSHeiko Stuebner !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 13564e257d9eSMark Yao break; 13571a0f7ed3SChris Zhong case DRM_MODE_CONNECTOR_DisplayPort: 13581f6c62caSNickey Yang VOP_REG_SET(vop, output, dp_dclk_pol, 0); 13599a61c54bSMark yao VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 13609a61c54bSMark yao VOP_REG_SET(vop, output, dp_en, 1); 13611a0f7ed3SChris Zhong break; 13624e257d9eSMark Yao default: 1363ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1364ee4d7899SSean Paul s->output_type); 13654e257d9eSMark Yao } 1366efd11cc8SMark yao 1367efd11cc8SMark yao /* 1368efd11cc8SMark yao * if vop is not support RGB10 output, need force RGB10 to RGB888. 1369efd11cc8SMark yao */ 1370efd11cc8SMark yao if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1371efd11cc8SMark yao !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1372efd11cc8SMark yao s->output_mode = ROCKCHIP_OUT_MODE_P888; 13736bda8112SMark Yao 1374a5c0fa44SUrja Rannikko if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 13756bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 1); 13766bda8112SMark Yao else 13776bda8112SMark Yao VOP_REG_SET(vop, common, pre_dither_down, 0); 13786bda8112SMark Yao 1379a5c0fa44SUrja Rannikko if (dither_bpc == 6) { 1380a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1381a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1382a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 1); 1383a5c0fa44SUrja Rannikko } else { 1384a5c0fa44SUrja Rannikko VOP_REG_SET(vop, common, dither_down_en, 0); 1385a5c0fa44SUrja Rannikko } 1386a5c0fa44SUrja Rannikko 13879a61c54bSMark yao VOP_REG_SET(vop, common, out_mode, s->output_mode); 13882048e328SMark Yao 13899a61c54bSMark yao VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 13902048e328SMark Yao val = hact_st << 16; 13912048e328SMark Yao val |= hact_end; 13929a61c54bSMark yao VOP_REG_SET(vop, modeset, hact_st_end, val); 13939a61c54bSMark yao VOP_REG_SET(vop, modeset, hpost_st_end, val); 13942048e328SMark Yao 13959a61c54bSMark yao VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 13962048e328SMark Yao val = vact_st << 16; 13972048e328SMark Yao val |= vact_end; 13989a61c54bSMark yao VOP_REG_SET(vop, modeset, vact_st_end, val); 13999a61c54bSMark yao VOP_REG_SET(vop, modeset, vpost_st_end, val); 14002048e328SMark Yao 14019a61c54bSMark yao VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1402459b086dSJeffy Chen 14032048e328SMark Yao clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1404ce3887edSMark Yao 14059a61c54bSMark yao VOP_REG_SET(vop, common, standby, 0); 1406e334d48bSzain wang mutex_unlock(&vop->vop_lock); 14072048e328SMark Yao } 14082048e328SMark Yao 14097caecdbeSTomasz Figa static bool vop_fs_irq_is_pending(struct vop *vop) 14107caecdbeSTomasz Figa { 14117caecdbeSTomasz Figa return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 14127caecdbeSTomasz Figa } 14137caecdbeSTomasz Figa 14147caecdbeSTomasz Figa static void vop_wait_for_irq_handler(struct vop *vop) 14157caecdbeSTomasz Figa { 14167caecdbeSTomasz Figa bool pending; 14177caecdbeSTomasz Figa int ret; 14187caecdbeSTomasz Figa 14197caecdbeSTomasz Figa /* 14207caecdbeSTomasz Figa * Spin until frame start interrupt status bit goes low, which means 14217caecdbeSTomasz Figa * that interrupt handler was invoked and cleared it. The timeout of 14227caecdbeSTomasz Figa * 10 msecs is really too long, but it is just a safety measure if 14237caecdbeSTomasz Figa * something goes really wrong. The wait will only happen in the very 14247caecdbeSTomasz Figa * unlikely case of a vblank happening exactly at the same time and 14257caecdbeSTomasz Figa * shouldn't exceed microseconds range. 14267caecdbeSTomasz Figa */ 14277caecdbeSTomasz Figa ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 14287caecdbeSTomasz Figa !pending, 0, 10 * 1000); 14297caecdbeSTomasz Figa if (ret) 14307caecdbeSTomasz Figa DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 14317caecdbeSTomasz Figa 14327caecdbeSTomasz Figa synchronize_irq(vop->irq); 14337caecdbeSTomasz Figa } 14347caecdbeSTomasz Figa 1435b23ab6acSEzequiel Garcia static int vop_crtc_atomic_check(struct drm_crtc *crtc, 143629b77ad7SMaxime Ripard struct drm_atomic_state *state) 1437b23ab6acSEzequiel Garcia { 143829b77ad7SMaxime Ripard struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 143929b77ad7SMaxime Ripard crtc); 1440b23ab6acSEzequiel Garcia struct vop *vop = to_vop(crtc); 14417707f722SAndrzej Pietrasiewicz struct drm_plane *plane; 14427707f722SAndrzej Pietrasiewicz struct drm_plane_state *plane_state; 14437707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 14447707f722SAndrzej Pietrasiewicz int afbc_planes = 0; 1445b23ab6acSEzequiel Garcia 1446b23ab6acSEzequiel Garcia if (vop->lut_regs && crtc_state->color_mgmt_changed && 1447b23ab6acSEzequiel Garcia crtc_state->gamma_lut) { 1448b23ab6acSEzequiel Garcia unsigned int len; 1449b23ab6acSEzequiel Garcia 1450b23ab6acSEzequiel Garcia len = drm_color_lut_size(crtc_state->gamma_lut); 1451b23ab6acSEzequiel Garcia if (len != crtc->gamma_size) { 1452b23ab6acSEzequiel Garcia DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1453b23ab6acSEzequiel Garcia len, crtc->gamma_size); 1454b23ab6acSEzequiel Garcia return -EINVAL; 1455b23ab6acSEzequiel Garcia } 1456b23ab6acSEzequiel Garcia } 1457b23ab6acSEzequiel Garcia 14587707f722SAndrzej Pietrasiewicz drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 14597707f722SAndrzej Pietrasiewicz plane_state = 14607707f722SAndrzej Pietrasiewicz drm_atomic_get_plane_state(crtc_state->state, plane); 14617707f722SAndrzej Pietrasiewicz if (IS_ERR(plane_state)) { 14627707f722SAndrzej Pietrasiewicz DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 14637707f722SAndrzej Pietrasiewicz plane->name); 14647707f722SAndrzej Pietrasiewicz return PTR_ERR(plane_state); 14657707f722SAndrzej Pietrasiewicz } 14667707f722SAndrzej Pietrasiewicz 14677707f722SAndrzej Pietrasiewicz if (drm_is_afbc(plane_state->fb->modifier)) 14687707f722SAndrzej Pietrasiewicz ++afbc_planes; 14697707f722SAndrzej Pietrasiewicz } 14707707f722SAndrzej Pietrasiewicz 14717707f722SAndrzej Pietrasiewicz if (afbc_planes > 1) { 14727707f722SAndrzej Pietrasiewicz DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 14737707f722SAndrzej Pietrasiewicz return -EINVAL; 14747707f722SAndrzej Pietrasiewicz } 14757707f722SAndrzej Pietrasiewicz 14767707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc_state); 14777707f722SAndrzej Pietrasiewicz s->enable_afbc = afbc_planes > 0; 14787707f722SAndrzej Pietrasiewicz 1479b23ab6acSEzequiel Garcia return 0; 1480b23ab6acSEzequiel Garcia } 1481b23ab6acSEzequiel Garcia 148263ebb9faSMark Yao static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1483f6ebe9f9SMaxime Ripard struct drm_atomic_state *state) 148463ebb9faSMark Yao { 1485f6ebe9f9SMaxime Ripard struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1486f6ebe9f9SMaxime Ripard crtc); 148747a7eb45STomasz Figa struct drm_atomic_state *old_state = old_crtc_state->state; 1488e741f2b1SMaarten Lankhorst struct drm_plane_state *old_plane_state, *new_plane_state; 148963ebb9faSMark Yao struct vop *vop = to_vop(crtc); 149047a7eb45STomasz Figa struct drm_plane *plane; 14917707f722SAndrzej Pietrasiewicz struct rockchip_crtc_state *s; 149247a7eb45STomasz Figa int i; 149363ebb9faSMark Yao 149463ebb9faSMark Yao if (WARN_ON(!vop->is_enabled)) 149563ebb9faSMark Yao return; 149663ebb9faSMark Yao 149763ebb9faSMark Yao spin_lock(&vop->reg_lock); 149863ebb9faSMark Yao 14997707f722SAndrzej Pietrasiewicz /* Enable AFBC if there is some AFBC window, disable otherwise. */ 15007707f722SAndrzej Pietrasiewicz s = to_rockchip_crtc_state(crtc->state); 15017707f722SAndrzej Pietrasiewicz VOP_AFBC_SET(vop, enable, s->enable_afbc); 150263ebb9faSMark Yao vop_cfg_done(vop); 150363ebb9faSMark Yao 150463ebb9faSMark Yao spin_unlock(&vop->reg_lock); 15057caecdbeSTomasz Figa 15067caecdbeSTomasz Figa /* 15077caecdbeSTomasz Figa * There is a (rather unlikely) possiblity that a vblank interrupt 15087caecdbeSTomasz Figa * fired before we set the cfg_done bit. To avoid spuriously 15097caecdbeSTomasz Figa * signalling flip completion we need to wait for it to finish. 15107caecdbeSTomasz Figa */ 15117caecdbeSTomasz Figa vop_wait_for_irq_handler(vop); 151247a7eb45STomasz Figa 151341ee4367STomasz Figa spin_lock_irq(&crtc->dev->event_lock); 151441ee4367STomasz Figa if (crtc->state->event) { 151541ee4367STomasz Figa WARN_ON(drm_crtc_vblank_get(crtc) != 0); 151641ee4367STomasz Figa WARN_ON(vop->event); 151741ee4367STomasz Figa 151841ee4367STomasz Figa vop->event = crtc->state->event; 151941ee4367STomasz Figa crtc->state->event = NULL; 152041ee4367STomasz Figa } 152141ee4367STomasz Figa spin_unlock_irq(&crtc->dev->event_lock); 152241ee4367STomasz Figa 1523e741f2b1SMaarten Lankhorst for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1524e741f2b1SMaarten Lankhorst new_plane_state, i) { 152547a7eb45STomasz Figa if (!old_plane_state->fb) 152647a7eb45STomasz Figa continue; 152747a7eb45STomasz Figa 1528e741f2b1SMaarten Lankhorst if (old_plane_state->fb == new_plane_state->fb) 152947a7eb45STomasz Figa continue; 153047a7eb45STomasz Figa 1531adedbf03SCihangir Akturk drm_framebuffer_get(old_plane_state->fb); 15322d078c2dSJohn Keeping WARN_ON(drm_crtc_vblank_get(crtc) != 0); 153347a7eb45STomasz Figa drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 153447a7eb45STomasz Figa set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 153547a7eb45STomasz Figa } 153663ebb9faSMark Yao } 153763ebb9faSMark Yao 15382048e328SMark Yao static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 15392048e328SMark Yao .mode_fixup = vop_crtc_mode_fixup, 1540b23ab6acSEzequiel Garcia .atomic_check = vop_crtc_atomic_check, 1541b23ab6acSEzequiel Garcia .atomic_begin = vop_crtc_atomic_begin, 154263ebb9faSMark Yao .atomic_flush = vop_crtc_atomic_flush, 15430b20a0f8SLaurent Pinchart .atomic_enable = vop_crtc_atomic_enable, 154464581714SLaurent Pinchart .atomic_disable = vop_crtc_atomic_disable, 15452048e328SMark Yao }; 15462048e328SMark Yao 15472048e328SMark Yao static void vop_crtc_destroy(struct drm_crtc *crtc) 15482048e328SMark Yao { 15492048e328SMark Yao drm_crtc_cleanup(crtc); 15502048e328SMark Yao } 15512048e328SMark Yao 15524e257d9eSMark Yao static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 15534e257d9eSMark Yao { 15544e257d9eSMark Yao struct rockchip_crtc_state *rockchip_state; 15554e257d9eSMark Yao 15564e257d9eSMark Yao rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 15574e257d9eSMark Yao if (!rockchip_state) 15584e257d9eSMark Yao return NULL; 15594e257d9eSMark Yao 15604e257d9eSMark Yao __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 15614e257d9eSMark Yao return &rockchip_state->base; 15624e257d9eSMark Yao } 15634e257d9eSMark Yao 15644e257d9eSMark Yao static void vop_crtc_destroy_state(struct drm_crtc *crtc, 15654e257d9eSMark Yao struct drm_crtc_state *state) 15664e257d9eSMark Yao { 15674e257d9eSMark Yao struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 15684e257d9eSMark Yao 1569ec2dc6a0SDaniel Vetter __drm_atomic_helper_crtc_destroy_state(&s->base); 15704e257d9eSMark Yao kfree(s); 15714e257d9eSMark Yao } 15724e257d9eSMark Yao 157301e2eaf4SMaarten Lankhorst static void vop_crtc_reset(struct drm_crtc *crtc) 157401e2eaf4SMaarten Lankhorst { 157501e2eaf4SMaarten Lankhorst struct rockchip_crtc_state *crtc_state = 157601e2eaf4SMaarten Lankhorst kzalloc(sizeof(*crtc_state), GFP_KERNEL); 157701e2eaf4SMaarten Lankhorst 157801e2eaf4SMaarten Lankhorst if (crtc->state) 157901e2eaf4SMaarten Lankhorst vop_crtc_destroy_state(crtc, crtc->state); 158001e2eaf4SMaarten Lankhorst 158101e2eaf4SMaarten Lankhorst __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 158201e2eaf4SMaarten Lankhorst } 158301e2eaf4SMaarten Lankhorst 15846cca3869SSean Paul #ifdef CONFIG_DRM_ANALOGIX_DP 15853190e58dSTomeu Vizoso static struct drm_connector *vop_get_edp_connector(struct vop *vop) 15863190e58dSTomeu Vizoso { 15873190e58dSTomeu Vizoso struct drm_connector *connector; 15882cbeb64fSGustavo Padovan struct drm_connector_list_iter conn_iter; 15893190e58dSTomeu Vizoso 15902cbeb64fSGustavo Padovan drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 15912cbeb64fSGustavo Padovan drm_for_each_connector_iter(connector, &conn_iter) { 15923190e58dSTomeu Vizoso if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 15932cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 15943190e58dSTomeu Vizoso return connector; 15953190e58dSTomeu Vizoso } 15962cbeb64fSGustavo Padovan } 15972cbeb64fSGustavo Padovan drm_connector_list_iter_end(&conn_iter); 15983190e58dSTomeu Vizoso 15993190e58dSTomeu Vizoso return NULL; 16003190e58dSTomeu Vizoso } 16013190e58dSTomeu Vizoso 16023190e58dSTomeu Vizoso static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1603c0811a7dSMahesh Kumar const char *source_name) 16043190e58dSTomeu Vizoso { 16053190e58dSTomeu Vizoso struct vop *vop = to_vop(crtc); 16063190e58dSTomeu Vizoso struct drm_connector *connector; 16073190e58dSTomeu Vizoso int ret; 16083190e58dSTomeu Vizoso 16093190e58dSTomeu Vizoso connector = vop_get_edp_connector(vop); 16103190e58dSTomeu Vizoso if (!connector) 16113190e58dSTomeu Vizoso return -EINVAL; 16123190e58dSTomeu Vizoso 16133190e58dSTomeu Vizoso if (source_name && strcmp(source_name, "auto") == 0) 16143190e58dSTomeu Vizoso ret = analogix_dp_start_crc(connector); 16153190e58dSTomeu Vizoso else if (!source_name) 16163190e58dSTomeu Vizoso ret = analogix_dp_stop_crc(connector); 16173190e58dSTomeu Vizoso else 16183190e58dSTomeu Vizoso ret = -EINVAL; 16193190e58dSTomeu Vizoso 16203190e58dSTomeu Vizoso return ret; 16213190e58dSTomeu Vizoso } 1622b8d913c0SMahesh Kumar 1623b8d913c0SMahesh Kumar static int 1624b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1625b8d913c0SMahesh Kumar size_t *values_cnt) 1626b8d913c0SMahesh Kumar { 1627b8d913c0SMahesh Kumar if (source_name && strcmp(source_name, "auto") != 0) 1628b8d913c0SMahesh Kumar return -EINVAL; 1629b8d913c0SMahesh Kumar 1630b8d913c0SMahesh Kumar *values_cnt = 3; 1631b8d913c0SMahesh Kumar return 0; 1632b8d913c0SMahesh Kumar } 1633b8d913c0SMahesh Kumar 16346cca3869SSean Paul #else 16356cca3869SSean Paul static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1636c0811a7dSMahesh Kumar const char *source_name) 16376cca3869SSean Paul { 16386cca3869SSean Paul return -ENODEV; 16396cca3869SSean Paul } 1640b8d913c0SMahesh Kumar 1641b8d913c0SMahesh Kumar static int 1642b8d913c0SMahesh Kumar vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1643b8d913c0SMahesh Kumar size_t *values_cnt) 1644b8d913c0SMahesh Kumar { 1645b8d913c0SMahesh Kumar return -ENODEV; 1646b8d913c0SMahesh Kumar } 16476cca3869SSean Paul #endif 16483190e58dSTomeu Vizoso 16492048e328SMark Yao static const struct drm_crtc_funcs vop_crtc_funcs = { 165063ebb9faSMark Yao .set_config = drm_atomic_helper_set_config, 165163ebb9faSMark Yao .page_flip = drm_atomic_helper_page_flip, 16522048e328SMark Yao .destroy = vop_crtc_destroy, 1653dc0b408fSJohn Keeping .reset = vop_crtc_reset, 16544e257d9eSMark Yao .atomic_duplicate_state = vop_crtc_duplicate_state, 16554e257d9eSMark Yao .atomic_destroy_state = vop_crtc_destroy_state, 1656c3605dfcSShawn Guo .enable_vblank = vop_crtc_enable_vblank, 1657c3605dfcSShawn Guo .disable_vblank = vop_crtc_disable_vblank, 16583190e58dSTomeu Vizoso .set_crc_source = vop_crtc_set_crc_source, 1659b8d913c0SMahesh Kumar .verify_crc_source = vop_crtc_verify_crc_source, 16602048e328SMark Yao }; 16612048e328SMark Yao 166247a7eb45STomasz Figa static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 166347a7eb45STomasz Figa { 166447a7eb45STomasz Figa struct vop *vop = container_of(work, struct vop, fb_unref_work); 166547a7eb45STomasz Figa struct drm_framebuffer *fb = val; 166647a7eb45STomasz Figa 166747a7eb45STomasz Figa drm_crtc_vblank_put(&vop->crtc); 1668adedbf03SCihangir Akturk drm_framebuffer_put(fb); 166947a7eb45STomasz Figa } 167047a7eb45STomasz Figa 167163ebb9faSMark Yao static void vop_handle_vblank(struct vop *vop) 16722048e328SMark Yao { 167363ebb9faSMark Yao struct drm_device *drm = vop->drm_dev; 167463ebb9faSMark Yao struct drm_crtc *crtc = &vop->crtc; 16752048e328SMark Yao 16761c85f2faSMarc Zyngier spin_lock(&drm->event_lock); 1677893b6cadSDaniel Vetter if (vop->event) { 167863ebb9faSMark Yao drm_crtc_send_vblank_event(crtc, vop->event); 16795b680403SSean Paul drm_crtc_vblank_put(crtc); 1680646ec687STomasz Figa vop->event = NULL; 16815b680403SSean Paul } 16821c85f2faSMarc Zyngier spin_unlock(&drm->event_lock); 1683893b6cadSDaniel Vetter 168447a7eb45STomasz Figa if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 168547a7eb45STomasz Figa drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 16862048e328SMark Yao } 16872048e328SMark Yao 16882048e328SMark Yao static irqreturn_t vop_isr(int irq, void *data) 16892048e328SMark Yao { 16902048e328SMark Yao struct vop *vop = data; 1691b5f7b755SMark Yao struct drm_crtc *crtc = &vop->crtc; 1692dbb3d944SMark Yao uint32_t active_irqs; 16931067219bSMark Yao int ret = IRQ_NONE; 16942048e328SMark Yao 16952048e328SMark Yao /* 16966456314fSSandy Huang * The irq is shared with the iommu. If the runtime-pm state of the 16976456314fSSandy Huang * vop-device is disabled the irq has to be targeted at the iommu. 16986456314fSSandy Huang */ 16996456314fSSandy Huang if (!pm_runtime_get_if_in_use(vop->dev)) 17006456314fSSandy Huang return IRQ_NONE; 17016456314fSSandy Huang 17026456314fSSandy Huang if (vop_core_clks_enable(vop)) { 17036456314fSSandy Huang DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 17046456314fSSandy Huang goto out; 17056456314fSSandy Huang } 17066456314fSSandy Huang 17076456314fSSandy Huang /* 1708dbb3d944SMark Yao * interrupt register has interrupt status, enable and clear bits, we 17092048e328SMark Yao * must hold irq_lock to avoid a race with enable/disable_vblank(). 17102048e328SMark Yao */ 17111c85f2faSMarc Zyngier spin_lock(&vop->irq_lock); 1712dbb3d944SMark Yao 1713dbb3d944SMark Yao active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 17142048e328SMark Yao /* Clear all active interrupt sources */ 17152048e328SMark Yao if (active_irqs) 1716dbb3d944SMark Yao VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1717dbb3d944SMark Yao 17181c85f2faSMarc Zyngier spin_unlock(&vop->irq_lock); 17192048e328SMark Yao 17202048e328SMark Yao /* This is expected for vop iommu irqs, since the irq is shared */ 17212048e328SMark Yao if (!active_irqs) 17226456314fSSandy Huang goto out_disable; 17232048e328SMark Yao 17241067219bSMark Yao if (active_irqs & DSP_HOLD_VALID_INTR) { 17251067219bSMark Yao complete(&vop->dsp_hold_completion); 17261067219bSMark Yao active_irqs &= ~DSP_HOLD_VALID_INTR; 17271067219bSMark Yao ret = IRQ_HANDLED; 17282048e328SMark Yao } 17292048e328SMark Yao 173069c34e41SYakir Yang if (active_irqs & LINE_FLAG_INTR) { 173169c34e41SYakir Yang complete(&vop->line_flag_completion); 173269c34e41SYakir Yang active_irqs &= ~LINE_FLAG_INTR; 173369c34e41SYakir Yang ret = IRQ_HANDLED; 173469c34e41SYakir Yang } 173569c34e41SYakir Yang 17361067219bSMark Yao if (active_irqs & FS_INTR) { 1737b5f7b755SMark Yao drm_crtc_handle_vblank(crtc); 173863ebb9faSMark Yao vop_handle_vblank(vop); 17391067219bSMark Yao active_irqs &= ~FS_INTR; 174063ebb9faSMark Yao ret = IRQ_HANDLED; 17411067219bSMark Yao } 17422048e328SMark Yao 17431067219bSMark Yao /* Unhandled irqs are spurious. */ 17441067219bSMark Yao if (active_irqs) 1745ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1746ee4d7899SSean Paul active_irqs); 17471067219bSMark Yao 17486456314fSSandy Huang out_disable: 17496456314fSSandy Huang vop_core_clks_disable(vop); 17506456314fSSandy Huang out: 17516456314fSSandy Huang pm_runtime_put(vop->dev); 17521067219bSMark Yao return ret; 17532048e328SMark Yao } 17542048e328SMark Yao 1755677e8bbcSDaniele Castagna static void vop_plane_add_properties(struct drm_plane *plane, 1756677e8bbcSDaniele Castagna const struct vop_win_data *win_data) 1757677e8bbcSDaniele Castagna { 1758677e8bbcSDaniele Castagna unsigned int flags = 0; 1759677e8bbcSDaniele Castagna 1760677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1761677e8bbcSDaniele Castagna flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1762677e8bbcSDaniele Castagna if (flags) 1763677e8bbcSDaniele Castagna drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1764677e8bbcSDaniele Castagna DRM_MODE_ROTATE_0 | flags); 1765677e8bbcSDaniele Castagna } 1766677e8bbcSDaniele Castagna 17672048e328SMark Yao static int vop_create_crtc(struct vop *vop) 17682048e328SMark Yao { 17692048e328SMark Yao const struct vop_data *vop_data = vop->data; 17702048e328SMark Yao struct device *dev = vop->dev; 17712048e328SMark Yao struct drm_device *drm_dev = vop->drm_dev; 1772328b51c0SDouglas Anderson struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 17732048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 17742048e328SMark Yao struct device_node *port; 17752048e328SMark Yao int ret; 17762048e328SMark Yao int i; 17772048e328SMark Yao 17782048e328SMark Yao /* 17792048e328SMark Yao * Create drm_plane for primary and cursor planes first, since we need 17802048e328SMark Yao * to pass them to drm_crtc_init_with_planes, which sets the 17812048e328SMark Yao * "possible_crtcs" to the newly initialized crtc. 17822048e328SMark Yao */ 17832048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 17842048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 17852048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 17862048e328SMark Yao 17872048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 17882048e328SMark Yao win_data->type != DRM_PLANE_TYPE_CURSOR) 17892048e328SMark Yao continue; 17902048e328SMark Yao 17912048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 17922048e328SMark Yao 0, &vop_plane_funcs, 17932048e328SMark Yao win_data->phy->data_formats, 17942048e328SMark Yao win_data->phy->nformats, 17957707f722SAndrzej Pietrasiewicz win_data->phy->format_modifiers, 17967707f722SAndrzej Pietrasiewicz win_data->type, NULL); 17972048e328SMark Yao if (ret) { 1798ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1799ee4d7899SSean Paul ret); 18002048e328SMark Yao goto err_cleanup_planes; 18012048e328SMark Yao } 18022048e328SMark Yao 18032048e328SMark Yao plane = &vop_win->base; 180463ebb9faSMark Yao drm_plane_helper_add(plane, &plane_helper_funcs); 1805677e8bbcSDaniele Castagna vop_plane_add_properties(plane, win_data); 18062048e328SMark Yao if (plane->type == DRM_PLANE_TYPE_PRIMARY) 18072048e328SMark Yao primary = plane; 18082048e328SMark Yao else if (plane->type == DRM_PLANE_TYPE_CURSOR) 18092048e328SMark Yao cursor = plane; 18102048e328SMark Yao } 18112048e328SMark Yao 18122048e328SMark Yao ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1813f9882876SVille Syrjälä &vop_crtc_funcs, NULL); 18142048e328SMark Yao if (ret) 1815328b51c0SDouglas Anderson goto err_cleanup_planes; 18162048e328SMark Yao 18172048e328SMark Yao drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1818b23ab6acSEzequiel Garcia if (vop->lut_regs) { 1819b23ab6acSEzequiel Garcia drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1820b23ab6acSEzequiel Garcia drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1821b23ab6acSEzequiel Garcia } 18222048e328SMark Yao 18232048e328SMark Yao /* 18242048e328SMark Yao * Create drm_planes for overlay windows with possible_crtcs restricted 18252048e328SMark Yao * to the newly created crtc. 18262048e328SMark Yao */ 18272048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 18282048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 18292048e328SMark Yao const struct vop_win_data *win_data = vop_win->data; 1830a3e77e16SVille Syrjälä unsigned long possible_crtcs = drm_crtc_mask(crtc); 18312048e328SMark Yao 18322048e328SMark Yao if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 18332048e328SMark Yao continue; 18342048e328SMark Yao 18352048e328SMark Yao ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 18362048e328SMark Yao possible_crtcs, 18372048e328SMark Yao &vop_plane_funcs, 18382048e328SMark Yao win_data->phy->data_formats, 18392048e328SMark Yao win_data->phy->nformats, 18407707f722SAndrzej Pietrasiewicz win_data->phy->format_modifiers, 18417707f722SAndrzej Pietrasiewicz win_data->type, NULL); 18422048e328SMark Yao if (ret) { 1843ee4d7899SSean Paul DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1844ee4d7899SSean Paul ret); 18452048e328SMark Yao goto err_cleanup_crtc; 18462048e328SMark Yao } 184763ebb9faSMark Yao drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1848677e8bbcSDaniele Castagna vop_plane_add_properties(&vop_win->base, win_data); 18492048e328SMark Yao } 18502048e328SMark Yao 18512048e328SMark Yao port = of_get_child_by_name(dev->of_node, "port"); 18522048e328SMark Yao if (!port) { 18534bf99144SRob Herring DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 18544bf99144SRob Herring dev->of_node); 1855328b51c0SDouglas Anderson ret = -ENOENT; 18562048e328SMark Yao goto err_cleanup_crtc; 18572048e328SMark Yao } 18582048e328SMark Yao 185947a7eb45STomasz Figa drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 186047a7eb45STomasz Figa vop_fb_unref_worker); 186147a7eb45STomasz Figa 18621067219bSMark Yao init_completion(&vop->dsp_hold_completion); 186369c34e41SYakir Yang init_completion(&vop->line_flag_completion); 18642048e328SMark Yao crtc->port = port; 18652048e328SMark Yao 1866d4da4e33SSean Paul ret = drm_self_refresh_helper_init(crtc); 18676c836d96SSean Paul if (ret) 18686c836d96SSean Paul DRM_DEV_DEBUG_KMS(vop->dev, 18696c836d96SSean Paul "Failed to init %s with SR helpers %d, ignoring\n", 18706c836d96SSean Paul crtc->name, ret); 18716c836d96SSean Paul 18722048e328SMark Yao return 0; 18732048e328SMark Yao 18742048e328SMark Yao err_cleanup_crtc: 18752048e328SMark Yao drm_crtc_cleanup(crtc); 18762048e328SMark Yao err_cleanup_planes: 1877328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1878328b51c0SDouglas Anderson head) 18792048e328SMark Yao drm_plane_cleanup(plane); 18802048e328SMark Yao return ret; 18812048e328SMark Yao } 18822048e328SMark Yao 18832048e328SMark Yao static void vop_destroy_crtc(struct vop *vop) 18842048e328SMark Yao { 18852048e328SMark Yao struct drm_crtc *crtc = &vop->crtc; 1886328b51c0SDouglas Anderson struct drm_device *drm_dev = vop->drm_dev; 1887328b51c0SDouglas Anderson struct drm_plane *plane, *tmp; 18882048e328SMark Yao 18896c836d96SSean Paul drm_self_refresh_helper_cleanup(crtc); 18906c836d96SSean Paul 18912048e328SMark Yao of_node_put(crtc->port); 1892328b51c0SDouglas Anderson 1893328b51c0SDouglas Anderson /* 1894328b51c0SDouglas Anderson * We need to cleanup the planes now. Why? 1895328b51c0SDouglas Anderson * 1896328b51c0SDouglas Anderson * The planes are "&vop->win[i].base". That means the memory is 1897328b51c0SDouglas Anderson * all part of the big "struct vop" chunk of memory. That memory 1898328b51c0SDouglas Anderson * was devm allocated and associated with this component. We need to 1899328b51c0SDouglas Anderson * free it ourselves before vop_unbind() finishes. 1900328b51c0SDouglas Anderson */ 1901328b51c0SDouglas Anderson list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1902328b51c0SDouglas Anderson head) 1903328b51c0SDouglas Anderson vop_plane_destroy(plane); 1904328b51c0SDouglas Anderson 1905328b51c0SDouglas Anderson /* 1906328b51c0SDouglas Anderson * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1907328b51c0SDouglas Anderson * references the CRTC. 1908328b51c0SDouglas Anderson */ 19092048e328SMark Yao drm_crtc_cleanup(crtc); 191047a7eb45STomasz Figa drm_flip_work_cleanup(&vop->fb_unref_work); 19112048e328SMark Yao } 19122048e328SMark Yao 19132048e328SMark Yao static int vop_initial(struct vop *vop) 19142048e328SMark Yao { 19152048e328SMark Yao struct reset_control *ahb_rst; 19162048e328SMark Yao int i, ret; 19172048e328SMark Yao 19182048e328SMark Yao vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 19192048e328SMark Yao if (IS_ERR(vop->hclk)) { 1920d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 19212048e328SMark Yao return PTR_ERR(vop->hclk); 19222048e328SMark Yao } 19232048e328SMark Yao vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 19242048e328SMark Yao if (IS_ERR(vop->aclk)) { 1925d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 19262048e328SMark Yao return PTR_ERR(vop->aclk); 19272048e328SMark Yao } 19282048e328SMark Yao vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 19292048e328SMark Yao if (IS_ERR(vop->dclk)) { 1930d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 19312048e328SMark Yao return PTR_ERR(vop->dclk); 19322048e328SMark Yao } 19332048e328SMark Yao 19345e570373SJeffy Chen ret = pm_runtime_get_sync(vop->dev); 19355e570373SJeffy Chen if (ret < 0) { 1936d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 19375e570373SJeffy Chen return ret; 19385e570373SJeffy Chen } 19395e570373SJeffy Chen 19402048e328SMark Yao ret = clk_prepare(vop->dclk); 19412048e328SMark Yao if (ret < 0) { 1942d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 19435e570373SJeffy Chen goto err_put_pm_runtime; 19442048e328SMark Yao } 19452048e328SMark Yao 1946d7b53fd9SSjoerd Simons /* Enable both the hclk and aclk to setup the vop */ 1947d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->hclk); 19482048e328SMark Yao if (ret < 0) { 1949d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 19502048e328SMark Yao goto err_unprepare_dclk; 19512048e328SMark Yao } 19522048e328SMark Yao 1953d7b53fd9SSjoerd Simons ret = clk_prepare_enable(vop->aclk); 19542048e328SMark Yao if (ret < 0) { 1955d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1956d7b53fd9SSjoerd Simons goto err_disable_hclk; 19572048e328SMark Yao } 1958d7b53fd9SSjoerd Simons 19592048e328SMark Yao /* 19602048e328SMark Yao * do hclk_reset, reset all vop registers. 19612048e328SMark Yao */ 19622048e328SMark Yao ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 19632048e328SMark Yao if (IS_ERR(ahb_rst)) { 1964d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 19652048e328SMark Yao ret = PTR_ERR(ahb_rst); 1966d7b53fd9SSjoerd Simons goto err_disable_aclk; 19672048e328SMark Yao } 19682048e328SMark Yao reset_control_assert(ahb_rst); 19692048e328SMark Yao usleep_range(10, 20); 19702048e328SMark Yao reset_control_deassert(ahb_rst); 19712048e328SMark Yao 19725f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 19735f9e93feSMarc Zyngier VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 19745f9e93feSMarc Zyngier 197576f1416eSMarc Zyngier for (i = 0; i < vop->len; i += sizeof(u32)) 197676f1416eSMarc Zyngier vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 19772048e328SMark Yao 19789a61c54bSMark yao VOP_REG_SET(vop, misc, global_regdone_en, 1); 19799a61c54bSMark yao VOP_REG_SET(vop, common, dsp_blank, 0); 19802048e328SMark Yao 19812b60e11dSSean Paul for (i = 0; i < vop->data->win_size; i++) { 19822b60e11dSSean Paul struct vop_win *vop_win = &vop->win[i]; 19832b60e11dSSean Paul const struct vop_win_data *win = vop_win->data; 19849dd2aca4SMark yao int channel = i * 2 + 1; 19852048e328SMark Yao 19869dd2aca4SMark yao VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 19872b60e11dSSean Paul vop_win_disable(vop, vop_win); 198860b7ae7fSMark yao VOP_WIN_SET(vop, win, gate, 1); 19892048e328SMark Yao } 19902048e328SMark Yao 19912048e328SMark Yao vop_cfg_done(vop); 19922048e328SMark Yao 19932048e328SMark Yao /* 19942048e328SMark Yao * do dclk_reset, let all config take affect. 19952048e328SMark Yao */ 19962048e328SMark Yao vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 19972048e328SMark Yao if (IS_ERR(vop->dclk_rst)) { 1998d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 19992048e328SMark Yao ret = PTR_ERR(vop->dclk_rst); 2000d7b53fd9SSjoerd Simons goto err_disable_aclk; 20012048e328SMark Yao } 20022048e328SMark Yao reset_control_assert(vop->dclk_rst); 20032048e328SMark Yao usleep_range(10, 20); 20042048e328SMark Yao reset_control_deassert(vop->dclk_rst); 20052048e328SMark Yao 20062048e328SMark Yao clk_disable(vop->hclk); 2007d7b53fd9SSjoerd Simons clk_disable(vop->aclk); 20082048e328SMark Yao 200931e980c5SMark Yao vop->is_enabled = false; 20102048e328SMark Yao 20115e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 20125e570373SJeffy Chen 20132048e328SMark Yao return 0; 20142048e328SMark Yao 2015d7b53fd9SSjoerd Simons err_disable_aclk: 2016d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->aclk); 20172048e328SMark Yao err_disable_hclk: 2018d7b53fd9SSjoerd Simons clk_disable_unprepare(vop->hclk); 20192048e328SMark Yao err_unprepare_dclk: 20202048e328SMark Yao clk_unprepare(vop->dclk); 20215e570373SJeffy Chen err_put_pm_runtime: 20225e570373SJeffy Chen pm_runtime_put_sync(vop->dev); 20232048e328SMark Yao return ret; 20242048e328SMark Yao } 20252048e328SMark Yao 20262048e328SMark Yao /* 20272048e328SMark Yao * Initialize the vop->win array elements. 20282048e328SMark Yao */ 20292048e328SMark Yao static void vop_win_init(struct vop *vop) 20302048e328SMark Yao { 20312048e328SMark Yao const struct vop_data *vop_data = vop->data; 20322048e328SMark Yao unsigned int i; 20332048e328SMark Yao 20342048e328SMark Yao for (i = 0; i < vop_data->win_size; i++) { 20352048e328SMark Yao struct vop_win *vop_win = &vop->win[i]; 20362048e328SMark Yao const struct vop_win_data *win_data = &vop_data->win[i]; 20372048e328SMark Yao 20382048e328SMark Yao vop_win->data = win_data; 20392048e328SMark Yao vop_win->vop = vop; 2040ce6912b4SHeiko Stuebner 2041ce6912b4SHeiko Stuebner if (vop_data->win_yuv2yuv) 20421c21aa8fSDaniele Castagna vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 20432048e328SMark Yao } 20442048e328SMark Yao } 20452048e328SMark Yao 204669c34e41SYakir Yang /** 2047459b086dSJeffy Chen * rockchip_drm_wait_vact_end 204869c34e41SYakir Yang * @crtc: CRTC to enable line flag 204969c34e41SYakir Yang * @mstimeout: millisecond for timeout 205069c34e41SYakir Yang * 2051459b086dSJeffy Chen * Wait for vact_end line flag irq or timeout. 205269c34e41SYakir Yang * 205369c34e41SYakir Yang * Returns: 205469c34e41SYakir Yang * Zero on success, negative errno on failure. 205569c34e41SYakir Yang */ 2056459b086dSJeffy Chen int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 205769c34e41SYakir Yang { 205869c34e41SYakir Yang struct vop *vop = to_vop(crtc); 205969c34e41SYakir Yang unsigned long jiffies_left; 2060e334d48bSzain wang int ret = 0; 206169c34e41SYakir Yang 206269c34e41SYakir Yang if (!crtc || !vop->is_enabled) 206369c34e41SYakir Yang return -ENODEV; 206469c34e41SYakir Yang 2065e334d48bSzain wang mutex_lock(&vop->vop_lock); 2066e334d48bSzain wang if (mstimeout <= 0) { 2067e334d48bSzain wang ret = -EINVAL; 2068e334d48bSzain wang goto out; 2069e334d48bSzain wang } 207069c34e41SYakir Yang 2071e334d48bSzain wang if (vop_line_flag_irq_is_enabled(vop)) { 2072e334d48bSzain wang ret = -EBUSY; 2073e334d48bSzain wang goto out; 2074e334d48bSzain wang } 207569c34e41SYakir Yang 207669c34e41SYakir Yang reinit_completion(&vop->line_flag_completion); 2077459b086dSJeffy Chen vop_line_flag_irq_enable(vop); 207869c34e41SYakir Yang 207969c34e41SYakir Yang jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 208069c34e41SYakir Yang msecs_to_jiffies(mstimeout)); 208169c34e41SYakir Yang vop_line_flag_irq_disable(vop); 208269c34e41SYakir Yang 208369c34e41SYakir Yang if (jiffies_left == 0) { 2084d8dd6804SHaneen Mohammed DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2085e334d48bSzain wang ret = -ETIMEDOUT; 2086e334d48bSzain wang goto out; 208769c34e41SYakir Yang } 208869c34e41SYakir Yang 2089e334d48bSzain wang out: 2090e334d48bSzain wang mutex_unlock(&vop->vop_lock); 2091e334d48bSzain wang return ret; 209269c34e41SYakir Yang } 2093459b086dSJeffy Chen EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 209469c34e41SYakir Yang 20952048e328SMark Yao static int vop_bind(struct device *dev, struct device *master, void *data) 20962048e328SMark Yao { 20972048e328SMark Yao struct platform_device *pdev = to_platform_device(dev); 20982048e328SMark Yao const struct vop_data *vop_data; 20992048e328SMark Yao struct drm_device *drm_dev = data; 21002048e328SMark Yao struct vop *vop; 21012048e328SMark Yao struct resource *res; 21023ea68922SHeiko Stuebner int ret, irq; 21032048e328SMark Yao 2104a67719d1SMark Yao vop_data = of_device_get_match_data(dev); 21052048e328SMark Yao if (!vop_data) 21062048e328SMark Yao return -ENODEV; 21072048e328SMark Yao 21082048e328SMark Yao /* Allocate vop struct and its vop_win array */ 210929adeb4fSGustavo A. R. Silva vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 211029adeb4fSGustavo A. R. Silva GFP_KERNEL); 21112048e328SMark Yao if (!vop) 21122048e328SMark Yao return -ENOMEM; 21132048e328SMark Yao 21142048e328SMark Yao vop->dev = dev; 21152048e328SMark Yao vop->data = vop_data; 21162048e328SMark Yao vop->drm_dev = drm_dev; 21172048e328SMark Yao dev_set_drvdata(dev, vop); 21182048e328SMark Yao 21192048e328SMark Yao vop_win_init(vop); 21202048e328SMark Yao 21212048e328SMark Yao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 21222048e328SMark Yao vop->len = resource_size(res); 21232048e328SMark Yao vop->regs = devm_ioremap_resource(dev, res); 21242048e328SMark Yao if (IS_ERR(vop->regs)) 21252048e328SMark Yao return PTR_ERR(vop->regs); 21262048e328SMark Yao 2127b23ab6acSEzequiel Garcia res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2128b23ab6acSEzequiel Garcia if (res) { 2129b23ab6acSEzequiel Garcia if (!vop_data->lut_size) { 2130b23ab6acSEzequiel Garcia DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); 2131b23ab6acSEzequiel Garcia return -EINVAL; 2132b23ab6acSEzequiel Garcia } 2133b23ab6acSEzequiel Garcia vop->lut_regs = devm_ioremap_resource(dev, res); 2134b23ab6acSEzequiel Garcia if (IS_ERR(vop->lut_regs)) 2135b23ab6acSEzequiel Garcia return PTR_ERR(vop->lut_regs); 2136b23ab6acSEzequiel Garcia } 2137b23ab6acSEzequiel Garcia 21382048e328SMark Yao vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 21392048e328SMark Yao if (!vop->regsbak) 21402048e328SMark Yao return -ENOMEM; 21412048e328SMark Yao 21423ea68922SHeiko Stuebner irq = platform_get_irq(pdev, 0); 21433ea68922SHeiko Stuebner if (irq < 0) { 2144d8dd6804SHaneen Mohammed DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 21453ea68922SHeiko Stuebner return irq; 21462048e328SMark Yao } 21473ea68922SHeiko Stuebner vop->irq = (unsigned int)irq; 21482048e328SMark Yao 21492048e328SMark Yao spin_lock_init(&vop->reg_lock); 21502048e328SMark Yao spin_lock_init(&vop->irq_lock); 2151e334d48bSzain wang mutex_init(&vop->vop_lock); 21522048e328SMark Yao 21532048e328SMark Yao ret = vop_create_crtc(vop); 21542048e328SMark Yao if (ret) 21555f9e93feSMarc Zyngier return ret; 21562048e328SMark Yao 21572048e328SMark Yao pm_runtime_enable(&pdev->dev); 21585182c1a5SYakir Yang 21595e570373SJeffy Chen ret = vop_initial(vop); 21605e570373SJeffy Chen if (ret < 0) { 2161d8dd6804SHaneen Mohammed DRM_DEV_ERROR(&pdev->dev, 2162d8dd6804SHaneen Mohammed "cannot initial vop dev - err %d\n", ret); 21635e570373SJeffy Chen goto err_disable_pm_runtime; 21645e570373SJeffy Chen } 21655e570373SJeffy Chen 21665f9e93feSMarc Zyngier ret = devm_request_irq(dev, vop->irq, vop_isr, 21675f9e93feSMarc Zyngier IRQF_SHARED, dev_name(dev), vop); 21685f9e93feSMarc Zyngier if (ret) 21695f9e93feSMarc Zyngier goto err_disable_pm_runtime; 21705f9e93feSMarc Zyngier 21711f0f0151SSandy Huang if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 21721f0f0151SSandy Huang vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 21731f0f0151SSandy Huang if (IS_ERR(vop->rgb)) { 21741f0f0151SSandy Huang ret = PTR_ERR(vop->rgb); 21751f0f0151SSandy Huang goto err_disable_pm_runtime; 21761f0f0151SSandy Huang } 21771f0f0151SSandy Huang } 21781f0f0151SSandy Huang 21792048e328SMark Yao return 0; 21808c763c9bSSean Paul 21815e570373SJeffy Chen err_disable_pm_runtime: 21825e570373SJeffy Chen pm_runtime_disable(&pdev->dev); 21835e570373SJeffy Chen vop_destroy_crtc(vop); 21848c763c9bSSean Paul return ret; 21852048e328SMark Yao } 21862048e328SMark Yao 21872048e328SMark Yao static void vop_unbind(struct device *dev, struct device *master, void *data) 21882048e328SMark Yao { 21892048e328SMark Yao struct vop *vop = dev_get_drvdata(dev); 21902048e328SMark Yao 21911f0f0151SSandy Huang if (vop->rgb) 21921f0f0151SSandy Huang rockchip_rgb_fini(vop->rgb); 21931f0f0151SSandy Huang 21942048e328SMark Yao pm_runtime_disable(dev); 21952048e328SMark Yao vop_destroy_crtc(vop); 2196ec6e7767SJeffy Chen 2197ec6e7767SJeffy Chen clk_unprepare(vop->aclk); 2198ec6e7767SJeffy Chen clk_unprepare(vop->hclk); 2199ec6e7767SJeffy Chen clk_unprepare(vop->dclk); 22002048e328SMark Yao } 22012048e328SMark Yao 2202a67719d1SMark Yao const struct component_ops vop_component_ops = { 22032048e328SMark Yao .bind = vop_bind, 22042048e328SMark Yao .unbind = vop_unbind, 22052048e328SMark Yao }; 220654255e81SStephen Rothwell EXPORT_SYMBOL_GPL(vop_component_ops); 2207