1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Zheng Yang <zhengyang@rock-chips.com> 5 */ 6 7 #include <drm/drm_of.h> 8 #include <drm/drm_probe_helper.h> 9 #include <drm/drm_simple_kms_helper.h> 10 11 #include <linux/clk.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include "rk3066_hdmi.h" 17 18 #include "rockchip_drm_drv.h" 19 #include "rockchip_drm_vop.h" 20 21 #define DEFAULT_PLLA_RATE 30000000 22 23 struct hdmi_data_info { 24 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ 25 unsigned int enc_out_format; 26 unsigned int colorimetry; 27 }; 28 29 struct rk3066_hdmi_i2c { 30 struct i2c_adapter adap; 31 32 u8 ddc_addr; 33 u8 segment_addr; 34 u8 stat; 35 36 struct mutex i2c_lock; /* For i2c operation. */ 37 struct completion cmpltn; 38 }; 39 40 struct rk3066_hdmi { 41 struct device *dev; 42 struct drm_device *drm_dev; 43 struct regmap *grf_regmap; 44 int irq; 45 struct clk *hclk; 46 void __iomem *regs; 47 48 struct drm_connector connector; 49 struct rockchip_encoder encoder; 50 51 struct rk3066_hdmi_i2c *i2c; 52 struct i2c_adapter *ddc; 53 54 unsigned int tmdsclk; 55 56 struct hdmi_data_info hdmi_data; 57 struct drm_display_mode previous_mode; 58 }; 59 60 static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder) 61 { 62 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 63 64 return container_of(rkencoder, struct rk3066_hdmi, encoder); 65 } 66 67 static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector) 68 { 69 return container_of(connector, struct rk3066_hdmi, connector); 70 } 71 72 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) 73 { 74 return readl_relaxed(hdmi->regs + offset); 75 } 76 77 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) 78 { 79 writel_relaxed(val, hdmi->regs + offset); 80 } 81 82 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, 83 u32 msk, u32 val) 84 { 85 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 86 87 temp |= val & msk; 88 hdmi_writeb(hdmi, offset, temp); 89 } 90 91 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi) 92 { 93 int ddc_bus_freq; 94 95 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; 96 97 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 98 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 99 100 /* Clear the EDID interrupt flag and mute the interrupt. */ 101 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 102 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK); 103 } 104 105 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi) 106 { 107 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK; 108 } 109 110 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode) 111 { 112 u8 current_mode, next_mode; 113 u8 i = 0; 114 115 current_mode = rk3066_hdmi_get_power_mode(hdmi); 116 117 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode); 118 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode); 119 120 if (current_mode == mode) 121 return; 122 123 do { 124 if (current_mode > mode) { 125 next_mode = current_mode / 2; 126 } else { 127 if (current_mode < HDMI_SYS_POWER_MODE_A) 128 next_mode = HDMI_SYS_POWER_MODE_A; 129 else 130 next_mode = current_mode * 2; 131 } 132 133 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode); 134 135 if (next_mode != HDMI_SYS_POWER_MODE_D) { 136 hdmi_modb(hdmi, HDMI_SYS_CTRL, 137 HDMI_SYS_POWER_MODE_MASK, next_mode); 138 } else { 139 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 140 HDMI_SYS_POWER_MODE_D | 141 HDMI_SYS_PLL_RESET_MASK); 142 usleep_range(90, 100); 143 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 144 HDMI_SYS_POWER_MODE_D | 145 HDMI_SYS_PLLB_RESET); 146 usleep_range(90, 100); 147 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 148 HDMI_SYS_POWER_MODE_D); 149 } 150 current_mode = next_mode; 151 i = i + 1; 152 } while ((next_mode != mode) && (i < 5)); 153 154 /* 155 * When the IP controller isn't configured with accurate video timing, 156 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz, 157 * so we need to init the TMDS rate to the PCLK rate and reconfigure 158 * the DDC clock. 159 */ 160 if (mode < HDMI_SYS_POWER_MODE_D) 161 hdmi->tmdsclk = DEFAULT_PLLA_RATE; 162 } 163 164 static int 165 rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc, 166 union hdmi_infoframe *frame, u32 frame_index, 167 u32 mask, u32 disable, u32 enable) 168 { 169 if (mask) 170 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable); 171 172 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index); 173 174 if (setup_rc >= 0) { 175 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE]; 176 ssize_t rc, i; 177 178 rc = hdmi_infoframe_pack(frame, packed_frame, 179 sizeof(packed_frame)); 180 if (rc < 0) 181 return rc; 182 183 for (i = 0; i < rc; i++) 184 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, 185 packed_frame[i]); 186 187 if (mask) 188 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable); 189 } 190 191 return setup_rc; 192 } 193 194 static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi, 195 struct drm_display_mode *mode) 196 { 197 union hdmi_infoframe frame; 198 int rc; 199 200 rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 201 &hdmi->connector, mode); 202 203 if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444) 204 frame.avi.colorspace = HDMI_COLORSPACE_YUV444; 205 else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422) 206 frame.avi.colorspace = HDMI_COLORSPACE_YUV422; 207 else 208 frame.avi.colorspace = HDMI_COLORSPACE_RGB; 209 210 frame.avi.colorimetry = hdmi->hdmi_data.colorimetry; 211 frame.avi.scan_mode = HDMI_SCAN_MODE_NONE; 212 213 return rk3066_hdmi_upload_frame(hdmi, rc, &frame, 214 HDMI_INFOFRAME_AVI, 0, 0, 0); 215 } 216 217 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi, 218 struct drm_display_mode *mode) 219 { 220 int value, vsync_offset; 221 222 /* Set the details for the external polarity and interlace mode. */ 223 value = HDMI_EXT_VIDEO_SET_EN; 224 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 225 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW; 226 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 227 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW; 228 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 229 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE; 230 231 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) 232 vsync_offset = 6; 233 else 234 vsync_offset = 0; 235 236 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT; 237 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value); 238 239 /* Set the details for the external video timing. */ 240 value = mode->htotal; 241 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF); 242 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF); 243 244 value = mode->htotal - mode->hdisplay; 245 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF); 246 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF); 247 248 value = mode->htotal - mode->hsync_start; 249 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF); 250 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF); 251 252 value = mode->hsync_end - mode->hsync_start; 253 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF); 254 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF); 255 256 value = mode->vtotal; 257 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF); 258 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF); 259 260 value = mode->vtotal - mode->vdisplay; 261 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF); 262 263 value = mode->vtotal - mode->vsync_start + vsync_offset; 264 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF); 265 266 value = mode->vsync_end - mode->vsync_start; 267 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF); 268 269 return 0; 270 } 271 272 static void 273 rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value) 274 { 275 hdmi_writeb(hdmi, offset, value); 276 hdmi_modb(hdmi, HDMI_SYS_CTRL, 277 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET); 278 usleep_range(90, 100); 279 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0); 280 usleep_range(900, 1000); 281 } 282 283 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi) 284 { 285 /* TMDS uses the same frequency as dclk. */ 286 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22); 287 288 /* 289 * The semi-public documentation does not describe the hdmi registers 290 * used by the function rk3066_hdmi_phy_write(), so we keep using 291 * these magic values for now. 292 */ 293 if (hdmi->tmdsclk > 100000000) { 294 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E); 295 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 296 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 297 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 298 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA); 299 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1); 300 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 301 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22); 302 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 303 } else if (hdmi->tmdsclk > 50000000) { 304 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06); 305 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 306 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 307 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 308 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA); 309 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3); 310 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 311 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 312 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 313 } else { 314 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02); 315 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 316 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 317 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 318 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2); 319 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2); 320 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 321 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 322 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 323 } 324 } 325 326 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, 327 struct drm_display_mode *mode) 328 { 329 struct drm_display_info *display = &hdmi->connector.display_info; 330 331 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); 332 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; 333 334 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || 335 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || 336 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || 337 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) 338 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; 339 else 340 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; 341 342 hdmi->tmdsclk = mode->clock * 1000; 343 344 /* Mute video and audio output. */ 345 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, 346 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE); 347 348 /* Set power state to mode B. */ 349 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B) 350 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 351 352 /* Input video mode is RGB 24 bit. Use external data enable signal. */ 353 hdmi_modb(hdmi, HDMI_AV_CTRL1, 354 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE); 355 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1, 356 HDMI_VIDEO_OUTPUT_RGB444 | 357 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT | 358 HDMI_VIDEO_INPUT_COLOR_RGB); 359 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20); 360 361 rk3066_hdmi_config_video_timing(hdmi, mode); 362 363 if (display->is_hdmi) { 364 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 365 HDMI_VIDEO_MODE_HDMI); 366 rk3066_hdmi_config_avi(hdmi, mode); 367 } else { 368 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0); 369 } 370 371 rk3066_hdmi_config_phy(hdmi); 372 373 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E); 374 375 /* 376 * When the IP controller is configured with accurate video 377 * timing, the TMDS clock source should be switched to 378 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode 379 * clock rate and reconfigure the DDC clock. 380 */ 381 rk3066_hdmi_i2c_init(hdmi); 382 383 /* Unmute video output. */ 384 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 385 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE); 386 return 0; 387 } 388 389 static void 390 rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder, 391 struct drm_display_mode *mode, 392 struct drm_display_mode *adj_mode) 393 { 394 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); 395 396 /* Store the display mode for plugin/DPMS poweron events. */ 397 memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); 398 } 399 400 static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) 401 { 402 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); 403 int mux, val; 404 405 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); 406 if (mux) 407 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL; 408 else 409 val = HDMI_VIDEO_SEL << 16; 410 411 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val); 412 413 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n", 414 (mux) ? "1" : "0"); 415 416 rk3066_hdmi_setup(hdmi, &hdmi->previous_mode); 417 } 418 419 static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder) 420 { 421 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); 422 423 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); 424 425 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) { 426 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2, 427 HDMI_VIDEO_AUDIO_DISABLE_MASK); 428 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 429 HDMI_AUDIO_CP_LOGIC_RESET_MASK, 430 HDMI_AUDIO_CP_LOGIC_RESET); 431 usleep_range(500, 510); 432 } 433 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 434 } 435 436 static bool 437 rk3066_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, 438 const struct drm_display_mode *mode, 439 struct drm_display_mode *adj_mode) 440 { 441 return true; 442 } 443 444 static int 445 rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 446 struct drm_crtc_state *crtc_state, 447 struct drm_connector_state *conn_state) 448 { 449 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 450 451 s->output_mode = ROCKCHIP_OUT_MODE_P888; 452 s->output_type = DRM_MODE_CONNECTOR_HDMIA; 453 454 return 0; 455 } 456 457 static const 458 struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { 459 .enable = rk3066_hdmi_encoder_enable, 460 .disable = rk3066_hdmi_encoder_disable, 461 .mode_fixup = rk3066_hdmi_encoder_mode_fixup, 462 .mode_set = rk3066_hdmi_encoder_mode_set, 463 .atomic_check = rk3066_hdmi_encoder_atomic_check, 464 }; 465 466 static enum drm_connector_status 467 rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) 468 { 469 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); 470 471 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? 472 connector_status_connected : connector_status_disconnected; 473 } 474 475 static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector) 476 { 477 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); 478 struct edid *edid; 479 int ret = 0; 480 481 if (!hdmi->ddc) 482 return 0; 483 484 edid = drm_get_edid(connector, hdmi->ddc); 485 if (edid) { 486 drm_connector_update_edid_property(connector, edid); 487 ret = drm_add_edid_modes(connector, edid); 488 kfree(edid); 489 } 490 491 return ret; 492 } 493 494 static enum drm_mode_status 495 rk3066_hdmi_connector_mode_valid(struct drm_connector *connector, 496 struct drm_display_mode *mode) 497 { 498 u32 vic = drm_match_cea_mode(mode); 499 500 if (vic > 1) 501 return MODE_OK; 502 else 503 return MODE_BAD; 504 } 505 506 static struct drm_encoder * 507 rk3066_hdmi_connector_best_encoder(struct drm_connector *connector) 508 { 509 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); 510 511 return &hdmi->encoder.encoder; 512 } 513 514 static int 515 rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector, 516 uint32_t maxX, uint32_t maxY) 517 { 518 if (maxX > 1920) 519 maxX = 1920; 520 if (maxY > 1080) 521 maxY = 1080; 522 523 return drm_helper_probe_single_connector_modes(connector, maxX, maxY); 524 } 525 526 static void rk3066_hdmi_connector_destroy(struct drm_connector *connector) 527 { 528 drm_connector_unregister(connector); 529 drm_connector_cleanup(connector); 530 } 531 532 static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = { 533 .fill_modes = rk3066_hdmi_probe_single_connector_modes, 534 .detect = rk3066_hdmi_connector_detect, 535 .destroy = rk3066_hdmi_connector_destroy, 536 .reset = drm_atomic_helper_connector_reset, 537 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 538 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 539 }; 540 541 static const 542 struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = { 543 .get_modes = rk3066_hdmi_connector_get_modes, 544 .mode_valid = rk3066_hdmi_connector_mode_valid, 545 .best_encoder = rk3066_hdmi_connector_best_encoder, 546 }; 547 548 static int 549 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) 550 { 551 struct drm_encoder *encoder = &hdmi->encoder.encoder; 552 struct device *dev = hdmi->dev; 553 554 encoder->possible_crtcs = 555 drm_of_find_possible_crtcs(drm, dev->of_node); 556 557 /* 558 * If we failed to find the CRTC(s) which this encoder is 559 * supposed to be connected to, it's because the CRTC has 560 * not been registered yet. Defer probing, and hope that 561 * the required CRTC is added later. 562 */ 563 if (encoder->possible_crtcs == 0) 564 return -EPROBE_DEFER; 565 566 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs); 567 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 568 569 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; 570 571 drm_connector_helper_add(&hdmi->connector, 572 &rk3066_hdmi_connector_helper_funcs); 573 drm_connector_init_with_ddc(drm, &hdmi->connector, 574 &rk3066_hdmi_connector_funcs, 575 DRM_MODE_CONNECTOR_HDMIA, 576 hdmi->ddc); 577 578 drm_connector_attach_encoder(&hdmi->connector, encoder); 579 580 return 0; 581 } 582 583 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id) 584 { 585 struct rk3066_hdmi *hdmi = dev_id; 586 irqreturn_t ret = IRQ_NONE; 587 u8 interrupt; 588 589 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A) 590 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B); 591 592 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1); 593 if (interrupt) 594 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt); 595 596 if (interrupt & HDMI_INTR_EDID_MASK) { 597 hdmi->i2c->stat = interrupt; 598 complete(&hdmi->i2c->cmpltn); 599 } 600 601 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS)) 602 ret = IRQ_WAKE_THREAD; 603 604 return ret; 605 } 606 607 static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id) 608 { 609 struct rk3066_hdmi *hdmi = dev_id; 610 611 drm_helper_hpd_irq_event(hdmi->connector.dev); 612 613 return IRQ_HANDLED; 614 } 615 616 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 617 { 618 int length = msgs->len; 619 u8 *buf = msgs->buf; 620 int ret; 621 622 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10); 623 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR) 624 return -EAGAIN; 625 626 while (length--) 627 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR); 628 629 return 0; 630 } 631 632 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 633 { 634 /* 635 * The DDC module only supports read EDID message, so 636 * we assume that each word write to this i2c adapter 637 * should be the offset of the EDID word address. 638 */ 639 if (msgs->len != 1 || 640 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) 641 return -EINVAL; 642 643 reinit_completion(&hdmi->i2c->cmpltn); 644 645 if (msgs->addr == DDC_SEGMENT_ADDR) 646 hdmi->i2c->segment_addr = msgs->buf[0]; 647 if (msgs->addr == DDC_ADDR) 648 hdmi->i2c->ddc_addr = msgs->buf[0]; 649 650 /* Set edid fifo first address. */ 651 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00); 652 653 /* Set edid word address 0x00/0x80. */ 654 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 655 656 /* Set edid segment pointer. */ 657 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 658 659 return 0; 660 } 661 662 static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap, 663 struct i2c_msg *msgs, int num) 664 { 665 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap); 666 struct rk3066_hdmi_i2c *i2c = hdmi->i2c; 667 int i, ret = 0; 668 669 mutex_lock(&i2c->i2c_lock); 670 671 rk3066_hdmi_i2c_init(hdmi); 672 673 /* Unmute HDMI EDID interrupt. */ 674 hdmi_modb(hdmi, HDMI_INTR_MASK1, 675 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK); 676 i2c->stat = 0; 677 678 for (i = 0; i < num; i++) { 679 DRM_DEV_DEBUG(hdmi->dev, 680 "xfer: num: %d/%d, len: %d, flags: %#x\n", 681 i + 1, num, msgs[i].len, msgs[i].flags); 682 683 if (msgs[i].flags & I2C_M_RD) 684 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]); 685 else 686 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]); 687 688 if (ret < 0) 689 break; 690 } 691 692 if (!ret) 693 ret = num; 694 695 /* Mute HDMI EDID interrupt. */ 696 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 697 698 mutex_unlock(&i2c->i2c_lock); 699 700 return ret; 701 } 702 703 static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter) 704 { 705 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 706 } 707 708 static const struct i2c_algorithm rk3066_hdmi_algorithm = { 709 .master_xfer = rk3066_hdmi_i2c_xfer, 710 .functionality = rk3066_hdmi_i2c_func, 711 }; 712 713 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi) 714 { 715 struct i2c_adapter *adap; 716 struct rk3066_hdmi_i2c *i2c; 717 int ret; 718 719 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 720 if (!i2c) 721 return ERR_PTR(-ENOMEM); 722 723 mutex_init(&i2c->i2c_lock); 724 init_completion(&i2c->cmpltn); 725 726 adap = &i2c->adap; 727 adap->class = I2C_CLASS_DDC; 728 adap->owner = THIS_MODULE; 729 adap->dev.parent = hdmi->dev; 730 adap->dev.of_node = hdmi->dev->of_node; 731 adap->algo = &rk3066_hdmi_algorithm; 732 strlcpy(adap->name, "RK3066 HDMI", sizeof(adap->name)); 733 i2c_set_adapdata(adap, hdmi); 734 735 ret = i2c_add_adapter(adap); 736 if (ret) { 737 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n", 738 adap->name); 739 devm_kfree(hdmi->dev, i2c); 740 return ERR_PTR(ret); 741 } 742 743 hdmi->i2c = i2c; 744 745 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 746 747 return adap; 748 } 749 750 static int rk3066_hdmi_bind(struct device *dev, struct device *master, 751 void *data) 752 { 753 struct platform_device *pdev = to_platform_device(dev); 754 struct drm_device *drm = data; 755 struct rk3066_hdmi *hdmi; 756 int irq; 757 int ret; 758 759 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 760 if (!hdmi) 761 return -ENOMEM; 762 763 hdmi->dev = dev; 764 hdmi->drm_dev = drm; 765 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 766 if (IS_ERR(hdmi->regs)) 767 return PTR_ERR(hdmi->regs); 768 769 irq = platform_get_irq(pdev, 0); 770 if (irq < 0) 771 return irq; 772 773 hdmi->hclk = devm_clk_get(dev, "hclk"); 774 if (IS_ERR(hdmi->hclk)) { 775 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n"); 776 return PTR_ERR(hdmi->hclk); 777 } 778 779 ret = clk_prepare_enable(hdmi->hclk); 780 if (ret) { 781 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret); 782 return ret; 783 } 784 785 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 786 "rockchip,grf"); 787 if (IS_ERR(hdmi->grf_regmap)) { 788 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n"); 789 ret = PTR_ERR(hdmi->grf_regmap); 790 goto err_disable_hclk; 791 } 792 793 /* internal hclk = hdmi_hclk / 25 */ 794 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25); 795 796 hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi); 797 if (IS_ERR(hdmi->ddc)) { 798 ret = PTR_ERR(hdmi->ddc); 799 hdmi->ddc = NULL; 800 goto err_disable_hclk; 801 } 802 803 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 804 usleep_range(999, 1000); 805 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG); 806 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0); 807 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0); 808 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0); 809 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 810 811 ret = rk3066_hdmi_register(drm, hdmi); 812 if (ret) 813 goto err_disable_i2c; 814 815 dev_set_drvdata(dev, hdmi); 816 817 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq, 818 rk3066_hdmi_irq, IRQF_SHARED, 819 dev_name(dev), hdmi); 820 if (ret) { 821 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret); 822 goto err_cleanup_hdmi; 823 } 824 825 return 0; 826 827 err_cleanup_hdmi: 828 hdmi->connector.funcs->destroy(&hdmi->connector); 829 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 830 err_disable_i2c: 831 i2c_put_adapter(hdmi->ddc); 832 err_disable_hclk: 833 clk_disable_unprepare(hdmi->hclk); 834 835 return ret; 836 } 837 838 static void rk3066_hdmi_unbind(struct device *dev, struct device *master, 839 void *data) 840 { 841 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); 842 843 hdmi->connector.funcs->destroy(&hdmi->connector); 844 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 845 846 i2c_put_adapter(hdmi->ddc); 847 clk_disable_unprepare(hdmi->hclk); 848 } 849 850 static const struct component_ops rk3066_hdmi_ops = { 851 .bind = rk3066_hdmi_bind, 852 .unbind = rk3066_hdmi_unbind, 853 }; 854 855 static int rk3066_hdmi_probe(struct platform_device *pdev) 856 { 857 return component_add(&pdev->dev, &rk3066_hdmi_ops); 858 } 859 860 static int rk3066_hdmi_remove(struct platform_device *pdev) 861 { 862 component_del(&pdev->dev, &rk3066_hdmi_ops); 863 864 return 0; 865 } 866 867 static const struct of_device_id rk3066_hdmi_dt_ids[] = { 868 { .compatible = "rockchip,rk3066-hdmi" }, 869 { /* sentinel */ }, 870 }; 871 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids); 872 873 struct platform_driver rk3066_hdmi_driver = { 874 .probe = rk3066_hdmi_probe, 875 .remove = rk3066_hdmi_remove, 876 .driver = { 877 .name = "rockchip-rk3066-hdmi", 878 .of_match_table = rk3066_hdmi_dt_ids, 879 }, 880 }; 881