1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4  *    Zheng Yang <zhengyang@rock-chips.com>
5  */
6 
7 #include <drm/drm_of.h>
8 #include <drm/drm_probe_helper.h>
9 #include <drm/drm_simple_kms_helper.h>
10 
11 #include <linux/clk.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 
16 #include "rk3066_hdmi.h"
17 
18 #include "rockchip_drm_drv.h"
19 #include "rockchip_drm_vop.h"
20 
21 #define DEFAULT_PLLA_RATE 30000000
22 
23 struct hdmi_data_info {
24 	int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
25 	bool sink_is_hdmi;
26 	unsigned int enc_out_format;
27 	unsigned int colorimetry;
28 };
29 
30 struct rk3066_hdmi_i2c {
31 	struct i2c_adapter adap;
32 
33 	u8 ddc_addr;
34 	u8 segment_addr;
35 	u8 stat;
36 
37 	struct mutex i2c_lock; /* For i2c operation. */
38 	struct completion cmpltn;
39 };
40 
41 struct rk3066_hdmi {
42 	struct device *dev;
43 	struct drm_device *drm_dev;
44 	struct regmap *grf_regmap;
45 	int irq;
46 	struct clk *hclk;
47 	void __iomem *regs;
48 
49 	struct drm_connector connector;
50 	struct drm_encoder encoder;
51 
52 	struct rk3066_hdmi_i2c *i2c;
53 	struct i2c_adapter *ddc;
54 
55 	unsigned int tmdsclk;
56 
57 	struct hdmi_data_info hdmi_data;
58 	struct drm_display_mode previous_mode;
59 };
60 
61 #define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
62 
63 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
64 {
65 	return readl_relaxed(hdmi->regs + offset);
66 }
67 
68 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
69 {
70 	writel_relaxed(val, hdmi->regs + offset);
71 }
72 
73 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset,
74 			     u32 msk, u32 val)
75 {
76 	u8 temp = hdmi_readb(hdmi, offset) & ~msk;
77 
78 	temp |= val & msk;
79 	hdmi_writeb(hdmi, offset, temp);
80 }
81 
82 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi)
83 {
84 	int ddc_bus_freq;
85 
86 	ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE;
87 
88 	hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
89 	hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
90 
91 	/* Clear the EDID interrupt flag and mute the interrupt. */
92 	hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
93 	hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
94 }
95 
96 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi)
97 {
98 	return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK;
99 }
100 
101 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
102 {
103 	u8 current_mode, next_mode;
104 	u8 i = 0;
105 
106 	current_mode = rk3066_hdmi_get_power_mode(hdmi);
107 
108 	DRM_DEV_DEBUG(hdmi->dev, "mode         :%d\n", mode);
109 	DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
110 
111 	if (current_mode == mode)
112 		return;
113 
114 	do {
115 		if (current_mode > mode) {
116 			next_mode = current_mode / 2;
117 		} else {
118 			if (current_mode < HDMI_SYS_POWER_MODE_A)
119 				next_mode = HDMI_SYS_POWER_MODE_A;
120 			else
121 				next_mode = current_mode * 2;
122 		}
123 
124 		DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
125 
126 		if (next_mode != HDMI_SYS_POWER_MODE_D) {
127 			hdmi_modb(hdmi, HDMI_SYS_CTRL,
128 				  HDMI_SYS_POWER_MODE_MASK, next_mode);
129 		} else {
130 			hdmi_writeb(hdmi, HDMI_SYS_CTRL,
131 				    HDMI_SYS_POWER_MODE_D |
132 				    HDMI_SYS_PLL_RESET_MASK);
133 			usleep_range(90, 100);
134 			hdmi_writeb(hdmi, HDMI_SYS_CTRL,
135 				    HDMI_SYS_POWER_MODE_D |
136 				    HDMI_SYS_PLLB_RESET);
137 			usleep_range(90, 100);
138 			hdmi_writeb(hdmi, HDMI_SYS_CTRL,
139 				    HDMI_SYS_POWER_MODE_D);
140 		}
141 		current_mode = next_mode;
142 		i = i + 1;
143 	} while ((next_mode != mode) && (i < 5));
144 
145 	/*
146 	 * When the IP controller isn't configured with accurate video timing,
147 	 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz,
148 	 * so we need to init the TMDS rate to the PCLK rate and reconfigure
149 	 * the DDC clock.
150 	 */
151 	if (mode < HDMI_SYS_POWER_MODE_D)
152 		hdmi->tmdsclk = DEFAULT_PLLA_RATE;
153 }
154 
155 static int
156 rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc,
157 			 union hdmi_infoframe *frame, u32 frame_index,
158 			 u32 mask, u32 disable, u32 enable)
159 {
160 	if (mask)
161 		hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable);
162 
163 	hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index);
164 
165 	if (setup_rc >= 0) {
166 		u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
167 		ssize_t rc, i;
168 
169 		rc = hdmi_infoframe_pack(frame, packed_frame,
170 					 sizeof(packed_frame));
171 		if (rc < 0)
172 			return rc;
173 
174 		for (i = 0; i < rc; i++)
175 			hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4,
176 				    packed_frame[i]);
177 
178 		if (mask)
179 			hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable);
180 	}
181 
182 	return setup_rc;
183 }
184 
185 static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi,
186 				  struct drm_display_mode *mode)
187 {
188 	union hdmi_infoframe frame;
189 	int rc;
190 
191 	rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
192 						      &hdmi->connector, mode);
193 
194 	if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
195 		frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
196 	else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
197 		frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
198 	else
199 		frame.avi.colorspace = HDMI_COLORSPACE_RGB;
200 
201 	frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;
202 	frame.avi.scan_mode = HDMI_SCAN_MODE_NONE;
203 
204 	return rk3066_hdmi_upload_frame(hdmi, rc, &frame,
205 					HDMI_INFOFRAME_AVI, 0, 0, 0);
206 }
207 
208 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
209 					   struct drm_display_mode *mode)
210 {
211 	int value, vsync_offset;
212 
213 	/* Set the details for the external polarity and interlace mode. */
214 	value = HDMI_EXT_VIDEO_SET_EN;
215 	value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
216 		 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW;
217 	value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
218 		 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW;
219 	value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
220 		 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE;
221 
222 	if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)
223 		vsync_offset = 6;
224 	else
225 		vsync_offset = 0;
226 
227 	value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT;
228 	hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
229 
230 	/* Set the details for the external video timing. */
231 	value = mode->htotal;
232 	hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
233 	hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF);
234 
235 	value = mode->htotal - mode->hdisplay;
236 	hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF);
237 	hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF);
238 
239 	value = mode->htotal - mode->hsync_start;
240 	hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF);
241 	hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF);
242 
243 	value = mode->hsync_end - mode->hsync_start;
244 	hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF);
245 	hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF);
246 
247 	value = mode->vtotal;
248 	hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF);
249 	hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF);
250 
251 	value = mode->vtotal - mode->vdisplay;
252 	hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF);
253 
254 	value = mode->vtotal - mode->vsync_start + vsync_offset;
255 	hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF);
256 
257 	value = mode->vsync_end - mode->vsync_start;
258 	hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF);
259 
260 	return 0;
261 }
262 
263 static void
264 rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value)
265 {
266 	hdmi_writeb(hdmi, offset, value);
267 	hdmi_modb(hdmi, HDMI_SYS_CTRL,
268 		  HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET);
269 	usleep_range(90, 100);
270 	hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0);
271 	usleep_range(900, 1000);
272 }
273 
274 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
275 {
276 	/* TMDS uses the same frequency as dclk. */
277 	hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
278 
279 	/*
280 	 * The semi-public documentation does not describe the hdmi registers
281 	 * used by the function rk3066_hdmi_phy_write(), so we keep using
282 	 * these magic values for now.
283 	 */
284 	if (hdmi->tmdsclk > 100000000) {
285 		rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
286 		rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
287 		rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
288 		rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
289 		rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA);
290 		rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1);
291 		rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
292 		rk3066_hdmi_phy_write(hdmi, 0x174, 0x22);
293 		rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
294 	} else if (hdmi->tmdsclk > 50000000) {
295 		rk3066_hdmi_phy_write(hdmi, 0x158, 0x06);
296 		rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
297 		rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
298 		rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
299 		rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA);
300 		rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3);
301 		rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
302 		rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
303 		rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
304 	} else {
305 		rk3066_hdmi_phy_write(hdmi, 0x158, 0x02);
306 		rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
307 		rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
308 		rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
309 		rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2);
310 		rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2);
311 		rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
312 		rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
313 		rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
314 	}
315 }
316 
317 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
318 			     struct drm_display_mode *mode)
319 {
320 	hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
321 	hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
322 
323 	if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||
324 	    hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 ||
325 	    hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 ||
326 	    hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18)
327 		hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
328 	else
329 		hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
330 
331 	hdmi->tmdsclk = mode->clock * 1000;
332 
333 	/* Mute video and audio output. */
334 	hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK,
335 		  HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE);
336 
337 	/* Set power state to mode B. */
338 	if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B)
339 		rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
340 
341 	/* Input video mode is RGB 24 bit. Use external data enable signal. */
342 	hdmi_modb(hdmi, HDMI_AV_CTRL1,
343 		  HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE);
344 	hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
345 		    HDMI_VIDEO_OUTPUT_RGB444 |
346 		    HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT |
347 		    HDMI_VIDEO_INPUT_COLOR_RGB);
348 	hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20);
349 
350 	rk3066_hdmi_config_video_timing(hdmi, mode);
351 
352 	if (hdmi->hdmi_data.sink_is_hdmi) {
353 		hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
354 			  HDMI_VIDEO_MODE_HDMI);
355 		rk3066_hdmi_config_avi(hdmi, mode);
356 	} else {
357 		hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
358 	}
359 
360 	rk3066_hdmi_config_phy(hdmi);
361 
362 	rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
363 
364 	/*
365 	 * When the IP controller is configured with accurate video
366 	 * timing, the TMDS clock source should be switched to
367 	 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode
368 	 * clock rate and reconfigure the DDC clock.
369 	 */
370 	rk3066_hdmi_i2c_init(hdmi);
371 
372 	/* Unmute video output. */
373 	hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
374 		  HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
375 	return 0;
376 }
377 
378 static void
379 rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
380 			     struct drm_display_mode *mode,
381 			     struct drm_display_mode *adj_mode)
382 {
383 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
384 
385 	/* Store the display mode for plugin/DPMS poweron events. */
386 	memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
387 }
388 
389 static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
390 {
391 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
392 	int mux, val;
393 
394 	mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
395 	if (mux)
396 		val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL;
397 	else
398 		val = HDMI_VIDEO_SEL << 16;
399 
400 	regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
401 
402 	DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n",
403 		      (mux) ? "1" : "0");
404 
405 	rk3066_hdmi_setup(hdmi, &hdmi->previous_mode);
406 }
407 
408 static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
409 {
410 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
411 
412 	DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
413 
414 	if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
415 		hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2,
416 			    HDMI_VIDEO_AUDIO_DISABLE_MASK);
417 		hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
418 			  HDMI_AUDIO_CP_LOGIC_RESET_MASK,
419 			  HDMI_AUDIO_CP_LOGIC_RESET);
420 		usleep_range(500, 510);
421 	}
422 	rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
423 }
424 
425 static bool
426 rk3066_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
427 			       const struct drm_display_mode *mode,
428 			       struct drm_display_mode *adj_mode)
429 {
430 	return true;
431 }
432 
433 static int
434 rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
435 				 struct drm_crtc_state *crtc_state,
436 				 struct drm_connector_state *conn_state)
437 {
438 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
439 
440 	s->output_mode = ROCKCHIP_OUT_MODE_P888;
441 	s->output_type = DRM_MODE_CONNECTOR_HDMIA;
442 
443 	return 0;
444 }
445 
446 static const
447 struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
448 	.enable       = rk3066_hdmi_encoder_enable,
449 	.disable      = rk3066_hdmi_encoder_disable,
450 	.mode_fixup   = rk3066_hdmi_encoder_mode_fixup,
451 	.mode_set     = rk3066_hdmi_encoder_mode_set,
452 	.atomic_check = rk3066_hdmi_encoder_atomic_check,
453 };
454 
455 static enum drm_connector_status
456 rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
457 {
458 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
459 
460 	return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
461 		connector_status_connected : connector_status_disconnected;
462 }
463 
464 static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
465 {
466 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
467 	struct edid *edid;
468 	int ret = 0;
469 
470 	if (!hdmi->ddc)
471 		return 0;
472 
473 	edid = drm_get_edid(connector, hdmi->ddc);
474 	if (edid) {
475 		hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
476 		drm_connector_update_edid_property(connector, edid);
477 		ret = drm_add_edid_modes(connector, edid);
478 		kfree(edid);
479 	}
480 
481 	return ret;
482 }
483 
484 static enum drm_mode_status
485 rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
486 				 struct drm_display_mode *mode)
487 {
488 	u32 vic = drm_match_cea_mode(mode);
489 
490 	if (vic > 1)
491 		return MODE_OK;
492 	else
493 		return MODE_BAD;
494 }
495 
496 static struct drm_encoder *
497 rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
498 {
499 	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
500 
501 	return &hdmi->encoder;
502 }
503 
504 static int
505 rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector,
506 					 uint32_t maxX, uint32_t maxY)
507 {
508 	if (maxX > 1920)
509 		maxX = 1920;
510 	if (maxY > 1080)
511 		maxY = 1080;
512 
513 	return drm_helper_probe_single_connector_modes(connector, maxX, maxY);
514 }
515 
516 static void rk3066_hdmi_connector_destroy(struct drm_connector *connector)
517 {
518 	drm_connector_unregister(connector);
519 	drm_connector_cleanup(connector);
520 }
521 
522 static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = {
523 	.fill_modes = rk3066_hdmi_probe_single_connector_modes,
524 	.detect = rk3066_hdmi_connector_detect,
525 	.destroy = rk3066_hdmi_connector_destroy,
526 	.reset = drm_atomic_helper_connector_reset,
527 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
528 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
529 };
530 
531 static const
532 struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
533 	.get_modes = rk3066_hdmi_connector_get_modes,
534 	.mode_valid = rk3066_hdmi_connector_mode_valid,
535 	.best_encoder = rk3066_hdmi_connector_best_encoder,
536 };
537 
538 static int
539 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
540 {
541 	struct drm_encoder *encoder = &hdmi->encoder;
542 	struct device *dev = hdmi->dev;
543 
544 	encoder->possible_crtcs =
545 		drm_of_find_possible_crtcs(drm, dev->of_node);
546 
547 	/*
548 	 * If we failed to find the CRTC(s) which this encoder is
549 	 * supposed to be connected to, it's because the CRTC has
550 	 * not been registered yet.  Defer probing, and hope that
551 	 * the required CRTC is added later.
552 	 */
553 	if (encoder->possible_crtcs == 0)
554 		return -EPROBE_DEFER;
555 
556 	drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs);
557 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
558 
559 	hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
560 
561 	drm_connector_helper_add(&hdmi->connector,
562 				 &rk3066_hdmi_connector_helper_funcs);
563 	drm_connector_init_with_ddc(drm, &hdmi->connector,
564 				    &rk3066_hdmi_connector_funcs,
565 				    DRM_MODE_CONNECTOR_HDMIA,
566 				    hdmi->ddc);
567 
568 	drm_connector_attach_encoder(&hdmi->connector, encoder);
569 
570 	return 0;
571 }
572 
573 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id)
574 {
575 	struct rk3066_hdmi *hdmi = dev_id;
576 	irqreturn_t ret = IRQ_NONE;
577 	u8 interrupt;
578 
579 	if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A)
580 		hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B);
581 
582 	interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1);
583 	if (interrupt)
584 		hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
585 
586 	if (interrupt & HDMI_INTR_EDID_MASK) {
587 		hdmi->i2c->stat = interrupt;
588 		complete(&hdmi->i2c->cmpltn);
589 	}
590 
591 	if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS))
592 		ret = IRQ_WAKE_THREAD;
593 
594 	return ret;
595 }
596 
597 static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id)
598 {
599 	struct rk3066_hdmi *hdmi = dev_id;
600 
601 	drm_helper_hpd_irq_event(hdmi->connector.dev);
602 
603 	return IRQ_HANDLED;
604 }
605 
606 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
607 {
608 	int length = msgs->len;
609 	u8 *buf = msgs->buf;
610 	int ret;
611 
612 	ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10);
613 	if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR)
614 		return -EAGAIN;
615 
616 	while (length--)
617 		*buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR);
618 
619 	return 0;
620 }
621 
622 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
623 {
624 	/*
625 	 * The DDC module only supports read EDID message, so
626 	 * we assume that each word write to this i2c adapter
627 	 * should be the offset of the EDID word address.
628 	 */
629 	if (msgs->len != 1 ||
630 	    (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
631 		return -EINVAL;
632 
633 	reinit_completion(&hdmi->i2c->cmpltn);
634 
635 	if (msgs->addr == DDC_SEGMENT_ADDR)
636 		hdmi->i2c->segment_addr = msgs->buf[0];
637 	if (msgs->addr == DDC_ADDR)
638 		hdmi->i2c->ddc_addr = msgs->buf[0];
639 
640 	/* Set edid fifo first address. */
641 	hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
642 
643 	/* Set edid word address 0x00/0x80. */
644 	hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
645 
646 	/* Set edid segment pointer. */
647 	hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
648 
649 	return 0;
650 }
651 
652 static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap,
653 				struct i2c_msg *msgs, int num)
654 {
655 	struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap);
656 	struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
657 	int i, ret = 0;
658 
659 	mutex_lock(&i2c->i2c_lock);
660 
661 	rk3066_hdmi_i2c_init(hdmi);
662 
663 	/* Unmute HDMI EDID interrupt. */
664 	hdmi_modb(hdmi, HDMI_INTR_MASK1,
665 		  HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK);
666 	i2c->stat = 0;
667 
668 	for (i = 0; i < num; i++) {
669 		DRM_DEV_DEBUG(hdmi->dev,
670 			      "xfer: num: %d/%d, len: %d, flags: %#x\n",
671 			      i + 1, num, msgs[i].len, msgs[i].flags);
672 
673 		if (msgs[i].flags & I2C_M_RD)
674 			ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
675 		else
676 			ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]);
677 
678 		if (ret < 0)
679 			break;
680 	}
681 
682 	if (!ret)
683 		ret = num;
684 
685 	/* Mute HDMI EDID interrupt. */
686 	hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
687 
688 	mutex_unlock(&i2c->i2c_lock);
689 
690 	return ret;
691 }
692 
693 static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter)
694 {
695 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
696 }
697 
698 static const struct i2c_algorithm rk3066_hdmi_algorithm = {
699 	.master_xfer   = rk3066_hdmi_i2c_xfer,
700 	.functionality = rk3066_hdmi_i2c_func,
701 };
702 
703 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
704 {
705 	struct i2c_adapter *adap;
706 	struct rk3066_hdmi_i2c *i2c;
707 	int ret;
708 
709 	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
710 	if (!i2c)
711 		return ERR_PTR(-ENOMEM);
712 
713 	mutex_init(&i2c->i2c_lock);
714 	init_completion(&i2c->cmpltn);
715 
716 	adap = &i2c->adap;
717 	adap->class = I2C_CLASS_DDC;
718 	adap->owner = THIS_MODULE;
719 	adap->dev.parent = hdmi->dev;
720 	adap->dev.of_node = hdmi->dev->of_node;
721 	adap->algo = &rk3066_hdmi_algorithm;
722 	strlcpy(adap->name, "RK3066 HDMI", sizeof(adap->name));
723 	i2c_set_adapdata(adap, hdmi);
724 
725 	ret = i2c_add_adapter(adap);
726 	if (ret) {
727 		DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n",
728 			      adap->name);
729 		devm_kfree(hdmi->dev, i2c);
730 		return ERR_PTR(ret);
731 	}
732 
733 	hdmi->i2c = i2c;
734 
735 	DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
736 
737 	return adap;
738 }
739 
740 static int rk3066_hdmi_bind(struct device *dev, struct device *master,
741 			    void *data)
742 {
743 	struct platform_device *pdev = to_platform_device(dev);
744 	struct drm_device *drm = data;
745 	struct rk3066_hdmi *hdmi;
746 	int irq;
747 	int ret;
748 
749 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
750 	if (!hdmi)
751 		return -ENOMEM;
752 
753 	hdmi->dev = dev;
754 	hdmi->drm_dev = drm;
755 	hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
756 	if (IS_ERR(hdmi->regs))
757 		return PTR_ERR(hdmi->regs);
758 
759 	irq = platform_get_irq(pdev, 0);
760 	if (irq < 0)
761 		return irq;
762 
763 	hdmi->hclk = devm_clk_get(dev, "hclk");
764 	if (IS_ERR(hdmi->hclk)) {
765 		DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
766 		return PTR_ERR(hdmi->hclk);
767 	}
768 
769 	ret = clk_prepare_enable(hdmi->hclk);
770 	if (ret) {
771 		DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
772 		return ret;
773 	}
774 
775 	hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
776 							   "rockchip,grf");
777 	if (IS_ERR(hdmi->grf_regmap)) {
778 		DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n");
779 		ret = PTR_ERR(hdmi->grf_regmap);
780 		goto err_disable_hclk;
781 	}
782 
783 	/* internal hclk = hdmi_hclk / 25 */
784 	hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25);
785 
786 	hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi);
787 	if (IS_ERR(hdmi->ddc)) {
788 		ret = PTR_ERR(hdmi->ddc);
789 		hdmi->ddc = NULL;
790 		goto err_disable_hclk;
791 	}
792 
793 	rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
794 	usleep_range(999, 1000);
795 	hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
796 	hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0);
797 	hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0);
798 	hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0);
799 	rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
800 
801 	ret = rk3066_hdmi_register(drm, hdmi);
802 	if (ret)
803 		goto err_disable_i2c;
804 
805 	dev_set_drvdata(dev, hdmi);
806 
807 	ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq,
808 					rk3066_hdmi_irq, IRQF_SHARED,
809 					dev_name(dev), hdmi);
810 	if (ret) {
811 		DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
812 		goto err_cleanup_hdmi;
813 	}
814 
815 	return 0;
816 
817 err_cleanup_hdmi:
818 	hdmi->connector.funcs->destroy(&hdmi->connector);
819 	hdmi->encoder.funcs->destroy(&hdmi->encoder);
820 err_disable_i2c:
821 	i2c_put_adapter(hdmi->ddc);
822 err_disable_hclk:
823 	clk_disable_unprepare(hdmi->hclk);
824 
825 	return ret;
826 }
827 
828 static void rk3066_hdmi_unbind(struct device *dev, struct device *master,
829 			       void *data)
830 {
831 	struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
832 
833 	hdmi->connector.funcs->destroy(&hdmi->connector);
834 	hdmi->encoder.funcs->destroy(&hdmi->encoder);
835 
836 	i2c_put_adapter(hdmi->ddc);
837 	clk_disable_unprepare(hdmi->hclk);
838 }
839 
840 static const struct component_ops rk3066_hdmi_ops = {
841 	.bind   = rk3066_hdmi_bind,
842 	.unbind = rk3066_hdmi_unbind,
843 };
844 
845 static int rk3066_hdmi_probe(struct platform_device *pdev)
846 {
847 	return component_add(&pdev->dev, &rk3066_hdmi_ops);
848 }
849 
850 static int rk3066_hdmi_remove(struct platform_device *pdev)
851 {
852 	component_del(&pdev->dev, &rk3066_hdmi_ops);
853 
854 	return 0;
855 }
856 
857 static const struct of_device_id rk3066_hdmi_dt_ids[] = {
858 	{ .compatible = "rockchip,rk3066-hdmi" },
859 	{ /* sentinel */ },
860 };
861 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids);
862 
863 struct platform_driver rk3066_hdmi_driver = {
864 	.probe  = rk3066_hdmi_probe,
865 	.remove = rk3066_hdmi_remove,
866 	.driver = {
867 		.name = "rockchip-rk3066-hdmi",
868 		.of_match_table = rk3066_hdmi_dt_ids,
869 	},
870 };
871