1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Zheng Yang <zhengyang@rock-chips.com> 5 * Yakir Yang <ykk@rock-chips.com> 6 */ 7 8 #include <linux/irq.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 18 #include <drm/drm_of.h> 19 #include <drm/drmP.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_edid.h> 22 #include <drm/drm_probe_helper.h> 23 24 #include "rockchip_drm_drv.h" 25 #include "rockchip_drm_vop.h" 26 27 #include "inno_hdmi.h" 28 29 #define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x) 30 31 struct hdmi_data_info { 32 int vic; 33 bool sink_is_hdmi; 34 bool sink_has_audio; 35 unsigned int enc_in_format; 36 unsigned int enc_out_format; 37 unsigned int colorimetry; 38 }; 39 40 struct inno_hdmi_i2c { 41 struct i2c_adapter adap; 42 43 u8 ddc_addr; 44 u8 segment_addr; 45 46 struct mutex lock; 47 struct completion cmp; 48 }; 49 50 struct inno_hdmi { 51 struct device *dev; 52 struct drm_device *drm_dev; 53 54 int irq; 55 struct clk *pclk; 56 void __iomem *regs; 57 58 struct drm_connector connector; 59 struct drm_encoder encoder; 60 61 struct inno_hdmi_i2c *i2c; 62 struct i2c_adapter *ddc; 63 64 unsigned int tmds_rate; 65 66 struct hdmi_data_info hdmi_data; 67 struct drm_display_mode previous_mode; 68 }; 69 70 enum { 71 CSC_ITU601_16_235_TO_RGB_0_255_8BIT, 72 CSC_ITU601_0_255_TO_RGB_0_255_8BIT, 73 CSC_ITU709_16_235_TO_RGB_0_255_8BIT, 74 CSC_RGB_0_255_TO_ITU601_16_235_8BIT, 75 CSC_RGB_0_255_TO_ITU709_16_235_8BIT, 76 CSC_RGB_0_255_TO_RGB_16_235_8BIT, 77 }; 78 79 static const char coeff_csc[][24] = { 80 /* 81 * YUV2RGB:601 SD mode(Y[16:235], UV[16:240], RGB[0:255]): 82 * R = 1.164*Y + 1.596*V - 204 83 * G = 1.164*Y - 0.391*U - 0.813*V + 154 84 * B = 1.164*Y + 2.018*U - 258 85 */ 86 { 87 0x04, 0xa7, 0x00, 0x00, 0x06, 0x62, 0x02, 0xcc, 88 0x04, 0xa7, 0x11, 0x90, 0x13, 0x40, 0x00, 0x9a, 89 0x04, 0xa7, 0x08, 0x12, 0x00, 0x00, 0x03, 0x02 90 }, 91 /* 92 * YUV2RGB:601 SD mode(YUV[0:255],RGB[0:255]): 93 * R = Y + 1.402*V - 248 94 * G = Y - 0.344*U - 0.714*V + 135 95 * B = Y + 1.772*U - 227 96 */ 97 { 98 0x04, 0x00, 0x00, 0x00, 0x05, 0x9b, 0x02, 0xf8, 99 0x04, 0x00, 0x11, 0x60, 0x12, 0xdb, 0x00, 0x87, 100 0x04, 0x00, 0x07, 0x16, 0x00, 0x00, 0x02, 0xe3 101 }, 102 /* 103 * YUV2RGB:709 HD mode(Y[16:235],UV[16:240],RGB[0:255]): 104 * R = 1.164*Y + 1.793*V - 248 105 * G = 1.164*Y - 0.213*U - 0.534*V + 77 106 * B = 1.164*Y + 2.115*U - 289 107 */ 108 { 109 0x04, 0xa7, 0x00, 0x00, 0x07, 0x2c, 0x02, 0xf8, 110 0x04, 0xa7, 0x10, 0xda, 0x12, 0x22, 0x00, 0x4d, 111 0x04, 0xa7, 0x08, 0x74, 0x00, 0x00, 0x03, 0x21 112 }, 113 114 /* 115 * RGB2YUV:601 SD mode: 116 * Cb = -0.291G - 0.148R + 0.439B + 128 117 * Y = 0.504G + 0.257R + 0.098B + 16 118 * Cr = -0.368G + 0.439R - 0.071B + 128 119 */ 120 { 121 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80, 122 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e, 123 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80 124 }, 125 /* 126 * RGB2YUV:709 HD mode: 127 * Cb = - 0.338G - 0.101R + 0.439B + 128 128 * Y = 0.614G + 0.183R + 0.062B + 16 129 * Cr = - 0.399G + 0.439R - 0.040B + 128 130 */ 131 { 132 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80, 133 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10, 134 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80 135 }, 136 /* 137 * RGB[0:255]2RGB[16:235]: 138 * R' = R x (235-16)/255 + 16; 139 * G' = G x (235-16)/255 + 16; 140 * B' = B x (235-16)/255 + 16; 141 */ 142 { 143 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10, 144 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 145 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10 146 }, 147 }; 148 149 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) 150 { 151 return readl_relaxed(hdmi->regs + (offset) * 0x04); 152 } 153 154 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) 155 { 156 writel_relaxed(val, hdmi->regs + (offset) * 0x04); 157 } 158 159 static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, 160 u32 msk, u32 val) 161 { 162 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 163 164 temp |= val & msk; 165 hdmi_writeb(hdmi, offset, temp); 166 } 167 168 static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi) 169 { 170 int ddc_bus_freq; 171 172 ddc_bus_freq = (hdmi->tmds_rate >> 2) / HDMI_SCL_RATE; 173 174 hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 175 hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 176 177 /* Clear the EDID interrupt flag and mute the interrupt */ 178 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); 179 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 180 } 181 182 static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable) 183 { 184 if (enable) 185 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON); 186 else 187 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF); 188 } 189 190 static void inno_hdmi_set_pwr_mode(struct inno_hdmi *hdmi, int mode) 191 { 192 switch (mode) { 193 case NORMAL: 194 inno_hdmi_sys_power(hdmi, false); 195 196 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x6f); 197 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0xbb); 198 199 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); 200 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14); 201 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10); 202 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f); 203 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00); 204 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01); 205 206 inno_hdmi_sys_power(hdmi, true); 207 break; 208 209 case LOWER_PWR: 210 inno_hdmi_sys_power(hdmi, false); 211 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00); 212 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00); 213 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00); 214 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); 215 216 break; 217 218 default: 219 DRM_DEV_ERROR(hdmi->dev, "Unknown power mode %d\n", mode); 220 } 221 } 222 223 static void inno_hdmi_reset(struct inno_hdmi *hdmi) 224 { 225 u32 val; 226 u32 msk; 227 228 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL); 229 udelay(100); 230 231 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG); 232 udelay(100); 233 234 msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL; 235 val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH; 236 hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val); 237 238 inno_hdmi_set_pwr_mode(hdmi, NORMAL); 239 } 240 241 static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi, int setup_rc, 242 union hdmi_infoframe *frame, u32 frame_index, 243 u32 mask, u32 disable, u32 enable) 244 { 245 if (mask) 246 hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, disable); 247 248 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, frame_index); 249 250 if (setup_rc >= 0) { 251 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE]; 252 ssize_t rc, i; 253 254 rc = hdmi_infoframe_pack(frame, packed_frame, 255 sizeof(packed_frame)); 256 if (rc < 0) 257 return rc; 258 259 for (i = 0; i < rc; i++) 260 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, 261 packed_frame[i]); 262 263 if (mask) 264 hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, enable); 265 } 266 267 return setup_rc; 268 } 269 270 static int inno_hdmi_config_video_vsi(struct inno_hdmi *hdmi, 271 struct drm_display_mode *mode) 272 { 273 union hdmi_infoframe frame; 274 int rc; 275 276 rc = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 277 &hdmi->connector, 278 mode); 279 280 return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_VSI, 281 m_PACKET_VSI_EN, v_PACKET_VSI_EN(0), v_PACKET_VSI_EN(1)); 282 } 283 284 static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi, 285 struct drm_display_mode *mode) 286 { 287 union hdmi_infoframe frame; 288 int rc; 289 290 rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 291 &hdmi->connector, 292 mode); 293 294 if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444) 295 frame.avi.colorspace = HDMI_COLORSPACE_YUV444; 296 else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422) 297 frame.avi.colorspace = HDMI_COLORSPACE_YUV422; 298 else 299 frame.avi.colorspace = HDMI_COLORSPACE_RGB; 300 301 return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_AVI, 0, 0, 0); 302 } 303 304 static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi) 305 { 306 struct hdmi_data_info *data = &hdmi->hdmi_data; 307 int c0_c2_change = 0; 308 int csc_enable = 0; 309 int csc_mode = 0; 310 int auto_csc = 0; 311 int value; 312 int i; 313 314 /* Input video mode is SDR RGB24bit, data enable signal from external */ 315 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL | 316 v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444)); 317 318 /* Input color hardcode to RGB, and output color hardcode to RGB888 */ 319 value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) | 320 v_VIDEO_OUTPUT_COLOR(0) | 321 v_VIDEO_INPUT_CSP(0); 322 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value); 323 324 if (data->enc_in_format == data->enc_out_format) { 325 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) || 326 (data->enc_in_format >= HDMI_COLORSPACE_YUV444)) { 327 value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1); 328 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); 329 330 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, 331 m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP, 332 v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) | 333 v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE)); 334 return 0; 335 } 336 } 337 338 if (data->colorimetry == HDMI_COLORIMETRY_ITU_601) { 339 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) && 340 (data->enc_out_format == HDMI_COLORSPACE_YUV444)) { 341 csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT; 342 auto_csc = AUTO_CSC_DISABLE; 343 c0_c2_change = C0_C2_CHANGE_DISABLE; 344 csc_enable = v_CSC_ENABLE; 345 } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) && 346 (data->enc_out_format == HDMI_COLORSPACE_RGB)) { 347 csc_mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT; 348 auto_csc = AUTO_CSC_ENABLE; 349 c0_c2_change = C0_C2_CHANGE_DISABLE; 350 csc_enable = v_CSC_DISABLE; 351 } 352 } else { 353 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) && 354 (data->enc_out_format == HDMI_COLORSPACE_YUV444)) { 355 csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT; 356 auto_csc = AUTO_CSC_DISABLE; 357 c0_c2_change = C0_C2_CHANGE_DISABLE; 358 csc_enable = v_CSC_ENABLE; 359 } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) && 360 (data->enc_out_format == HDMI_COLORSPACE_RGB)) { 361 csc_mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT; 362 auto_csc = AUTO_CSC_ENABLE; 363 c0_c2_change = C0_C2_CHANGE_DISABLE; 364 csc_enable = v_CSC_DISABLE; 365 } 366 } 367 368 for (i = 0; i < 24; i++) 369 hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, 370 coeff_csc[csc_mode][i]); 371 372 value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1); 373 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); 374 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC | 375 m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) | 376 v_VIDEO_C0_C2_SWAP(c0_c2_change)); 377 378 return 0; 379 } 380 381 static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, 382 struct drm_display_mode *mode) 383 { 384 int value; 385 386 /* Set detail external video timing polarity and interlace mode */ 387 value = v_EXTERANL_VIDEO(1); 388 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 389 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0); 390 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 391 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0); 392 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 393 v_INETLACE(1) : v_INETLACE(0); 394 hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value); 395 396 /* Set detail external video timing */ 397 value = mode->htotal; 398 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF); 399 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF); 400 401 value = mode->htotal - mode->hdisplay; 402 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF); 403 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF); 404 405 value = mode->hsync_start - mode->hdisplay; 406 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF); 407 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF); 408 409 value = mode->hsync_end - mode->hsync_start; 410 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF); 411 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF); 412 413 value = mode->vtotal; 414 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF); 415 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF); 416 417 value = mode->vtotal - mode->vdisplay; 418 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF); 419 420 value = mode->vsync_start - mode->vdisplay; 421 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF); 422 423 value = mode->vsync_end - mode->vsync_start; 424 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF); 425 426 hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e); 427 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c); 428 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01); 429 430 return 0; 431 } 432 433 static int inno_hdmi_setup(struct inno_hdmi *hdmi, 434 struct drm_display_mode *mode) 435 { 436 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); 437 438 hdmi->hdmi_data.enc_in_format = HDMI_COLORSPACE_RGB; 439 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; 440 441 if ((hdmi->hdmi_data.vic == 6) || (hdmi->hdmi_data.vic == 7) || 442 (hdmi->hdmi_data.vic == 21) || (hdmi->hdmi_data.vic == 22) || 443 (hdmi->hdmi_data.vic == 2) || (hdmi->hdmi_data.vic == 3) || 444 (hdmi->hdmi_data.vic == 17) || (hdmi->hdmi_data.vic == 18)) 445 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; 446 else 447 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; 448 449 /* Mute video and audio output */ 450 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, 451 v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1)); 452 453 /* Set HDMI Mode */ 454 hdmi_writeb(hdmi, HDMI_HDCP_CTRL, 455 v_HDMI_DVI(hdmi->hdmi_data.sink_is_hdmi)); 456 457 inno_hdmi_config_video_timing(hdmi, mode); 458 459 inno_hdmi_config_video_csc(hdmi); 460 461 if (hdmi->hdmi_data.sink_is_hdmi) { 462 inno_hdmi_config_video_avi(hdmi, mode); 463 inno_hdmi_config_video_vsi(hdmi, mode); 464 } 465 466 /* 467 * When IP controller have configured to an accurate video 468 * timing, then the TMDS clock source would be switched to 469 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel 470 * clock rate, and reconfigure the DDC clock. 471 */ 472 hdmi->tmds_rate = mode->clock * 1000; 473 inno_hdmi_i2c_init(hdmi); 474 475 /* Unmute video and audio output */ 476 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, 477 v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0)); 478 479 return 0; 480 } 481 482 static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder, 483 struct drm_display_mode *mode, 484 struct drm_display_mode *adj_mode) 485 { 486 struct inno_hdmi *hdmi = to_inno_hdmi(encoder); 487 488 inno_hdmi_setup(hdmi, adj_mode); 489 490 /* Store the display mode for plugin/DPMS poweron events */ 491 memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); 492 } 493 494 static void inno_hdmi_encoder_enable(struct drm_encoder *encoder) 495 { 496 struct inno_hdmi *hdmi = to_inno_hdmi(encoder); 497 498 inno_hdmi_set_pwr_mode(hdmi, NORMAL); 499 } 500 501 static void inno_hdmi_encoder_disable(struct drm_encoder *encoder) 502 { 503 struct inno_hdmi *hdmi = to_inno_hdmi(encoder); 504 505 inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR); 506 } 507 508 static bool inno_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, 509 const struct drm_display_mode *mode, 510 struct drm_display_mode *adj_mode) 511 { 512 return true; 513 } 514 515 static int 516 inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 517 struct drm_crtc_state *crtc_state, 518 struct drm_connector_state *conn_state) 519 { 520 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 521 522 s->output_mode = ROCKCHIP_OUT_MODE_P888; 523 s->output_type = DRM_MODE_CONNECTOR_HDMIA; 524 525 return 0; 526 } 527 528 static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = { 529 .enable = inno_hdmi_encoder_enable, 530 .disable = inno_hdmi_encoder_disable, 531 .mode_fixup = inno_hdmi_encoder_mode_fixup, 532 .mode_set = inno_hdmi_encoder_mode_set, 533 .atomic_check = inno_hdmi_encoder_atomic_check, 534 }; 535 536 static struct drm_encoder_funcs inno_hdmi_encoder_funcs = { 537 .destroy = drm_encoder_cleanup, 538 }; 539 540 static enum drm_connector_status 541 inno_hdmi_connector_detect(struct drm_connector *connector, bool force) 542 { 543 struct inno_hdmi *hdmi = to_inno_hdmi(connector); 544 545 return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? 546 connector_status_connected : connector_status_disconnected; 547 } 548 549 static int inno_hdmi_connector_get_modes(struct drm_connector *connector) 550 { 551 struct inno_hdmi *hdmi = to_inno_hdmi(connector); 552 struct edid *edid; 553 int ret = 0; 554 555 if (!hdmi->ddc) 556 return 0; 557 558 edid = drm_get_edid(connector, hdmi->ddc); 559 if (edid) { 560 hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid); 561 hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid); 562 drm_connector_update_edid_property(connector, edid); 563 ret = drm_add_edid_modes(connector, edid); 564 kfree(edid); 565 } 566 567 return ret; 568 } 569 570 static enum drm_mode_status 571 inno_hdmi_connector_mode_valid(struct drm_connector *connector, 572 struct drm_display_mode *mode) 573 { 574 return MODE_OK; 575 } 576 577 static int 578 inno_hdmi_probe_single_connector_modes(struct drm_connector *connector, 579 uint32_t maxX, uint32_t maxY) 580 { 581 return drm_helper_probe_single_connector_modes(connector, 1920, 1080); 582 } 583 584 static void inno_hdmi_connector_destroy(struct drm_connector *connector) 585 { 586 drm_connector_unregister(connector); 587 drm_connector_cleanup(connector); 588 } 589 590 static const struct drm_connector_funcs inno_hdmi_connector_funcs = { 591 .fill_modes = inno_hdmi_probe_single_connector_modes, 592 .detect = inno_hdmi_connector_detect, 593 .destroy = inno_hdmi_connector_destroy, 594 .reset = drm_atomic_helper_connector_reset, 595 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 596 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 597 }; 598 599 static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = { 600 .get_modes = inno_hdmi_connector_get_modes, 601 .mode_valid = inno_hdmi_connector_mode_valid, 602 }; 603 604 static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) 605 { 606 struct drm_encoder *encoder = &hdmi->encoder; 607 struct device *dev = hdmi->dev; 608 609 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 610 611 /* 612 * If we failed to find the CRTC(s) which this encoder is 613 * supposed to be connected to, it's because the CRTC has 614 * not been registered yet. Defer probing, and hope that 615 * the required CRTC is added later. 616 */ 617 if (encoder->possible_crtcs == 0) 618 return -EPROBE_DEFER; 619 620 drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs); 621 drm_encoder_init(drm, encoder, &inno_hdmi_encoder_funcs, 622 DRM_MODE_ENCODER_TMDS, NULL); 623 624 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; 625 626 drm_connector_helper_add(&hdmi->connector, 627 &inno_hdmi_connector_helper_funcs); 628 drm_connector_init(drm, &hdmi->connector, &inno_hdmi_connector_funcs, 629 DRM_MODE_CONNECTOR_HDMIA); 630 631 drm_connector_attach_encoder(&hdmi->connector, encoder); 632 633 return 0; 634 } 635 636 static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi) 637 { 638 struct inno_hdmi_i2c *i2c = hdmi->i2c; 639 u8 stat; 640 641 stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1); 642 if (!(stat & m_INT_EDID_READY)) 643 return IRQ_NONE; 644 645 /* Clear HDMI EDID interrupt flag */ 646 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 647 648 complete(&i2c->cmp); 649 650 return IRQ_HANDLED; 651 } 652 653 static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id) 654 { 655 struct inno_hdmi *hdmi = dev_id; 656 irqreturn_t ret = IRQ_NONE; 657 u8 interrupt; 658 659 if (hdmi->i2c) 660 ret = inno_hdmi_i2c_irq(hdmi); 661 662 interrupt = hdmi_readb(hdmi, HDMI_STATUS); 663 if (interrupt & m_INT_HOTPLUG) { 664 hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG); 665 ret = IRQ_WAKE_THREAD; 666 } 667 668 return ret; 669 } 670 671 static irqreturn_t inno_hdmi_irq(int irq, void *dev_id) 672 { 673 struct inno_hdmi *hdmi = dev_id; 674 675 drm_helper_hpd_irq_event(hdmi->connector.dev); 676 677 return IRQ_HANDLED; 678 } 679 680 static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs) 681 { 682 int length = msgs->len; 683 u8 *buf = msgs->buf; 684 int ret; 685 686 ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10); 687 if (!ret) 688 return -EAGAIN; 689 690 while (length--) 691 *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR); 692 693 return 0; 694 } 695 696 static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs) 697 { 698 /* 699 * The DDC module only support read EDID message, so 700 * we assume that each word write to this i2c adapter 701 * should be the offset of EDID word address. 702 */ 703 if ((msgs->len != 1) || 704 ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR))) 705 return -EINVAL; 706 707 reinit_completion(&hdmi->i2c->cmp); 708 709 if (msgs->addr == DDC_SEGMENT_ADDR) 710 hdmi->i2c->segment_addr = msgs->buf[0]; 711 if (msgs->addr == DDC_ADDR) 712 hdmi->i2c->ddc_addr = msgs->buf[0]; 713 714 /* Set edid fifo first addr */ 715 hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00); 716 717 /* Set edid word address 0x00/0x80 */ 718 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 719 720 /* Set edid segment pointer */ 721 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 722 723 return 0; 724 } 725 726 static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap, 727 struct i2c_msg *msgs, int num) 728 { 729 struct inno_hdmi *hdmi = i2c_get_adapdata(adap); 730 struct inno_hdmi_i2c *i2c = hdmi->i2c; 731 int i, ret = 0; 732 733 mutex_lock(&i2c->lock); 734 735 /* Clear the EDID interrupt flag and unmute the interrupt */ 736 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY); 737 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 738 739 for (i = 0; i < num; i++) { 740 DRM_DEV_DEBUG(hdmi->dev, 741 "xfer: num: %d/%d, len: %d, flags: %#x\n", 742 i + 1, num, msgs[i].len, msgs[i].flags); 743 744 if (msgs[i].flags & I2C_M_RD) 745 ret = inno_hdmi_i2c_read(hdmi, &msgs[i]); 746 else 747 ret = inno_hdmi_i2c_write(hdmi, &msgs[i]); 748 749 if (ret < 0) 750 break; 751 } 752 753 if (!ret) 754 ret = num; 755 756 /* Mute HDMI EDID interrupt */ 757 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); 758 759 mutex_unlock(&i2c->lock); 760 761 return ret; 762 } 763 764 static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter) 765 { 766 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 767 } 768 769 static const struct i2c_algorithm inno_hdmi_algorithm = { 770 .master_xfer = inno_hdmi_i2c_xfer, 771 .functionality = inno_hdmi_i2c_func, 772 }; 773 774 static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi) 775 { 776 struct i2c_adapter *adap; 777 struct inno_hdmi_i2c *i2c; 778 int ret; 779 780 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 781 if (!i2c) 782 return ERR_PTR(-ENOMEM); 783 784 mutex_init(&i2c->lock); 785 init_completion(&i2c->cmp); 786 787 adap = &i2c->adap; 788 adap->class = I2C_CLASS_DDC; 789 adap->owner = THIS_MODULE; 790 adap->dev.parent = hdmi->dev; 791 adap->dev.of_node = hdmi->dev->of_node; 792 adap->algo = &inno_hdmi_algorithm; 793 strlcpy(adap->name, "Inno HDMI", sizeof(adap->name)); 794 i2c_set_adapdata(adap, hdmi); 795 796 ret = i2c_add_adapter(adap); 797 if (ret) { 798 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 799 devm_kfree(hdmi->dev, i2c); 800 return ERR_PTR(ret); 801 } 802 803 hdmi->i2c = i2c; 804 805 DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 806 807 return adap; 808 } 809 810 static int inno_hdmi_bind(struct device *dev, struct device *master, 811 void *data) 812 { 813 struct platform_device *pdev = to_platform_device(dev); 814 struct drm_device *drm = data; 815 struct inno_hdmi *hdmi; 816 struct resource *iores; 817 int irq; 818 int ret; 819 820 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 821 if (!hdmi) 822 return -ENOMEM; 823 824 hdmi->dev = dev; 825 hdmi->drm_dev = drm; 826 827 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 828 hdmi->regs = devm_ioremap_resource(dev, iores); 829 if (IS_ERR(hdmi->regs)) 830 return PTR_ERR(hdmi->regs); 831 832 hdmi->pclk = devm_clk_get(hdmi->dev, "pclk"); 833 if (IS_ERR(hdmi->pclk)) { 834 DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n"); 835 return PTR_ERR(hdmi->pclk); 836 } 837 838 ret = clk_prepare_enable(hdmi->pclk); 839 if (ret) { 840 DRM_DEV_ERROR(hdmi->dev, 841 "Cannot enable HDMI pclk clock: %d\n", ret); 842 return ret; 843 } 844 845 irq = platform_get_irq(pdev, 0); 846 if (irq < 0) { 847 ret = irq; 848 goto err_disable_clk; 849 } 850 851 inno_hdmi_reset(hdmi); 852 853 hdmi->ddc = inno_hdmi_i2c_adapter(hdmi); 854 if (IS_ERR(hdmi->ddc)) { 855 ret = PTR_ERR(hdmi->ddc); 856 hdmi->ddc = NULL; 857 goto err_disable_clk; 858 } 859 860 /* 861 * When IP controller haven't configured to an accurate video 862 * timing, then the TMDS clock source would be switched to 863 * PCLK_HDMI, so we need to init the TMDS rate to PCLK rate, 864 * and reconfigure the DDC clock. 865 */ 866 hdmi->tmds_rate = clk_get_rate(hdmi->pclk); 867 inno_hdmi_i2c_init(hdmi); 868 869 ret = inno_hdmi_register(drm, hdmi); 870 if (ret) 871 goto err_put_adapter; 872 873 dev_set_drvdata(dev, hdmi); 874 875 /* Unmute hotplug interrupt */ 876 hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1)); 877 878 ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq, 879 inno_hdmi_irq, IRQF_SHARED, 880 dev_name(dev), hdmi); 881 if (ret < 0) 882 goto err_cleanup_hdmi; 883 884 return 0; 885 err_cleanup_hdmi: 886 hdmi->connector.funcs->destroy(&hdmi->connector); 887 hdmi->encoder.funcs->destroy(&hdmi->encoder); 888 err_put_adapter: 889 i2c_put_adapter(hdmi->ddc); 890 err_disable_clk: 891 clk_disable_unprepare(hdmi->pclk); 892 return ret; 893 } 894 895 static void inno_hdmi_unbind(struct device *dev, struct device *master, 896 void *data) 897 { 898 struct inno_hdmi *hdmi = dev_get_drvdata(dev); 899 900 hdmi->connector.funcs->destroy(&hdmi->connector); 901 hdmi->encoder.funcs->destroy(&hdmi->encoder); 902 903 i2c_put_adapter(hdmi->ddc); 904 clk_disable_unprepare(hdmi->pclk); 905 } 906 907 static const struct component_ops inno_hdmi_ops = { 908 .bind = inno_hdmi_bind, 909 .unbind = inno_hdmi_unbind, 910 }; 911 912 static int inno_hdmi_probe(struct platform_device *pdev) 913 { 914 return component_add(&pdev->dev, &inno_hdmi_ops); 915 } 916 917 static int inno_hdmi_remove(struct platform_device *pdev) 918 { 919 component_del(&pdev->dev, &inno_hdmi_ops); 920 921 return 0; 922 } 923 924 static const struct of_device_id inno_hdmi_dt_ids[] = { 925 { .compatible = "rockchip,rk3036-inno-hdmi", 926 }, 927 {}, 928 }; 929 MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids); 930 931 struct platform_driver inno_hdmi_driver = { 932 .probe = inno_hdmi_probe, 933 .remove = inno_hdmi_remove, 934 .driver = { 935 .name = "innohdmi-rockchip", 936 .of_match_table = inno_hdmi_dt_ids, 937 }, 938 }; 939