1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/math64.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/phy/phy.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/bridge/dw_mipi_dsi.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #include "rockchip_drm_drv.h" 27 #include "rockchip_drm_vop.h" 28 29 #define DSI_PHY_RSTZ 0xa0 30 #define PHY_DISFORCEPLL 0 31 #define PHY_ENFORCEPLL BIT(3) 32 #define PHY_DISABLECLK 0 33 #define PHY_ENABLECLK BIT(2) 34 #define PHY_RSTZ 0 35 #define PHY_UNRSTZ BIT(1) 36 #define PHY_SHUTDOWNZ 0 37 #define PHY_UNSHUTDOWNZ BIT(0) 38 39 #define DSI_PHY_IF_CFG 0xa4 40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 41 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 42 43 #define DSI_PHY_STATUS 0xb0 44 #define LOCK BIT(0) 45 #define STOP_STATE_CLK_LANE BIT(2) 46 47 #define DSI_PHY_TST_CTRL0 0xb4 48 #define PHY_TESTCLK BIT(1) 49 #define PHY_UNTESTCLK 0 50 #define PHY_TESTCLR BIT(0) 51 #define PHY_UNTESTCLR 0 52 53 #define DSI_PHY_TST_CTRL1 0xb8 54 #define PHY_TESTEN BIT(16) 55 #define PHY_UNTESTEN 0 56 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 57 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 58 59 #define DSI_INT_ST0 0xbc 60 #define DSI_INT_ST1 0xc0 61 #define DSI_INT_MSK0 0xc4 62 #define DSI_INT_MSK1 0xc8 63 64 #define PHY_STATUS_TIMEOUT_US 10000 65 #define CMD_PKT_STATUS_TIMEOUT_US 20000 66 67 #define BYPASS_VCO_RANGE BIT(7) 68 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 69 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 70 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 71 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 72 #define REF_BIAS_CUR_SEL BIT(0) 73 74 #define CP_CURRENT_3UA 0x1 75 #define CP_CURRENT_4_5UA 0x2 76 #define CP_CURRENT_7_5UA 0x6 77 #define CP_CURRENT_6UA 0x9 78 #define CP_CURRENT_12UA 0xb 79 #define CP_CURRENT_SEL(val) ((val) & 0xf) 80 #define CP_PROGRAM_EN BIT(7) 81 82 #define LPF_RESISTORS_15_5KOHM 0x1 83 #define LPF_RESISTORS_13KOHM 0x2 84 #define LPF_RESISTORS_11_5KOHM 0x4 85 #define LPF_RESISTORS_10_5KOHM 0x8 86 #define LPF_RESISTORS_8KOHM 0x10 87 #define LPF_PROGRAM_EN BIT(6) 88 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 89 90 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 91 92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 93 #define LOW_PROGRAM_EN 0 94 #define HIGH_PROGRAM_EN BIT(7) 95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 97 #define PLL_LOOP_DIV_EN BIT(5) 98 #define PLL_INPUT_DIV_EN BIT(4) 99 100 #define POWER_CONTROL BIT(6) 101 #define INTERNAL_REG_CURRENT BIT(3) 102 #define BIAS_BLOCK_ON BIT(2) 103 #define BANDGAP_ON BIT(0) 104 105 #define TER_RESISTOR_HIGH BIT(7) 106 #define TER_RESISTOR_LOW 0 107 #define LEVEL_SHIFTERS_ON BIT(6) 108 #define TER_CAL_DONE BIT(5) 109 #define SETRD_MAX (0x7 << 2) 110 #define POWER_MANAGE BIT(1) 111 #define TER_RESISTORS_ON BIT(0) 112 113 #define BIASEXTR_SEL(val) ((val) & 0x7) 114 #define BANDGAP_SEL(val) ((val) & 0x7) 115 #define TLP_PROGRAM_EN BIT(7) 116 #define THS_PRE_PROGRAM_EN BIT(7) 117 #define THS_ZERO_PROGRAM_EN BIT(6) 118 119 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 120 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 121 #define PLL_LPF_AND_CP_CONTROL 0x12 122 #define PLL_INPUT_DIVIDER_RATIO 0x17 123 #define PLL_LOOP_DIVIDER_RATIO 0x18 124 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 125 #define BANDGAP_AND_BIAS_CONTROL 0x20 126 #define TERMINATION_RESISTER_CONTROL 0x21 127 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 128 #define HS_RX_CONTROL_OF_LANE_CLK 0x34 129 #define HS_RX_CONTROL_OF_LANE_0 0x44 130 #define HS_RX_CONTROL_OF_LANE_1 0x54 131 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 132 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 133 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 134 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 135 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 136 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 137 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 138 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 139 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 140 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 141 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 142 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 143 #define HS_RX_CONTROL_OF_LANE_2 0x84 144 #define HS_RX_CONTROL_OF_LANE_3 0x94 145 146 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 147 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 148 149 #define PX30_GRF_PD_VO_CON1 0x0438 150 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 151 #define PX30_DSI_FORCERXMODE BIT(6) 152 #define PX30_DSI_TURNDISABLE BIT(5) 153 #define PX30_DSI_LCDC_SEL BIT(0) 154 155 #define RK3288_GRF_SOC_CON6 0x025c 156 #define RK3288_DSI0_LCDC_SEL BIT(6) 157 #define RK3288_DSI1_LCDC_SEL BIT(9) 158 159 #define RK3399_GRF_SOC_CON20 0x6250 160 #define RK3399_DSI0_LCDC_SEL BIT(0) 161 #define RK3399_DSI1_LCDC_SEL BIT(4) 162 163 #define RK3399_GRF_SOC_CON22 0x6258 164 #define RK3399_DSI0_TURNREQUEST (0xf << 12) 165 #define RK3399_DSI0_TURNDISABLE (0xf << 8) 166 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 167 #define RK3399_DSI0_FORCERXMODE (0xf << 0) 168 169 #define RK3399_GRF_SOC_CON23 0x625c 170 #define RK3399_DSI1_TURNDISABLE (0xf << 12) 171 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 172 #define RK3399_DSI1_FORCERXMODE (0xf << 4) 173 #define RK3399_DSI1_ENABLE (0xf << 0) 174 175 #define RK3399_GRF_SOC_CON24 0x6260 176 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 177 #define RK3399_TXRX_ENABLECLK BIT(6) 178 #define RK3399_TXRX_BASEDIR BIT(5) 179 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 180 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 181 182 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 183 184 #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) 185 186 enum { 187 DW_DSI_USAGE_IDLE, 188 DW_DSI_USAGE_DSI, 189 DW_DSI_USAGE_PHY, 190 }; 191 192 enum { 193 BANDGAP_97_07, 194 BANDGAP_98_05, 195 BANDGAP_99_02, 196 BANDGAP_100_00, 197 BANDGAP_93_17, 198 BANDGAP_94_15, 199 BANDGAP_95_12, 200 BANDGAP_96_10, 201 }; 202 203 enum { 204 BIASEXTR_87_1, 205 BIASEXTR_91_5, 206 BIASEXTR_95_9, 207 BIASEXTR_100, 208 BIASEXTR_105_94, 209 BIASEXTR_111_88, 210 BIASEXTR_118_8, 211 BIASEXTR_127_7, 212 }; 213 214 struct rockchip_dw_dsi_chip_data { 215 u32 reg; 216 217 u32 lcdsel_grf_reg; 218 u32 lcdsel_big; 219 u32 lcdsel_lit; 220 221 u32 enable_grf_reg; 222 u32 enable; 223 224 u32 lanecfg1_grf_reg; 225 u32 lanecfg1; 226 u32 lanecfg2_grf_reg; 227 u32 lanecfg2; 228 229 int (*dphy_rx_init)(struct phy *phy); 230 int (*dphy_rx_power_on)(struct phy *phy); 231 int (*dphy_rx_power_off)(struct phy *phy); 232 233 unsigned int flags; 234 unsigned int max_data_lanes; 235 }; 236 237 struct dw_mipi_dsi_rockchip { 238 struct device *dev; 239 struct drm_encoder encoder; 240 void __iomem *base; 241 242 struct regmap *grf_regmap; 243 struct clk *pclk; 244 struct clk *pllref_clk; 245 struct clk *grf_clk; 246 struct clk *phy_cfg_clk; 247 248 /* dual-channel */ 249 bool is_slave; 250 struct dw_mipi_dsi_rockchip *slave; 251 252 /* optional external dphy */ 253 struct phy *phy; 254 union phy_configure_opts phy_opts; 255 256 /* being a phy for other mipi hosts */ 257 unsigned int usage_mode; 258 struct mutex usage_mutex; 259 struct phy *dphy; 260 struct phy_configure_opts_mipi_dphy dphy_config; 261 262 unsigned int lane_mbps; /* per lane */ 263 u16 input_div; 264 u16 feedback_div; 265 u32 format; 266 267 struct dw_mipi_dsi *dmd; 268 const struct rockchip_dw_dsi_chip_data *cdata; 269 struct dw_mipi_dsi_plat_data pdata; 270 271 bool dsi_bound; 272 }; 273 274 struct dphy_pll_parameter_map { 275 unsigned int max_mbps; 276 u8 hsfreqrange; 277 u8 icpctrl; 278 u8 lpfctrl; 279 }; 280 281 /* The table is based on 27MHz DPHY pll reference clock. */ 282 static const struct dphy_pll_parameter_map dppa_map[] = { 283 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 284 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 285 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 286 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 287 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 288 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 289 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 290 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 291 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 292 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 293 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 294 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 295 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 296 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 297 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 298 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 299 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 300 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 301 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 302 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 303 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 304 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 305 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 306 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 307 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 308 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 309 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 310 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 311 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 312 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 313 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 314 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 315 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 316 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 317 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 318 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 319 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 320 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 321 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 322 }; 323 324 static int max_mbps_to_parameter(unsigned int max_mbps) 325 { 326 int i; 327 328 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 329 if (dppa_map[i].max_mbps >= max_mbps) 330 return i; 331 332 return -EINVAL; 333 } 334 335 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 336 { 337 writel(val, dsi->base + reg); 338 } 339 340 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) 341 { 342 return readl(dsi->base + reg); 343 } 344 345 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg, 346 u32 mask, u32 val) 347 { 348 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 349 } 350 351 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 352 u8 test_code, 353 u8 test_data) 354 { 355 /* 356 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 357 * is latched internally as the current test code. Test data is 358 * programmed internally by rising edge on TESTCLK. 359 */ 360 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 361 362 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 363 PHY_TESTDIN(test_code)); 364 365 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 366 367 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 368 PHY_TESTDIN(test_data)); 369 370 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 371 } 372 373 /* 374 * ns2bc - Nanoseconds to byte clock cycles 375 */ 376 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 377 { 378 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 379 } 380 381 /* 382 * ns2ui - Nanoseconds to UI time periods 383 */ 384 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 385 { 386 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 387 } 388 389 static int dw_mipi_dsi_phy_init(void *priv_data) 390 { 391 struct dw_mipi_dsi_rockchip *dsi = priv_data; 392 int ret, i, vco; 393 394 if (dsi->phy) 395 return 0; 396 397 /* 398 * Get vco from frequency(lane_mbps) 399 * vco frequency table 400 * 000 - between 80 and 200 MHz 401 * 001 - between 200 and 300 MHz 402 * 010 - between 300 and 500 MHz 403 * 011 - between 500 and 700 MHz 404 * 100 - between 700 and 900 MHz 405 * 101 - between 900 and 1100 MHz 406 * 110 - between 1100 and 1300 MHz 407 * 111 - between 1300 and 1500 MHz 408 */ 409 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 410 411 i = max_mbps_to_parameter(dsi->lane_mbps); 412 if (i < 0) { 413 DRM_DEV_ERROR(dsi->dev, 414 "failed to get parameter for %dmbps clock\n", 415 dsi->lane_mbps); 416 return i; 417 } 418 419 ret = clk_prepare_enable(dsi->phy_cfg_clk); 420 if (ret) { 421 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 422 return ret; 423 } 424 425 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 426 BYPASS_VCO_RANGE | 427 VCO_RANGE_CON_SEL(vco) | 428 VCO_IN_CAP_CON_LOW | 429 REF_BIAS_CUR_SEL); 430 431 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 432 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 433 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 434 CP_PROGRAM_EN | LPF_PROGRAM_EN | 435 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 436 437 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 438 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 439 440 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 441 INPUT_DIVIDER(dsi->input_div)); 442 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 443 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 444 LOW_PROGRAM_EN); 445 /* 446 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 447 * to make the configured LSB effective according to IP simulation 448 * and lab test results. 449 * Only in this way can we get correct mipi phy pll frequency. 450 */ 451 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 452 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 453 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 454 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 455 HIGH_PROGRAM_EN); 456 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 457 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 458 459 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 460 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 461 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 462 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 463 464 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 465 POWER_CONTROL | INTERNAL_REG_CURRENT | 466 BIAS_BLOCK_ON | BANDGAP_ON); 467 468 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 469 TER_RESISTOR_LOW | TER_CAL_DONE | 470 SETRD_MAX | TER_RESISTORS_ON); 471 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 472 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 473 SETRD_MAX | POWER_MANAGE | 474 TER_RESISTORS_ON); 475 476 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 477 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 478 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 479 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 480 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 481 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 482 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 483 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 484 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 485 BIT(5) | ns2bc(dsi, 100)); 486 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 487 BIT(5) | (ns2bc(dsi, 60) + 7)); 488 489 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 490 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 491 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 492 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 493 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 494 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 495 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 496 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 497 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 498 BIT(5) | ns2bc(dsi, 100)); 499 500 clk_disable_unprepare(dsi->phy_cfg_clk); 501 502 return ret; 503 } 504 505 static void dw_mipi_dsi_phy_power_on(void *priv_data) 506 { 507 struct dw_mipi_dsi_rockchip *dsi = priv_data; 508 int ret; 509 510 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 511 if (ret) { 512 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 513 return; 514 } 515 516 phy_configure(dsi->phy, &dsi->phy_opts); 517 phy_power_on(dsi->phy); 518 } 519 520 static void dw_mipi_dsi_phy_power_off(void *priv_data) 521 { 522 struct dw_mipi_dsi_rockchip *dsi = priv_data; 523 524 phy_power_off(dsi->phy); 525 } 526 527 static int 528 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 529 unsigned long mode_flags, u32 lanes, u32 format, 530 unsigned int *lane_mbps) 531 { 532 struct dw_mipi_dsi_rockchip *dsi = priv_data; 533 int bpp; 534 unsigned long mpclk, tmp; 535 unsigned int target_mbps = 1000; 536 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 537 unsigned long best_freq = 0; 538 unsigned long fvco_min, fvco_max, fin, fout; 539 unsigned int min_prediv, max_prediv; 540 unsigned int _prediv, best_prediv; 541 unsigned long _fbdiv, best_fbdiv; 542 unsigned long min_delta = ULONG_MAX; 543 544 dsi->format = format; 545 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 546 if (bpp < 0) { 547 DRM_DEV_ERROR(dsi->dev, 548 "failed to get bpp for pixel format %d\n", 549 dsi->format); 550 return bpp; 551 } 552 553 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 554 if (mpclk) { 555 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 556 tmp = mpclk * (bpp / lanes) * 10 / 8; 557 if (tmp < max_mbps) 558 target_mbps = tmp; 559 else 560 DRM_DEV_ERROR(dsi->dev, 561 "DPHY clock frequency is out of range\n"); 562 } 563 564 /* for external phy only a the mipi_dphy_config is necessary */ 565 if (dsi->phy) { 566 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 567 bpp, lanes, 568 &dsi->phy_opts.mipi_dphy); 569 dsi->lane_mbps = target_mbps; 570 *lane_mbps = dsi->lane_mbps; 571 572 return 0; 573 } 574 575 fin = clk_get_rate(dsi->pllref_clk); 576 fout = target_mbps * USEC_PER_SEC; 577 578 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 579 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 580 max_prediv = fin / (5 * USEC_PER_SEC); 581 582 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 583 fvco_min = 80 * USEC_PER_SEC; 584 fvco_max = 1500 * USEC_PER_SEC; 585 586 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 587 u64 tmp; 588 u32 delta; 589 /* Fvco = Fref * M / N */ 590 tmp = (u64)fout * _prediv; 591 do_div(tmp, fin); 592 _fbdiv = tmp; 593 /* 594 * Due to the use of a "by 2 pre-scaler," the range of the 595 * feedback multiplication value M is limited to even division 596 * numbers, and m must be greater than 6, not bigger than 512. 597 */ 598 if (_fbdiv < 6 || _fbdiv > 512) 599 continue; 600 601 _fbdiv += _fbdiv % 2; 602 603 tmp = (u64)_fbdiv * fin; 604 do_div(tmp, _prediv); 605 if (tmp < fvco_min || tmp > fvco_max) 606 continue; 607 608 delta = abs(fout - tmp); 609 if (delta < min_delta) { 610 best_prediv = _prediv; 611 best_fbdiv = _fbdiv; 612 min_delta = delta; 613 best_freq = tmp; 614 } 615 } 616 617 if (best_freq) { 618 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 619 *lane_mbps = dsi->lane_mbps; 620 dsi->input_div = best_prediv; 621 dsi->feedback_div = best_fbdiv; 622 } else { 623 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 624 return -EINVAL; 625 } 626 627 return 0; 628 } 629 630 struct hstt { 631 unsigned int maxfreq; 632 struct dw_mipi_dsi_dphy_timing timing; 633 }; 634 635 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 636 { \ 637 .maxfreq = _maxfreq, \ 638 .timing = { \ 639 .clk_lp2hs = _c_lp2hs, \ 640 .clk_hs2lp = _c_hs2lp, \ 641 .data_lp2hs = _d_lp2hs, \ 642 .data_hs2lp = _d_hs2lp, \ 643 } \ 644 } 645 646 /* Table A-3 High-Speed Transition Times */ 647 static struct hstt hstt_table[] = { 648 HSTT( 90, 32, 20, 26, 13), 649 HSTT( 100, 35, 23, 28, 14), 650 HSTT( 110, 32, 22, 26, 13), 651 HSTT( 130, 31, 20, 27, 13), 652 HSTT( 140, 33, 22, 26, 14), 653 HSTT( 150, 33, 21, 26, 14), 654 HSTT( 170, 32, 20, 27, 13), 655 HSTT( 180, 36, 23, 30, 15), 656 HSTT( 200, 40, 22, 33, 15), 657 HSTT( 220, 40, 22, 33, 15), 658 HSTT( 240, 44, 24, 36, 16), 659 HSTT( 250, 48, 24, 38, 17), 660 HSTT( 270, 48, 24, 38, 17), 661 HSTT( 300, 50, 27, 41, 18), 662 HSTT( 330, 56, 28, 45, 18), 663 HSTT( 360, 59, 28, 48, 19), 664 HSTT( 400, 61, 30, 50, 20), 665 HSTT( 450, 67, 31, 55, 21), 666 HSTT( 500, 73, 31, 59, 22), 667 HSTT( 550, 79, 36, 63, 24), 668 HSTT( 600, 83, 37, 68, 25), 669 HSTT( 650, 90, 38, 73, 27), 670 HSTT( 700, 95, 40, 77, 28), 671 HSTT( 750, 102, 40, 84, 28), 672 HSTT( 800, 106, 42, 87, 30), 673 HSTT( 850, 113, 44, 93, 31), 674 HSTT( 900, 118, 47, 98, 32), 675 HSTT( 950, 124, 47, 102, 34), 676 HSTT(1000, 130, 49, 107, 35), 677 HSTT(1050, 135, 51, 111, 37), 678 HSTT(1100, 139, 51, 114, 38), 679 HSTT(1150, 146, 54, 120, 40), 680 HSTT(1200, 153, 57, 125, 41), 681 HSTT(1250, 158, 58, 130, 42), 682 HSTT(1300, 163, 58, 135, 44), 683 HSTT(1350, 168, 60, 140, 45), 684 HSTT(1400, 172, 64, 144, 47), 685 HSTT(1450, 176, 65, 148, 48), 686 HSTT(1500, 181, 66, 153, 50) 687 }; 688 689 static int 690 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 691 struct dw_mipi_dsi_dphy_timing *timing) 692 { 693 int i; 694 695 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 696 if (lane_mbps < hstt_table[i].maxfreq) 697 break; 698 699 if (i == ARRAY_SIZE(hstt_table)) 700 i--; 701 702 *timing = hstt_table[i].timing; 703 704 return 0; 705 } 706 707 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 708 .init = dw_mipi_dsi_phy_init, 709 .power_on = dw_mipi_dsi_phy_power_on, 710 .power_off = dw_mipi_dsi_phy_power_off, 711 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 712 .get_timing = dw_mipi_dsi_phy_get_timing, 713 }; 714 715 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 716 { 717 if (dsi->cdata->lanecfg1_grf_reg) 718 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 719 dsi->cdata->lanecfg1); 720 721 if (dsi->cdata->lanecfg2_grf_reg) 722 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 723 dsi->cdata->lanecfg2); 724 725 if (dsi->cdata->enable_grf_reg) 726 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 727 dsi->cdata->enable); 728 } 729 730 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 731 int mux) 732 { 733 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 734 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 735 } 736 737 static int 738 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 739 struct drm_crtc_state *crtc_state, 740 struct drm_connector_state *conn_state) 741 { 742 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 743 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 744 745 switch (dsi->format) { 746 case MIPI_DSI_FMT_RGB888: 747 s->output_mode = ROCKCHIP_OUT_MODE_P888; 748 break; 749 case MIPI_DSI_FMT_RGB666: 750 s->output_mode = ROCKCHIP_OUT_MODE_P666; 751 break; 752 case MIPI_DSI_FMT_RGB565: 753 s->output_mode = ROCKCHIP_OUT_MODE_P565; 754 break; 755 default: 756 WARN_ON(1); 757 return -EINVAL; 758 } 759 760 s->output_type = DRM_MODE_CONNECTOR_DSI; 761 if (dsi->slave) 762 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 763 764 return 0; 765 } 766 767 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 768 { 769 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 770 int ret, mux; 771 772 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 773 &dsi->encoder); 774 if (mux < 0) 775 return; 776 777 /* 778 * For the RK3399, the clk of grf must be enabled before writing grf 779 * register. And for RK3288 or other soc, this grf_clk must be NULL, 780 * the clk_prepare_enable return true directly. 781 */ 782 ret = clk_prepare_enable(dsi->grf_clk); 783 if (ret) { 784 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 785 return; 786 } 787 788 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 789 if (dsi->slave) 790 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 791 792 clk_disable_unprepare(dsi->grf_clk); 793 } 794 795 static const struct drm_encoder_helper_funcs 796 dw_mipi_dsi_encoder_helper_funcs = { 797 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 798 .enable = dw_mipi_dsi_encoder_enable, 799 }; 800 801 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 802 struct drm_device *drm_dev) 803 { 804 struct drm_encoder *encoder = &dsi->encoder; 805 int ret; 806 807 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 808 dsi->dev->of_node); 809 810 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 811 if (ret) { 812 DRM_ERROR("Failed to initialize encoder with drm\n"); 813 return ret; 814 } 815 816 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 817 818 return 0; 819 } 820 821 static struct device 822 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 823 { 824 const struct of_device_id *match; 825 struct device_node *node = NULL, *local; 826 827 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 828 829 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 830 if (!local) 831 return NULL; 832 833 while ((node = of_find_compatible_node(node, NULL, 834 match->compatible))) { 835 struct device_node *remote; 836 837 /* found ourself */ 838 if (node == dsi->dev->of_node) 839 continue; 840 841 remote = of_graph_get_remote_node(node, 1, 0); 842 if (!remote) 843 continue; 844 845 /* same display device in port1-ep0 for both */ 846 if (remote == local) { 847 struct dw_mipi_dsi_rockchip *dsi2; 848 struct platform_device *pdev; 849 850 pdev = of_find_device_by_node(node); 851 852 /* 853 * we have found the second, so will either return it 854 * or return with an error. In any case won't need the 855 * nodes anymore nor continue the loop. 856 */ 857 of_node_put(remote); 858 of_node_put(node); 859 of_node_put(local); 860 861 if (!pdev) 862 return ERR_PTR(-EPROBE_DEFER); 863 864 dsi2 = platform_get_drvdata(pdev); 865 if (!dsi2) { 866 platform_device_put(pdev); 867 return ERR_PTR(-EPROBE_DEFER); 868 } 869 870 return &pdev->dev; 871 } 872 873 of_node_put(remote); 874 } 875 876 of_node_put(local); 877 878 return NULL; 879 } 880 881 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 882 struct device *master, 883 void *data) 884 { 885 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 886 struct drm_device *drm_dev = data; 887 struct device *second; 888 bool master1, master2; 889 int ret; 890 891 second = dw_mipi_dsi_rockchip_find_second(dsi); 892 if (IS_ERR(second)) 893 return PTR_ERR(second); 894 895 if (second) { 896 master1 = of_property_read_bool(dsi->dev->of_node, 897 "clock-master"); 898 master2 = of_property_read_bool(second->of_node, 899 "clock-master"); 900 901 if (master1 && master2) { 902 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 903 return -EINVAL; 904 } 905 906 if (!master1 && !master2) { 907 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 908 return -EINVAL; 909 } 910 911 /* we are the slave in dual-DSI */ 912 if (!master1) { 913 dsi->is_slave = true; 914 return 0; 915 } 916 917 dsi->slave = dev_get_drvdata(second); 918 if (!dsi->slave) { 919 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 920 return -ENODEV; 921 } 922 923 dsi->slave->is_slave = true; 924 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 925 put_device(second); 926 } 927 928 pm_runtime_get_sync(dsi->dev); 929 if (dsi->slave) 930 pm_runtime_get_sync(dsi->slave->dev); 931 932 ret = clk_prepare_enable(dsi->pllref_clk); 933 if (ret) { 934 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 935 goto out_pm_runtime; 936 } 937 938 /* 939 * With the GRF clock running, write lane and dual-mode configurations 940 * that won't change immediately. If we waited until enable() to do 941 * this, things like panel preparation would not be able to send 942 * commands over DSI. 943 */ 944 ret = clk_prepare_enable(dsi->grf_clk); 945 if (ret) { 946 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 947 goto out_pll_clk; 948 } 949 950 dw_mipi_dsi_rockchip_config(dsi); 951 if (dsi->slave) 952 dw_mipi_dsi_rockchip_config(dsi->slave); 953 954 clk_disable_unprepare(dsi->grf_clk); 955 956 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 957 if (ret) { 958 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 959 goto out_pll_clk; 960 } 961 962 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); 963 if (ret) { 964 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 965 goto out_pll_clk; 966 } 967 968 dsi->dsi_bound = true; 969 970 return 0; 971 972 out_pll_clk: 973 clk_disable_unprepare(dsi->pllref_clk); 974 out_pm_runtime: 975 pm_runtime_put(dsi->dev); 976 if (dsi->slave) 977 pm_runtime_put(dsi->slave->dev); 978 979 return ret; 980 } 981 982 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 983 struct device *master, 984 void *data) 985 { 986 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 987 988 if (dsi->is_slave) 989 return; 990 991 dsi->dsi_bound = false; 992 993 dw_mipi_dsi_unbind(dsi->dmd); 994 995 clk_disable_unprepare(dsi->pllref_clk); 996 997 pm_runtime_put(dsi->dev); 998 if (dsi->slave) 999 pm_runtime_put(dsi->slave->dev); 1000 } 1001 1002 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1003 .bind = dw_mipi_dsi_rockchip_bind, 1004 .unbind = dw_mipi_dsi_rockchip_unbind, 1005 }; 1006 1007 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1008 struct mipi_dsi_device *device) 1009 { 1010 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1011 struct device *second; 1012 int ret; 1013 1014 mutex_lock(&dsi->usage_mutex); 1015 1016 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1017 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1018 mutex_unlock(&dsi->usage_mutex); 1019 return -EBUSY; 1020 } 1021 1022 dsi->usage_mode = DW_DSI_USAGE_DSI; 1023 mutex_unlock(&dsi->usage_mutex); 1024 1025 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1026 if (ret) { 1027 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1028 ret); 1029 return ret; 1030 } 1031 1032 second = dw_mipi_dsi_rockchip_find_second(dsi); 1033 if (IS_ERR(second)) 1034 return PTR_ERR(second); 1035 if (second) { 1036 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1037 if (ret) { 1038 DRM_DEV_ERROR(second, 1039 "Failed to register component: %d\n", 1040 ret); 1041 return ret; 1042 } 1043 } 1044 1045 return 0; 1046 } 1047 1048 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1049 struct mipi_dsi_device *device) 1050 { 1051 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1052 struct device *second; 1053 1054 second = dw_mipi_dsi_rockchip_find_second(dsi); 1055 if (second && !IS_ERR(second)) 1056 component_del(second, &dw_mipi_dsi_rockchip_ops); 1057 1058 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1059 1060 mutex_lock(&dsi->usage_mutex); 1061 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1062 mutex_unlock(&dsi->usage_mutex); 1063 1064 return 0; 1065 } 1066 1067 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1068 .attach = dw_mipi_dsi_rockchip_host_attach, 1069 .detach = dw_mipi_dsi_rockchip_host_detach, 1070 }; 1071 1072 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1073 struct device *master, 1074 void *data) 1075 { 1076 /* 1077 * Nothing to do when used as a dphy. 1078 * Just make the rest of Rockchip-DRM happy 1079 * by being here. 1080 */ 1081 1082 return 0; 1083 } 1084 1085 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1086 struct device *master, 1087 void *data) 1088 { 1089 /* Nothing to do when used as a dphy. */ 1090 } 1091 1092 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1093 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1094 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1095 }; 1096 1097 static int dw_mipi_dsi_dphy_init(struct phy *phy) 1098 { 1099 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1100 int ret; 1101 1102 mutex_lock(&dsi->usage_mutex); 1103 1104 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1105 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1106 mutex_unlock(&dsi->usage_mutex); 1107 return -EBUSY; 1108 } 1109 1110 dsi->usage_mode = DW_DSI_USAGE_PHY; 1111 mutex_unlock(&dsi->usage_mutex); 1112 1113 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1114 if (ret < 0) 1115 goto err_graph; 1116 1117 if (dsi->cdata->dphy_rx_init) { 1118 ret = clk_prepare_enable(dsi->pclk); 1119 if (ret < 0) 1120 goto err_init; 1121 1122 ret = clk_prepare_enable(dsi->grf_clk); 1123 if (ret) { 1124 clk_disable_unprepare(dsi->pclk); 1125 goto err_init; 1126 } 1127 1128 ret = dsi->cdata->dphy_rx_init(phy); 1129 clk_disable_unprepare(dsi->grf_clk); 1130 clk_disable_unprepare(dsi->pclk); 1131 if (ret < 0) 1132 goto err_init; 1133 } 1134 1135 return 0; 1136 1137 err_init: 1138 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1139 err_graph: 1140 mutex_lock(&dsi->usage_mutex); 1141 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1142 mutex_unlock(&dsi->usage_mutex); 1143 1144 return ret; 1145 } 1146 1147 static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1148 { 1149 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1150 1151 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1152 1153 mutex_lock(&dsi->usage_mutex); 1154 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1155 mutex_unlock(&dsi->usage_mutex); 1156 1157 return 0; 1158 } 1159 1160 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1161 { 1162 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1163 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1164 int ret; 1165 1166 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1167 if (ret) 1168 return ret; 1169 1170 dsi->dphy_config = *config; 1171 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1172 1173 return 0; 1174 } 1175 1176 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1177 { 1178 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1179 int i, ret; 1180 1181 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1182 dsi->dphy_config.lanes, dsi->lane_mbps); 1183 1184 i = max_mbps_to_parameter(dsi->lane_mbps); 1185 if (i < 0) { 1186 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1187 dsi->lane_mbps); 1188 return i; 1189 } 1190 1191 ret = pm_runtime_get_sync(dsi->dev); 1192 if (ret < 0) { 1193 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1194 return ret; 1195 } 1196 1197 ret = clk_prepare_enable(dsi->pclk); 1198 if (ret) { 1199 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1200 goto err_pclk; 1201 } 1202 1203 ret = clk_prepare_enable(dsi->grf_clk); 1204 if (ret) { 1205 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1206 goto err_grf_clk; 1207 } 1208 1209 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1210 if (ret) { 1211 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1212 goto err_phy_cfg_clk; 1213 } 1214 1215 /* do soc-variant specific init */ 1216 if (dsi->cdata->dphy_rx_power_on) { 1217 ret = dsi->cdata->dphy_rx_power_on(phy); 1218 if (ret < 0) { 1219 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1220 goto err_pwr_on; 1221 } 1222 } 1223 1224 /* 1225 * Configure hsfreqrange according to frequency values 1226 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1227 */ 1228 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1229 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1230 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1231 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1232 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1233 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1234 1235 /* Normal operation */ 1236 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1237 1238 clk_disable_unprepare(dsi->phy_cfg_clk); 1239 clk_disable_unprepare(dsi->grf_clk); 1240 1241 return ret; 1242 1243 err_pwr_on: 1244 clk_disable_unprepare(dsi->phy_cfg_clk); 1245 err_phy_cfg_clk: 1246 clk_disable_unprepare(dsi->grf_clk); 1247 err_grf_clk: 1248 clk_disable_unprepare(dsi->pclk); 1249 err_pclk: 1250 pm_runtime_put(dsi->dev); 1251 return ret; 1252 } 1253 1254 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1255 { 1256 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1257 int ret; 1258 1259 ret = clk_prepare_enable(dsi->grf_clk); 1260 if (ret) { 1261 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1262 return ret; 1263 } 1264 1265 if (dsi->cdata->dphy_rx_power_off) { 1266 ret = dsi->cdata->dphy_rx_power_off(phy); 1267 if (ret < 0) 1268 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1269 } 1270 1271 clk_disable_unprepare(dsi->grf_clk); 1272 clk_disable_unprepare(dsi->pclk); 1273 1274 pm_runtime_put(dsi->dev); 1275 1276 return ret; 1277 } 1278 1279 static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1280 .configure = dw_mipi_dsi_dphy_configure, 1281 .power_on = dw_mipi_dsi_dphy_power_on, 1282 .power_off = dw_mipi_dsi_dphy_power_off, 1283 .init = dw_mipi_dsi_dphy_init, 1284 .exit = dw_mipi_dsi_dphy_exit, 1285 }; 1286 1287 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1288 { 1289 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1290 int ret; 1291 1292 /* 1293 * Re-configure DSI state, if we were previously initialized. We need 1294 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1295 */ 1296 if (dsi->dsi_bound) { 1297 ret = clk_prepare_enable(dsi->grf_clk); 1298 if (ret) { 1299 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1300 return ret; 1301 } 1302 1303 dw_mipi_dsi_rockchip_config(dsi); 1304 if (dsi->slave) 1305 dw_mipi_dsi_rockchip_config(dsi->slave); 1306 1307 clk_disable_unprepare(dsi->grf_clk); 1308 } 1309 1310 return 0; 1311 } 1312 1313 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1314 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1315 }; 1316 1317 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1318 { 1319 struct device *dev = &pdev->dev; 1320 struct device_node *np = dev->of_node; 1321 struct dw_mipi_dsi_rockchip *dsi; 1322 struct phy_provider *phy_provider; 1323 struct resource *res; 1324 const struct rockchip_dw_dsi_chip_data *cdata = 1325 of_device_get_match_data(dev); 1326 int ret, i; 1327 1328 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1329 if (!dsi) 1330 return -ENOMEM; 1331 1332 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1333 dsi->base = devm_ioremap_resource(dev, res); 1334 if (IS_ERR(dsi->base)) { 1335 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1336 return PTR_ERR(dsi->base); 1337 } 1338 1339 i = 0; 1340 while (cdata[i].reg) { 1341 if (cdata[i].reg == res->start) { 1342 dsi->cdata = &cdata[i]; 1343 break; 1344 } 1345 1346 i++; 1347 } 1348 1349 if (!dsi->cdata) { 1350 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1351 return -EINVAL; 1352 } 1353 1354 /* try to get a possible external dphy */ 1355 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1356 if (IS_ERR(dsi->phy)) { 1357 ret = PTR_ERR(dsi->phy); 1358 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1359 return ret; 1360 } 1361 1362 dsi->pclk = devm_clk_get(dev, "pclk"); 1363 if (IS_ERR(dsi->pclk)) { 1364 ret = PTR_ERR(dsi->pclk); 1365 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1366 return ret; 1367 } 1368 1369 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1370 if (IS_ERR(dsi->pllref_clk)) { 1371 if (dsi->phy) { 1372 /* 1373 * if external phy is present, pll will be 1374 * generated there. 1375 */ 1376 dsi->pllref_clk = NULL; 1377 } else { 1378 ret = PTR_ERR(dsi->pllref_clk); 1379 DRM_DEV_ERROR(dev, 1380 "Unable to get pll reference clock: %d\n", 1381 ret); 1382 return ret; 1383 } 1384 } 1385 1386 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1387 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1388 if (IS_ERR(dsi->phy_cfg_clk)) { 1389 ret = PTR_ERR(dsi->phy_cfg_clk); 1390 DRM_DEV_ERROR(dev, 1391 "Unable to get phy_cfg_clk: %d\n", ret); 1392 return ret; 1393 } 1394 } 1395 1396 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1397 dsi->grf_clk = devm_clk_get(dev, "grf"); 1398 if (IS_ERR(dsi->grf_clk)) { 1399 ret = PTR_ERR(dsi->grf_clk); 1400 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1401 return ret; 1402 } 1403 } 1404 1405 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1406 if (IS_ERR(dsi->grf_regmap)) { 1407 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1408 return PTR_ERR(dsi->grf_regmap); 1409 } 1410 1411 dsi->dev = dev; 1412 dsi->pdata.base = dsi->base; 1413 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1414 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1415 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1416 dsi->pdata.priv_data = dsi; 1417 platform_set_drvdata(pdev, dsi); 1418 1419 mutex_init(&dsi->usage_mutex); 1420 1421 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1422 if (IS_ERR(dsi->dphy)) { 1423 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1424 return PTR_ERR(dsi->dphy); 1425 } 1426 1427 phy_set_drvdata(dsi->dphy, dsi); 1428 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1429 if (IS_ERR(phy_provider)) 1430 return PTR_ERR(phy_provider); 1431 1432 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1433 if (IS_ERR(dsi->dmd)) { 1434 ret = PTR_ERR(dsi->dmd); 1435 if (ret != -EPROBE_DEFER) 1436 DRM_DEV_ERROR(dev, 1437 "Failed to probe dw_mipi_dsi: %d\n", ret); 1438 return ret; 1439 } 1440 1441 return 0; 1442 } 1443 1444 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1445 { 1446 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1447 1448 dw_mipi_dsi_remove(dsi->dmd); 1449 1450 return 0; 1451 } 1452 1453 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1454 { 1455 .reg = 0xff450000, 1456 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1457 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1458 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1459 PX30_DSI_LCDC_SEL), 1460 1461 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1462 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1463 PX30_DSI_FORCERXMODE | 1464 PX30_DSI_FORCETXSTOPMODE), 1465 1466 .max_data_lanes = 4, 1467 }, 1468 { /* sentinel */ } 1469 }; 1470 1471 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1472 { 1473 .reg = 0xff960000, 1474 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1475 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1476 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1477 1478 .max_data_lanes = 4, 1479 }, 1480 { 1481 .reg = 0xff964000, 1482 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1483 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1484 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1485 1486 .max_data_lanes = 4, 1487 }, 1488 { /* sentinel */ } 1489 }; 1490 1491 static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1492 { 1493 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1494 1495 /* 1496 * Set TX1RX1 source to isp1. 1497 * Assume ISP0 is supplied by the RX0 dphy. 1498 */ 1499 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1500 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); 1501 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1502 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1503 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1504 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR)); 1505 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1506 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1507 1508 return 0; 1509 } 1510 1511 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1512 { 1513 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1514 1515 /* tester reset pulse */ 1516 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1517 usleep_range(100, 150); 1518 1519 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1520 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1521 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1522 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR)); 1523 1524 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1525 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE)); 1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1527 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE)); 1528 1529 /* Disable lane turn around, which is ignored in receive mode */ 1530 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1531 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST)); 1532 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1533 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE, 1534 RK3399_DSI1_TURNDISABLE)); 1535 usleep_range(100, 150); 1536 1537 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1538 usleep_range(100, 150); 1539 1540 /* Enable dphy lanes */ 1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1542 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), 1543 RK3399_DSI1_ENABLE)); 1544 1545 usleep_range(100, 150); 1546 1547 return 0; 1548 } 1549 1550 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1551 { 1552 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1553 1554 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1555 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1556 1557 return 0; 1558 } 1559 1560 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1561 { 1562 .reg = 0xff960000, 1563 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1564 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1565 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1566 RK3399_DSI0_LCDC_SEL), 1567 1568 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1569 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1570 RK3399_DSI0_TURNDISABLE | 1571 RK3399_DSI0_FORCETXSTOPMODE | 1572 RK3399_DSI0_FORCERXMODE), 1573 1574 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1575 .max_data_lanes = 4, 1576 }, 1577 { 1578 .reg = 0xff968000, 1579 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1580 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1581 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1582 RK3399_DSI1_LCDC_SEL), 1583 1584 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1585 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1586 RK3399_DSI1_FORCETXSTOPMODE | 1587 RK3399_DSI1_FORCERXMODE | 1588 RK3399_DSI1_ENABLE), 1589 1590 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1591 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1592 RK3399_TXRX_ENABLECLK, 1593 RK3399_TXRX_MASTERSLAVEZ | 1594 RK3399_TXRX_ENABLECLK | 1595 RK3399_TXRX_BASEDIR), 1596 1597 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1598 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1599 1600 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1601 .max_data_lanes = 4, 1602 1603 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1604 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1605 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1606 }, 1607 { /* sentinel */ } 1608 }; 1609 1610 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1611 { 1612 .compatible = "rockchip,px30-mipi-dsi", 1613 .data = &px30_chip_data, 1614 }, { 1615 .compatible = "rockchip,rk3288-mipi-dsi", 1616 .data = &rk3288_chip_data, 1617 }, { 1618 .compatible = "rockchip,rk3399-mipi-dsi", 1619 .data = &rk3399_chip_data, 1620 }, 1621 { /* sentinel */ } 1622 }; 1623 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1624 1625 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1626 .probe = dw_mipi_dsi_rockchip_probe, 1627 .remove = dw_mipi_dsi_rockchip_remove, 1628 .driver = { 1629 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1630 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1631 .name = "dw-mipi-dsi-rockchip", 1632 }, 1633 }; 1634