1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/math64.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/phy/phy.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/bridge/dw_mipi_dsi.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #include "rockchip_drm_drv.h" 27 #include "rockchip_drm_vop.h" 28 29 #define DSI_PHY_RSTZ 0xa0 30 #define PHY_DISFORCEPLL 0 31 #define PHY_ENFORCEPLL BIT(3) 32 #define PHY_DISABLECLK 0 33 #define PHY_ENABLECLK BIT(2) 34 #define PHY_RSTZ 0 35 #define PHY_UNRSTZ BIT(1) 36 #define PHY_SHUTDOWNZ 0 37 #define PHY_UNSHUTDOWNZ BIT(0) 38 39 #define DSI_PHY_IF_CFG 0xa4 40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 41 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 42 43 #define DSI_PHY_STATUS 0xb0 44 #define LOCK BIT(0) 45 #define STOP_STATE_CLK_LANE BIT(2) 46 47 #define DSI_PHY_TST_CTRL0 0xb4 48 #define PHY_TESTCLK BIT(1) 49 #define PHY_UNTESTCLK 0 50 #define PHY_TESTCLR BIT(0) 51 #define PHY_UNTESTCLR 0 52 53 #define DSI_PHY_TST_CTRL1 0xb8 54 #define PHY_TESTEN BIT(16) 55 #define PHY_UNTESTEN 0 56 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 57 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 58 59 #define DSI_INT_ST0 0xbc 60 #define DSI_INT_ST1 0xc0 61 #define DSI_INT_MSK0 0xc4 62 #define DSI_INT_MSK1 0xc8 63 64 #define PHY_STATUS_TIMEOUT_US 10000 65 #define CMD_PKT_STATUS_TIMEOUT_US 20000 66 67 #define BYPASS_VCO_RANGE BIT(7) 68 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 69 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 70 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 71 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 72 #define REF_BIAS_CUR_SEL BIT(0) 73 74 #define CP_CURRENT_3UA 0x1 75 #define CP_CURRENT_4_5UA 0x2 76 #define CP_CURRENT_7_5UA 0x6 77 #define CP_CURRENT_6UA 0x9 78 #define CP_CURRENT_12UA 0xb 79 #define CP_CURRENT_SEL(val) ((val) & 0xf) 80 #define CP_PROGRAM_EN BIT(7) 81 82 #define LPF_RESISTORS_15_5KOHM 0x1 83 #define LPF_RESISTORS_13KOHM 0x2 84 #define LPF_RESISTORS_11_5KOHM 0x4 85 #define LPF_RESISTORS_10_5KOHM 0x8 86 #define LPF_RESISTORS_8KOHM 0x10 87 #define LPF_PROGRAM_EN BIT(6) 88 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 89 90 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 91 92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 93 #define LOW_PROGRAM_EN 0 94 #define HIGH_PROGRAM_EN BIT(7) 95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 97 #define PLL_LOOP_DIV_EN BIT(5) 98 #define PLL_INPUT_DIV_EN BIT(4) 99 100 #define POWER_CONTROL BIT(6) 101 #define INTERNAL_REG_CURRENT BIT(3) 102 #define BIAS_BLOCK_ON BIT(2) 103 #define BANDGAP_ON BIT(0) 104 105 #define TER_RESISTOR_HIGH BIT(7) 106 #define TER_RESISTOR_LOW 0 107 #define LEVEL_SHIFTERS_ON BIT(6) 108 #define TER_CAL_DONE BIT(5) 109 #define SETRD_MAX (0x7 << 2) 110 #define POWER_MANAGE BIT(1) 111 #define TER_RESISTORS_ON BIT(0) 112 113 #define BIASEXTR_SEL(val) ((val) & 0x7) 114 #define BANDGAP_SEL(val) ((val) & 0x7) 115 #define TLP_PROGRAM_EN BIT(7) 116 #define THS_PRE_PROGRAM_EN BIT(7) 117 #define THS_ZERO_PROGRAM_EN BIT(6) 118 119 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 120 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 121 #define PLL_LPF_AND_CP_CONTROL 0x12 122 #define PLL_INPUT_DIVIDER_RATIO 0x17 123 #define PLL_LOOP_DIVIDER_RATIO 0x18 124 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 125 #define BANDGAP_AND_BIAS_CONTROL 0x20 126 #define TERMINATION_RESISTER_CONTROL 0x21 127 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 128 #define HS_RX_CONTROL_OF_LANE_CLK 0x34 129 #define HS_RX_CONTROL_OF_LANE_0 0x44 130 #define HS_RX_CONTROL_OF_LANE_1 0x54 131 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 132 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 133 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 134 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 135 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 136 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 137 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 138 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 139 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 140 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 141 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 142 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 143 #define HS_RX_CONTROL_OF_LANE_2 0x84 144 #define HS_RX_CONTROL_OF_LANE_3 0x94 145 146 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 147 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 148 149 #define PX30_GRF_PD_VO_CON1 0x0438 150 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 151 #define PX30_DSI_FORCERXMODE BIT(6) 152 #define PX30_DSI_TURNDISABLE BIT(5) 153 #define PX30_DSI_LCDC_SEL BIT(0) 154 155 #define RK3288_GRF_SOC_CON6 0x025c 156 #define RK3288_DSI0_LCDC_SEL BIT(6) 157 #define RK3288_DSI1_LCDC_SEL BIT(9) 158 159 #define RK3399_GRF_SOC_CON20 0x6250 160 #define RK3399_DSI0_LCDC_SEL BIT(0) 161 #define RK3399_DSI1_LCDC_SEL BIT(4) 162 163 #define RK3399_GRF_SOC_CON22 0x6258 164 #define RK3399_DSI0_TURNREQUEST (0xf << 12) 165 #define RK3399_DSI0_TURNDISABLE (0xf << 8) 166 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 167 #define RK3399_DSI0_FORCERXMODE (0xf << 0) 168 169 #define RK3399_GRF_SOC_CON23 0x625c 170 #define RK3399_DSI1_TURNDISABLE (0xf << 12) 171 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 172 #define RK3399_DSI1_FORCERXMODE (0xf << 4) 173 #define RK3399_DSI1_ENABLE (0xf << 0) 174 175 #define RK3399_GRF_SOC_CON24 0x6260 176 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 177 #define RK3399_TXRX_ENABLECLK BIT(6) 178 #define RK3399_TXRX_BASEDIR BIT(5) 179 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 180 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 181 182 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 183 184 #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) 185 186 enum { 187 DW_DSI_USAGE_IDLE, 188 DW_DSI_USAGE_DSI, 189 DW_DSI_USAGE_PHY, 190 }; 191 192 enum { 193 BANDGAP_97_07, 194 BANDGAP_98_05, 195 BANDGAP_99_02, 196 BANDGAP_100_00, 197 BANDGAP_93_17, 198 BANDGAP_94_15, 199 BANDGAP_95_12, 200 BANDGAP_96_10, 201 }; 202 203 enum { 204 BIASEXTR_87_1, 205 BIASEXTR_91_5, 206 BIASEXTR_95_9, 207 BIASEXTR_100, 208 BIASEXTR_105_94, 209 BIASEXTR_111_88, 210 BIASEXTR_118_8, 211 BIASEXTR_127_7, 212 }; 213 214 struct rockchip_dw_dsi_chip_data { 215 u32 reg; 216 217 u32 lcdsel_grf_reg; 218 u32 lcdsel_big; 219 u32 lcdsel_lit; 220 221 u32 enable_grf_reg; 222 u32 enable; 223 224 u32 lanecfg1_grf_reg; 225 u32 lanecfg1; 226 u32 lanecfg2_grf_reg; 227 u32 lanecfg2; 228 229 int (*dphy_rx_init)(struct phy *phy); 230 int (*dphy_rx_power_on)(struct phy *phy); 231 int (*dphy_rx_power_off)(struct phy *phy); 232 233 unsigned int flags; 234 unsigned int max_data_lanes; 235 }; 236 237 struct dw_mipi_dsi_rockchip { 238 struct device *dev; 239 struct drm_encoder encoder; 240 void __iomem *base; 241 242 struct regmap *grf_regmap; 243 struct clk *pclk; 244 struct clk *pllref_clk; 245 struct clk *grf_clk; 246 struct clk *phy_cfg_clk; 247 248 /* dual-channel */ 249 bool is_slave; 250 struct dw_mipi_dsi_rockchip *slave; 251 252 /* optional external dphy */ 253 struct phy *phy; 254 union phy_configure_opts phy_opts; 255 256 /* being a phy for other mipi hosts */ 257 unsigned int usage_mode; 258 struct mutex usage_mutex; 259 struct phy *dphy; 260 struct phy_configure_opts_mipi_dphy dphy_config; 261 262 unsigned int lane_mbps; /* per lane */ 263 u16 input_div; 264 u16 feedback_div; 265 u32 format; 266 267 struct dw_mipi_dsi *dmd; 268 const struct rockchip_dw_dsi_chip_data *cdata; 269 struct dw_mipi_dsi_plat_data pdata; 270 }; 271 272 struct dphy_pll_parameter_map { 273 unsigned int max_mbps; 274 u8 hsfreqrange; 275 u8 icpctrl; 276 u8 lpfctrl; 277 }; 278 279 /* The table is based on 27MHz DPHY pll reference clock. */ 280 static const struct dphy_pll_parameter_map dppa_map[] = { 281 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 282 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 283 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 284 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 285 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 286 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 287 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 288 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 289 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 290 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 291 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 292 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 293 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 294 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 295 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 296 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 297 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 298 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 299 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 300 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 301 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 302 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 303 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 304 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 305 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 306 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 307 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 308 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 309 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 310 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 311 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 312 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 313 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 314 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 315 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 316 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 317 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 318 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 319 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 320 }; 321 322 static int max_mbps_to_parameter(unsigned int max_mbps) 323 { 324 int i; 325 326 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 327 if (dppa_map[i].max_mbps >= max_mbps) 328 return i; 329 330 return -EINVAL; 331 } 332 333 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 334 { 335 writel(val, dsi->base + reg); 336 } 337 338 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) 339 { 340 return readl(dsi->base + reg); 341 } 342 343 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg, 344 u32 mask, u32 val) 345 { 346 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 347 } 348 349 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 350 u8 test_code, 351 u8 test_data) 352 { 353 /* 354 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 355 * is latched internally as the current test code. Test data is 356 * programmed internally by rising edge on TESTCLK. 357 */ 358 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 359 360 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 361 PHY_TESTDIN(test_code)); 362 363 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 364 365 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 366 PHY_TESTDIN(test_data)); 367 368 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 369 } 370 371 /* 372 * ns2bc - Nanoseconds to byte clock cycles 373 */ 374 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 375 { 376 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 377 } 378 379 /* 380 * ns2ui - Nanoseconds to UI time periods 381 */ 382 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 383 { 384 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 385 } 386 387 static int dw_mipi_dsi_phy_init(void *priv_data) 388 { 389 struct dw_mipi_dsi_rockchip *dsi = priv_data; 390 int ret, i, vco; 391 392 if (dsi->phy) 393 return 0; 394 395 /* 396 * Get vco from frequency(lane_mbps) 397 * vco frequency table 398 * 000 - between 80 and 200 MHz 399 * 001 - between 200 and 300 MHz 400 * 010 - between 300 and 500 MHz 401 * 011 - between 500 and 700 MHz 402 * 100 - between 700 and 900 MHz 403 * 101 - between 900 and 1100 MHz 404 * 110 - between 1100 and 1300 MHz 405 * 111 - between 1300 and 1500 MHz 406 */ 407 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 408 409 i = max_mbps_to_parameter(dsi->lane_mbps); 410 if (i < 0) { 411 DRM_DEV_ERROR(dsi->dev, 412 "failed to get parameter for %dmbps clock\n", 413 dsi->lane_mbps); 414 return i; 415 } 416 417 ret = clk_prepare_enable(dsi->phy_cfg_clk); 418 if (ret) { 419 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 420 return ret; 421 } 422 423 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 424 BYPASS_VCO_RANGE | 425 VCO_RANGE_CON_SEL(vco) | 426 VCO_IN_CAP_CON_LOW | 427 REF_BIAS_CUR_SEL); 428 429 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 430 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 431 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 432 CP_PROGRAM_EN | LPF_PROGRAM_EN | 433 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 434 435 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 436 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 437 438 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 439 INPUT_DIVIDER(dsi->input_div)); 440 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 441 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 442 LOW_PROGRAM_EN); 443 /* 444 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 445 * to make the configured LSB effective according to IP simulation 446 * and lab test results. 447 * Only in this way can we get correct mipi phy pll frequency. 448 */ 449 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 450 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 451 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 452 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 453 HIGH_PROGRAM_EN); 454 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 455 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 456 457 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 458 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 459 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 460 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 461 462 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 463 POWER_CONTROL | INTERNAL_REG_CURRENT | 464 BIAS_BLOCK_ON | BANDGAP_ON); 465 466 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 467 TER_RESISTOR_LOW | TER_CAL_DONE | 468 SETRD_MAX | TER_RESISTORS_ON); 469 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 470 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 471 SETRD_MAX | POWER_MANAGE | 472 TER_RESISTORS_ON); 473 474 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 475 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 476 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 477 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 478 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 479 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 480 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 481 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 482 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 483 BIT(5) | ns2bc(dsi, 100)); 484 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 485 BIT(5) | (ns2bc(dsi, 60) + 7)); 486 487 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 488 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 489 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 490 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 491 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 492 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 493 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 494 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 495 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 496 BIT(5) | ns2bc(dsi, 100)); 497 498 clk_disable_unprepare(dsi->phy_cfg_clk); 499 500 return ret; 501 } 502 503 static void dw_mipi_dsi_phy_power_on(void *priv_data) 504 { 505 struct dw_mipi_dsi_rockchip *dsi = priv_data; 506 int ret; 507 508 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 509 if (ret) { 510 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 511 return; 512 } 513 514 phy_configure(dsi->phy, &dsi->phy_opts); 515 phy_power_on(dsi->phy); 516 } 517 518 static void dw_mipi_dsi_phy_power_off(void *priv_data) 519 { 520 struct dw_mipi_dsi_rockchip *dsi = priv_data; 521 522 phy_power_off(dsi->phy); 523 } 524 525 static int 526 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 527 unsigned long mode_flags, u32 lanes, u32 format, 528 unsigned int *lane_mbps) 529 { 530 struct dw_mipi_dsi_rockchip *dsi = priv_data; 531 int bpp; 532 unsigned long mpclk, tmp; 533 unsigned int target_mbps = 1000; 534 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 535 unsigned long best_freq = 0; 536 unsigned long fvco_min, fvco_max, fin, fout; 537 unsigned int min_prediv, max_prediv; 538 unsigned int _prediv, best_prediv; 539 unsigned long _fbdiv, best_fbdiv; 540 unsigned long min_delta = ULONG_MAX; 541 542 dsi->format = format; 543 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 544 if (bpp < 0) { 545 DRM_DEV_ERROR(dsi->dev, 546 "failed to get bpp for pixel format %d\n", 547 dsi->format); 548 return bpp; 549 } 550 551 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 552 if (mpclk) { 553 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 554 tmp = mpclk * (bpp / lanes) * 10 / 8; 555 if (tmp < max_mbps) 556 target_mbps = tmp; 557 else 558 DRM_DEV_ERROR(dsi->dev, 559 "DPHY clock frequency is out of range\n"); 560 } 561 562 /* for external phy only a the mipi_dphy_config is necessary */ 563 if (dsi->phy) { 564 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 565 bpp, lanes, 566 &dsi->phy_opts.mipi_dphy); 567 dsi->lane_mbps = target_mbps; 568 *lane_mbps = dsi->lane_mbps; 569 570 return 0; 571 } 572 573 fin = clk_get_rate(dsi->pllref_clk); 574 fout = target_mbps * USEC_PER_SEC; 575 576 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 577 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 578 max_prediv = fin / (5 * USEC_PER_SEC); 579 580 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 581 fvco_min = 80 * USEC_PER_SEC; 582 fvco_max = 1500 * USEC_PER_SEC; 583 584 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 585 u64 tmp; 586 u32 delta; 587 /* Fvco = Fref * M / N */ 588 tmp = (u64)fout * _prediv; 589 do_div(tmp, fin); 590 _fbdiv = tmp; 591 /* 592 * Due to the use of a "by 2 pre-scaler," the range of the 593 * feedback multiplication value M is limited to even division 594 * numbers, and m must be greater than 6, not bigger than 512. 595 */ 596 if (_fbdiv < 6 || _fbdiv > 512) 597 continue; 598 599 _fbdiv += _fbdiv % 2; 600 601 tmp = (u64)_fbdiv * fin; 602 do_div(tmp, _prediv); 603 if (tmp < fvco_min || tmp > fvco_max) 604 continue; 605 606 delta = abs(fout - tmp); 607 if (delta < min_delta) { 608 best_prediv = _prediv; 609 best_fbdiv = _fbdiv; 610 min_delta = delta; 611 best_freq = tmp; 612 } 613 } 614 615 if (best_freq) { 616 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 617 *lane_mbps = dsi->lane_mbps; 618 dsi->input_div = best_prediv; 619 dsi->feedback_div = best_fbdiv; 620 } else { 621 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 622 return -EINVAL; 623 } 624 625 return 0; 626 } 627 628 struct hstt { 629 unsigned int maxfreq; 630 struct dw_mipi_dsi_dphy_timing timing; 631 }; 632 633 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 634 { \ 635 .maxfreq = _maxfreq, \ 636 .timing = { \ 637 .clk_lp2hs = _c_lp2hs, \ 638 .clk_hs2lp = _c_hs2lp, \ 639 .data_lp2hs = _d_lp2hs, \ 640 .data_hs2lp = _d_hs2lp, \ 641 } \ 642 } 643 644 /* Table A-3 High-Speed Transition Times */ 645 static struct hstt hstt_table[] = { 646 HSTT( 90, 32, 20, 26, 13), 647 HSTT( 100, 35, 23, 28, 14), 648 HSTT( 110, 32, 22, 26, 13), 649 HSTT( 130, 31, 20, 27, 13), 650 HSTT( 140, 33, 22, 26, 14), 651 HSTT( 150, 33, 21, 26, 14), 652 HSTT( 170, 32, 20, 27, 13), 653 HSTT( 180, 36, 23, 30, 15), 654 HSTT( 200, 40, 22, 33, 15), 655 HSTT( 220, 40, 22, 33, 15), 656 HSTT( 240, 44, 24, 36, 16), 657 HSTT( 250, 48, 24, 38, 17), 658 HSTT( 270, 48, 24, 38, 17), 659 HSTT( 300, 50, 27, 41, 18), 660 HSTT( 330, 56, 28, 45, 18), 661 HSTT( 360, 59, 28, 48, 19), 662 HSTT( 400, 61, 30, 50, 20), 663 HSTT( 450, 67, 31, 55, 21), 664 HSTT( 500, 73, 31, 59, 22), 665 HSTT( 550, 79, 36, 63, 24), 666 HSTT( 600, 83, 37, 68, 25), 667 HSTT( 650, 90, 38, 73, 27), 668 HSTT( 700, 95, 40, 77, 28), 669 HSTT( 750, 102, 40, 84, 28), 670 HSTT( 800, 106, 42, 87, 30), 671 HSTT( 850, 113, 44, 93, 31), 672 HSTT( 900, 118, 47, 98, 32), 673 HSTT( 950, 124, 47, 102, 34), 674 HSTT(1000, 130, 49, 107, 35), 675 HSTT(1050, 135, 51, 111, 37), 676 HSTT(1100, 139, 51, 114, 38), 677 HSTT(1150, 146, 54, 120, 40), 678 HSTT(1200, 153, 57, 125, 41), 679 HSTT(1250, 158, 58, 130, 42), 680 HSTT(1300, 163, 58, 135, 44), 681 HSTT(1350, 168, 60, 140, 45), 682 HSTT(1400, 172, 64, 144, 47), 683 HSTT(1450, 176, 65, 148, 48), 684 HSTT(1500, 181, 66, 153, 50) 685 }; 686 687 static int 688 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 689 struct dw_mipi_dsi_dphy_timing *timing) 690 { 691 int i; 692 693 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 694 if (lane_mbps < hstt_table[i].maxfreq) 695 break; 696 697 if (i == ARRAY_SIZE(hstt_table)) 698 i--; 699 700 *timing = hstt_table[i].timing; 701 702 return 0; 703 } 704 705 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 706 .init = dw_mipi_dsi_phy_init, 707 .power_on = dw_mipi_dsi_phy_power_on, 708 .power_off = dw_mipi_dsi_phy_power_off, 709 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 710 .get_timing = dw_mipi_dsi_phy_get_timing, 711 }; 712 713 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 714 { 715 if (dsi->cdata->lanecfg1_grf_reg) 716 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 717 dsi->cdata->lanecfg1); 718 719 if (dsi->cdata->lanecfg2_grf_reg) 720 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 721 dsi->cdata->lanecfg2); 722 723 if (dsi->cdata->enable_grf_reg) 724 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 725 dsi->cdata->enable); 726 } 727 728 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 729 int mux) 730 { 731 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 732 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 733 } 734 735 static int 736 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 737 struct drm_crtc_state *crtc_state, 738 struct drm_connector_state *conn_state) 739 { 740 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 741 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 742 743 switch (dsi->format) { 744 case MIPI_DSI_FMT_RGB888: 745 s->output_mode = ROCKCHIP_OUT_MODE_P888; 746 break; 747 case MIPI_DSI_FMT_RGB666: 748 s->output_mode = ROCKCHIP_OUT_MODE_P666; 749 break; 750 case MIPI_DSI_FMT_RGB565: 751 s->output_mode = ROCKCHIP_OUT_MODE_P565; 752 break; 753 default: 754 WARN_ON(1); 755 return -EINVAL; 756 } 757 758 s->output_type = DRM_MODE_CONNECTOR_DSI; 759 if (dsi->slave) 760 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 761 762 return 0; 763 } 764 765 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 766 { 767 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 768 int ret, mux; 769 770 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 771 &dsi->encoder); 772 if (mux < 0) 773 return; 774 775 pm_runtime_get_sync(dsi->dev); 776 if (dsi->slave) 777 pm_runtime_get_sync(dsi->slave->dev); 778 779 /* 780 * For the RK3399, the clk of grf must be enabled before writing grf 781 * register. And for RK3288 or other soc, this grf_clk must be NULL, 782 * the clk_prepare_enable return true directly. 783 */ 784 ret = clk_prepare_enable(dsi->grf_clk); 785 if (ret) { 786 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 787 return; 788 } 789 790 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 791 if (dsi->slave) 792 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 793 794 clk_disable_unprepare(dsi->grf_clk); 795 } 796 797 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) 798 { 799 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 800 801 if (dsi->slave) 802 pm_runtime_put(dsi->slave->dev); 803 pm_runtime_put(dsi->dev); 804 } 805 806 static const struct drm_encoder_helper_funcs 807 dw_mipi_dsi_encoder_helper_funcs = { 808 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 809 .enable = dw_mipi_dsi_encoder_enable, 810 .disable = dw_mipi_dsi_encoder_disable, 811 }; 812 813 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 814 struct drm_device *drm_dev) 815 { 816 struct drm_encoder *encoder = &dsi->encoder; 817 int ret; 818 819 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 820 dsi->dev->of_node); 821 822 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 823 if (ret) { 824 DRM_ERROR("Failed to initialize encoder with drm\n"); 825 return ret; 826 } 827 828 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 829 830 return 0; 831 } 832 833 static struct device 834 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 835 { 836 const struct of_device_id *match; 837 struct device_node *node = NULL, *local; 838 839 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 840 841 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 842 if (!local) 843 return NULL; 844 845 while ((node = of_find_compatible_node(node, NULL, 846 match->compatible))) { 847 struct device_node *remote; 848 849 /* found ourself */ 850 if (node == dsi->dev->of_node) 851 continue; 852 853 remote = of_graph_get_remote_node(node, 1, 0); 854 if (!remote) 855 continue; 856 857 /* same display device in port1-ep0 for both */ 858 if (remote == local) { 859 struct dw_mipi_dsi_rockchip *dsi2; 860 struct platform_device *pdev; 861 862 pdev = of_find_device_by_node(node); 863 864 /* 865 * we have found the second, so will either return it 866 * or return with an error. In any case won't need the 867 * nodes anymore nor continue the loop. 868 */ 869 of_node_put(remote); 870 of_node_put(node); 871 of_node_put(local); 872 873 if (!pdev) 874 return ERR_PTR(-EPROBE_DEFER); 875 876 dsi2 = platform_get_drvdata(pdev); 877 if (!dsi2) { 878 platform_device_put(pdev); 879 return ERR_PTR(-EPROBE_DEFER); 880 } 881 882 return &pdev->dev; 883 } 884 885 of_node_put(remote); 886 } 887 888 of_node_put(local); 889 890 return NULL; 891 } 892 893 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 894 struct device *master, 895 void *data) 896 { 897 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 898 struct drm_device *drm_dev = data; 899 struct device *second; 900 bool master1, master2; 901 int ret; 902 903 second = dw_mipi_dsi_rockchip_find_second(dsi); 904 if (IS_ERR(second)) 905 return PTR_ERR(second); 906 907 if (second) { 908 master1 = of_property_read_bool(dsi->dev->of_node, 909 "clock-master"); 910 master2 = of_property_read_bool(second->of_node, 911 "clock-master"); 912 913 if (master1 && master2) { 914 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 915 return -EINVAL; 916 } 917 918 if (!master1 && !master2) { 919 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 920 return -EINVAL; 921 } 922 923 /* we are the slave in dual-DSI */ 924 if (!master1) { 925 dsi->is_slave = true; 926 return 0; 927 } 928 929 dsi->slave = dev_get_drvdata(second); 930 if (!dsi->slave) { 931 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 932 return -ENODEV; 933 } 934 935 dsi->slave->is_slave = true; 936 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 937 put_device(second); 938 } 939 940 ret = clk_prepare_enable(dsi->pllref_clk); 941 if (ret) { 942 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 943 return ret; 944 } 945 946 /* 947 * With the GRF clock running, write lane and dual-mode configurations 948 * that won't change immediately. If we waited until enable() to do 949 * this, things like panel preparation would not be able to send 950 * commands over DSI. 951 */ 952 ret = clk_prepare_enable(dsi->grf_clk); 953 if (ret) { 954 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 955 return ret; 956 } 957 958 dw_mipi_dsi_rockchip_config(dsi); 959 if (dsi->slave) 960 dw_mipi_dsi_rockchip_config(dsi->slave); 961 962 clk_disable_unprepare(dsi->grf_clk); 963 964 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 965 if (ret) { 966 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 967 return ret; 968 } 969 970 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); 971 if (ret) { 972 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 973 return ret; 974 } 975 976 return 0; 977 } 978 979 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 980 struct device *master, 981 void *data) 982 { 983 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 984 985 if (dsi->is_slave) 986 return; 987 988 dw_mipi_dsi_unbind(dsi->dmd); 989 990 clk_disable_unprepare(dsi->pllref_clk); 991 } 992 993 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 994 .bind = dw_mipi_dsi_rockchip_bind, 995 .unbind = dw_mipi_dsi_rockchip_unbind, 996 }; 997 998 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 999 struct mipi_dsi_device *device) 1000 { 1001 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1002 struct device *second; 1003 int ret; 1004 1005 mutex_lock(&dsi->usage_mutex); 1006 1007 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1008 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1009 mutex_unlock(&dsi->usage_mutex); 1010 return -EBUSY; 1011 } 1012 1013 dsi->usage_mode = DW_DSI_USAGE_DSI; 1014 mutex_unlock(&dsi->usage_mutex); 1015 1016 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1017 if (ret) { 1018 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1019 ret); 1020 return ret; 1021 } 1022 1023 second = dw_mipi_dsi_rockchip_find_second(dsi); 1024 if (IS_ERR(second)) 1025 return PTR_ERR(second); 1026 if (second) { 1027 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1028 if (ret) { 1029 DRM_DEV_ERROR(second, 1030 "Failed to register component: %d\n", 1031 ret); 1032 return ret; 1033 } 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1040 struct mipi_dsi_device *device) 1041 { 1042 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1043 struct device *second; 1044 1045 second = dw_mipi_dsi_rockchip_find_second(dsi); 1046 if (second && !IS_ERR(second)) 1047 component_del(second, &dw_mipi_dsi_rockchip_ops); 1048 1049 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1050 1051 mutex_lock(&dsi->usage_mutex); 1052 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1053 mutex_unlock(&dsi->usage_mutex); 1054 1055 return 0; 1056 } 1057 1058 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1059 .attach = dw_mipi_dsi_rockchip_host_attach, 1060 .detach = dw_mipi_dsi_rockchip_host_detach, 1061 }; 1062 1063 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1064 struct device *master, 1065 void *data) 1066 { 1067 /* 1068 * Nothing to do when used as a dphy. 1069 * Just make the rest of Rockchip-DRM happy 1070 * by being here. 1071 */ 1072 1073 return 0; 1074 } 1075 1076 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1077 struct device *master, 1078 void *data) 1079 { 1080 /* Nothing to do when used as a dphy. */ 1081 } 1082 1083 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1084 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1085 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1086 }; 1087 1088 static int dw_mipi_dsi_dphy_init(struct phy *phy) 1089 { 1090 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1091 int ret; 1092 1093 mutex_lock(&dsi->usage_mutex); 1094 1095 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1096 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1097 mutex_unlock(&dsi->usage_mutex); 1098 return -EBUSY; 1099 } 1100 1101 dsi->usage_mode = DW_DSI_USAGE_PHY; 1102 mutex_unlock(&dsi->usage_mutex); 1103 1104 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1105 if (ret < 0) 1106 goto err_graph; 1107 1108 if (dsi->cdata->dphy_rx_init) { 1109 ret = clk_prepare_enable(dsi->pclk); 1110 if (ret < 0) 1111 goto err_init; 1112 1113 ret = clk_prepare_enable(dsi->grf_clk); 1114 if (ret) { 1115 clk_disable_unprepare(dsi->pclk); 1116 goto err_init; 1117 } 1118 1119 ret = dsi->cdata->dphy_rx_init(phy); 1120 clk_disable_unprepare(dsi->grf_clk); 1121 clk_disable_unprepare(dsi->pclk); 1122 if (ret < 0) 1123 goto err_init; 1124 } 1125 1126 return 0; 1127 1128 err_init: 1129 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1130 err_graph: 1131 mutex_lock(&dsi->usage_mutex); 1132 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1133 mutex_unlock(&dsi->usage_mutex); 1134 1135 return ret; 1136 } 1137 1138 static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1139 { 1140 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1141 1142 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1143 1144 mutex_lock(&dsi->usage_mutex); 1145 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1146 mutex_unlock(&dsi->usage_mutex); 1147 1148 return 0; 1149 } 1150 1151 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1152 { 1153 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1154 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1155 int ret; 1156 1157 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1158 if (ret) 1159 return ret; 1160 1161 dsi->dphy_config = *config; 1162 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1163 1164 return 0; 1165 } 1166 1167 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1168 { 1169 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1170 int i, ret; 1171 1172 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1173 dsi->dphy_config.lanes, dsi->lane_mbps); 1174 1175 i = max_mbps_to_parameter(dsi->lane_mbps); 1176 if (i < 0) { 1177 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1178 dsi->lane_mbps); 1179 return i; 1180 } 1181 1182 ret = pm_runtime_get_sync(dsi->dev); 1183 if (ret < 0) { 1184 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1185 return ret; 1186 } 1187 1188 ret = clk_prepare_enable(dsi->pclk); 1189 if (ret) { 1190 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1191 goto err_pclk; 1192 } 1193 1194 ret = clk_prepare_enable(dsi->grf_clk); 1195 if (ret) { 1196 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1197 goto err_grf_clk; 1198 } 1199 1200 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1201 if (ret) { 1202 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1203 goto err_phy_cfg_clk; 1204 } 1205 1206 /* do soc-variant specific init */ 1207 if (dsi->cdata->dphy_rx_power_on) { 1208 ret = dsi->cdata->dphy_rx_power_on(phy); 1209 if (ret < 0) { 1210 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1211 goto err_pwr_on; 1212 } 1213 } 1214 1215 /* 1216 * Configure hsfreqrange according to frequency values 1217 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1218 */ 1219 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1220 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1221 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1222 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1223 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1224 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1225 1226 /* Normal operation */ 1227 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1228 1229 clk_disable_unprepare(dsi->phy_cfg_clk); 1230 clk_disable_unprepare(dsi->grf_clk); 1231 1232 return ret; 1233 1234 err_pwr_on: 1235 clk_disable_unprepare(dsi->phy_cfg_clk); 1236 err_phy_cfg_clk: 1237 clk_disable_unprepare(dsi->grf_clk); 1238 err_grf_clk: 1239 clk_disable_unprepare(dsi->pclk); 1240 err_pclk: 1241 pm_runtime_put(dsi->dev); 1242 return ret; 1243 } 1244 1245 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1246 { 1247 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1248 int ret; 1249 1250 ret = clk_prepare_enable(dsi->grf_clk); 1251 if (ret) { 1252 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1253 return ret; 1254 } 1255 1256 if (dsi->cdata->dphy_rx_power_off) { 1257 ret = dsi->cdata->dphy_rx_power_off(phy); 1258 if (ret < 0) 1259 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1260 } 1261 1262 clk_disable_unprepare(dsi->grf_clk); 1263 clk_disable_unprepare(dsi->pclk); 1264 1265 pm_runtime_put(dsi->dev); 1266 1267 return ret; 1268 } 1269 1270 static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1271 .configure = dw_mipi_dsi_dphy_configure, 1272 .power_on = dw_mipi_dsi_dphy_power_on, 1273 .power_off = dw_mipi_dsi_dphy_power_off, 1274 .init = dw_mipi_dsi_dphy_init, 1275 .exit = dw_mipi_dsi_dphy_exit, 1276 }; 1277 1278 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1279 { 1280 struct device *dev = &pdev->dev; 1281 struct device_node *np = dev->of_node; 1282 struct dw_mipi_dsi_rockchip *dsi; 1283 struct phy_provider *phy_provider; 1284 struct resource *res; 1285 const struct rockchip_dw_dsi_chip_data *cdata = 1286 of_device_get_match_data(dev); 1287 int ret, i; 1288 1289 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1290 if (!dsi) 1291 return -ENOMEM; 1292 1293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1294 dsi->base = devm_ioremap_resource(dev, res); 1295 if (IS_ERR(dsi->base)) { 1296 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1297 return PTR_ERR(dsi->base); 1298 } 1299 1300 i = 0; 1301 while (cdata[i].reg) { 1302 if (cdata[i].reg == res->start) { 1303 dsi->cdata = &cdata[i]; 1304 break; 1305 } 1306 1307 i++; 1308 } 1309 1310 if (!dsi->cdata) { 1311 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1312 return -EINVAL; 1313 } 1314 1315 /* try to get a possible external dphy */ 1316 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1317 if (IS_ERR(dsi->phy)) { 1318 ret = PTR_ERR(dsi->phy); 1319 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1320 return ret; 1321 } 1322 1323 dsi->pclk = devm_clk_get(dev, "pclk"); 1324 if (IS_ERR(dsi->pclk)) { 1325 ret = PTR_ERR(dsi->pclk); 1326 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1327 return ret; 1328 } 1329 1330 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1331 if (IS_ERR(dsi->pllref_clk)) { 1332 if (dsi->phy) { 1333 /* 1334 * if external phy is present, pll will be 1335 * generated there. 1336 */ 1337 dsi->pllref_clk = NULL; 1338 } else { 1339 ret = PTR_ERR(dsi->pllref_clk); 1340 DRM_DEV_ERROR(dev, 1341 "Unable to get pll reference clock: %d\n", 1342 ret); 1343 return ret; 1344 } 1345 } 1346 1347 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1348 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1349 if (IS_ERR(dsi->phy_cfg_clk)) { 1350 ret = PTR_ERR(dsi->phy_cfg_clk); 1351 DRM_DEV_ERROR(dev, 1352 "Unable to get phy_cfg_clk: %d\n", ret); 1353 return ret; 1354 } 1355 } 1356 1357 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1358 dsi->grf_clk = devm_clk_get(dev, "grf"); 1359 if (IS_ERR(dsi->grf_clk)) { 1360 ret = PTR_ERR(dsi->grf_clk); 1361 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1362 return ret; 1363 } 1364 } 1365 1366 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1367 if (IS_ERR(dsi->grf_regmap)) { 1368 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1369 return PTR_ERR(dsi->grf_regmap); 1370 } 1371 1372 dsi->dev = dev; 1373 dsi->pdata.base = dsi->base; 1374 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1375 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1376 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1377 dsi->pdata.priv_data = dsi; 1378 platform_set_drvdata(pdev, dsi); 1379 1380 mutex_init(&dsi->usage_mutex); 1381 1382 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1383 if (IS_ERR(dsi->dphy)) { 1384 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1385 return PTR_ERR(dsi->dphy); 1386 } 1387 1388 phy_set_drvdata(dsi->dphy, dsi); 1389 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1390 if (IS_ERR(phy_provider)) 1391 return PTR_ERR(phy_provider); 1392 1393 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1394 if (IS_ERR(dsi->dmd)) { 1395 ret = PTR_ERR(dsi->dmd); 1396 if (ret != -EPROBE_DEFER) 1397 DRM_DEV_ERROR(dev, 1398 "Failed to probe dw_mipi_dsi: %d\n", ret); 1399 goto err_clkdisable; 1400 } 1401 1402 return 0; 1403 1404 err_clkdisable: 1405 clk_disable_unprepare(dsi->pllref_clk); 1406 return ret; 1407 } 1408 1409 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1410 { 1411 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1412 1413 dw_mipi_dsi_remove(dsi->dmd); 1414 1415 return 0; 1416 } 1417 1418 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1419 { 1420 .reg = 0xff450000, 1421 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1422 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1423 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1424 PX30_DSI_LCDC_SEL), 1425 1426 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1427 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1428 PX30_DSI_FORCERXMODE | 1429 PX30_DSI_FORCETXSTOPMODE), 1430 1431 .max_data_lanes = 4, 1432 }, 1433 { /* sentinel */ } 1434 }; 1435 1436 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1437 { 1438 .reg = 0xff960000, 1439 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1440 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1441 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1442 1443 .max_data_lanes = 4, 1444 }, 1445 { 1446 .reg = 0xff964000, 1447 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1448 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1449 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1450 1451 .max_data_lanes = 4, 1452 }, 1453 { /* sentinel */ } 1454 }; 1455 1456 static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1457 { 1458 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1459 1460 /* 1461 * Set TX1RX1 source to isp1. 1462 * Assume ISP0 is supplied by the RX0 dphy. 1463 */ 1464 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1465 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); 1466 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1467 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1468 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1469 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR)); 1470 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1471 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1472 1473 return 0; 1474 } 1475 1476 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1477 { 1478 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1479 1480 /* tester reset pulse */ 1481 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1482 usleep_range(100, 150); 1483 1484 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1485 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1486 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1487 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR)); 1488 1489 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1490 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE)); 1491 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1492 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE)); 1493 1494 /* Disable lane turn around, which is ignored in receive mode */ 1495 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1496 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST)); 1497 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1498 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE, 1499 RK3399_DSI1_TURNDISABLE)); 1500 usleep_range(100, 150); 1501 1502 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1503 usleep_range(100, 150); 1504 1505 /* Enable dphy lanes */ 1506 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1507 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), 1508 RK3399_DSI1_ENABLE)); 1509 1510 usleep_range(100, 150); 1511 1512 return 0; 1513 } 1514 1515 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1516 { 1517 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1518 1519 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1520 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1521 1522 return 0; 1523 } 1524 1525 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1526 { 1527 .reg = 0xff960000, 1528 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1529 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1530 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1531 RK3399_DSI0_LCDC_SEL), 1532 1533 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1534 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1535 RK3399_DSI0_TURNDISABLE | 1536 RK3399_DSI0_FORCETXSTOPMODE | 1537 RK3399_DSI0_FORCERXMODE), 1538 1539 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1540 .max_data_lanes = 4, 1541 }, 1542 { 1543 .reg = 0xff968000, 1544 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1545 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1546 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1547 RK3399_DSI1_LCDC_SEL), 1548 1549 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1550 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1551 RK3399_DSI1_FORCETXSTOPMODE | 1552 RK3399_DSI1_FORCERXMODE | 1553 RK3399_DSI1_ENABLE), 1554 1555 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1556 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1557 RK3399_TXRX_ENABLECLK, 1558 RK3399_TXRX_MASTERSLAVEZ | 1559 RK3399_TXRX_ENABLECLK | 1560 RK3399_TXRX_BASEDIR), 1561 1562 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1563 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1564 1565 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1566 .max_data_lanes = 4, 1567 1568 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1569 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1570 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1571 }, 1572 { /* sentinel */ } 1573 }; 1574 1575 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1576 { 1577 .compatible = "rockchip,px30-mipi-dsi", 1578 .data = &px30_chip_data, 1579 }, { 1580 .compatible = "rockchip,rk3288-mipi-dsi", 1581 .data = &rk3288_chip_data, 1582 }, { 1583 .compatible = "rockchip,rk3399-mipi-dsi", 1584 .data = &rk3399_chip_data, 1585 }, 1586 { /* sentinel */ } 1587 }; 1588 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1589 1590 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1591 .probe = dw_mipi_dsi_rockchip_probe, 1592 .remove = dw_mipi_dsi_rockchip_remove, 1593 .driver = { 1594 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1595 .name = "dw-mipi-dsi-rockchip", 1596 }, 1597 }; 1598