1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/math64.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/phy/phy.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/bridge/dw_mipi_dsi.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #include "rockchip_drm_drv.h" 27 #include "rockchip_drm_vop.h" 28 29 #define DSI_PHY_RSTZ 0xa0 30 #define PHY_DISFORCEPLL 0 31 #define PHY_ENFORCEPLL BIT(3) 32 #define PHY_DISABLECLK 0 33 #define PHY_ENABLECLK BIT(2) 34 #define PHY_RSTZ 0 35 #define PHY_UNRSTZ BIT(1) 36 #define PHY_SHUTDOWNZ 0 37 #define PHY_UNSHUTDOWNZ BIT(0) 38 39 #define DSI_PHY_IF_CFG 0xa4 40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 41 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 42 43 #define DSI_PHY_STATUS 0xb0 44 #define LOCK BIT(0) 45 #define STOP_STATE_CLK_LANE BIT(2) 46 47 #define DSI_PHY_TST_CTRL0 0xb4 48 #define PHY_TESTCLK BIT(1) 49 #define PHY_UNTESTCLK 0 50 #define PHY_TESTCLR BIT(0) 51 #define PHY_UNTESTCLR 0 52 53 #define DSI_PHY_TST_CTRL1 0xb8 54 #define PHY_TESTEN BIT(16) 55 #define PHY_UNTESTEN 0 56 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 57 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 58 59 #define DSI_INT_ST0 0xbc 60 #define DSI_INT_ST1 0xc0 61 #define DSI_INT_MSK0 0xc4 62 #define DSI_INT_MSK1 0xc8 63 64 #define PHY_STATUS_TIMEOUT_US 10000 65 #define CMD_PKT_STATUS_TIMEOUT_US 20000 66 67 #define BYPASS_VCO_RANGE BIT(7) 68 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 69 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 70 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 71 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 72 #define REF_BIAS_CUR_SEL BIT(0) 73 74 #define CP_CURRENT_3UA 0x1 75 #define CP_CURRENT_4_5UA 0x2 76 #define CP_CURRENT_7_5UA 0x6 77 #define CP_CURRENT_6UA 0x9 78 #define CP_CURRENT_12UA 0xb 79 #define CP_CURRENT_SEL(val) ((val) & 0xf) 80 #define CP_PROGRAM_EN BIT(7) 81 82 #define LPF_RESISTORS_15_5KOHM 0x1 83 #define LPF_RESISTORS_13KOHM 0x2 84 #define LPF_RESISTORS_11_5KOHM 0x4 85 #define LPF_RESISTORS_10_5KOHM 0x8 86 #define LPF_RESISTORS_8KOHM 0x10 87 #define LPF_PROGRAM_EN BIT(6) 88 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 89 90 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 91 92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 93 #define LOW_PROGRAM_EN 0 94 #define HIGH_PROGRAM_EN BIT(7) 95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 97 #define PLL_LOOP_DIV_EN BIT(5) 98 #define PLL_INPUT_DIV_EN BIT(4) 99 100 #define POWER_CONTROL BIT(6) 101 #define INTERNAL_REG_CURRENT BIT(3) 102 #define BIAS_BLOCK_ON BIT(2) 103 #define BANDGAP_ON BIT(0) 104 105 #define TER_RESISTOR_HIGH BIT(7) 106 #define TER_RESISTOR_LOW 0 107 #define LEVEL_SHIFTERS_ON BIT(6) 108 #define TER_CAL_DONE BIT(5) 109 #define SETRD_MAX (0x7 << 2) 110 #define POWER_MANAGE BIT(1) 111 #define TER_RESISTORS_ON BIT(0) 112 113 #define BIASEXTR_SEL(val) ((val) & 0x7) 114 #define BANDGAP_SEL(val) ((val) & 0x7) 115 #define TLP_PROGRAM_EN BIT(7) 116 #define THS_PRE_PROGRAM_EN BIT(7) 117 #define THS_ZERO_PROGRAM_EN BIT(6) 118 119 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 120 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 121 #define PLL_LPF_AND_CP_CONTROL 0x12 122 #define PLL_INPUT_DIVIDER_RATIO 0x17 123 #define PLL_LOOP_DIVIDER_RATIO 0x18 124 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 125 #define BANDGAP_AND_BIAS_CONTROL 0x20 126 #define TERMINATION_RESISTER_CONTROL 0x21 127 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 128 #define HS_RX_CONTROL_OF_LANE_CLK 0x34 129 #define HS_RX_CONTROL_OF_LANE_0 0x44 130 #define HS_RX_CONTROL_OF_LANE_1 0x54 131 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 132 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 133 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 134 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 135 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 136 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 137 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 138 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 139 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 140 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 141 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 142 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 143 #define HS_RX_CONTROL_OF_LANE_2 0x84 144 #define HS_RX_CONTROL_OF_LANE_3 0x94 145 146 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 147 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 148 149 #define PX30_GRF_PD_VO_CON1 0x0438 150 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 151 #define PX30_DSI_FORCERXMODE BIT(6) 152 #define PX30_DSI_TURNDISABLE BIT(5) 153 #define PX30_DSI_LCDC_SEL BIT(0) 154 155 #define RK3288_GRF_SOC_CON6 0x025c 156 #define RK3288_DSI0_LCDC_SEL BIT(6) 157 #define RK3288_DSI1_LCDC_SEL BIT(9) 158 159 #define RK3399_GRF_SOC_CON20 0x6250 160 #define RK3399_DSI0_LCDC_SEL BIT(0) 161 #define RK3399_DSI1_LCDC_SEL BIT(4) 162 163 #define RK3399_GRF_SOC_CON22 0x6258 164 #define RK3399_DSI0_TURNREQUEST (0xf << 12) 165 #define RK3399_DSI0_TURNDISABLE (0xf << 8) 166 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 167 #define RK3399_DSI0_FORCERXMODE (0xf << 0) 168 169 #define RK3399_GRF_SOC_CON23 0x625c 170 #define RK3399_DSI1_TURNDISABLE (0xf << 12) 171 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 172 #define RK3399_DSI1_FORCERXMODE (0xf << 4) 173 #define RK3399_DSI1_ENABLE (0xf << 0) 174 175 #define RK3399_GRF_SOC_CON24 0x6260 176 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 177 #define RK3399_TXRX_ENABLECLK BIT(6) 178 #define RK3399_TXRX_BASEDIR BIT(5) 179 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 180 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 181 182 #define RK3568_GRF_VO_CON2 0x0368 183 #define RK3568_DSI0_SKEWCALHS (0x1f << 11) 184 #define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) 185 #define RK3568_DSI0_TURNDISABLE BIT(2) 186 #define RK3568_DSI0_FORCERXMODE BIT(0) 187 188 /* 189 * Note these registers do not appear in the datasheet, they are 190 * however present in the BSP driver which is where these values 191 * come from. Name GRF_VO_CON3 is assumed. 192 */ 193 #define RK3568_GRF_VO_CON3 0x36c 194 #define RK3568_DSI1_SKEWCALHS (0x1f << 11) 195 #define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4) 196 #define RK3568_DSI1_TURNDISABLE BIT(2) 197 #define RK3568_DSI1_FORCERXMODE BIT(0) 198 199 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 200 201 enum { 202 DW_DSI_USAGE_IDLE, 203 DW_DSI_USAGE_DSI, 204 DW_DSI_USAGE_PHY, 205 }; 206 207 enum { 208 BANDGAP_97_07, 209 BANDGAP_98_05, 210 BANDGAP_99_02, 211 BANDGAP_100_00, 212 BANDGAP_93_17, 213 BANDGAP_94_15, 214 BANDGAP_95_12, 215 BANDGAP_96_10, 216 }; 217 218 enum { 219 BIASEXTR_87_1, 220 BIASEXTR_91_5, 221 BIASEXTR_95_9, 222 BIASEXTR_100, 223 BIASEXTR_105_94, 224 BIASEXTR_111_88, 225 BIASEXTR_118_8, 226 BIASEXTR_127_7, 227 }; 228 229 struct rockchip_dw_dsi_chip_data { 230 u32 reg; 231 232 u32 lcdsel_grf_reg; 233 u32 lcdsel_big; 234 u32 lcdsel_lit; 235 236 u32 enable_grf_reg; 237 u32 enable; 238 239 u32 lanecfg1_grf_reg; 240 u32 lanecfg1; 241 u32 lanecfg2_grf_reg; 242 u32 lanecfg2; 243 244 int (*dphy_rx_init)(struct phy *phy); 245 int (*dphy_rx_power_on)(struct phy *phy); 246 int (*dphy_rx_power_off)(struct phy *phy); 247 248 unsigned int flags; 249 unsigned int max_data_lanes; 250 }; 251 252 struct dw_mipi_dsi_rockchip { 253 struct device *dev; 254 struct rockchip_encoder encoder; 255 void __iomem *base; 256 257 struct regmap *grf_regmap; 258 struct clk *pclk; 259 struct clk *pllref_clk; 260 struct clk *grf_clk; 261 struct clk *phy_cfg_clk; 262 263 /* dual-channel */ 264 bool is_slave; 265 struct dw_mipi_dsi_rockchip *slave; 266 267 /* optional external dphy */ 268 struct phy *phy; 269 union phy_configure_opts phy_opts; 270 271 /* being a phy for other mipi hosts */ 272 unsigned int usage_mode; 273 struct mutex usage_mutex; 274 struct phy *dphy; 275 struct phy_configure_opts_mipi_dphy dphy_config; 276 277 unsigned int lane_mbps; /* per lane */ 278 u16 input_div; 279 u16 feedback_div; 280 u32 format; 281 282 struct dw_mipi_dsi *dmd; 283 const struct rockchip_dw_dsi_chip_data *cdata; 284 struct dw_mipi_dsi_plat_data pdata; 285 286 bool dsi_bound; 287 }; 288 289 static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) 290 { 291 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 292 293 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); 294 } 295 296 struct dphy_pll_parameter_map { 297 unsigned int max_mbps; 298 u8 hsfreqrange; 299 u8 icpctrl; 300 u8 lpfctrl; 301 }; 302 303 /* The table is based on 27MHz DPHY pll reference clock. */ 304 static const struct dphy_pll_parameter_map dppa_map[] = { 305 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 306 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 307 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 308 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 309 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 310 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 311 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 312 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 313 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 314 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 315 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 316 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 317 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 318 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 319 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 320 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 321 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 322 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 323 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 324 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 325 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 326 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 327 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 328 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 329 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 330 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 331 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 332 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 333 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 334 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 335 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 336 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 337 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 338 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 339 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 340 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 341 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 342 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 343 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 344 }; 345 346 static int max_mbps_to_parameter(unsigned int max_mbps) 347 { 348 int i; 349 350 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 351 if (dppa_map[i].max_mbps >= max_mbps) 352 return i; 353 354 return -EINVAL; 355 } 356 357 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 358 { 359 writel(val, dsi->base + reg); 360 } 361 362 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 363 u8 test_code, 364 u8 test_data) 365 { 366 /* 367 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 368 * is latched internally as the current test code. Test data is 369 * programmed internally by rising edge on TESTCLK. 370 */ 371 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 372 373 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 374 PHY_TESTDIN(test_code)); 375 376 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 377 378 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 379 PHY_TESTDIN(test_data)); 380 381 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 382 } 383 384 /* 385 * ns2bc - Nanoseconds to byte clock cycles 386 */ 387 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 388 { 389 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 390 } 391 392 /* 393 * ns2ui - Nanoseconds to UI time periods 394 */ 395 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 396 { 397 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 398 } 399 400 static int dw_mipi_dsi_phy_init(void *priv_data) 401 { 402 struct dw_mipi_dsi_rockchip *dsi = priv_data; 403 int ret, i, vco; 404 405 if (dsi->phy) 406 return 0; 407 408 /* 409 * Get vco from frequency(lane_mbps) 410 * vco frequency table 411 * 000 - between 80 and 200 MHz 412 * 001 - between 200 and 300 MHz 413 * 010 - between 300 and 500 MHz 414 * 011 - between 500 and 700 MHz 415 * 100 - between 700 and 900 MHz 416 * 101 - between 900 and 1100 MHz 417 * 110 - between 1100 and 1300 MHz 418 * 111 - between 1300 and 1500 MHz 419 */ 420 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 421 422 i = max_mbps_to_parameter(dsi->lane_mbps); 423 if (i < 0) { 424 DRM_DEV_ERROR(dsi->dev, 425 "failed to get parameter for %dmbps clock\n", 426 dsi->lane_mbps); 427 return i; 428 } 429 430 ret = clk_prepare_enable(dsi->phy_cfg_clk); 431 if (ret) { 432 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 433 return ret; 434 } 435 436 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 437 BYPASS_VCO_RANGE | 438 VCO_RANGE_CON_SEL(vco) | 439 VCO_IN_CAP_CON_LOW | 440 REF_BIAS_CUR_SEL); 441 442 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 443 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 444 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 445 CP_PROGRAM_EN | LPF_PROGRAM_EN | 446 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 447 448 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 449 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 450 451 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 452 INPUT_DIVIDER(dsi->input_div)); 453 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 454 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 455 LOW_PROGRAM_EN); 456 /* 457 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 458 * to make the configured LSB effective according to IP simulation 459 * and lab test results. 460 * Only in this way can we get correct mipi phy pll frequency. 461 */ 462 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 463 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 464 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 465 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 466 HIGH_PROGRAM_EN); 467 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 468 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 469 470 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 471 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 472 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 473 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 474 475 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 476 POWER_CONTROL | INTERNAL_REG_CURRENT | 477 BIAS_BLOCK_ON | BANDGAP_ON); 478 479 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 480 TER_RESISTOR_LOW | TER_CAL_DONE | 481 SETRD_MAX | TER_RESISTORS_ON); 482 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 483 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 484 SETRD_MAX | POWER_MANAGE | 485 TER_RESISTORS_ON); 486 487 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 488 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 489 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 490 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 491 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 492 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 493 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 494 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 495 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 496 BIT(5) | ns2bc(dsi, 100)); 497 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 498 BIT(5) | (ns2bc(dsi, 60) + 7)); 499 500 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 501 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 502 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 503 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 504 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 505 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 506 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 507 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 508 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 509 BIT(5) | ns2bc(dsi, 100)); 510 511 clk_disable_unprepare(dsi->phy_cfg_clk); 512 513 return ret; 514 } 515 516 static void dw_mipi_dsi_phy_power_on(void *priv_data) 517 { 518 struct dw_mipi_dsi_rockchip *dsi = priv_data; 519 int ret; 520 521 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 522 if (ret) { 523 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 524 return; 525 } 526 527 phy_configure(dsi->phy, &dsi->phy_opts); 528 phy_power_on(dsi->phy); 529 } 530 531 static void dw_mipi_dsi_phy_power_off(void *priv_data) 532 { 533 struct dw_mipi_dsi_rockchip *dsi = priv_data; 534 535 phy_power_off(dsi->phy); 536 } 537 538 static int 539 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 540 unsigned long mode_flags, u32 lanes, u32 format, 541 unsigned int *lane_mbps) 542 { 543 struct dw_mipi_dsi_rockchip *dsi = priv_data; 544 int bpp; 545 unsigned long mpclk, tmp; 546 unsigned int target_mbps = 1000; 547 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 548 unsigned long best_freq = 0; 549 unsigned long fvco_min, fvco_max, fin, fout; 550 unsigned int min_prediv, max_prediv; 551 unsigned int _prediv, best_prediv; 552 unsigned long _fbdiv, best_fbdiv; 553 unsigned long min_delta = ULONG_MAX; 554 555 dsi->format = format; 556 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 557 if (bpp < 0) { 558 DRM_DEV_ERROR(dsi->dev, 559 "failed to get bpp for pixel format %d\n", 560 dsi->format); 561 return bpp; 562 } 563 564 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 565 if (mpclk) { 566 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 567 tmp = mpclk * (bpp / lanes) * 10 / 8; 568 if (tmp < max_mbps) 569 target_mbps = tmp; 570 else 571 DRM_DEV_ERROR(dsi->dev, 572 "DPHY clock frequency is out of range\n"); 573 } 574 575 /* for external phy only a the mipi_dphy_config is necessary */ 576 if (dsi->phy) { 577 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 578 bpp, lanes, 579 &dsi->phy_opts.mipi_dphy); 580 dsi->lane_mbps = target_mbps; 581 *lane_mbps = dsi->lane_mbps; 582 583 return 0; 584 } 585 586 fin = clk_get_rate(dsi->pllref_clk); 587 fout = target_mbps * USEC_PER_SEC; 588 589 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 590 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 591 max_prediv = fin / (5 * USEC_PER_SEC); 592 593 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 594 fvco_min = 80 * USEC_PER_SEC; 595 fvco_max = 1500 * USEC_PER_SEC; 596 597 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 598 u64 tmp; 599 u32 delta; 600 /* Fvco = Fref * M / N */ 601 tmp = (u64)fout * _prediv; 602 do_div(tmp, fin); 603 _fbdiv = tmp; 604 /* 605 * Due to the use of a "by 2 pre-scaler," the range of the 606 * feedback multiplication value M is limited to even division 607 * numbers, and m must be greater than 6, not bigger than 512. 608 */ 609 if (_fbdiv < 6 || _fbdiv > 512) 610 continue; 611 612 _fbdiv += _fbdiv % 2; 613 614 tmp = (u64)_fbdiv * fin; 615 do_div(tmp, _prediv); 616 if (tmp < fvco_min || tmp > fvco_max) 617 continue; 618 619 delta = abs(fout - tmp); 620 if (delta < min_delta) { 621 best_prediv = _prediv; 622 best_fbdiv = _fbdiv; 623 min_delta = delta; 624 best_freq = tmp; 625 } 626 } 627 628 if (best_freq) { 629 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 630 *lane_mbps = dsi->lane_mbps; 631 dsi->input_div = best_prediv; 632 dsi->feedback_div = best_fbdiv; 633 } else { 634 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 635 return -EINVAL; 636 } 637 638 return 0; 639 } 640 641 struct hstt { 642 unsigned int maxfreq; 643 struct dw_mipi_dsi_dphy_timing timing; 644 }; 645 646 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 647 { \ 648 .maxfreq = _maxfreq, \ 649 .timing = { \ 650 .clk_lp2hs = _c_lp2hs, \ 651 .clk_hs2lp = _c_hs2lp, \ 652 .data_lp2hs = _d_lp2hs, \ 653 .data_hs2lp = _d_hs2lp, \ 654 } \ 655 } 656 657 /* Table A-3 High-Speed Transition Times */ 658 static struct hstt hstt_table[] = { 659 HSTT( 90, 32, 20, 26, 13), 660 HSTT( 100, 35, 23, 28, 14), 661 HSTT( 110, 32, 22, 26, 13), 662 HSTT( 130, 31, 20, 27, 13), 663 HSTT( 140, 33, 22, 26, 14), 664 HSTT( 150, 33, 21, 26, 14), 665 HSTT( 170, 32, 20, 27, 13), 666 HSTT( 180, 36, 23, 30, 15), 667 HSTT( 200, 40, 22, 33, 15), 668 HSTT( 220, 40, 22, 33, 15), 669 HSTT( 240, 44, 24, 36, 16), 670 HSTT( 250, 48, 24, 38, 17), 671 HSTT( 270, 48, 24, 38, 17), 672 HSTT( 300, 50, 27, 41, 18), 673 HSTT( 330, 56, 28, 45, 18), 674 HSTT( 360, 59, 28, 48, 19), 675 HSTT( 400, 61, 30, 50, 20), 676 HSTT( 450, 67, 31, 55, 21), 677 HSTT( 500, 73, 31, 59, 22), 678 HSTT( 550, 79, 36, 63, 24), 679 HSTT( 600, 83, 37, 68, 25), 680 HSTT( 650, 90, 38, 73, 27), 681 HSTT( 700, 95, 40, 77, 28), 682 HSTT( 750, 102, 40, 84, 28), 683 HSTT( 800, 106, 42, 87, 30), 684 HSTT( 850, 113, 44, 93, 31), 685 HSTT( 900, 118, 47, 98, 32), 686 HSTT( 950, 124, 47, 102, 34), 687 HSTT(1000, 130, 49, 107, 35), 688 HSTT(1050, 135, 51, 111, 37), 689 HSTT(1100, 139, 51, 114, 38), 690 HSTT(1150, 146, 54, 120, 40), 691 HSTT(1200, 153, 57, 125, 41), 692 HSTT(1250, 158, 58, 130, 42), 693 HSTT(1300, 163, 58, 135, 44), 694 HSTT(1350, 168, 60, 140, 45), 695 HSTT(1400, 172, 64, 144, 47), 696 HSTT(1450, 176, 65, 148, 48), 697 HSTT(1500, 181, 66, 153, 50) 698 }; 699 700 static int 701 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 702 struct dw_mipi_dsi_dphy_timing *timing) 703 { 704 int i; 705 706 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 707 if (lane_mbps < hstt_table[i].maxfreq) 708 break; 709 710 if (i == ARRAY_SIZE(hstt_table)) 711 i--; 712 713 *timing = hstt_table[i].timing; 714 715 return 0; 716 } 717 718 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 719 .init = dw_mipi_dsi_phy_init, 720 .power_on = dw_mipi_dsi_phy_power_on, 721 .power_off = dw_mipi_dsi_phy_power_off, 722 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 723 .get_timing = dw_mipi_dsi_phy_get_timing, 724 }; 725 726 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 727 { 728 if (dsi->cdata->lanecfg1_grf_reg) 729 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 730 dsi->cdata->lanecfg1); 731 732 if (dsi->cdata->lanecfg2_grf_reg) 733 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 734 dsi->cdata->lanecfg2); 735 736 if (dsi->cdata->enable_grf_reg) 737 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 738 dsi->cdata->enable); 739 } 740 741 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 742 int mux) 743 { 744 if (dsi->cdata->lcdsel_grf_reg) 745 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 746 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 747 } 748 749 static int 750 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 751 struct drm_crtc_state *crtc_state, 752 struct drm_connector_state *conn_state) 753 { 754 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 755 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 756 757 switch (dsi->format) { 758 case MIPI_DSI_FMT_RGB888: 759 s->output_mode = ROCKCHIP_OUT_MODE_P888; 760 break; 761 case MIPI_DSI_FMT_RGB666: 762 s->output_mode = ROCKCHIP_OUT_MODE_P666; 763 break; 764 case MIPI_DSI_FMT_RGB565: 765 s->output_mode = ROCKCHIP_OUT_MODE_P565; 766 break; 767 default: 768 WARN_ON(1); 769 return -EINVAL; 770 } 771 772 s->output_type = DRM_MODE_CONNECTOR_DSI; 773 if (dsi->slave) 774 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 775 776 return 0; 777 } 778 779 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 780 { 781 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 782 int ret, mux; 783 784 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 785 &dsi->encoder.encoder); 786 if (mux < 0) 787 return; 788 789 /* 790 * For the RK3399, the clk of grf must be enabled before writing grf 791 * register. And for RK3288 or other soc, this grf_clk must be NULL, 792 * the clk_prepare_enable return true directly. 793 */ 794 ret = clk_prepare_enable(dsi->grf_clk); 795 if (ret) { 796 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 797 return; 798 } 799 800 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 801 if (dsi->slave) 802 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 803 804 clk_disable_unprepare(dsi->grf_clk); 805 } 806 807 static const struct drm_encoder_helper_funcs 808 dw_mipi_dsi_encoder_helper_funcs = { 809 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 810 .enable = dw_mipi_dsi_encoder_enable, 811 }; 812 813 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 814 struct drm_device *drm_dev) 815 { 816 struct drm_encoder *encoder = &dsi->encoder.encoder; 817 int ret; 818 819 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 820 dsi->dev->of_node); 821 822 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 823 if (ret) { 824 DRM_ERROR("Failed to initialize encoder with drm\n"); 825 return ret; 826 } 827 828 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 829 830 return 0; 831 } 832 833 static struct device 834 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 835 { 836 const struct of_device_id *match; 837 struct device_node *node = NULL, *local; 838 839 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 840 841 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 842 if (!local) 843 return NULL; 844 845 while ((node = of_find_compatible_node(node, NULL, 846 match->compatible))) { 847 struct device_node *remote; 848 849 /* found ourself */ 850 if (node == dsi->dev->of_node) 851 continue; 852 853 remote = of_graph_get_remote_node(node, 1, 0); 854 if (!remote) 855 continue; 856 857 /* same display device in port1-ep0 for both */ 858 if (remote == local) { 859 struct dw_mipi_dsi_rockchip *dsi2; 860 struct platform_device *pdev; 861 862 pdev = of_find_device_by_node(node); 863 864 /* 865 * we have found the second, so will either return it 866 * or return with an error. In any case won't need the 867 * nodes anymore nor continue the loop. 868 */ 869 of_node_put(remote); 870 of_node_put(node); 871 of_node_put(local); 872 873 if (!pdev) 874 return ERR_PTR(-EPROBE_DEFER); 875 876 dsi2 = platform_get_drvdata(pdev); 877 if (!dsi2) { 878 platform_device_put(pdev); 879 return ERR_PTR(-EPROBE_DEFER); 880 } 881 882 return &pdev->dev; 883 } 884 885 of_node_put(remote); 886 } 887 888 of_node_put(local); 889 890 return NULL; 891 } 892 893 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 894 struct device *master, 895 void *data) 896 { 897 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 898 struct drm_device *drm_dev = data; 899 struct device *second; 900 bool master1, master2; 901 int ret; 902 903 second = dw_mipi_dsi_rockchip_find_second(dsi); 904 if (IS_ERR(second)) 905 return PTR_ERR(second); 906 907 if (second) { 908 master1 = of_property_read_bool(dsi->dev->of_node, 909 "clock-master"); 910 master2 = of_property_read_bool(second->of_node, 911 "clock-master"); 912 913 if (master1 && master2) { 914 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 915 return -EINVAL; 916 } 917 918 if (!master1 && !master2) { 919 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 920 return -EINVAL; 921 } 922 923 /* we are the slave in dual-DSI */ 924 if (!master1) { 925 dsi->is_slave = true; 926 return 0; 927 } 928 929 dsi->slave = dev_get_drvdata(second); 930 if (!dsi->slave) { 931 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 932 return -ENODEV; 933 } 934 935 dsi->slave->is_slave = true; 936 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 937 put_device(second); 938 } 939 940 pm_runtime_get_sync(dsi->dev); 941 if (dsi->slave) 942 pm_runtime_get_sync(dsi->slave->dev); 943 944 ret = clk_prepare_enable(dsi->pllref_clk); 945 if (ret) { 946 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 947 goto out_pm_runtime; 948 } 949 950 /* 951 * With the GRF clock running, write lane and dual-mode configurations 952 * that won't change immediately. If we waited until enable() to do 953 * this, things like panel preparation would not be able to send 954 * commands over DSI. 955 */ 956 ret = clk_prepare_enable(dsi->grf_clk); 957 if (ret) { 958 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 959 goto out_pll_clk; 960 } 961 962 dw_mipi_dsi_rockchip_config(dsi); 963 if (dsi->slave) 964 dw_mipi_dsi_rockchip_config(dsi->slave); 965 966 clk_disable_unprepare(dsi->grf_clk); 967 968 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 969 if (ret) { 970 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 971 goto out_pll_clk; 972 } 973 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, 974 dev->of_node, 0, 0); 975 976 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); 977 if (ret) { 978 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 979 goto out_pll_clk; 980 } 981 982 dsi->dsi_bound = true; 983 984 return 0; 985 986 out_pll_clk: 987 clk_disable_unprepare(dsi->pllref_clk); 988 out_pm_runtime: 989 pm_runtime_put(dsi->dev); 990 if (dsi->slave) 991 pm_runtime_put(dsi->slave->dev); 992 993 return ret; 994 } 995 996 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 997 struct device *master, 998 void *data) 999 { 1000 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1001 1002 if (dsi->is_slave) 1003 return; 1004 1005 dsi->dsi_bound = false; 1006 1007 dw_mipi_dsi_unbind(dsi->dmd); 1008 1009 clk_disable_unprepare(dsi->pllref_clk); 1010 1011 pm_runtime_put(dsi->dev); 1012 if (dsi->slave) 1013 pm_runtime_put(dsi->slave->dev); 1014 } 1015 1016 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1017 .bind = dw_mipi_dsi_rockchip_bind, 1018 .unbind = dw_mipi_dsi_rockchip_unbind, 1019 }; 1020 1021 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1022 struct mipi_dsi_device *device) 1023 { 1024 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1025 struct device *second; 1026 int ret; 1027 1028 mutex_lock(&dsi->usage_mutex); 1029 1030 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1031 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1032 mutex_unlock(&dsi->usage_mutex); 1033 return -EBUSY; 1034 } 1035 1036 dsi->usage_mode = DW_DSI_USAGE_DSI; 1037 mutex_unlock(&dsi->usage_mutex); 1038 1039 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1040 if (ret) { 1041 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1042 ret); 1043 goto out; 1044 } 1045 1046 second = dw_mipi_dsi_rockchip_find_second(dsi); 1047 if (IS_ERR(second)) { 1048 ret = PTR_ERR(second); 1049 goto out; 1050 } 1051 if (second) { 1052 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1053 if (ret) { 1054 DRM_DEV_ERROR(second, 1055 "Failed to register component: %d\n", 1056 ret); 1057 goto out; 1058 } 1059 } 1060 1061 return 0; 1062 1063 out: 1064 mutex_lock(&dsi->usage_mutex); 1065 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1066 mutex_unlock(&dsi->usage_mutex); 1067 return ret; 1068 } 1069 1070 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1071 struct mipi_dsi_device *device) 1072 { 1073 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1074 struct device *second; 1075 1076 second = dw_mipi_dsi_rockchip_find_second(dsi); 1077 if (second && !IS_ERR(second)) 1078 component_del(second, &dw_mipi_dsi_rockchip_ops); 1079 1080 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1081 1082 mutex_lock(&dsi->usage_mutex); 1083 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1084 mutex_unlock(&dsi->usage_mutex); 1085 1086 return 0; 1087 } 1088 1089 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1090 .attach = dw_mipi_dsi_rockchip_host_attach, 1091 .detach = dw_mipi_dsi_rockchip_host_detach, 1092 }; 1093 1094 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1095 struct device *master, 1096 void *data) 1097 { 1098 /* 1099 * Nothing to do when used as a dphy. 1100 * Just make the rest of Rockchip-DRM happy 1101 * by being here. 1102 */ 1103 1104 return 0; 1105 } 1106 1107 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1108 struct device *master, 1109 void *data) 1110 { 1111 /* Nothing to do when used as a dphy. */ 1112 } 1113 1114 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1115 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1116 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1117 }; 1118 1119 static int dw_mipi_dsi_dphy_init(struct phy *phy) 1120 { 1121 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1122 int ret; 1123 1124 mutex_lock(&dsi->usage_mutex); 1125 1126 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1127 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1128 mutex_unlock(&dsi->usage_mutex); 1129 return -EBUSY; 1130 } 1131 1132 dsi->usage_mode = DW_DSI_USAGE_PHY; 1133 mutex_unlock(&dsi->usage_mutex); 1134 1135 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1136 if (ret < 0) 1137 goto err_graph; 1138 1139 if (dsi->cdata->dphy_rx_init) { 1140 ret = clk_prepare_enable(dsi->pclk); 1141 if (ret < 0) 1142 goto err_init; 1143 1144 ret = clk_prepare_enable(dsi->grf_clk); 1145 if (ret) { 1146 clk_disable_unprepare(dsi->pclk); 1147 goto err_init; 1148 } 1149 1150 ret = dsi->cdata->dphy_rx_init(phy); 1151 clk_disable_unprepare(dsi->grf_clk); 1152 clk_disable_unprepare(dsi->pclk); 1153 if (ret < 0) 1154 goto err_init; 1155 } 1156 1157 return 0; 1158 1159 err_init: 1160 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1161 err_graph: 1162 mutex_lock(&dsi->usage_mutex); 1163 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1164 mutex_unlock(&dsi->usage_mutex); 1165 1166 return ret; 1167 } 1168 1169 static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1170 { 1171 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1172 1173 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1174 1175 mutex_lock(&dsi->usage_mutex); 1176 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1177 mutex_unlock(&dsi->usage_mutex); 1178 1179 return 0; 1180 } 1181 1182 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1183 { 1184 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1185 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1186 int ret; 1187 1188 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1189 if (ret) 1190 return ret; 1191 1192 dsi->dphy_config = *config; 1193 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1194 1195 return 0; 1196 } 1197 1198 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1199 { 1200 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1201 int i, ret; 1202 1203 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1204 dsi->dphy_config.lanes, dsi->lane_mbps); 1205 1206 i = max_mbps_to_parameter(dsi->lane_mbps); 1207 if (i < 0) { 1208 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1209 dsi->lane_mbps); 1210 return i; 1211 } 1212 1213 ret = pm_runtime_resume_and_get(dsi->dev); 1214 if (ret < 0) { 1215 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1216 return ret; 1217 } 1218 1219 ret = clk_prepare_enable(dsi->pclk); 1220 if (ret) { 1221 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1222 goto err_pclk; 1223 } 1224 1225 ret = clk_prepare_enable(dsi->grf_clk); 1226 if (ret) { 1227 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1228 goto err_grf_clk; 1229 } 1230 1231 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1232 if (ret) { 1233 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1234 goto err_phy_cfg_clk; 1235 } 1236 1237 /* do soc-variant specific init */ 1238 if (dsi->cdata->dphy_rx_power_on) { 1239 ret = dsi->cdata->dphy_rx_power_on(phy); 1240 if (ret < 0) { 1241 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1242 goto err_pwr_on; 1243 } 1244 } 1245 1246 /* 1247 * Configure hsfreqrange according to frequency values 1248 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1249 */ 1250 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1251 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1252 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1253 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1254 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1255 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1256 1257 /* Normal operation */ 1258 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1259 1260 clk_disable_unprepare(dsi->phy_cfg_clk); 1261 clk_disable_unprepare(dsi->grf_clk); 1262 1263 return ret; 1264 1265 err_pwr_on: 1266 clk_disable_unprepare(dsi->phy_cfg_clk); 1267 err_phy_cfg_clk: 1268 clk_disable_unprepare(dsi->grf_clk); 1269 err_grf_clk: 1270 clk_disable_unprepare(dsi->pclk); 1271 err_pclk: 1272 pm_runtime_put(dsi->dev); 1273 return ret; 1274 } 1275 1276 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1277 { 1278 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1279 int ret; 1280 1281 ret = clk_prepare_enable(dsi->grf_clk); 1282 if (ret) { 1283 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1284 return ret; 1285 } 1286 1287 if (dsi->cdata->dphy_rx_power_off) { 1288 ret = dsi->cdata->dphy_rx_power_off(phy); 1289 if (ret < 0) 1290 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1291 } 1292 1293 clk_disable_unprepare(dsi->grf_clk); 1294 clk_disable_unprepare(dsi->pclk); 1295 1296 pm_runtime_put(dsi->dev); 1297 1298 return ret; 1299 } 1300 1301 static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1302 .configure = dw_mipi_dsi_dphy_configure, 1303 .power_on = dw_mipi_dsi_dphy_power_on, 1304 .power_off = dw_mipi_dsi_dphy_power_off, 1305 .init = dw_mipi_dsi_dphy_init, 1306 .exit = dw_mipi_dsi_dphy_exit, 1307 }; 1308 1309 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1310 { 1311 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1312 int ret; 1313 1314 /* 1315 * Re-configure DSI state, if we were previously initialized. We need 1316 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1317 */ 1318 if (dsi->dsi_bound) { 1319 ret = clk_prepare_enable(dsi->grf_clk); 1320 if (ret) { 1321 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1322 return ret; 1323 } 1324 1325 dw_mipi_dsi_rockchip_config(dsi); 1326 if (dsi->slave) 1327 dw_mipi_dsi_rockchip_config(dsi->slave); 1328 1329 clk_disable_unprepare(dsi->grf_clk); 1330 } 1331 1332 return 0; 1333 } 1334 1335 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1336 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1337 }; 1338 1339 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1340 { 1341 struct device *dev = &pdev->dev; 1342 struct device_node *np = dev->of_node; 1343 struct dw_mipi_dsi_rockchip *dsi; 1344 struct phy_provider *phy_provider; 1345 struct resource *res; 1346 const struct rockchip_dw_dsi_chip_data *cdata = 1347 of_device_get_match_data(dev); 1348 int ret, i; 1349 1350 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1351 if (!dsi) 1352 return -ENOMEM; 1353 1354 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1355 dsi->base = devm_ioremap_resource(dev, res); 1356 if (IS_ERR(dsi->base)) { 1357 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1358 return PTR_ERR(dsi->base); 1359 } 1360 1361 i = 0; 1362 while (cdata[i].reg) { 1363 if (cdata[i].reg == res->start) { 1364 dsi->cdata = &cdata[i]; 1365 break; 1366 } 1367 1368 i++; 1369 } 1370 1371 if (!dsi->cdata) { 1372 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1373 return -EINVAL; 1374 } 1375 1376 /* try to get a possible external dphy */ 1377 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1378 if (IS_ERR(dsi->phy)) { 1379 ret = PTR_ERR(dsi->phy); 1380 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1381 return ret; 1382 } 1383 1384 dsi->pclk = devm_clk_get(dev, "pclk"); 1385 if (IS_ERR(dsi->pclk)) { 1386 ret = PTR_ERR(dsi->pclk); 1387 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1388 return ret; 1389 } 1390 1391 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1392 if (IS_ERR(dsi->pllref_clk)) { 1393 if (dsi->phy) { 1394 /* 1395 * if external phy is present, pll will be 1396 * generated there. 1397 */ 1398 dsi->pllref_clk = NULL; 1399 } else { 1400 ret = PTR_ERR(dsi->pllref_clk); 1401 DRM_DEV_ERROR(dev, 1402 "Unable to get pll reference clock: %d\n", 1403 ret); 1404 return ret; 1405 } 1406 } 1407 1408 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1409 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1410 if (IS_ERR(dsi->phy_cfg_clk)) { 1411 ret = PTR_ERR(dsi->phy_cfg_clk); 1412 DRM_DEV_ERROR(dev, 1413 "Unable to get phy_cfg_clk: %d\n", ret); 1414 return ret; 1415 } 1416 } 1417 1418 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1419 dsi->grf_clk = devm_clk_get(dev, "grf"); 1420 if (IS_ERR(dsi->grf_clk)) { 1421 ret = PTR_ERR(dsi->grf_clk); 1422 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1423 return ret; 1424 } 1425 } 1426 1427 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1428 if (IS_ERR(dsi->grf_regmap)) { 1429 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1430 return PTR_ERR(dsi->grf_regmap); 1431 } 1432 1433 dsi->dev = dev; 1434 dsi->pdata.base = dsi->base; 1435 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1436 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1437 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1438 dsi->pdata.priv_data = dsi; 1439 platform_set_drvdata(pdev, dsi); 1440 1441 mutex_init(&dsi->usage_mutex); 1442 1443 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1444 if (IS_ERR(dsi->dphy)) { 1445 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1446 return PTR_ERR(dsi->dphy); 1447 } 1448 1449 phy_set_drvdata(dsi->dphy, dsi); 1450 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1451 if (IS_ERR(phy_provider)) 1452 return PTR_ERR(phy_provider); 1453 1454 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1455 if (IS_ERR(dsi->dmd)) { 1456 ret = PTR_ERR(dsi->dmd); 1457 if (ret != -EPROBE_DEFER) 1458 DRM_DEV_ERROR(dev, 1459 "Failed to probe dw_mipi_dsi: %d\n", ret); 1460 return ret; 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1467 { 1468 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1469 1470 dw_mipi_dsi_remove(dsi->dmd); 1471 1472 return 0; 1473 } 1474 1475 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1476 { 1477 .reg = 0xff450000, 1478 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1479 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1480 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1481 PX30_DSI_LCDC_SEL), 1482 1483 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1484 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1485 PX30_DSI_FORCERXMODE | 1486 PX30_DSI_FORCETXSTOPMODE), 1487 1488 .max_data_lanes = 4, 1489 }, 1490 { /* sentinel */ } 1491 }; 1492 1493 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1494 { 1495 .reg = 0xff960000, 1496 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1497 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1498 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1499 1500 .max_data_lanes = 4, 1501 }, 1502 { 1503 .reg = 0xff964000, 1504 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1505 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1506 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1507 1508 .max_data_lanes = 4, 1509 }, 1510 { /* sentinel */ } 1511 }; 1512 1513 static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1514 { 1515 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1516 1517 /* 1518 * Set TX1RX1 source to isp1. 1519 * Assume ISP0 is supplied by the RX0 dphy. 1520 */ 1521 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1522 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); 1523 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1524 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1525 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1526 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR)); 1527 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1528 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1529 1530 return 0; 1531 } 1532 1533 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1534 { 1535 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1536 1537 /* tester reset pulse */ 1538 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1539 usleep_range(100, 150); 1540 1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1542 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1543 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1544 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR)); 1545 1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1547 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE)); 1548 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1549 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE)); 1550 1551 /* Disable lane turn around, which is ignored in receive mode */ 1552 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1553 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST)); 1554 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1555 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE, 1556 RK3399_DSI1_TURNDISABLE)); 1557 usleep_range(100, 150); 1558 1559 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1560 usleep_range(100, 150); 1561 1562 /* Enable dphy lanes */ 1563 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1564 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), 1565 RK3399_DSI1_ENABLE)); 1566 1567 usleep_range(100, 150); 1568 1569 return 0; 1570 } 1571 1572 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1573 { 1574 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1575 1576 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1577 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1578 1579 return 0; 1580 } 1581 1582 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1583 { 1584 .reg = 0xff960000, 1585 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1586 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1587 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1588 RK3399_DSI0_LCDC_SEL), 1589 1590 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1591 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1592 RK3399_DSI0_TURNDISABLE | 1593 RK3399_DSI0_FORCETXSTOPMODE | 1594 RK3399_DSI0_FORCERXMODE), 1595 1596 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1597 .max_data_lanes = 4, 1598 }, 1599 { 1600 .reg = 0xff968000, 1601 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1602 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1603 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1604 RK3399_DSI1_LCDC_SEL), 1605 1606 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1607 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1608 RK3399_DSI1_FORCETXSTOPMODE | 1609 RK3399_DSI1_FORCERXMODE | 1610 RK3399_DSI1_ENABLE), 1611 1612 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1613 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1614 RK3399_TXRX_ENABLECLK, 1615 RK3399_TXRX_MASTERSLAVEZ | 1616 RK3399_TXRX_ENABLECLK | 1617 RK3399_TXRX_BASEDIR), 1618 1619 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1620 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1621 1622 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1623 .max_data_lanes = 4, 1624 1625 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1626 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1627 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1628 }, 1629 { /* sentinel */ } 1630 }; 1631 1632 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { 1633 { 1634 .reg = 0xfe060000, 1635 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, 1636 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS | 1637 RK3568_DSI0_FORCETXSTOPMODE | 1638 RK3568_DSI0_TURNDISABLE | 1639 RK3568_DSI0_FORCERXMODE), 1640 .max_data_lanes = 4, 1641 }, 1642 { 1643 .reg = 0xfe070000, 1644 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, 1645 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS | 1646 RK3568_DSI1_FORCETXSTOPMODE | 1647 RK3568_DSI1_TURNDISABLE | 1648 RK3568_DSI1_FORCERXMODE), 1649 .max_data_lanes = 4, 1650 }, 1651 { /* sentinel */ } 1652 }; 1653 1654 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1655 { 1656 .compatible = "rockchip,px30-mipi-dsi", 1657 .data = &px30_chip_data, 1658 }, { 1659 .compatible = "rockchip,rk3288-mipi-dsi", 1660 .data = &rk3288_chip_data, 1661 }, { 1662 .compatible = "rockchip,rk3399-mipi-dsi", 1663 .data = &rk3399_chip_data, 1664 }, { 1665 .compatible = "rockchip,rk3568-mipi-dsi", 1666 .data = &rk3568_chip_data, 1667 }, 1668 { /* sentinel */ } 1669 }; 1670 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1671 1672 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1673 .probe = dw_mipi_dsi_rockchip_probe, 1674 .remove = dw_mipi_dsi_rockchip_remove, 1675 .driver = { 1676 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1677 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1678 .name = "dw-mipi-dsi-rockchip", 1679 /* 1680 * For dual-DSI display, one DSI pokes at the other DSI's 1681 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1682 * safe for asynchronous probe. 1683 */ 1684 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1685 }, 1686 }; 1687