1 /*
2  * Rockchip SoC DP (Display Port) interface driver.
3  *
4  * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
5  * Author: Andy Yan <andy.yan@rock-chips.com>
6  *         Yakir Yang <ykk@rock-chips.com>
7  *         Jeff Chen <jeff.chen@rock-chips.com>
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms of the GNU General Public License as published by the
11  * Free Software Foundation; either version 2 of the License, or (at your
12  * option) any later version.
13  */
14 
15 #include <linux/component.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/of_device.h>
18 #include <linux/of_graph.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 #include <linux/clk.h>
22 
23 #include <drm/drmP.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_dp_helper.h>
26 #include <drm/drm_of.h>
27 #include <drm/drm_panel.h>
28 
29 #include <video/of_videomode.h>
30 #include <video/videomode.h>
31 
32 #include <drm/bridge/analogix_dp.h>
33 
34 #include "rockchip_drm_drv.h"
35 #include "rockchip_drm_psr.h"
36 #include "rockchip_drm_vop.h"
37 
38 #define RK3288_GRF_SOC_CON6		0x25c
39 #define RK3288_EDP_LCDC_SEL		BIT(5)
40 #define RK3399_GRF_SOC_CON20		0x6250
41 #define RK3399_EDP_LCDC_SEL		BIT(5)
42 
43 #define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)
44 
45 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS	100
46 
47 #define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
48 
49 /**
50  * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
51  * @lcdsel_grf_reg: grf register offset of lcdc select
52  * @lcdsel_big: reg value of selecting vop big for eDP
53  * @lcdsel_lit: reg value of selecting vop little for eDP
54  * @chip_type: specific chip type
55  */
56 struct rockchip_dp_chip_data {
57 	u32	lcdsel_grf_reg;
58 	u32	lcdsel_big;
59 	u32	lcdsel_lit;
60 	u32	chip_type;
61 };
62 
63 struct rockchip_dp_device {
64 	struct drm_device        *drm_dev;
65 	struct device            *dev;
66 	struct drm_encoder       encoder;
67 	struct drm_display_mode  mode;
68 
69 	struct clk               *pclk;
70 	struct clk               *grfclk;
71 	struct regmap            *grf;
72 	struct reset_control     *rst;
73 
74 	struct work_struct	 psr_work;
75 	struct mutex             psr_lock;
76 	unsigned int             psr_state;
77 
78 	const struct rockchip_dp_chip_data *data;
79 
80 	struct analogix_dp_plat_data plat_data;
81 };
82 
83 static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
84 {
85 	struct rockchip_dp_device *dp = to_dp(encoder);
86 
87 	if (!analogix_dp_psr_supported(dp->dev))
88 		return;
89 
90 	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
91 
92 	mutex_lock(&dp->psr_lock);
93 	if (enabled)
94 		dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
95 	else
96 		dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
97 
98 	schedule_work(&dp->psr_work);
99 	mutex_unlock(&dp->psr_lock);
100 }
101 
102 static void analogix_dp_psr_work(struct work_struct *work)
103 {
104 	struct rockchip_dp_device *dp =
105 				container_of(work, typeof(*dp), psr_work);
106 	int ret;
107 
108 	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
109 					 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
110 	if (ret) {
111 		DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
112 		return;
113 	}
114 
115 	mutex_lock(&dp->psr_lock);
116 	if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
117 		analogix_dp_enable_psr(dp->dev);
118 	else
119 		analogix_dp_disable_psr(dp->dev);
120 	mutex_unlock(&dp->psr_lock);
121 }
122 
123 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
124 {
125 	reset_control_assert(dp->rst);
126 	usleep_range(10, 20);
127 	reset_control_deassert(dp->rst);
128 
129 	return 0;
130 }
131 
132 static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
133 {
134 	struct rockchip_dp_device *dp = to_dp(plat_data);
135 	int ret;
136 
137 	cancel_work_sync(&dp->psr_work);
138 
139 	ret = clk_prepare_enable(dp->pclk);
140 	if (ret < 0) {
141 		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
142 		return ret;
143 	}
144 
145 	ret = rockchip_dp_pre_init(dp);
146 	if (ret < 0) {
147 		DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
148 		clk_disable_unprepare(dp->pclk);
149 		return ret;
150 	}
151 
152 	return 0;
153 }
154 
155 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
156 {
157 	struct rockchip_dp_device *dp = to_dp(plat_data);
158 
159 	clk_disable_unprepare(dp->pclk);
160 
161 	return 0;
162 }
163 
164 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
165 				 struct drm_connector *connector)
166 {
167 	struct drm_display_info *di = &connector->display_info;
168 	/* VOP couldn't output YUV video format for eDP rightly */
169 	u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
170 
171 	if ((di->color_formats & mask)) {
172 		DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
173 		di->color_formats &= ~mask;
174 		di->color_formats |= DRM_COLOR_FORMAT_RGB444;
175 		di->bpc = 8;
176 	}
177 
178 	return 0;
179 }
180 
181 static bool
182 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
183 				   const struct drm_display_mode *mode,
184 				   struct drm_display_mode *adjusted_mode)
185 {
186 	/* do nothing */
187 	return true;
188 }
189 
190 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
191 					     struct drm_display_mode *mode,
192 					     struct drm_display_mode *adjusted)
193 {
194 	/* do nothing */
195 }
196 
197 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
198 {
199 	struct rockchip_dp_device *dp = to_dp(encoder);
200 	int ret;
201 	u32 val;
202 
203 	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
204 	if (ret < 0)
205 		return;
206 
207 	if (ret)
208 		val = dp->data->lcdsel_lit;
209 	else
210 		val = dp->data->lcdsel_big;
211 
212 	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
213 
214 	ret = clk_prepare_enable(dp->grfclk);
215 	if (ret < 0) {
216 		DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
217 		return;
218 	}
219 
220 	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
221 	if (ret != 0)
222 		DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
223 
224 	clk_disable_unprepare(dp->grfclk);
225 }
226 
227 static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
228 {
229 	/* do nothing */
230 }
231 
232 static int
233 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
234 				      struct drm_crtc_state *crtc_state,
235 				      struct drm_connector_state *conn_state)
236 {
237 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
238 
239 	/*
240 	 * The hardware IC designed that VOP must output the RGB10 video
241 	 * format to eDP controller, and if eDP panel only support RGB8,
242 	 * then eDP controller should cut down the video data, not via VOP
243 	 * controller, that's why we need to hardcode the VOP output mode
244 	 * to RGA10 here.
245 	 */
246 
247 	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
248 	s->output_type = DRM_MODE_CONNECTOR_eDP;
249 
250 	return 0;
251 }
252 
253 static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
254 	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
255 	.mode_set = rockchip_dp_drm_encoder_mode_set,
256 	.enable = rockchip_dp_drm_encoder_enable,
257 	.disable = rockchip_dp_drm_encoder_nop,
258 	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
259 };
260 
261 static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
262 {
263 	drm_encoder_cleanup(encoder);
264 }
265 
266 static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
267 	.destroy = rockchip_dp_drm_encoder_destroy,
268 };
269 
270 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
271 {
272 	struct device *dev = dp->dev;
273 	struct device_node *np = dev->of_node;
274 
275 	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
276 	if (IS_ERR(dp->grf)) {
277 		DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
278 		return PTR_ERR(dp->grf);
279 	}
280 
281 	dp->grfclk = devm_clk_get(dev, "grf");
282 	if (PTR_ERR(dp->grfclk) == -ENOENT) {
283 		dp->grfclk = NULL;
284 	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
285 		return -EPROBE_DEFER;
286 	} else if (IS_ERR(dp->grfclk)) {
287 		DRM_DEV_ERROR(dev, "failed to get grf clock\n");
288 		return PTR_ERR(dp->grfclk);
289 	}
290 
291 	dp->pclk = devm_clk_get(dev, "pclk");
292 	if (IS_ERR(dp->pclk)) {
293 		DRM_DEV_ERROR(dev, "failed to get pclk property\n");
294 		return PTR_ERR(dp->pclk);
295 	}
296 
297 	dp->rst = devm_reset_control_get(dev, "dp");
298 	if (IS_ERR(dp->rst)) {
299 		DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
300 		return PTR_ERR(dp->rst);
301 	}
302 
303 	return 0;
304 }
305 
306 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
307 {
308 	struct drm_encoder *encoder = &dp->encoder;
309 	struct drm_device *drm_dev = dp->drm_dev;
310 	struct device *dev = dp->dev;
311 	int ret;
312 
313 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
314 							     dev->of_node);
315 	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
316 
317 	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
318 			       DRM_MODE_ENCODER_TMDS, NULL);
319 	if (ret) {
320 		DRM_ERROR("failed to initialize encoder with drm\n");
321 		return ret;
322 	}
323 
324 	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
325 
326 	return 0;
327 }
328 
329 static int rockchip_dp_bind(struct device *dev, struct device *master,
330 			    void *data)
331 {
332 	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
333 	const struct rockchip_dp_chip_data *dp_data;
334 	struct drm_device *drm_dev = data;
335 	int ret;
336 
337 	/*
338 	 * Just like the probe function said, we don't need the
339 	 * device drvrate anymore, we should leave the charge to
340 	 * analogix dp driver, set the device drvdata to NULL.
341 	 */
342 	dev_set_drvdata(dev, NULL);
343 
344 	dp_data = of_device_get_match_data(dev);
345 	if (!dp_data)
346 		return -ENODEV;
347 
348 	dp->data = dp_data;
349 	dp->drm_dev = drm_dev;
350 
351 	ret = rockchip_dp_drm_create_encoder(dp);
352 	if (ret) {
353 		DRM_ERROR("failed to create drm encoder\n");
354 		return ret;
355 	}
356 
357 	dp->plat_data.encoder = &dp->encoder;
358 
359 	dp->plat_data.dev_type = dp->data->chip_type;
360 	dp->plat_data.power_on = rockchip_dp_poweron;
361 	dp->plat_data.power_off = rockchip_dp_powerdown;
362 	dp->plat_data.get_modes = rockchip_dp_get_modes;
363 
364 	mutex_init(&dp->psr_lock);
365 	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
366 	INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
367 
368 	rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
369 
370 	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
371 }
372 
373 static void rockchip_dp_unbind(struct device *dev, struct device *master,
374 			       void *data)
375 {
376 	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
377 
378 	rockchip_drm_psr_unregister(&dp->encoder);
379 
380 	analogix_dp_unbind(dev, master, data);
381 }
382 
383 static const struct component_ops rockchip_dp_component_ops = {
384 	.bind = rockchip_dp_bind,
385 	.unbind = rockchip_dp_unbind,
386 };
387 
388 static int rockchip_dp_probe(struct platform_device *pdev)
389 {
390 	struct device *dev = &pdev->dev;
391 	struct drm_panel *panel = NULL;
392 	struct rockchip_dp_device *dp;
393 	int ret;
394 
395 	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
396 	if (ret < 0)
397 		return ret;
398 
399 	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
400 	if (!dp)
401 		return -ENOMEM;
402 
403 	dp->dev = dev;
404 	dp->plat_data.panel = panel;
405 
406 	ret = rockchip_dp_of_probe(dp);
407 	if (ret < 0)
408 		return ret;
409 
410 	/*
411 	 * We just use the drvdata until driver run into component
412 	 * add function, and then we would set drvdata to null, so
413 	 * that analogix dp driver could take charge of the drvdata.
414 	 */
415 	platform_set_drvdata(pdev, dp);
416 
417 	return component_add(dev, &rockchip_dp_component_ops);
418 }
419 
420 static int rockchip_dp_remove(struct platform_device *pdev)
421 {
422 	component_del(&pdev->dev, &rockchip_dp_component_ops);
423 
424 	return 0;
425 }
426 
427 static const struct dev_pm_ops rockchip_dp_pm_ops = {
428 #ifdef CONFIG_PM_SLEEP
429 	.suspend = analogix_dp_suspend,
430 	.resume_early = analogix_dp_resume,
431 #endif
432 };
433 
434 static const struct rockchip_dp_chip_data rk3399_edp = {
435 	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
436 	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
437 	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
438 	.chip_type = RK3399_EDP,
439 };
440 
441 static const struct rockchip_dp_chip_data rk3288_dp = {
442 	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
443 	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
444 	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
445 	.chip_type = RK3288_DP,
446 };
447 
448 static const struct of_device_id rockchip_dp_dt_ids[] = {
449 	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
450 	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
451 	{}
452 };
453 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
454 
455 struct platform_driver rockchip_dp_driver = {
456 	.probe = rockchip_dp_probe,
457 	.remove = rockchip_dp_remove,
458 	.driver = {
459 		   .name = "rockchip-dp",
460 		   .pm = &rockchip_dp_pm_ops,
461 		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
462 	},
463 };
464