1 /* 2 * Rockchip SoC DP (Display Port) interface driver. 3 * 4 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd. 5 * Author: Andy Yan <andy.yan@rock-chips.com> 6 * Yakir Yang <ykk@rock-chips.com> 7 * Jeff Chen <jeff.chen@rock-chips.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/component.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/of_device.h> 18 #include <linux/of_graph.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/clk.h> 22 23 #include <drm/drmP.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_dp_helper.h> 26 #include <drm/drm_of.h> 27 #include <drm/drm_panel.h> 28 29 #include <video/of_videomode.h> 30 #include <video/videomode.h> 31 32 #include <drm/bridge/analogix_dp.h> 33 34 #include "rockchip_drm_drv.h" 35 #include "rockchip_drm_psr.h" 36 #include "rockchip_drm_vop.h" 37 38 #define RK3288_GRF_SOC_CON6 0x25c 39 #define RK3288_EDP_LCDC_SEL BIT(5) 40 #define RK3399_GRF_SOC_CON20 0x6250 41 #define RK3399_EDP_LCDC_SEL BIT(5) 42 43 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 44 45 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 46 47 #define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm) 48 49 /** 50 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 51 * @lcdsel_grf_reg: grf register offset of lcdc select 52 * @lcdsel_big: reg value of selecting vop big for eDP 53 * @lcdsel_lit: reg value of selecting vop little for eDP 54 * @chip_type: specific chip type 55 */ 56 struct rockchip_dp_chip_data { 57 u32 lcdsel_grf_reg; 58 u32 lcdsel_big; 59 u32 lcdsel_lit; 60 u32 chip_type; 61 }; 62 63 struct rockchip_dp_device { 64 struct drm_device *drm_dev; 65 struct device *dev; 66 struct drm_encoder encoder; 67 struct drm_display_mode mode; 68 69 struct clk *pclk; 70 struct clk *grfclk; 71 struct regmap *grf; 72 struct reset_control *rst; 73 74 struct work_struct psr_work; 75 spinlock_t psr_lock; 76 unsigned int psr_state; 77 78 const struct rockchip_dp_chip_data *data; 79 80 struct analogix_dp_plat_data plat_data; 81 }; 82 83 static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled) 84 { 85 struct rockchip_dp_device *dp = to_dp(encoder); 86 unsigned long flags; 87 88 if (!analogix_dp_psr_supported(dp->dev)) 89 return; 90 91 dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit"); 92 93 spin_lock_irqsave(&dp->psr_lock, flags); 94 if (enabled) 95 dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE; 96 else 97 dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE; 98 99 schedule_work(&dp->psr_work); 100 spin_unlock_irqrestore(&dp->psr_lock, flags); 101 } 102 103 static void analogix_dp_psr_work(struct work_struct *work) 104 { 105 struct rockchip_dp_device *dp = 106 container_of(work, typeof(*dp), psr_work); 107 int ret; 108 unsigned long flags; 109 110 ret = rockchip_drm_wait_vact_end(dp->encoder.crtc, 111 PSR_WAIT_LINE_FLAG_TIMEOUT_MS); 112 if (ret) { 113 dev_err(dp->dev, "line flag interrupt did not arrive\n"); 114 return; 115 } 116 117 spin_lock_irqsave(&dp->psr_lock, flags); 118 if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE) 119 analogix_dp_enable_psr(dp->dev); 120 else 121 analogix_dp_disable_psr(dp->dev); 122 spin_unlock_irqrestore(&dp->psr_lock, flags); 123 } 124 125 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) 126 { 127 reset_control_assert(dp->rst); 128 usleep_range(10, 20); 129 reset_control_deassert(dp->rst); 130 131 return 0; 132 } 133 134 static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data) 135 { 136 struct rockchip_dp_device *dp = to_dp(plat_data); 137 int ret; 138 139 cancel_work_sync(&dp->psr_work); 140 141 ret = clk_prepare_enable(dp->pclk); 142 if (ret < 0) { 143 dev_err(dp->dev, "failed to enable pclk %d\n", ret); 144 return ret; 145 } 146 147 ret = rockchip_dp_pre_init(dp); 148 if (ret < 0) { 149 dev_err(dp->dev, "failed to dp pre init %d\n", ret); 150 clk_disable_unprepare(dp->pclk); 151 return ret; 152 } 153 154 return 0; 155 } 156 157 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) 158 { 159 struct rockchip_dp_device *dp = to_dp(plat_data); 160 161 clk_disable_unprepare(dp->pclk); 162 163 return 0; 164 } 165 166 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data, 167 struct drm_connector *connector) 168 { 169 struct drm_display_info *di = &connector->display_info; 170 /* VOP couldn't output YUV video format for eDP rightly */ 171 u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; 172 173 if ((di->color_formats & mask)) { 174 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n"); 175 di->color_formats &= ~mask; 176 di->color_formats |= DRM_COLOR_FORMAT_RGB444; 177 di->bpc = 8; 178 } 179 180 return 0; 181 } 182 183 static bool 184 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder, 185 const struct drm_display_mode *mode, 186 struct drm_display_mode *adjusted_mode) 187 { 188 /* do nothing */ 189 return true; 190 } 191 192 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder, 193 struct drm_display_mode *mode, 194 struct drm_display_mode *adjusted) 195 { 196 /* do nothing */ 197 } 198 199 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) 200 { 201 struct rockchip_dp_device *dp = to_dp(encoder); 202 int ret; 203 u32 val; 204 205 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); 206 if (ret < 0) 207 return; 208 209 if (ret) 210 val = dp->data->lcdsel_lit; 211 else 212 val = dp->data->lcdsel_big; 213 214 dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); 215 216 ret = clk_prepare_enable(dp->grfclk); 217 if (ret < 0) { 218 dev_err(dp->dev, "failed to enable grfclk %d\n", ret); 219 return; 220 } 221 222 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); 223 if (ret != 0) 224 dev_err(dp->dev, "Could not write to GRF: %d\n", ret); 225 226 clk_disable_unprepare(dp->grfclk); 227 } 228 229 static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) 230 { 231 /* do nothing */ 232 } 233 234 static int 235 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, 236 struct drm_crtc_state *crtc_state, 237 struct drm_connector_state *conn_state) 238 { 239 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 240 struct rockchip_dp_device *dp = to_dp(encoder); 241 int ret; 242 243 /* 244 * The hardware IC designed that VOP must output the RGB10 video 245 * format to eDP controller, and if eDP panel only support RGB8, 246 * then eDP controller should cut down the video data, not via VOP 247 * controller, that's why we need to hardcode the VOP output mode 248 * to RGA10 here. 249 */ 250 251 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; 252 s->output_type = DRM_MODE_CONNECTOR_eDP; 253 if (dp->data->chip_type == RK3399_EDP) { 254 /* 255 * For RK3399, VOP Lit must code the out mode to RGB888, 256 * VOP Big must code the out mode to RGB10. 257 */ 258 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, 259 encoder); 260 if (ret > 0) 261 s->output_mode = ROCKCHIP_OUT_MODE_P888; 262 } 263 264 return 0; 265 } 266 267 static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = { 268 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup, 269 .mode_set = rockchip_dp_drm_encoder_mode_set, 270 .enable = rockchip_dp_drm_encoder_enable, 271 .disable = rockchip_dp_drm_encoder_nop, 272 .atomic_check = rockchip_dp_drm_encoder_atomic_check, 273 }; 274 275 static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder) 276 { 277 drm_encoder_cleanup(encoder); 278 } 279 280 static struct drm_encoder_funcs rockchip_dp_encoder_funcs = { 281 .destroy = rockchip_dp_drm_encoder_destroy, 282 }; 283 284 static int rockchip_dp_init(struct rockchip_dp_device *dp) 285 { 286 struct device *dev = dp->dev; 287 struct device_node *np = dev->of_node; 288 int ret; 289 290 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 291 if (IS_ERR(dp->grf)) { 292 dev_err(dev, "failed to get rockchip,grf property\n"); 293 return PTR_ERR(dp->grf); 294 } 295 296 dp->grfclk = devm_clk_get(dev, "grf"); 297 if (PTR_ERR(dp->grfclk) == -ENOENT) { 298 dp->grfclk = NULL; 299 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) { 300 return -EPROBE_DEFER; 301 } else if (IS_ERR(dp->grfclk)) { 302 dev_err(dev, "failed to get grf clock\n"); 303 return PTR_ERR(dp->grfclk); 304 } 305 306 dp->pclk = devm_clk_get(dev, "pclk"); 307 if (IS_ERR(dp->pclk)) { 308 dev_err(dev, "failed to get pclk property\n"); 309 return PTR_ERR(dp->pclk); 310 } 311 312 dp->rst = devm_reset_control_get(dev, "dp"); 313 if (IS_ERR(dp->rst)) { 314 dev_err(dev, "failed to get dp reset control\n"); 315 return PTR_ERR(dp->rst); 316 } 317 318 ret = clk_prepare_enable(dp->pclk); 319 if (ret < 0) { 320 dev_err(dp->dev, "failed to enable pclk %d\n", ret); 321 return ret; 322 } 323 324 ret = rockchip_dp_pre_init(dp); 325 if (ret < 0) { 326 dev_err(dp->dev, "failed to pre init %d\n", ret); 327 clk_disable_unprepare(dp->pclk); 328 return ret; 329 } 330 331 return 0; 332 } 333 334 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) 335 { 336 struct drm_encoder *encoder = &dp->encoder; 337 struct drm_device *drm_dev = dp->drm_dev; 338 struct device *dev = dp->dev; 339 int ret; 340 341 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 342 dev->of_node); 343 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 344 345 ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs, 346 DRM_MODE_ENCODER_TMDS, NULL); 347 if (ret) { 348 DRM_ERROR("failed to initialize encoder with drm\n"); 349 return ret; 350 } 351 352 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs); 353 354 return 0; 355 } 356 357 static int rockchip_dp_bind(struct device *dev, struct device *master, 358 void *data) 359 { 360 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 361 const struct rockchip_dp_chip_data *dp_data; 362 struct drm_device *drm_dev = data; 363 int ret; 364 365 /* 366 * Just like the probe function said, we don't need the 367 * device drvrate anymore, we should leave the charge to 368 * analogix dp driver, set the device drvdata to NULL. 369 */ 370 dev_set_drvdata(dev, NULL); 371 372 dp_data = of_device_get_match_data(dev); 373 if (!dp_data) 374 return -ENODEV; 375 376 ret = rockchip_dp_init(dp); 377 if (ret < 0) 378 return ret; 379 380 dp->data = dp_data; 381 dp->drm_dev = drm_dev; 382 383 ret = rockchip_dp_drm_create_encoder(dp); 384 if (ret) { 385 DRM_ERROR("failed to create drm encoder\n"); 386 return ret; 387 } 388 389 dp->plat_data.encoder = &dp->encoder; 390 391 dp->plat_data.dev_type = dp->data->chip_type; 392 dp->plat_data.power_on = rockchip_dp_poweron; 393 dp->plat_data.power_off = rockchip_dp_powerdown; 394 dp->plat_data.get_modes = rockchip_dp_get_modes; 395 396 spin_lock_init(&dp->psr_lock); 397 dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE; 398 INIT_WORK(&dp->psr_work, analogix_dp_psr_work); 399 400 rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set); 401 402 return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data); 403 } 404 405 static void rockchip_dp_unbind(struct device *dev, struct device *master, 406 void *data) 407 { 408 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 409 410 rockchip_drm_psr_unregister(&dp->encoder); 411 412 analogix_dp_unbind(dev, master, data); 413 clk_disable_unprepare(dp->pclk); 414 } 415 416 static const struct component_ops rockchip_dp_component_ops = { 417 .bind = rockchip_dp_bind, 418 .unbind = rockchip_dp_unbind, 419 }; 420 421 static int rockchip_dp_probe(struct platform_device *pdev) 422 { 423 struct device *dev = &pdev->dev; 424 struct drm_panel *panel = NULL; 425 struct rockchip_dp_device *dp; 426 int ret; 427 428 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL); 429 if (ret) 430 return ret; 431 432 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); 433 if (!dp) 434 return -ENOMEM; 435 436 dp->dev = dev; 437 438 dp->plat_data.panel = panel; 439 440 /* 441 * We just use the drvdata until driver run into component 442 * add function, and then we would set drvdata to null, so 443 * that analogix dp driver could take charge of the drvdata. 444 */ 445 platform_set_drvdata(pdev, dp); 446 447 return component_add(dev, &rockchip_dp_component_ops); 448 } 449 450 static int rockchip_dp_remove(struct platform_device *pdev) 451 { 452 component_del(&pdev->dev, &rockchip_dp_component_ops); 453 454 return 0; 455 } 456 457 static const struct dev_pm_ops rockchip_dp_pm_ops = { 458 #ifdef CONFIG_PM_SLEEP 459 .suspend = analogix_dp_suspend, 460 .resume_early = analogix_dp_resume, 461 #endif 462 }; 463 464 static const struct rockchip_dp_chip_data rk3399_edp = { 465 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 466 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL), 467 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL), 468 .chip_type = RK3399_EDP, 469 }; 470 471 static const struct rockchip_dp_chip_data rk3288_dp = { 472 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 473 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL), 474 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL), 475 .chip_type = RK3288_DP, 476 }; 477 478 static const struct of_device_id rockchip_dp_dt_ids[] = { 479 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp }, 480 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp }, 481 {} 482 }; 483 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids); 484 485 struct platform_driver rockchip_dp_driver = { 486 .probe = rockchip_dp_probe, 487 .remove = rockchip_dp_remove, 488 .driver = { 489 .name = "rockchip-dp", 490 .pm = &rockchip_dp_pm_ops, 491 .of_match_table = of_match_ptr(rockchip_dp_dt_ids), 492 }, 493 }; 494