1 /* 2 * Rockchip SoC DP (Display Port) interface driver. 3 * 4 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd. 5 * Author: Andy Yan <andy.yan@rock-chips.com> 6 * Yakir Yang <ykk@rock-chips.com> 7 * Jeff Chen <jeff.chen@rock-chips.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/component.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/of_device.h> 18 #include <linux/of_graph.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/clk.h> 22 23 #include <drm/drmP.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_dp_helper.h> 26 #include <drm/drm_of.h> 27 #include <drm/drm_panel.h> 28 29 #include <video/of_videomode.h> 30 #include <video/videomode.h> 31 32 #include <drm/bridge/analogix_dp.h> 33 34 #include "rockchip_drm_drv.h" 35 #include "rockchip_drm_psr.h" 36 #include "rockchip_drm_vop.h" 37 38 #define RK3288_GRF_SOC_CON6 0x25c 39 #define RK3288_EDP_LCDC_SEL BIT(5) 40 #define RK3399_GRF_SOC_CON20 0x6250 41 #define RK3399_EDP_LCDC_SEL BIT(5) 42 43 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 44 45 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 46 47 #define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm) 48 49 /** 50 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 51 * @lcdsel_grf_reg: grf register offset of lcdc select 52 * @lcdsel_big: reg value of selecting vop big for eDP 53 * @lcdsel_lit: reg value of selecting vop little for eDP 54 * @chip_type: specific chip type 55 */ 56 struct rockchip_dp_chip_data { 57 u32 lcdsel_grf_reg; 58 u32 lcdsel_big; 59 u32 lcdsel_lit; 60 u32 chip_type; 61 }; 62 63 struct rockchip_dp_device { 64 struct drm_device *drm_dev; 65 struct device *dev; 66 struct drm_encoder encoder; 67 struct drm_display_mode mode; 68 69 struct clk *pclk; 70 struct clk *grfclk; 71 struct regmap *grf; 72 struct reset_control *rst; 73 74 const struct rockchip_dp_chip_data *data; 75 76 struct analogix_dp_device *adp; 77 struct analogix_dp_plat_data plat_data; 78 }; 79 80 static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled) 81 { 82 struct rockchip_dp_device *dp = to_dp(encoder); 83 int ret; 84 85 if (!analogix_dp_psr_enabled(dp->adp)) 86 return 0; 87 88 DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit"); 89 90 ret = rockchip_drm_wait_vact_end(dp->encoder.crtc, 91 PSR_WAIT_LINE_FLAG_TIMEOUT_MS); 92 if (ret) { 93 DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n"); 94 return -ETIMEDOUT; 95 } 96 97 if (enabled) 98 return analogix_dp_enable_psr(dp->adp); 99 else 100 return analogix_dp_disable_psr(dp->adp); 101 } 102 103 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) 104 { 105 reset_control_assert(dp->rst); 106 usleep_range(10, 20); 107 reset_control_deassert(dp->rst); 108 109 return 0; 110 } 111 112 static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data) 113 { 114 struct rockchip_dp_device *dp = to_dp(plat_data); 115 int ret; 116 117 ret = clk_prepare_enable(dp->pclk); 118 if (ret < 0) { 119 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret); 120 return ret; 121 } 122 123 ret = rockchip_dp_pre_init(dp); 124 if (ret < 0) { 125 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret); 126 clk_disable_unprepare(dp->pclk); 127 return ret; 128 } 129 130 return rockchip_drm_psr_activate(&dp->encoder); 131 } 132 133 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) 134 { 135 struct rockchip_dp_device *dp = to_dp(plat_data); 136 int ret; 137 138 ret = rockchip_drm_psr_deactivate(&dp->encoder); 139 if (ret != 0) 140 return ret; 141 142 clk_disable_unprepare(dp->pclk); 143 144 return 0; 145 } 146 147 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data, 148 struct drm_connector *connector) 149 { 150 struct drm_display_info *di = &connector->display_info; 151 /* VOP couldn't output YUV video format for eDP rightly */ 152 u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; 153 154 if ((di->color_formats & mask)) { 155 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n"); 156 di->color_formats &= ~mask; 157 di->color_formats |= DRM_COLOR_FORMAT_RGB444; 158 di->bpc = 8; 159 } 160 161 return 0; 162 } 163 164 static bool 165 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder, 166 const struct drm_display_mode *mode, 167 struct drm_display_mode *adjusted_mode) 168 { 169 /* do nothing */ 170 return true; 171 } 172 173 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder, 174 struct drm_display_mode *mode, 175 struct drm_display_mode *adjusted) 176 { 177 /* do nothing */ 178 } 179 180 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) 181 { 182 struct rockchip_dp_device *dp = to_dp(encoder); 183 int ret; 184 u32 val; 185 186 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); 187 if (ret < 0) 188 return; 189 190 if (ret) 191 val = dp->data->lcdsel_lit; 192 else 193 val = dp->data->lcdsel_big; 194 195 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); 196 197 ret = clk_prepare_enable(dp->grfclk); 198 if (ret < 0) { 199 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret); 200 return; 201 } 202 203 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); 204 if (ret != 0) 205 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); 206 207 clk_disable_unprepare(dp->grfclk); 208 } 209 210 static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) 211 { 212 /* do nothing */ 213 } 214 215 static int 216 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, 217 struct drm_crtc_state *crtc_state, 218 struct drm_connector_state *conn_state) 219 { 220 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 221 struct drm_display_info *di = &conn_state->connector->display_info; 222 223 /* 224 * The hardware IC designed that VOP must output the RGB10 video 225 * format to eDP controller, and if eDP panel only support RGB8, 226 * then eDP controller should cut down the video data, not via VOP 227 * controller, that's why we need to hardcode the VOP output mode 228 * to RGA10 here. 229 */ 230 231 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; 232 s->output_type = DRM_MODE_CONNECTOR_eDP; 233 s->output_bpc = di->bpc; 234 235 return 0; 236 } 237 238 static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = { 239 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup, 240 .mode_set = rockchip_dp_drm_encoder_mode_set, 241 .enable = rockchip_dp_drm_encoder_enable, 242 .disable = rockchip_dp_drm_encoder_nop, 243 .atomic_check = rockchip_dp_drm_encoder_atomic_check, 244 }; 245 246 static struct drm_encoder_funcs rockchip_dp_encoder_funcs = { 247 .destroy = drm_encoder_cleanup, 248 }; 249 250 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp) 251 { 252 struct device *dev = dp->dev; 253 struct device_node *np = dev->of_node; 254 255 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 256 if (IS_ERR(dp->grf)) { 257 DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n"); 258 return PTR_ERR(dp->grf); 259 } 260 261 dp->grfclk = devm_clk_get(dev, "grf"); 262 if (PTR_ERR(dp->grfclk) == -ENOENT) { 263 dp->grfclk = NULL; 264 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) { 265 return -EPROBE_DEFER; 266 } else if (IS_ERR(dp->grfclk)) { 267 DRM_DEV_ERROR(dev, "failed to get grf clock\n"); 268 return PTR_ERR(dp->grfclk); 269 } 270 271 dp->pclk = devm_clk_get(dev, "pclk"); 272 if (IS_ERR(dp->pclk)) { 273 DRM_DEV_ERROR(dev, "failed to get pclk property\n"); 274 return PTR_ERR(dp->pclk); 275 } 276 277 dp->rst = devm_reset_control_get(dev, "dp"); 278 if (IS_ERR(dp->rst)) { 279 DRM_DEV_ERROR(dev, "failed to get dp reset control\n"); 280 return PTR_ERR(dp->rst); 281 } 282 283 return 0; 284 } 285 286 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) 287 { 288 struct drm_encoder *encoder = &dp->encoder; 289 struct drm_device *drm_dev = dp->drm_dev; 290 struct device *dev = dp->dev; 291 int ret; 292 293 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 294 dev->of_node); 295 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 296 297 ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs, 298 DRM_MODE_ENCODER_TMDS, NULL); 299 if (ret) { 300 DRM_ERROR("failed to initialize encoder with drm\n"); 301 return ret; 302 } 303 304 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs); 305 306 return 0; 307 } 308 309 static int rockchip_dp_bind(struct device *dev, struct device *master, 310 void *data) 311 { 312 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 313 const struct rockchip_dp_chip_data *dp_data; 314 struct drm_device *drm_dev = data; 315 int ret; 316 317 dp_data = of_device_get_match_data(dev); 318 if (!dp_data) 319 return -ENODEV; 320 321 dp->data = dp_data; 322 dp->drm_dev = drm_dev; 323 324 ret = rockchip_dp_drm_create_encoder(dp); 325 if (ret) { 326 DRM_ERROR("failed to create drm encoder\n"); 327 return ret; 328 } 329 330 dp->plat_data.encoder = &dp->encoder; 331 332 dp->plat_data.dev_type = dp->data->chip_type; 333 dp->plat_data.power_on = rockchip_dp_poweron; 334 dp->plat_data.power_off = rockchip_dp_powerdown; 335 dp->plat_data.get_modes = rockchip_dp_get_modes; 336 337 ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set); 338 if (ret < 0) 339 goto err_cleanup_encoder; 340 341 dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data); 342 if (IS_ERR(dp->adp)) { 343 ret = PTR_ERR(dp->adp); 344 goto err_unreg_psr; 345 } 346 347 return 0; 348 err_unreg_psr: 349 rockchip_drm_psr_unregister(&dp->encoder); 350 err_cleanup_encoder: 351 dp->encoder.funcs->destroy(&dp->encoder); 352 return ret; 353 } 354 355 static void rockchip_dp_unbind(struct device *dev, struct device *master, 356 void *data) 357 { 358 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 359 360 analogix_dp_unbind(dp->adp); 361 rockchip_drm_psr_unregister(&dp->encoder); 362 dp->encoder.funcs->destroy(&dp->encoder); 363 } 364 365 static const struct component_ops rockchip_dp_component_ops = { 366 .bind = rockchip_dp_bind, 367 .unbind = rockchip_dp_unbind, 368 }; 369 370 static int rockchip_dp_probe(struct platform_device *pdev) 371 { 372 struct device *dev = &pdev->dev; 373 struct drm_panel *panel = NULL; 374 struct rockchip_dp_device *dp; 375 int ret; 376 377 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL); 378 if (ret < 0) 379 return ret; 380 381 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); 382 if (!dp) 383 return -ENOMEM; 384 385 dp->dev = dev; 386 dp->plat_data.panel = panel; 387 388 ret = rockchip_dp_of_probe(dp); 389 if (ret < 0) 390 return ret; 391 392 platform_set_drvdata(pdev, dp); 393 394 return component_add(dev, &rockchip_dp_component_ops); 395 } 396 397 static int rockchip_dp_remove(struct platform_device *pdev) 398 { 399 component_del(&pdev->dev, &rockchip_dp_component_ops); 400 401 return 0; 402 } 403 404 #ifdef CONFIG_PM_SLEEP 405 static int rockchip_dp_suspend(struct device *dev) 406 { 407 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 408 409 return analogix_dp_suspend(dp->adp); 410 } 411 412 static int rockchip_dp_resume(struct device *dev) 413 { 414 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 415 416 return analogix_dp_resume(dp->adp); 417 } 418 #endif 419 420 static const struct dev_pm_ops rockchip_dp_pm_ops = { 421 #ifdef CONFIG_PM_SLEEP 422 .suspend = rockchip_dp_suspend, 423 .resume_early = rockchip_dp_resume, 424 #endif 425 }; 426 427 static const struct rockchip_dp_chip_data rk3399_edp = { 428 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 429 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL), 430 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL), 431 .chip_type = RK3399_EDP, 432 }; 433 434 static const struct rockchip_dp_chip_data rk3288_dp = { 435 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 436 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL), 437 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL), 438 .chip_type = RK3288_DP, 439 }; 440 441 static const struct of_device_id rockchip_dp_dt_ids[] = { 442 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp }, 443 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp }, 444 {} 445 }; 446 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids); 447 448 struct platform_driver rockchip_dp_driver = { 449 .probe = rockchip_dp_probe, 450 .remove = rockchip_dp_remove, 451 .driver = { 452 .name = "rockchip-dp", 453 .pm = &rockchip_dp_pm_ops, 454 .of_match_table = of_match_ptr(rockchip_dp_dt_ids), 455 }, 456 }; 457