19e32e16eSYakir Yang /*
29e32e16eSYakir Yang  * Rockchip SoC DP (Display Port) interface driver.
39e32e16eSYakir Yang  *
49e32e16eSYakir Yang  * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
59e32e16eSYakir Yang  * Author: Andy Yan <andy.yan@rock-chips.com>
69e32e16eSYakir Yang  *         Yakir Yang <ykk@rock-chips.com>
79e32e16eSYakir Yang  *         Jeff Chen <jeff.chen@rock-chips.com>
89e32e16eSYakir Yang  *
99e32e16eSYakir Yang  * This program is free software; you can redistribute it and/or modify it
109e32e16eSYakir Yang  * under the terms of the GNU General Public License as published by the
119e32e16eSYakir Yang  * Free Software Foundation; either version 2 of the License, or (at your
129e32e16eSYakir Yang  * option) any later version.
139e32e16eSYakir Yang  */
149e32e16eSYakir Yang 
159e32e16eSYakir Yang #include <linux/component.h>
169e32e16eSYakir Yang #include <linux/mfd/syscon.h>
17d9c900b0SYakir Yang #include <linux/of_device.h>
189e32e16eSYakir Yang #include <linux/of_graph.h>
199e32e16eSYakir Yang #include <linux/regmap.h>
209e32e16eSYakir Yang #include <linux/reset.h>
219e32e16eSYakir Yang #include <linux/clk.h>
229e32e16eSYakir Yang 
239e32e16eSYakir Yang #include <drm/drmP.h>
249e32e16eSYakir Yang #include <drm/drm_crtc_helper.h>
259e32e16eSYakir Yang #include <drm/drm_dp_helper.h>
269e32e16eSYakir Yang #include <drm/drm_of.h>
279e32e16eSYakir Yang #include <drm/drm_panel.h>
289e32e16eSYakir Yang 
299e32e16eSYakir Yang #include <video/of_videomode.h>
309e32e16eSYakir Yang #include <video/videomode.h>
319e32e16eSYakir Yang 
329e32e16eSYakir Yang #include <drm/bridge/analogix_dp.h>
339e32e16eSYakir Yang 
349e32e16eSYakir Yang #include "rockchip_drm_drv.h"
358f0ac5c4SYakir Yang #include "rockchip_drm_psr.h"
369e32e16eSYakir Yang #include "rockchip_drm_vop.h"
379e32e16eSYakir Yang 
38d9c900b0SYakir Yang #define RK3288_GRF_SOC_CON6		0x25c
39d9c900b0SYakir Yang #define RK3288_EDP_LCDC_SEL		BIT(5)
4082872e42SYakir Yang #define RK3399_GRF_SOC_CON20		0x6250
4182872e42SYakir Yang #define RK3399_EDP_LCDC_SEL		BIT(5)
42d9c900b0SYakir Yang 
43d9c900b0SYakir Yang #define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)
44d9c900b0SYakir Yang 
458f0ac5c4SYakir Yang #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS	100
468f0ac5c4SYakir Yang 
479e32e16eSYakir Yang #define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
489e32e16eSYakir Yang 
49d9c900b0SYakir Yang /**
50d9c900b0SYakir Yang  * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
51d9c900b0SYakir Yang  * @lcdsel_grf_reg: grf register offset of lcdc select
52d9c900b0SYakir Yang  * @lcdsel_big: reg value of selecting vop big for eDP
53d9c900b0SYakir Yang  * @lcdsel_lit: reg value of selecting vop little for eDP
54d9c900b0SYakir Yang  * @chip_type: specific chip type
55d9c900b0SYakir Yang  */
56d9c900b0SYakir Yang struct rockchip_dp_chip_data {
57d9c900b0SYakir Yang 	u32	lcdsel_grf_reg;
58d9c900b0SYakir Yang 	u32	lcdsel_big;
59d9c900b0SYakir Yang 	u32	lcdsel_lit;
60d9c900b0SYakir Yang 	u32	chip_type;
61d9c900b0SYakir Yang };
629e32e16eSYakir Yang 
639e32e16eSYakir Yang struct rockchip_dp_device {
649e32e16eSYakir Yang 	struct drm_device        *drm_dev;
659e32e16eSYakir Yang 	struct device            *dev;
669e32e16eSYakir Yang 	struct drm_encoder       encoder;
679e32e16eSYakir Yang 	struct drm_display_mode  mode;
689e32e16eSYakir Yang 
699e32e16eSYakir Yang 	struct clk               *pclk;
70dc1c93beSYakir Yang 	struct clk               *grfclk;
719e32e16eSYakir Yang 	struct regmap            *grf;
729e32e16eSYakir Yang 	struct reset_control     *rst;
739e32e16eSYakir Yang 
74d761b2dfSSean Paul 	struct work_struct	 psr_work;
75d761b2dfSSean Paul 	spinlock_t		 psr_lock;
768f0ac5c4SYakir Yang 	unsigned int             psr_state;
778f0ac5c4SYakir Yang 
78d9c900b0SYakir Yang 	const struct rockchip_dp_chip_data *data;
79d9c900b0SYakir Yang 
809e32e16eSYakir Yang 	struct analogix_dp_plat_data plat_data;
819e32e16eSYakir Yang };
829e32e16eSYakir Yang 
838f0ac5c4SYakir Yang static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
848f0ac5c4SYakir Yang {
858f0ac5c4SYakir Yang 	struct rockchip_dp_device *dp = to_dp(encoder);
86d761b2dfSSean Paul 	unsigned long flags;
878f0ac5c4SYakir Yang 
880546d685STomeu Vizoso 	if (!analogix_dp_psr_supported(dp->dev))
890546d685STomeu Vizoso 		return;
900546d685STomeu Vizoso 
918f0ac5c4SYakir Yang 	dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
928f0ac5c4SYakir Yang 
93d761b2dfSSean Paul 	spin_lock_irqsave(&dp->psr_lock, flags);
948f0ac5c4SYakir Yang 	if (enabled)
958f0ac5c4SYakir Yang 		dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
968f0ac5c4SYakir Yang 	else
978f0ac5c4SYakir Yang 		dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
988f0ac5c4SYakir Yang 
99d761b2dfSSean Paul 	schedule_work(&dp->psr_work);
100d761b2dfSSean Paul 	spin_unlock_irqrestore(&dp->psr_lock, flags);
1018f0ac5c4SYakir Yang }
1028f0ac5c4SYakir Yang 
1038f0ac5c4SYakir Yang static void analogix_dp_psr_work(struct work_struct *work)
1048f0ac5c4SYakir Yang {
1058f0ac5c4SYakir Yang 	struct rockchip_dp_device *dp =
106d761b2dfSSean Paul 				container_of(work, typeof(*dp), psr_work);
1078f0ac5c4SYakir Yang 	struct drm_crtc *crtc = dp->encoder.crtc;
1088f0ac5c4SYakir Yang 	int psr_state = dp->psr_state;
1098f0ac5c4SYakir Yang 	int vact_end;
1108f0ac5c4SYakir Yang 	int ret;
111d761b2dfSSean Paul 	unsigned long flags;
1128f0ac5c4SYakir Yang 
1138f0ac5c4SYakir Yang 	if (!crtc)
1148f0ac5c4SYakir Yang 		return;
1158f0ac5c4SYakir Yang 
1168f0ac5c4SYakir Yang 	vact_end = crtc->mode.vtotal - crtc->mode.vsync_start + crtc->mode.vdisplay;
1178f0ac5c4SYakir Yang 
1188f0ac5c4SYakir Yang 	ret = rockchip_drm_wait_line_flag(dp->encoder.crtc, vact_end,
1198f0ac5c4SYakir Yang 					  PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
1208f0ac5c4SYakir Yang 	if (ret) {
1218f0ac5c4SYakir Yang 		dev_err(dp->dev, "line flag interrupt did not arrive\n");
1228f0ac5c4SYakir Yang 		return;
1238f0ac5c4SYakir Yang 	}
1248f0ac5c4SYakir Yang 
125d761b2dfSSean Paul 	spin_lock_irqsave(&dp->psr_lock, flags);
1268f0ac5c4SYakir Yang 	if (psr_state == EDP_VSC_PSR_STATE_ACTIVE)
1278f0ac5c4SYakir Yang 		analogix_dp_enable_psr(dp->dev);
1288f0ac5c4SYakir Yang 	else
1298f0ac5c4SYakir Yang 		analogix_dp_disable_psr(dp->dev);
130d761b2dfSSean Paul 	spin_unlock_irqrestore(&dp->psr_lock, flags);
1318f0ac5c4SYakir Yang }
1328f0ac5c4SYakir Yang 
1339e32e16eSYakir Yang static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
1349e32e16eSYakir Yang {
1359e32e16eSYakir Yang 	reset_control_assert(dp->rst);
1369e32e16eSYakir Yang 	usleep_range(10, 20);
1379e32e16eSYakir Yang 	reset_control_deassert(dp->rst);
1389e32e16eSYakir Yang 
1399e32e16eSYakir Yang 	return 0;
1409e32e16eSYakir Yang }
1419e32e16eSYakir Yang 
1429e32e16eSYakir Yang static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
1439e32e16eSYakir Yang {
1449e32e16eSYakir Yang 	struct rockchip_dp_device *dp = to_dp(plat_data);
1459e32e16eSYakir Yang 	int ret;
1469e32e16eSYakir Yang 
147d761b2dfSSean Paul 	cancel_work_sync(&dp->psr_work);
148d761b2dfSSean Paul 
1499e32e16eSYakir Yang 	ret = clk_prepare_enable(dp->pclk);
1509e32e16eSYakir Yang 	if (ret < 0) {
1519e32e16eSYakir Yang 		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
1529e32e16eSYakir Yang 		return ret;
1539e32e16eSYakir Yang 	}
1549e32e16eSYakir Yang 
1559e32e16eSYakir Yang 	ret = rockchip_dp_pre_init(dp);
1569e32e16eSYakir Yang 	if (ret < 0) {
1579e32e16eSYakir Yang 		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
1583694c5c3SWei Yongjun 		clk_disable_unprepare(dp->pclk);
1599e32e16eSYakir Yang 		return ret;
1609e32e16eSYakir Yang 	}
1619e32e16eSYakir Yang 
1629e32e16eSYakir Yang 	return 0;
1639e32e16eSYakir Yang }
1649e32e16eSYakir Yang 
1659e32e16eSYakir Yang static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
1669e32e16eSYakir Yang {
1679e32e16eSYakir Yang 	struct rockchip_dp_device *dp = to_dp(plat_data);
1689e32e16eSYakir Yang 
1699e32e16eSYakir Yang 	clk_disable_unprepare(dp->pclk);
1709e32e16eSYakir Yang 
1719e32e16eSYakir Yang 	return 0;
1729e32e16eSYakir Yang }
1739e32e16eSYakir Yang 
174db8a9aedSYakir Yang static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
175db8a9aedSYakir Yang 				 struct drm_connector *connector)
176db8a9aedSYakir Yang {
177db8a9aedSYakir Yang 	struct drm_display_info *di = &connector->display_info;
178db8a9aedSYakir Yang 	/* VOP couldn't output YUV video format for eDP rightly */
179db8a9aedSYakir Yang 	u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
180db8a9aedSYakir Yang 
181db8a9aedSYakir Yang 	if ((di->color_formats & mask)) {
182db8a9aedSYakir Yang 		DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
183db8a9aedSYakir Yang 		di->color_formats &= ~mask;
184db8a9aedSYakir Yang 		di->color_formats |= DRM_COLOR_FORMAT_RGB444;
185db8a9aedSYakir Yang 		di->bpc = 8;
186db8a9aedSYakir Yang 	}
187db8a9aedSYakir Yang 
188db8a9aedSYakir Yang 	return 0;
189db8a9aedSYakir Yang }
190db8a9aedSYakir Yang 
1919e32e16eSYakir Yang static bool
1929e32e16eSYakir Yang rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
1939e32e16eSYakir Yang 				   const struct drm_display_mode *mode,
1949e32e16eSYakir Yang 				   struct drm_display_mode *adjusted_mode)
1959e32e16eSYakir Yang {
1969e32e16eSYakir Yang 	/* do nothing */
1979e32e16eSYakir Yang 	return true;
1989e32e16eSYakir Yang }
1999e32e16eSYakir Yang 
2009e32e16eSYakir Yang static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
2019e32e16eSYakir Yang 					     struct drm_display_mode *mode,
2029e32e16eSYakir Yang 					     struct drm_display_mode *adjusted)
2039e32e16eSYakir Yang {
2049e32e16eSYakir Yang 	/* do nothing */
2059e32e16eSYakir Yang }
2069e32e16eSYakir Yang 
2079e32e16eSYakir Yang static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
2089e32e16eSYakir Yang {
2099e32e16eSYakir Yang 	struct rockchip_dp_device *dp = to_dp(encoder);
2109e32e16eSYakir Yang 	int ret;
2119e32e16eSYakir Yang 	u32 val;
2129e32e16eSYakir Yang 
2139e32e16eSYakir Yang 	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
2149e32e16eSYakir Yang 	if (ret < 0)
2159e32e16eSYakir Yang 		return;
2169e32e16eSYakir Yang 
2179e32e16eSYakir Yang 	if (ret)
218d9c900b0SYakir Yang 		val = dp->data->lcdsel_lit;
2199e32e16eSYakir Yang 	else
220d9c900b0SYakir Yang 		val = dp->data->lcdsel_big;
2219e32e16eSYakir Yang 
2229e32e16eSYakir Yang 	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
2239e32e16eSYakir Yang 
224dc1c93beSYakir Yang 	ret = clk_prepare_enable(dp->grfclk);
225dc1c93beSYakir Yang 	if (ret < 0) {
226dc1c93beSYakir Yang 		dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
2279e32e16eSYakir Yang 		return;
2289e32e16eSYakir Yang 	}
229dc1c93beSYakir Yang 
230dc1c93beSYakir Yang 	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
231dc1c93beSYakir Yang 	if (ret != 0)
232dc1c93beSYakir Yang 		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
233dc1c93beSYakir Yang 
234dc1c93beSYakir Yang 	clk_disable_unprepare(dp->grfclk);
2359e32e16eSYakir Yang }
2369e32e16eSYakir Yang 
2379e32e16eSYakir Yang static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
2389e32e16eSYakir Yang {
2399e32e16eSYakir Yang 	/* do nothing */
2409e32e16eSYakir Yang }
2419e32e16eSYakir Yang 
2424e257d9eSMark Yao static int
2434e257d9eSMark Yao rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
2444e257d9eSMark Yao 				      struct drm_crtc_state *crtc_state,
2454e257d9eSMark Yao 				      struct drm_connector_state *conn_state)
2464e257d9eSMark Yao {
2474e257d9eSMark Yao 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
24882872e42SYakir Yang 	struct rockchip_dp_device *dp = to_dp(encoder);
24982872e42SYakir Yang 	int ret;
2504e257d9eSMark Yao 
2514e257d9eSMark Yao 	/*
252d698f0ebSYakir Yang 	 * The hardware IC designed that VOP must output the RGB10 video
253d698f0ebSYakir Yang 	 * format to eDP controller, and if eDP panel only support RGB8,
254d698f0ebSYakir Yang 	 * then eDP controller should cut down the video data, not via VOP
255d698f0ebSYakir Yang 	 * controller, that's why we need to hardcode the VOP output mode
256d698f0ebSYakir Yang 	 * to RGA10 here.
2574e257d9eSMark Yao 	 */
25882872e42SYakir Yang 
2594e257d9eSMark Yao 	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
2604e257d9eSMark Yao 	s->output_type = DRM_MODE_CONNECTOR_eDP;
26182872e42SYakir Yang 	if (dp->data->chip_type == RK3399_EDP) {
26282872e42SYakir Yang 		/*
26382872e42SYakir Yang 		 * For RK3399, VOP Lit must code the out mode to RGB888,
26482872e42SYakir Yang 		 * VOP Big must code the out mode to RGB10.
26582872e42SYakir Yang 		 */
26682872e42SYakir Yang 		ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
26782872e42SYakir Yang 							encoder);
26882872e42SYakir Yang 		if (ret > 0)
26982872e42SYakir Yang 			s->output_mode = ROCKCHIP_OUT_MODE_P888;
27082872e42SYakir Yang 	}
2714e257d9eSMark Yao 
2724e257d9eSMark Yao 	return 0;
2734e257d9eSMark Yao }
2744e257d9eSMark Yao 
2759e32e16eSYakir Yang static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
2769e32e16eSYakir Yang 	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
2779e32e16eSYakir Yang 	.mode_set = rockchip_dp_drm_encoder_mode_set,
2789e32e16eSYakir Yang 	.enable = rockchip_dp_drm_encoder_enable,
2799e32e16eSYakir Yang 	.disable = rockchip_dp_drm_encoder_nop,
2804e257d9eSMark Yao 	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
2819e32e16eSYakir Yang };
2829e32e16eSYakir Yang 
2839e32e16eSYakir Yang static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
2849e32e16eSYakir Yang {
2859e32e16eSYakir Yang 	drm_encoder_cleanup(encoder);
2869e32e16eSYakir Yang }
2879e32e16eSYakir Yang 
2889e32e16eSYakir Yang static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
2899e32e16eSYakir Yang 	.destroy = rockchip_dp_drm_encoder_destroy,
2909e32e16eSYakir Yang };
2919e32e16eSYakir Yang 
2929e32e16eSYakir Yang static int rockchip_dp_init(struct rockchip_dp_device *dp)
2939e32e16eSYakir Yang {
2949e32e16eSYakir Yang 	struct device *dev = dp->dev;
2959e32e16eSYakir Yang 	struct device_node *np = dev->of_node;
2969e32e16eSYakir Yang 	int ret;
2979e32e16eSYakir Yang 
2989e32e16eSYakir Yang 	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2999e32e16eSYakir Yang 	if (IS_ERR(dp->grf)) {
3009e32e16eSYakir Yang 		dev_err(dev, "failed to get rockchip,grf property\n");
3019e32e16eSYakir Yang 		return PTR_ERR(dp->grf);
3029e32e16eSYakir Yang 	}
3039e32e16eSYakir Yang 
304dc1c93beSYakir Yang 	dp->grfclk = devm_clk_get(dev, "grf");
305dc1c93beSYakir Yang 	if (PTR_ERR(dp->grfclk) == -ENOENT) {
306dc1c93beSYakir Yang 		dp->grfclk = NULL;
307dc1c93beSYakir Yang 	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
308dc1c93beSYakir Yang 		return -EPROBE_DEFER;
309dc1c93beSYakir Yang 	} else if (IS_ERR(dp->grfclk)) {
310dc1c93beSYakir Yang 		dev_err(dev, "failed to get grf clock\n");
311dc1c93beSYakir Yang 		return PTR_ERR(dp->grfclk);
312dc1c93beSYakir Yang 	}
313dc1c93beSYakir Yang 
3149e32e16eSYakir Yang 	dp->pclk = devm_clk_get(dev, "pclk");
3159e32e16eSYakir Yang 	if (IS_ERR(dp->pclk)) {
3169e32e16eSYakir Yang 		dev_err(dev, "failed to get pclk property\n");
3179e32e16eSYakir Yang 		return PTR_ERR(dp->pclk);
3189e32e16eSYakir Yang 	}
3199e32e16eSYakir Yang 
3209e32e16eSYakir Yang 	dp->rst = devm_reset_control_get(dev, "dp");
3219e32e16eSYakir Yang 	if (IS_ERR(dp->rst)) {
3229e32e16eSYakir Yang 		dev_err(dev, "failed to get dp reset control\n");
3239e32e16eSYakir Yang 		return PTR_ERR(dp->rst);
3249e32e16eSYakir Yang 	}
3259e32e16eSYakir Yang 
3269e32e16eSYakir Yang 	ret = clk_prepare_enable(dp->pclk);
3279e32e16eSYakir Yang 	if (ret < 0) {
3289e32e16eSYakir Yang 		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
3299e32e16eSYakir Yang 		return ret;
3309e32e16eSYakir Yang 	}
3319e32e16eSYakir Yang 
3329e32e16eSYakir Yang 	ret = rockchip_dp_pre_init(dp);
3339e32e16eSYakir Yang 	if (ret < 0) {
3349e32e16eSYakir Yang 		dev_err(dp->dev, "failed to pre init %d\n", ret);
3353694c5c3SWei Yongjun 		clk_disable_unprepare(dp->pclk);
3369e32e16eSYakir Yang 		return ret;
3379e32e16eSYakir Yang 	}
3389e32e16eSYakir Yang 
3399e32e16eSYakir Yang 	return 0;
3409e32e16eSYakir Yang }
3419e32e16eSYakir Yang 
3429e32e16eSYakir Yang static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
3439e32e16eSYakir Yang {
3449e32e16eSYakir Yang 	struct drm_encoder *encoder = &dp->encoder;
3459e32e16eSYakir Yang 	struct drm_device *drm_dev = dp->drm_dev;
3469e32e16eSYakir Yang 	struct device *dev = dp->dev;
3479e32e16eSYakir Yang 	int ret;
3489e32e16eSYakir Yang 
3499e32e16eSYakir Yang 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
3509e32e16eSYakir Yang 							     dev->of_node);
3519e32e16eSYakir Yang 	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
3529e32e16eSYakir Yang 
3539e32e16eSYakir Yang 	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
3549e32e16eSYakir Yang 			       DRM_MODE_ENCODER_TMDS, NULL);
3559e32e16eSYakir Yang 	if (ret) {
3569e32e16eSYakir Yang 		DRM_ERROR("failed to initialize encoder with drm\n");
3579e32e16eSYakir Yang 		return ret;
3589e32e16eSYakir Yang 	}
3599e32e16eSYakir Yang 
3609e32e16eSYakir Yang 	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
3619e32e16eSYakir Yang 
3629e32e16eSYakir Yang 	return 0;
3639e32e16eSYakir Yang }
3649e32e16eSYakir Yang 
3659e32e16eSYakir Yang static int rockchip_dp_bind(struct device *dev, struct device *master,
3669e32e16eSYakir Yang 			    void *data)
3679e32e16eSYakir Yang {
3689e32e16eSYakir Yang 	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
369d9c900b0SYakir Yang 	const struct rockchip_dp_chip_data *dp_data;
3709e32e16eSYakir Yang 	struct drm_device *drm_dev = data;
3719e32e16eSYakir Yang 	int ret;
3729e32e16eSYakir Yang 
3739e32e16eSYakir Yang 	/*
3749e32e16eSYakir Yang 	 * Just like the probe function said, we don't need the
3759e32e16eSYakir Yang 	 * device drvrate anymore, we should leave the charge to
3769e32e16eSYakir Yang 	 * analogix dp driver, set the device drvdata to NULL.
3779e32e16eSYakir Yang 	 */
3789e32e16eSYakir Yang 	dev_set_drvdata(dev, NULL);
3799e32e16eSYakir Yang 
380d9c900b0SYakir Yang 	dp_data = of_device_get_match_data(dev);
381d9c900b0SYakir Yang 	if (!dp_data)
382d9c900b0SYakir Yang 		return -ENODEV;
383d9c900b0SYakir Yang 
3849e32e16eSYakir Yang 	ret = rockchip_dp_init(dp);
3859e32e16eSYakir Yang 	if (ret < 0)
3869e32e16eSYakir Yang 		return ret;
3879e32e16eSYakir Yang 
388d9c900b0SYakir Yang 	dp->data = dp_data;
3899e32e16eSYakir Yang 	dp->drm_dev = drm_dev;
3909e32e16eSYakir Yang 
3919e32e16eSYakir Yang 	ret = rockchip_dp_drm_create_encoder(dp);
3929e32e16eSYakir Yang 	if (ret) {
3939e32e16eSYakir Yang 		DRM_ERROR("failed to create drm encoder\n");
3949e32e16eSYakir Yang 		return ret;
3959e32e16eSYakir Yang 	}
3969e32e16eSYakir Yang 
3979e32e16eSYakir Yang 	dp->plat_data.encoder = &dp->encoder;
3989e32e16eSYakir Yang 
399d9c900b0SYakir Yang 	dp->plat_data.dev_type = dp->data->chip_type;
4009e32e16eSYakir Yang 	dp->plat_data.power_on = rockchip_dp_poweron;
4019e32e16eSYakir Yang 	dp->plat_data.power_off = rockchip_dp_powerdown;
402db8a9aedSYakir Yang 	dp->plat_data.get_modes = rockchip_dp_get_modes;
4039e32e16eSYakir Yang 
404d761b2dfSSean Paul 	spin_lock_init(&dp->psr_lock);
4058f0ac5c4SYakir Yang 	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
406d761b2dfSSean Paul 	INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
4078f0ac5c4SYakir Yang 
4088f0ac5c4SYakir Yang 	rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
4098f0ac5c4SYakir Yang 
4109e32e16eSYakir Yang 	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
4119e32e16eSYakir Yang }
4129e32e16eSYakir Yang 
4139e32e16eSYakir Yang static void rockchip_dp_unbind(struct device *dev, struct device *master,
4149e32e16eSYakir Yang 			       void *data)
4159e32e16eSYakir Yang {
4168f0ac5c4SYakir Yang 	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
4178f0ac5c4SYakir Yang 
4188f0ac5c4SYakir Yang 	rockchip_drm_psr_unregister(&dp->encoder);
4198f0ac5c4SYakir Yang 
4209e32e16eSYakir Yang 	return analogix_dp_unbind(dev, master, data);
4219e32e16eSYakir Yang }
4229e32e16eSYakir Yang 
4239e32e16eSYakir Yang static const struct component_ops rockchip_dp_component_ops = {
4249e32e16eSYakir Yang 	.bind = rockchip_dp_bind,
4259e32e16eSYakir Yang 	.unbind = rockchip_dp_unbind,
4269e32e16eSYakir Yang };
4279e32e16eSYakir Yang 
4289e32e16eSYakir Yang static int rockchip_dp_probe(struct platform_device *pdev)
4299e32e16eSYakir Yang {
4309e32e16eSYakir Yang 	struct device *dev = &pdev->dev;
431eb87c91cSYakir Yang 	struct drm_panel *panel = NULL;
4329e32e16eSYakir Yang 	struct rockchip_dp_device *dp;
433ebc94461SRob Herring 	int ret;
4349e32e16eSYakir Yang 
435ebc94461SRob Herring 	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
436ebc94461SRob Herring 	if (ret)
437ebc94461SRob Herring 		return ret;
4389e32e16eSYakir Yang 
4399e32e16eSYakir Yang 	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
4409e32e16eSYakir Yang 	if (!dp)
4419e32e16eSYakir Yang 		return -ENOMEM;
4429e32e16eSYakir Yang 
4439e32e16eSYakir Yang 	dp->dev = dev;
4449e32e16eSYakir Yang 
4459e32e16eSYakir Yang 	dp->plat_data.panel = panel;
4469e32e16eSYakir Yang 
4479e32e16eSYakir Yang 	/*
4489e32e16eSYakir Yang 	 * We just use the drvdata until driver run into component
4499e32e16eSYakir Yang 	 * add function, and then we would set drvdata to null, so
4509e32e16eSYakir Yang 	 * that analogix dp driver could take charge of the drvdata.
4519e32e16eSYakir Yang 	 */
4529e32e16eSYakir Yang 	platform_set_drvdata(pdev, dp);
4539e32e16eSYakir Yang 
4549e32e16eSYakir Yang 	return component_add(dev, &rockchip_dp_component_ops);
4559e32e16eSYakir Yang }
4569e32e16eSYakir Yang 
4579e32e16eSYakir Yang static int rockchip_dp_remove(struct platform_device *pdev)
4589e32e16eSYakir Yang {
4599e32e16eSYakir Yang 	component_del(&pdev->dev, &rockchip_dp_component_ops);
4609e32e16eSYakir Yang 
4619e32e16eSYakir Yang 	return 0;
4629e32e16eSYakir Yang }
4639e32e16eSYakir Yang 
4649e32e16eSYakir Yang static const struct dev_pm_ops rockchip_dp_pm_ops = {
465fe64ba5cSTomeu Vizoso #ifdef CONFIG_PM_SLEEP
466fe64ba5cSTomeu Vizoso 	.suspend = analogix_dp_suspend,
467fe64ba5cSTomeu Vizoso 	.resume_early = analogix_dp_resume,
468fe64ba5cSTomeu Vizoso #endif
4699e32e16eSYakir Yang };
4709e32e16eSYakir Yang 
47182872e42SYakir Yang static const struct rockchip_dp_chip_data rk3399_edp = {
47282872e42SYakir Yang 	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
47382872e42SYakir Yang 	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
47482872e42SYakir Yang 	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
47582872e42SYakir Yang 	.chip_type = RK3399_EDP,
47682872e42SYakir Yang };
47782872e42SYakir Yang 
478d9c900b0SYakir Yang static const struct rockchip_dp_chip_data rk3288_dp = {
479d9c900b0SYakir Yang 	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
480d9c900b0SYakir Yang 	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
481d9c900b0SYakir Yang 	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
482d9c900b0SYakir Yang 	.chip_type = RK3288_DP,
483d9c900b0SYakir Yang };
484d9c900b0SYakir Yang 
4859e32e16eSYakir Yang static const struct of_device_id rockchip_dp_dt_ids[] = {
486d9c900b0SYakir Yang 	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
48782872e42SYakir Yang 	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
4889e32e16eSYakir Yang 	{}
4899e32e16eSYakir Yang };
4909e32e16eSYakir Yang MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
4919e32e16eSYakir Yang 
4928820b68bSJeffy Chen struct platform_driver rockchip_dp_driver = {
4939e32e16eSYakir Yang 	.probe = rockchip_dp_probe,
4949e32e16eSYakir Yang 	.remove = rockchip_dp_remove,
4959e32e16eSYakir Yang 	.driver = {
4969e32e16eSYakir Yang 		   .name = "rockchip-dp",
4979e32e16eSYakir Yang 		   .pm = &rockchip_dp_pm_ops,
4989e32e16eSYakir Yang 		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
4999e32e16eSYakir Yang 	},
5009e32e16eSYakir Yang };
501