1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * shmob_drm_regs.h  --  SH Mobile DRM registers
4  *
5  * Copyright (C) 2012 Renesas Electronics Corporation
6  *
7  * Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8  */
9 
10 #ifndef __SHMOB_DRM_REGS_H__
11 #define __SHMOB_DRM_REGS_H__
12 
13 #include <linux/io.h>
14 #include <linux/jiffies.h>
15 
16 #include "shmob_drm_drv.h"
17 
18 /* Register definitions */
19 #define LDDCKPAT1R		0x400
20 #define LDDCKPAT2R		0x404
21 #define LDDCKR			0x410
22 #define LDDCKR_ICKSEL_BUS	(0 << 16)
23 #define LDDCKR_ICKSEL_MIPI	(1 << 16)
24 #define LDDCKR_ICKSEL_HDMI	(2 << 16)
25 #define LDDCKR_ICKSEL_EXT	(3 << 16)
26 #define LDDCKR_ICKSEL_MASK	(7 << 16)
27 #define LDDCKR_MOSEL		(1 << 6)
28 #define LDDCKSTPR		0x414
29 #define LDDCKSTPR_DCKSTS	(1 << 16)
30 #define LDDCKSTPR_DCKSTP	(1 << 0)
31 #define LDMT1R			0x418
32 #define LDMT1R_VPOL		(1 << 28)
33 #define LDMT1R_HPOL		(1 << 27)
34 #define LDMT1R_DWPOL		(1 << 26)
35 #define LDMT1R_DIPOL		(1 << 25)
36 #define LDMT1R_DAPOL		(1 << 24)
37 #define LDMT1R_HSCNT		(1 << 17)
38 #define LDMT1R_DWCNT		(1 << 16)
39 #define LDMT1R_IFM		(1 << 12)
40 #define LDMT1R_MIFTYP_RGB8	(0x0 << 0)
41 #define LDMT1R_MIFTYP_RGB9	(0x4 << 0)
42 #define LDMT1R_MIFTYP_RGB12A	(0x5 << 0)
43 #define LDMT1R_MIFTYP_RGB12B	(0x6 << 0)
44 #define LDMT1R_MIFTYP_RGB16	(0x7 << 0)
45 #define LDMT1R_MIFTYP_RGB18	(0xa << 0)
46 #define LDMT1R_MIFTYP_RGB24	(0xb << 0)
47 #define LDMT1R_MIFTYP_YCBCR	(0xf << 0)
48 #define LDMT1R_MIFTYP_SYS8A	(0x0 << 0)
49 #define LDMT1R_MIFTYP_SYS8B	(0x1 << 0)
50 #define LDMT1R_MIFTYP_SYS8C	(0x2 << 0)
51 #define LDMT1R_MIFTYP_SYS8D	(0x3 << 0)
52 #define LDMT1R_MIFTYP_SYS9	(0x4 << 0)
53 #define LDMT1R_MIFTYP_SYS12	(0x5 << 0)
54 #define LDMT1R_MIFTYP_SYS16A	(0x7 << 0)
55 #define LDMT1R_MIFTYP_SYS16B	(0x8 << 0)
56 #define LDMT1R_MIFTYP_SYS16C	(0x9 << 0)
57 #define LDMT1R_MIFTYP_SYS18	(0xa << 0)
58 #define LDMT1R_MIFTYP_SYS24	(0xb << 0)
59 #define LDMT1R_MIFTYP_MASK	(0xf << 0)
60 #define LDMT2R			0x41c
61 #define LDMT2R_CSUP_MASK	(7 << 26)
62 #define LDMT2R_CSUP_SHIFT	26
63 #define LDMT2R_RSV		(1 << 25)
64 #define LDMT2R_VSEL		(1 << 24)
65 #define LDMT2R_WCSC_MASK	(0xff << 16)
66 #define LDMT2R_WCSC_SHIFT	16
67 #define LDMT2R_WCEC_MASK	(0xff << 8)
68 #define LDMT2R_WCEC_SHIFT	8
69 #define LDMT2R_WCLW_MASK	(0xff << 0)
70 #define LDMT2R_WCLW_SHIFT	0
71 #define LDMT3R			0x420
72 #define LDMT3R_RDLC_MASK	(0x3f << 24)
73 #define LDMT3R_RDLC_SHIFT	24
74 #define LDMT3R_RCSC_MASK	(0xff << 16)
75 #define LDMT3R_RCSC_SHIFT	16
76 #define LDMT3R_RCEC_MASK	(0xff << 8)
77 #define LDMT3R_RCEC_SHIFT	8
78 #define LDMT3R_RCLW_MASK	(0xff << 0)
79 #define LDMT3R_RCLW_SHIFT	0
80 #define LDDFR			0x424
81 #define LDDFR_CF1		(1 << 18)
82 #define LDDFR_CF0		(1 << 17)
83 #define LDDFR_CC		(1 << 16)
84 #define LDDFR_YF_420		(0 << 8)
85 #define LDDFR_YF_422		(1 << 8)
86 #define LDDFR_YF_444		(2 << 8)
87 #define LDDFR_YF_MASK		(3 << 8)
88 #define LDDFR_PKF_ARGB32	(0x00 << 0)
89 #define LDDFR_PKF_RGB16		(0x03 << 0)
90 #define LDDFR_PKF_RGB24		(0x0b << 0)
91 #define LDDFR_PKF_MASK		(0x1f << 0)
92 #define LDSM1R			0x428
93 #define LDSM1R_OS		(1 << 0)
94 #define LDSM2R			0x42c
95 #define LDSM2R_OSTRG		(1 << 0)
96 #define LDSA1R			0x430
97 #define LDSA2R			0x434
98 #define LDMLSR			0x438
99 #define LDWBFR			0x43c
100 #define LDWBCNTR		0x440
101 #define LDWBAR			0x444
102 #define LDHCNR			0x448
103 #define LDHSYNR			0x44c
104 #define LDVLNR			0x450
105 #define LDVSYNR			0x454
106 #define LDHPDR			0x458
107 #define LDVPDR			0x45c
108 #define LDPMR			0x460
109 #define LDPMR_LPS		(3 << 0)
110 #define LDINTR			0x468
111 #define LDINTR_FE		(1 << 10)
112 #define LDINTR_VSE		(1 << 9)
113 #define LDINTR_VEE		(1 << 8)
114 #define LDINTR_FS		(1 << 2)
115 #define LDINTR_VSS		(1 << 1)
116 #define LDINTR_VES		(1 << 0)
117 #define LDINTR_STATUS_MASK	(0xff << 0)
118 #define LDSR			0x46c
119 #define LDSR_MSS		(1 << 10)
120 #define LDSR_MRS		(1 << 8)
121 #define LDSR_AS			(1 << 1)
122 #define LDCNT1R			0x470
123 #define LDCNT1R_DE		(1 << 0)
124 #define LDCNT2R			0x474
125 #define LDCNT2R_BR		(1 << 8)
126 #define LDCNT2R_MD		(1 << 3)
127 #define LDCNT2R_SE		(1 << 2)
128 #define LDCNT2R_ME		(1 << 1)
129 #define LDCNT2R_DO		(1 << 0)
130 #define LDRCNTR			0x478
131 #define LDRCNTR_SRS		(1 << 17)
132 #define LDRCNTR_SRC		(1 << 16)
133 #define LDRCNTR_MRS		(1 << 1)
134 #define LDRCNTR_MRC		(1 << 0)
135 #define LDDDSR			0x47c
136 #define LDDDSR_LS		(1 << 2)
137 #define LDDDSR_WS		(1 << 1)
138 #define LDDDSR_BS		(1 << 0)
139 #define LDHAJR			0x4a0
140 
141 #define LDDWD0R			0x800
142 #define LDDWDxR_WDACT		(1 << 28)
143 #define LDDWDxR_RSW		(1 << 24)
144 #define LDDRDR			0x840
145 #define LDDRDR_RSR		(1 << 24)
146 #define LDDRDR_DRD_MASK		(0x3ffff << 0)
147 #define LDDWAR			0x900
148 #define LDDWAR_WA		(1 << 0)
149 #define LDDRAR			0x904
150 #define LDDRAR_RA		(1 << 0)
151 
152 #define LDBCR			0xb00
153 #define LDBCR_UPC(n)		(1 << ((n) + 16))
154 #define LDBCR_UPF(n)		(1 << ((n) + 8))
155 #define LDBCR_UPD(n)		(1 << ((n) + 0))
156 #define LDBnBSIFR(n)		(0xb20 + (n) * 0x20 + 0x00)
157 #define LDBBSIFR_EN		(1 << 31)
158 #define LDBBSIFR_VS		(1 << 29)
159 #define LDBBSIFR_BRSEL		(1 << 28)
160 #define LDBBSIFR_MX		(1 << 27)
161 #define LDBBSIFR_MY		(1 << 26)
162 #define LDBBSIFR_CV3		(3 << 24)
163 #define LDBBSIFR_CV2		(2 << 24)
164 #define LDBBSIFR_CV1		(1 << 24)
165 #define LDBBSIFR_CV0		(0 << 24)
166 #define LDBBSIFR_CV_MASK	(3 << 24)
167 #define LDBBSIFR_LAY_MASK	(0xff << 16)
168 #define LDBBSIFR_LAY_SHIFT	16
169 #define LDBBSIFR_ROP3_MASK	(0xff << 16)
170 #define LDBBSIFR_ROP3_SHIFT	16
171 #define LDBBSIFR_AL_PL8		(3 << 14)
172 #define LDBBSIFR_AL_PL1		(2 << 14)
173 #define LDBBSIFR_AL_PK		(1 << 14)
174 #define LDBBSIFR_AL_1		(0 << 14)
175 #define LDBBSIFR_AL_MASK	(3 << 14)
176 #define LDBBSIFR_SWPL		(1 << 10)
177 #define LDBBSIFR_SWPW		(1 << 9)
178 #define LDBBSIFR_SWPB		(1 << 8)
179 #define LDBBSIFR_RY		(1 << 7)
180 #define LDBBSIFR_CHRR_420	(2 << 0)
181 #define LDBBSIFR_CHRR_422	(1 << 0)
182 #define LDBBSIFR_CHRR_444	(0 << 0)
183 #define LDBBSIFR_RPKF_ARGB32	(0x00 << 0)
184 #define LDBBSIFR_RPKF_RGB16	(0x03 << 0)
185 #define LDBBSIFR_RPKF_RGB24	(0x0b << 0)
186 #define LDBBSIFR_RPKF_MASK	(0x1f << 0)
187 #define LDBnBSSZR(n)		(0xb20 + (n) * 0x20 + 0x04)
188 #define LDBBSSZR_BVSS_MASK	(0xfff << 16)
189 #define LDBBSSZR_BVSS_SHIFT	16
190 #define LDBBSSZR_BHSS_MASK	(0xfff << 0)
191 #define LDBBSSZR_BHSS_SHIFT	0
192 #define LDBnBLOCR(n)		(0xb20 + (n) * 0x20 + 0x08)
193 #define LDBBLOCR_CVLC_MASK	(0xfff << 16)
194 #define LDBBLOCR_CVLC_SHIFT	16
195 #define LDBBLOCR_CHLC_MASK	(0xfff << 0)
196 #define LDBBLOCR_CHLC_SHIFT	0
197 #define LDBnBSMWR(n)		(0xb20 + (n) * 0x20 + 0x0c)
198 #define LDBBSMWR_BSMWA_MASK	(0xffff << 16)
199 #define LDBBSMWR_BSMWA_SHIFT	16
200 #define LDBBSMWR_BSMW_MASK	(0xffff << 0)
201 #define LDBBSMWR_BSMW_SHIFT	0
202 #define LDBnBSAYR(n)		(0xb20 + (n) * 0x20 + 0x10)
203 #define LDBBSAYR_FG1A_MASK	(0xff << 24)
204 #define LDBBSAYR_FG1A_SHIFT	24
205 #define LDBBSAYR_FG1R_MASK	(0xff << 16)
206 #define LDBBSAYR_FG1R_SHIFT	16
207 #define LDBBSAYR_FG1G_MASK	(0xff << 8)
208 #define LDBBSAYR_FG1G_SHIFT	8
209 #define LDBBSAYR_FG1B_MASK	(0xff << 0)
210 #define LDBBSAYR_FG1B_SHIFT	0
211 #define LDBnBSACR(n)		(0xb20 + (n) * 0x20 + 0x14)
212 #define LDBBSACR_FG2A_MASK	(0xff << 24)
213 #define LDBBSACR_FG2A_SHIFT	24
214 #define LDBBSACR_FG2R_MASK	(0xff << 16)
215 #define LDBBSACR_FG2R_SHIFT	16
216 #define LDBBSACR_FG2G_MASK	(0xff << 8)
217 #define LDBBSACR_FG2G_SHIFT	8
218 #define LDBBSACR_FG2B_MASK	(0xff << 0)
219 #define LDBBSACR_FG2B_SHIFT	0
220 #define LDBnBSAAR(n)		(0xb20 + (n) * 0x20 + 0x18)
221 #define LDBBSAAR_AP_MASK	(0xff << 24)
222 #define LDBBSAAR_AP_SHIFT	24
223 #define LDBBSAAR_R_MASK		(0xff << 16)
224 #define LDBBSAAR_R_SHIFT	16
225 #define LDBBSAAR_GY_MASK	(0xff << 8)
226 #define LDBBSAAR_GY_SHIFT	8
227 #define LDBBSAAR_B_MASK		(0xff << 0)
228 #define LDBBSAAR_B_SHIFT	0
229 #define LDBnBPPCR(n)		(0xb20 + (n) * 0x20 + 0x1c)
230 #define LDBBPPCR_AP_MASK	(0xff << 24)
231 #define LDBBPPCR_AP_SHIFT	24
232 #define LDBBPPCR_R_MASK		(0xff << 16)
233 #define LDBBPPCR_R_SHIFT	16
234 #define LDBBPPCR_GY_MASK	(0xff << 8)
235 #define LDBBPPCR_GY_SHIFT	8
236 #define LDBBPPCR_B_MASK		(0xff << 0)
237 #define LDBBPPCR_B_SHIFT	0
238 #define LDBnBBGCL(n)		(0xb10 + (n) * 0x04)
239 #define LDBBBGCL_BGA_MASK	(0xff << 24)
240 #define LDBBBGCL_BGA_SHIFT	24
241 #define LDBBBGCL_BGR_MASK	(0xff << 16)
242 #define LDBBBGCL_BGR_SHIFT	16
243 #define LDBBBGCL_BGG_MASK	(0xff << 8)
244 #define LDBBBGCL_BGG_SHIFT	8
245 #define LDBBBGCL_BGB_MASK	(0xff << 0)
246 #define LDBBBGCL_BGB_SHIFT	0
247 
248 #define LCDC_SIDE_B_OFFSET	0x1000
249 #define LCDC_MIRROR_OFFSET	0x2000
250 
251 static inline bool lcdc_is_banked(u32 reg)
252 {
253 	switch (reg) {
254 	case LDMT1R:
255 	case LDMT2R:
256 	case LDMT3R:
257 	case LDDFR:
258 	case LDSM1R:
259 	case LDSA1R:
260 	case LDSA2R:
261 	case LDMLSR:
262 	case LDWBFR:
263 	case LDWBCNTR:
264 	case LDWBAR:
265 	case LDHCNR:
266 	case LDHSYNR:
267 	case LDVLNR:
268 	case LDVSYNR:
269 	case LDHPDR:
270 	case LDVPDR:
271 	case LDHAJR:
272 		return true;
273 	default:
274 		return reg >= LDBnBBGCL(0) && reg <= LDBnBPPCR(3);
275 	}
276 }
277 
278 static inline void lcdc_write_mirror(struct shmob_drm_device *sdev, u32 reg,
279 				     u32 data)
280 {
281 	iowrite32(data, sdev->mmio + reg + LCDC_MIRROR_OFFSET);
282 }
283 
284 static inline void lcdc_write(struct shmob_drm_device *sdev, u32 reg, u32 data)
285 {
286 	iowrite32(data, sdev->mmio + reg);
287 	if (lcdc_is_banked(reg))
288 		iowrite32(data, sdev->mmio + reg + LCDC_SIDE_B_OFFSET);
289 }
290 
291 static inline u32 lcdc_read(struct shmob_drm_device *sdev, u32 reg)
292 {
293 	return ioread32(sdev->mmio + reg);
294 }
295 
296 static inline int lcdc_wait_bit(struct shmob_drm_device *sdev, u32 reg,
297 				u32 mask, u32 until)
298 {
299 	unsigned long timeout = jiffies + msecs_to_jiffies(5);
300 
301 	while ((lcdc_read(sdev, reg) & mask) != until) {
302 		if (time_after(jiffies, timeout))
303 			return -ETIMEDOUT;
304 		cpu_relax();
305 	}
306 
307 	return 0;
308 }
309 
310 #endif /* __SHMOB_DRM_REGS_H__ */
311