1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G2L MIPI DSI Encoder Driver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corporation 6 */ 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/slab.h> 19 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <drm/drm_probe_helper.h> 27 28 #include "rzg2l_mipi_dsi_regs.h" 29 30 struct rzg2l_mipi_dsi { 31 struct device *dev; 32 void __iomem *mmio; 33 34 struct reset_control *rstc; 35 struct reset_control *arstc; 36 struct reset_control *prstc; 37 38 struct mipi_dsi_host host; 39 struct drm_bridge bridge; 40 struct drm_bridge *next_bridge; 41 42 struct clk *vclk; 43 44 enum mipi_dsi_pixel_format format; 45 unsigned int num_data_lanes; 46 unsigned int lanes; 47 unsigned long mode_flags; 48 }; 49 50 static inline struct rzg2l_mipi_dsi * 51 bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge) 52 { 53 return container_of(bridge, struct rzg2l_mipi_dsi, bridge); 54 } 55 56 static inline struct rzg2l_mipi_dsi * 57 host_to_rzg2l_mipi_dsi(struct mipi_dsi_host *host) 58 { 59 return container_of(host, struct rzg2l_mipi_dsi, host); 60 } 61 62 struct rzg2l_mipi_dsi_timings { 63 unsigned long hsfreq_max; 64 u32 t_init; 65 u32 tclk_prepare; 66 u32 ths_prepare; 67 u32 tclk_zero; 68 u32 tclk_pre; 69 u32 tclk_post; 70 u32 tclk_trail; 71 u32 ths_zero; 72 u32 ths_trail; 73 u32 ths_exit; 74 u32 tlpx; 75 }; 76 77 static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = { 78 { 79 .hsfreq_max = 80000, 80 .t_init = 79801, 81 .tclk_prepare = 8, 82 .ths_prepare = 13, 83 .tclk_zero = 33, 84 .tclk_pre = 24, 85 .tclk_post = 94, 86 .tclk_trail = 10, 87 .ths_zero = 23, 88 .ths_trail = 17, 89 .ths_exit = 13, 90 .tlpx = 6, 91 }, 92 { 93 .hsfreq_max = 125000, 94 .t_init = 79801, 95 .tclk_prepare = 8, 96 .ths_prepare = 12, 97 .tclk_zero = 33, 98 .tclk_pre = 15, 99 .tclk_post = 94, 100 .tclk_trail = 10, 101 .ths_zero = 23, 102 .ths_trail = 17, 103 .ths_exit = 13, 104 .tlpx = 6, 105 }, 106 { 107 .hsfreq_max = 250000, 108 .t_init = 79801, 109 .tclk_prepare = 8, 110 .ths_prepare = 12, 111 .tclk_zero = 33, 112 .tclk_pre = 13, 113 .tclk_post = 94, 114 .tclk_trail = 10, 115 .ths_zero = 23, 116 .ths_trail = 16, 117 .ths_exit = 13, 118 .tlpx = 6, 119 }, 120 { 121 .hsfreq_max = 360000, 122 .t_init = 79801, 123 .tclk_prepare = 8, 124 .ths_prepare = 10, 125 .tclk_zero = 33, 126 .tclk_pre = 4, 127 .tclk_post = 35, 128 .tclk_trail = 7, 129 .ths_zero = 16, 130 .ths_trail = 9, 131 .ths_exit = 13, 132 .tlpx = 6, 133 }, 134 { 135 .hsfreq_max = 720000, 136 .t_init = 79801, 137 .tclk_prepare = 8, 138 .ths_prepare = 9, 139 .tclk_zero = 33, 140 .tclk_pre = 4, 141 .tclk_post = 35, 142 .tclk_trail = 7, 143 .ths_zero = 16, 144 .ths_trail = 9, 145 .ths_exit = 13, 146 .tlpx = 6, 147 }, 148 { 149 .hsfreq_max = 1500000, 150 .t_init = 79801, 151 .tclk_prepare = 8, 152 .ths_prepare = 9, 153 .tclk_zero = 33, 154 .tclk_pre = 4, 155 .tclk_post = 35, 156 .tclk_trail = 7, 157 .ths_zero = 16, 158 .ths_trail = 9, 159 .ths_exit = 13, 160 .tlpx = 6, 161 }, 162 }; 163 164 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) 165 { 166 iowrite32(data, dsi->mmio + reg); 167 } 168 169 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) 170 { 171 iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); 172 } 173 174 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg) 175 { 176 return ioread32(dsi->mmio + reg); 177 } 178 179 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) 180 { 181 return ioread32(dsi->mmio + LINK_REG_OFFSET + reg); 182 } 183 184 /* ----------------------------------------------------------------------------- 185 * Hardware Setup 186 */ 187 188 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, 189 unsigned long hsfreq) 190 { 191 const struct rzg2l_mipi_dsi_timings *dphy_timings; 192 unsigned int i; 193 u32 dphyctrl0; 194 u32 dphytim0; 195 u32 dphytim1; 196 u32 dphytim2; 197 u32 dphytim3; 198 int ret; 199 200 /* All DSI global operation timings are set with recommended setting */ 201 for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { 202 dphy_timings = &rzg2l_mipi_dsi_global_timings[i]; 203 if (hsfreq <= dphy_timings->hsfreq_max) 204 break; 205 } 206 207 /* Initializing DPHY before accessing LINK */ 208 dphyctrl0 = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN | 209 DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR; 210 211 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0); 212 usleep_range(20, 30); 213 214 dphyctrl0 |= DSIDPHYCTRL0_EN_LDO1200; 215 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0); 216 usleep_range(10, 20); 217 218 dphytim0 = DSIDPHYTIM0_TCLK_MISS(0) | 219 DSIDPHYTIM0_T_INIT(dphy_timings->t_init); 220 dphytim1 = DSIDPHYTIM1_THS_PREPARE(dphy_timings->ths_prepare) | 221 DSIDPHYTIM1_TCLK_PREPARE(dphy_timings->tclk_prepare) | 222 DSIDPHYTIM1_THS_SETTLE(0) | 223 DSIDPHYTIM1_TCLK_SETTLE(0); 224 dphytim2 = DSIDPHYTIM2_TCLK_TRAIL(dphy_timings->tclk_trail) | 225 DSIDPHYTIM2_TCLK_POST(dphy_timings->tclk_post) | 226 DSIDPHYTIM2_TCLK_PRE(dphy_timings->tclk_pre) | 227 DSIDPHYTIM2_TCLK_ZERO(dphy_timings->tclk_zero); 228 dphytim3 = DSIDPHYTIM3_TLPX(dphy_timings->tlpx) | 229 DSIDPHYTIM3_THS_EXIT(dphy_timings->ths_exit) | 230 DSIDPHYTIM3_THS_TRAIL(dphy_timings->ths_trail) | 231 DSIDPHYTIM3_THS_ZERO(dphy_timings->ths_zero); 232 233 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM0, dphytim0); 234 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM1, dphytim1); 235 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2); 236 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3); 237 238 ret = reset_control_deassert(dsi->rstc); 239 if (ret < 0) 240 return ret; 241 242 udelay(1); 243 244 return 0; 245 } 246 247 static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi) 248 { 249 u32 dphyctrl0; 250 251 dphyctrl0 = rzg2l_mipi_dsi_phy_read(dsi, DSIDPHYCTRL0); 252 253 dphyctrl0 &= ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR); 254 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0); 255 256 reset_control_assert(dsi->rstc); 257 } 258 259 static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, 260 const struct drm_display_mode *mode) 261 { 262 unsigned long hsfreq; 263 unsigned int bpp; 264 u32 txsetr; 265 u32 clstptsetr; 266 u32 lptrnstsetr; 267 u32 clkkpt; 268 u32 clkbfht; 269 u32 clkstpt; 270 u32 golpbkt; 271 int ret; 272 273 /* 274 * Relationship between hsclk and vclk must follow 275 * vclk * bpp = hsclk * 8 * lanes 276 * where vclk: video clock (Hz) 277 * bpp: video pixel bit depth 278 * hsclk: DSI HS Byte clock frequency (Hz) 279 * lanes: number of data lanes 280 * 281 * hsclk(bit) = hsclk(byte) * 8 282 */ 283 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 284 hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes); 285 286 ret = pm_runtime_resume_and_get(dsi->dev); 287 if (ret < 0) 288 return ret; 289 290 clk_set_rate(dsi->vclk, mode->clock * 1000); 291 292 ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); 293 if (ret < 0) 294 goto err_phy; 295 296 /* Enable Data lanes and Clock lanes */ 297 txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; 298 rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); 299 300 /* 301 * Global timings characteristic depends on high speed Clock Frequency 302 * Currently MIPI DSI-IF just supports maximum FHD@60 with: 303 * - videoclock = 148.5 (MHz) 304 * - bpp: maximum 24bpp 305 * - data lanes: maximum 4 lanes 306 * Therefore maximum hsclk will be 891 Mbps. 307 */ 308 if (hsfreq > 445500) { 309 clkkpt = 12; 310 clkbfht = 15; 311 clkstpt = 48; 312 golpbkt = 75; 313 } else if (hsfreq > 250000) { 314 clkkpt = 7; 315 clkbfht = 8; 316 clkstpt = 27; 317 golpbkt = 40; 318 } else { 319 clkkpt = 8; 320 clkbfht = 6; 321 clkstpt = 24; 322 golpbkt = 29; 323 } 324 325 clstptsetr = CLSTPTSETR_CLKKPT(clkkpt) | CLSTPTSETR_CLKBFHT(clkbfht) | 326 CLSTPTSETR_CLKSTPT(clkstpt); 327 rzg2l_mipi_dsi_link_write(dsi, CLSTPTSETR, clstptsetr); 328 329 lptrnstsetr = LPTRNSTSETR_GOLPBKT(golpbkt); 330 rzg2l_mipi_dsi_link_write(dsi, LPTRNSTSETR, lptrnstsetr); 331 332 return 0; 333 334 err_phy: 335 rzg2l_mipi_dsi_dphy_exit(dsi); 336 pm_runtime_put(dsi->dev); 337 338 return ret; 339 } 340 341 static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi) 342 { 343 rzg2l_mipi_dsi_dphy_exit(dsi); 344 pm_runtime_put(dsi->dev); 345 } 346 347 static void rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi *dsi, 348 const struct drm_display_mode *mode) 349 { 350 u32 vich1ppsetr; 351 u32 vich1vssetr; 352 u32 vich1vpsetr; 353 u32 vich1hssetr; 354 u32 vich1hpsetr; 355 int dsi_format; 356 u32 delay[2]; 357 u8 index; 358 359 /* Configuration for Pixel Packet */ 360 dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format); 361 switch (dsi_format) { 362 case 24: 363 vich1ppsetr = VICH1PPSETR_DT_RGB24; 364 break; 365 case 18: 366 vich1ppsetr = VICH1PPSETR_DT_RGB18; 367 break; 368 } 369 370 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) && 371 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) 372 vich1ppsetr |= VICH1PPSETR_TXESYNC_PULSE; 373 374 rzg2l_mipi_dsi_link_write(dsi, VICH1PPSETR, vich1ppsetr); 375 376 /* Configuration for Video Parameters */ 377 vich1vssetr = VICH1VSSETR_VACTIVE(mode->vdisplay) | 378 VICH1VSSETR_VSA(mode->vsync_end - mode->vsync_start); 379 vich1vssetr |= (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 380 VICH1VSSETR_VSPOL_HIGH : VICH1VSSETR_VSPOL_LOW; 381 382 vich1vpsetr = VICH1VPSETR_VFP(mode->vsync_start - mode->vdisplay) | 383 VICH1VPSETR_VBP(mode->vtotal - mode->vsync_end); 384 385 vich1hssetr = VICH1HSSETR_HACTIVE(mode->hdisplay) | 386 VICH1HSSETR_HSA(mode->hsync_end - mode->hsync_start); 387 vich1hssetr |= (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 388 VICH1HSSETR_HSPOL_HIGH : VICH1HSSETR_HSPOL_LOW; 389 390 vich1hpsetr = VICH1HPSETR_HFP(mode->hsync_start - mode->hdisplay) | 391 VICH1HPSETR_HBP(mode->htotal - mode->hsync_end); 392 393 rzg2l_mipi_dsi_link_write(dsi, VICH1VSSETR, vich1vssetr); 394 rzg2l_mipi_dsi_link_write(dsi, VICH1VPSETR, vich1vpsetr); 395 rzg2l_mipi_dsi_link_write(dsi, VICH1HSSETR, vich1hssetr); 396 rzg2l_mipi_dsi_link_write(dsi, VICH1HPSETR, vich1hpsetr); 397 398 /* 399 * Configuration for Delay Value 400 * Delay value based on 2 ranges of video clock. 401 * 74.25MHz is videoclock of HD@60p or FHD@30p 402 */ 403 if (mode->clock > 74250) { 404 delay[0] = 231; 405 delay[1] = 216; 406 } else { 407 delay[0] = 220; 408 delay[1] = 212; 409 } 410 411 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 412 index = 0; 413 else 414 index = 1; 415 416 rzg2l_mipi_dsi_link_write(dsi, VICH1SET1R, 417 VICH1SET1R_DLY(delay[index])); 418 } 419 420 static int rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi *dsi) 421 { 422 bool is_clk_cont; 423 u32 hsclksetr; 424 u32 status; 425 int ret; 426 427 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS); 428 429 /* Start HS clock */ 430 hsclksetr = HSCLKSETR_HSCLKRUN_HS | (is_clk_cont ? 431 HSCLKSETR_HSCLKMODE_CONT : 432 HSCLKSETR_HSCLKMODE_NON_CONT); 433 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR, hsclksetr); 434 435 if (is_clk_cont) { 436 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, 437 status & PLSR_CLLP2HS, 438 2000, 20000, false, dsi, PLSR); 439 if (ret < 0) { 440 dev_err(dsi->dev, "failed to start HS clock\n"); 441 return ret; 442 } 443 } 444 445 dev_dbg(dsi->dev, "Start High Speed Clock with %s clock mode", 446 is_clk_cont ? "continuous" : "non-continuous"); 447 448 return 0; 449 } 450 451 static int rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi *dsi) 452 { 453 bool is_clk_cont; 454 u32 status; 455 int ret; 456 457 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS); 458 459 /* Stop HS clock */ 460 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR, 461 is_clk_cont ? HSCLKSETR_HSCLKMODE_CONT : 462 HSCLKSETR_HSCLKMODE_NON_CONT); 463 464 if (is_clk_cont) { 465 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, 466 status & PLSR_CLHS2LP, 467 2000, 20000, false, dsi, PLSR); 468 if (ret < 0) { 469 dev_err(dsi->dev, "failed to stop HS clock\n"); 470 return ret; 471 } 472 } 473 474 return 0; 475 } 476 477 static int rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi *dsi) 478 { 479 u32 vich1set0r; 480 u32 status; 481 int ret; 482 483 /* Configuration for Blanking sequence and start video input*/ 484 vich1set0r = VICH1SET0R_HFPNOLP | VICH1SET0R_HBPNOLP | 485 VICH1SET0R_HSANOLP | VICH1SET0R_VSTART; 486 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, vich1set0r); 487 488 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, 489 status & VICH1SR_VIRDY, 490 2000, 20000, false, dsi, VICH1SR); 491 if (ret < 0) 492 dev_err(dsi->dev, "Failed to start video signal input\n"); 493 494 return ret; 495 } 496 497 static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi) 498 { 499 u32 status; 500 int ret; 501 502 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, VICH1SET0R_VSTPAFT); 503 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, 504 (status & VICH1SR_STOP) && (!(status & VICH1SR_RUNNING)), 505 2000, 20000, false, dsi, VICH1SR); 506 if (ret < 0) 507 goto err; 508 509 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status, 510 !(status & LINKSR_HSBUSY), 511 2000, 20000, false, dsi, LINKSR); 512 if (ret < 0) 513 goto err; 514 515 return 0; 516 517 err: 518 dev_err(dsi->dev, "Failed to stop video signal input\n"); 519 return ret; 520 } 521 522 /* ----------------------------------------------------------------------------- 523 * Bridge 524 */ 525 526 static int rzg2l_mipi_dsi_attach(struct drm_bridge *bridge, 527 enum drm_bridge_attach_flags flags) 528 { 529 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); 530 531 return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge, 532 flags); 533 } 534 535 static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge, 536 struct drm_bridge_state *old_bridge_state) 537 { 538 struct drm_atomic_state *state = old_bridge_state->base.state; 539 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); 540 const struct drm_display_mode *mode; 541 struct drm_connector *connector; 542 struct drm_crtc *crtc; 543 int ret; 544 545 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 546 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 547 mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode; 548 549 ret = rzg2l_mipi_dsi_startup(dsi, mode); 550 if (ret < 0) 551 return; 552 553 rzg2l_mipi_dsi_set_display_timing(dsi, mode); 554 555 ret = rzg2l_mipi_dsi_start_hs_clock(dsi); 556 if (ret < 0) 557 goto err_stop; 558 559 ret = rzg2l_mipi_dsi_start_video(dsi); 560 if (ret < 0) 561 goto err_stop_clock; 562 563 return; 564 565 err_stop_clock: 566 rzg2l_mipi_dsi_stop_hs_clock(dsi); 567 err_stop: 568 rzg2l_mipi_dsi_stop(dsi); 569 } 570 571 static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge, 572 struct drm_bridge_state *old_bridge_state) 573 { 574 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); 575 576 rzg2l_mipi_dsi_stop_video(dsi); 577 rzg2l_mipi_dsi_stop_hs_clock(dsi); 578 rzg2l_mipi_dsi_stop(dsi); 579 } 580 581 static enum drm_mode_status 582 rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 583 const struct drm_display_info *info, 584 const struct drm_display_mode *mode) 585 { 586 if (mode->clock > 148500) 587 return MODE_CLOCK_HIGH; 588 589 return MODE_OK; 590 } 591 592 static const struct drm_bridge_funcs rzg2l_mipi_dsi_bridge_ops = { 593 .attach = rzg2l_mipi_dsi_attach, 594 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 595 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 596 .atomic_reset = drm_atomic_helper_bridge_reset, 597 .atomic_enable = rzg2l_mipi_dsi_atomic_enable, 598 .atomic_disable = rzg2l_mipi_dsi_atomic_disable, 599 .mode_valid = rzg2l_mipi_dsi_bridge_mode_valid, 600 }; 601 602 /* ----------------------------------------------------------------------------- 603 * Host setting 604 */ 605 606 static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, 607 struct mipi_dsi_device *device) 608 { 609 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host); 610 int ret; 611 612 if (device->lanes > dsi->num_data_lanes) { 613 dev_err(dsi->dev, 614 "Number of lines of device (%u) exceeds host (%u)\n", 615 device->lanes, dsi->num_data_lanes); 616 return -EINVAL; 617 } 618 619 switch (mipi_dsi_pixel_format_to_bpp(device->format)) { 620 case 24: 621 case 18: 622 break; 623 default: 624 dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format); 625 return -EINVAL; 626 } 627 628 dsi->lanes = device->lanes; 629 dsi->format = device->format; 630 dsi->mode_flags = device->mode_flags; 631 632 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 633 1, 0); 634 if (IS_ERR(dsi->next_bridge)) { 635 ret = PTR_ERR(dsi->next_bridge); 636 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret); 637 return ret; 638 } 639 640 drm_bridge_add(&dsi->bridge); 641 642 return 0; 643 } 644 645 static int rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host *host, 646 struct mipi_dsi_device *device) 647 { 648 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host); 649 650 drm_bridge_remove(&dsi->bridge); 651 652 return 0; 653 } 654 655 static const struct mipi_dsi_host_ops rzg2l_mipi_dsi_host_ops = { 656 .attach = rzg2l_mipi_dsi_host_attach, 657 .detach = rzg2l_mipi_dsi_host_detach, 658 }; 659 660 /* ----------------------------------------------------------------------------- 661 * Power Management 662 */ 663 664 static int __maybe_unused rzg2l_mipi_pm_runtime_suspend(struct device *dev) 665 { 666 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev); 667 668 reset_control_assert(dsi->prstc); 669 reset_control_assert(dsi->arstc); 670 671 return 0; 672 } 673 674 static int __maybe_unused rzg2l_mipi_pm_runtime_resume(struct device *dev) 675 { 676 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev); 677 int ret; 678 679 ret = reset_control_deassert(dsi->arstc); 680 if (ret < 0) 681 return ret; 682 683 ret = reset_control_deassert(dsi->prstc); 684 if (ret < 0) 685 reset_control_assert(dsi->arstc); 686 687 return ret; 688 } 689 690 static const struct dev_pm_ops rzg2l_mipi_pm_ops = { 691 SET_RUNTIME_PM_OPS(rzg2l_mipi_pm_runtime_suspend, rzg2l_mipi_pm_runtime_resume, NULL) 692 }; 693 694 /* ----------------------------------------------------------------------------- 695 * Probe & Remove 696 */ 697 698 static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) 699 { 700 unsigned int num_data_lanes; 701 struct rzg2l_mipi_dsi *dsi; 702 u32 txsetr; 703 int ret; 704 705 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 706 if (!dsi) 707 return -ENOMEM; 708 709 platform_set_drvdata(pdev, dsi); 710 dsi->dev = &pdev->dev; 711 712 ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); 713 if (ret < 0) 714 return dev_err_probe(dsi->dev, ret, 715 "missing or invalid data-lanes property\n"); 716 717 num_data_lanes = ret; 718 719 dsi->mmio = devm_platform_ioremap_resource(pdev, 0); 720 if (IS_ERR(dsi->mmio)) 721 return PTR_ERR(dsi->mmio); 722 723 dsi->vclk = devm_clk_get(dsi->dev, "vclk"); 724 if (IS_ERR(dsi->vclk)) 725 return PTR_ERR(dsi->vclk); 726 727 dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); 728 if (IS_ERR(dsi->rstc)) 729 return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), 730 "failed to get rst\n"); 731 732 dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst"); 733 if (IS_ERR(dsi->arstc)) 734 return dev_err_probe(&pdev->dev, PTR_ERR(dsi->arstc), 735 "failed to get arst\n"); 736 737 dsi->prstc = devm_reset_control_get_exclusive(dsi->dev, "prst"); 738 if (IS_ERR(dsi->prstc)) 739 return dev_err_probe(dsi->dev, PTR_ERR(dsi->prstc), 740 "failed to get prst\n"); 741 742 platform_set_drvdata(pdev, dsi); 743 744 pm_runtime_enable(dsi->dev); 745 746 ret = pm_runtime_resume_and_get(dsi->dev); 747 if (ret < 0) 748 goto err_pm_disable; 749 750 /* 751 * TXSETR register can be read only after DPHY init. But during probe 752 * mode->clock and format are not available. So initialize DPHY with 753 * timing parameters for 80Mbps. 754 */ 755 ret = rzg2l_mipi_dsi_dphy_init(dsi, 80000); 756 if (ret < 0) 757 goto err_phy; 758 759 txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR); 760 dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes); 761 rzg2l_mipi_dsi_dphy_exit(dsi); 762 pm_runtime_put(dsi->dev); 763 764 /* Initialize the DRM bridge. */ 765 dsi->bridge.funcs = &rzg2l_mipi_dsi_bridge_ops; 766 dsi->bridge.of_node = dsi->dev->of_node; 767 768 /* Init host device */ 769 dsi->host.dev = dsi->dev; 770 dsi->host.ops = &rzg2l_mipi_dsi_host_ops; 771 ret = mipi_dsi_host_register(&dsi->host); 772 if (ret < 0) 773 goto err_pm_disable; 774 775 return 0; 776 777 err_phy: 778 rzg2l_mipi_dsi_dphy_exit(dsi); 779 pm_runtime_put(dsi->dev); 780 err_pm_disable: 781 pm_runtime_disable(dsi->dev); 782 return ret; 783 } 784 785 static int rzg2l_mipi_dsi_remove(struct platform_device *pdev) 786 { 787 struct rzg2l_mipi_dsi *dsi = platform_get_drvdata(pdev); 788 789 mipi_dsi_host_unregister(&dsi->host); 790 pm_runtime_disable(&pdev->dev); 791 792 return 0; 793 } 794 795 static const struct of_device_id rzg2l_mipi_dsi_of_table[] = { 796 { .compatible = "renesas,rzg2l-mipi-dsi" }, 797 { /* sentinel */ } 798 }; 799 800 MODULE_DEVICE_TABLE(of, rzg2l_mipi_dsi_of_table); 801 802 static struct platform_driver rzg2l_mipi_dsi_platform_driver = { 803 .probe = rzg2l_mipi_dsi_probe, 804 .remove = rzg2l_mipi_dsi_remove, 805 .driver = { 806 .name = "rzg2l-mipi-dsi", 807 .pm = &rzg2l_mipi_pm_ops, 808 .of_match_table = rzg2l_mipi_dsi_of_table, 809 }, 810 }; 811 812 module_platform_driver(rzg2l_mipi_dsi_platform_driver); 813 814 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 815 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI DSI Encoder Driver"); 816 MODULE_LICENSE("GPL"); 817