1*11696c5eSBiju Das /* SPDX-License-Identifier: GPL-2.0 */ 2*11696c5eSBiju Das /* 3*11696c5eSBiju Das * R-Car LVDS Interface Registers Definitions 4*11696c5eSBiju Das * 5*11696c5eSBiju Das * Copyright (C) 2013-2015 Renesas Electronics Corporation 6*11696c5eSBiju Das * 7*11696c5eSBiju Das * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8*11696c5eSBiju Das */ 9*11696c5eSBiju Das 10*11696c5eSBiju Das #ifndef __RCAR_LVDS_REGS_H__ 11*11696c5eSBiju Das #define __RCAR_LVDS_REGS_H__ 12*11696c5eSBiju Das 13*11696c5eSBiju Das #define LVDCR0 0x0000 14*11696c5eSBiju Das #define LVDCR0_DUSEL (1 << 15) 15*11696c5eSBiju Das #define LVDCR0_DMD (1 << 12) /* Gen2 only */ 16*11696c5eSBiju Das #define LVDCR0_LVMD_MASK (0xf << 8) 17*11696c5eSBiju Das #define LVDCR0_LVMD_SHIFT 8 18*11696c5eSBiju Das #define LVDCR0_PLLON (1 << 4) 19*11696c5eSBiju Das #define LVDCR0_PWD (1 << 2) /* Gen3 only */ 20*11696c5eSBiju Das #define LVDCR0_BEN (1 << 2) /* Gen2 only */ 21*11696c5eSBiju Das #define LVDCR0_LVEN (1 << 1) 22*11696c5eSBiju Das #define LVDCR0_LVRES (1 << 0) 23*11696c5eSBiju Das 24*11696c5eSBiju Das #define LVDCR1 0x0004 25*11696c5eSBiju Das #define LVDCR1_CKSEL (1 << 15) /* Gen2 only */ 26*11696c5eSBiju Das #define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2)) 27*11696c5eSBiju Das #define LVDCR1_CLKSTBY (3 << 0) 28*11696c5eSBiju Das 29*11696c5eSBiju Das #define LVDPLLCR 0x0008 30*11696c5eSBiju Das /* Gen2 & V3M */ 31*11696c5eSBiju Das #define LVDPLLCR_CEEN (1 << 14) 32*11696c5eSBiju Das #define LVDPLLCR_FBEN (1 << 13) 33*11696c5eSBiju Das #define LVDPLLCR_COSEL (1 << 12) 34*11696c5eSBiju Das #define LVDPLLCR_PLLDLYCNT_150M (0x1bf << 0) 35*11696c5eSBiju Das #define LVDPLLCR_PLLDLYCNT_121M (0x22c << 0) 36*11696c5eSBiju Das #define LVDPLLCR_PLLDLYCNT_60M (0x77b << 0) 37*11696c5eSBiju Das #define LVDPLLCR_PLLDLYCNT_38M (0x69a << 0) 38*11696c5eSBiju Das #define LVDPLLCR_PLLDLYCNT_MASK (0x7ff << 0) 39*11696c5eSBiju Das /* Gen3 but V3M,D3 and E3 */ 40*11696c5eSBiju Das #define LVDPLLCR_PLLDIVCNT_42M (0x014cb << 0) 41*11696c5eSBiju Das #define LVDPLLCR_PLLDIVCNT_85M (0x00a45 << 0) 42*11696c5eSBiju Das #define LVDPLLCR_PLLDIVCNT_128M (0x006c3 << 0) 43*11696c5eSBiju Das #define LVDPLLCR_PLLDIVCNT_148M (0x046c1 << 0) 44*11696c5eSBiju Das #define LVDPLLCR_PLLDIVCNT_MASK (0x7ffff << 0) 45*11696c5eSBiju Das /* D3 and E3 */ 46*11696c5eSBiju Das #define LVDPLLCR_PLLON (1 << 22) 47*11696c5eSBiju Das #define LVDPLLCR_PLLSEL_PLL0 (0 << 20) 48*11696c5eSBiju Das #define LVDPLLCR_PLLSEL_LVX (1 << 20) 49*11696c5eSBiju Das #define LVDPLLCR_PLLSEL_PLL1 (2 << 20) 50*11696c5eSBiju Das #define LVDPLLCR_CKSEL_LVX (1 << 17) 51*11696c5eSBiju Das #define LVDPLLCR_CKSEL_EXTAL (3 << 17) 52*11696c5eSBiju Das #define LVDPLLCR_CKSEL_DU_DOTCLKIN(n) ((5 + (n) * 2) << 17) 53*11696c5eSBiju Das #define LVDPLLCR_OCKSEL (1 << 16) 54*11696c5eSBiju Das #define LVDPLLCR_STP_CLKOUTE (1 << 14) 55*11696c5eSBiju Das #define LVDPLLCR_OUTCLKSEL (1 << 12) 56*11696c5eSBiju Das #define LVDPLLCR_CLKOUT (1 << 11) 57*11696c5eSBiju Das #define LVDPLLCR_PLLE(n) ((n) << 10) 58*11696c5eSBiju Das #define LVDPLLCR_PLLN(n) ((n) << 3) 59*11696c5eSBiju Das #define LVDPLLCR_PLLM(n) ((n) << 0) 60*11696c5eSBiju Das 61*11696c5eSBiju Das #define LVDCTRCR 0x000c 62*11696c5eSBiju Das #define LVDCTRCR_CTR3SEL_ZERO (0 << 12) 63*11696c5eSBiju Das #define LVDCTRCR_CTR3SEL_ODD (1 << 12) 64*11696c5eSBiju Das #define LVDCTRCR_CTR3SEL_CDE (2 << 12) 65*11696c5eSBiju Das #define LVDCTRCR_CTR3SEL_MASK (7 << 12) 66*11696c5eSBiju Das #define LVDCTRCR_CTR2SEL_DISP (0 << 8) 67*11696c5eSBiju Das #define LVDCTRCR_CTR2SEL_ODD (1 << 8) 68*11696c5eSBiju Das #define LVDCTRCR_CTR2SEL_CDE (2 << 8) 69*11696c5eSBiju Das #define LVDCTRCR_CTR2SEL_HSYNC (3 << 8) 70*11696c5eSBiju Das #define LVDCTRCR_CTR2SEL_VSYNC (4 << 8) 71*11696c5eSBiju Das #define LVDCTRCR_CTR2SEL_MASK (7 << 8) 72*11696c5eSBiju Das #define LVDCTRCR_CTR1SEL_VSYNC (0 << 4) 73*11696c5eSBiju Das #define LVDCTRCR_CTR1SEL_DISP (1 << 4) 74*11696c5eSBiju Das #define LVDCTRCR_CTR1SEL_ODD (2 << 4) 75*11696c5eSBiju Das #define LVDCTRCR_CTR1SEL_CDE (3 << 4) 76*11696c5eSBiju Das #define LVDCTRCR_CTR1SEL_HSYNC (4 << 4) 77*11696c5eSBiju Das #define LVDCTRCR_CTR1SEL_MASK (7 << 4) 78*11696c5eSBiju Das #define LVDCTRCR_CTR0SEL_HSYNC (0 << 0) 79*11696c5eSBiju Das #define LVDCTRCR_CTR0SEL_VSYNC (1 << 0) 80*11696c5eSBiju Das #define LVDCTRCR_CTR0SEL_DISP (2 << 0) 81*11696c5eSBiju Das #define LVDCTRCR_CTR0SEL_ODD (3 << 0) 82*11696c5eSBiju Das #define LVDCTRCR_CTR0SEL_CDE (4 << 0) 83*11696c5eSBiju Das #define LVDCTRCR_CTR0SEL_MASK (7 << 0) 84*11696c5eSBiju Das 85*11696c5eSBiju Das #define LVDCHCR 0x0010 86*11696c5eSBiju Das #define LVDCHCR_CHSEL_CH(n, c) ((((c) - (n)) & 3) << ((n) * 4)) 87*11696c5eSBiju Das #define LVDCHCR_CHSEL_MASK(n) (3 << ((n) * 4)) 88*11696c5eSBiju Das 89*11696c5eSBiju Das /* All registers below are specific to D3 and E3 */ 90*11696c5eSBiju Das #define LVDSTRIPE 0x0014 91*11696c5eSBiju Das #define LVDSTRIPE_ST_TRGSEL_DISP (0 << 2) 92*11696c5eSBiju Das #define LVDSTRIPE_ST_TRGSEL_HSYNC_R (1 << 2) 93*11696c5eSBiju Das #define LVDSTRIPE_ST_TRGSEL_HSYNC_F (2 << 2) 94*11696c5eSBiju Das #define LVDSTRIPE_ST_SWAP (1 << 1) 95*11696c5eSBiju Das #define LVDSTRIPE_ST_ON (1 << 0) 96*11696c5eSBiju Das 97*11696c5eSBiju Das #define LVDSCR 0x0018 98*11696c5eSBiju Das #define LVDSCR_DEPTH(n) (((n) - 1) << 29) 99*11696c5eSBiju Das #define LVDSCR_BANDSET (1 << 28) 100*11696c5eSBiju Das #define LVDSCR_TWGCNT(n) ((((n) - 256) / 16) << 24) 101*11696c5eSBiju Das #define LVDSCR_SDIV(n) ((n) << 22) 102*11696c5eSBiju Das #define LVDSCR_MODE (1 << 21) 103*11696c5eSBiju Das #define LVDSCR_RSTN (1 << 20) 104*11696c5eSBiju Das 105*11696c5eSBiju Das #define LVDDIV 0x001c 106*11696c5eSBiju Das #define LVDDIV_DIVSEL (1 << 8) 107*11696c5eSBiju Das #define LVDDIV_DIVRESET (1 << 7) 108*11696c5eSBiju Das #define LVDDIV_DIVSTP (1 << 6) 109*11696c5eSBiju Das #define LVDDIV_DIV(n) ((n) << 0) 110*11696c5eSBiju Das 111*11696c5eSBiju Das #endif /* __RCAR_LVDS_REGS_H__ */ 112