1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * R-Car Display Unit Mode Setting 4 * 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 6 * 7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8 */ 9 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_atomic_helper.h> 12 #include <drm/drm_crtc.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_framebuffer.h> 15 #include <drm/drm_gem_dma_helper.h> 16 #include <drm/drm_gem_framebuffer_helper.h> 17 #include <drm/drm_managed.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_vblank.h> 20 21 #include <linux/device.h> 22 #include <linux/dma-buf.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_platform.h> 25 #include <linux/wait.h> 26 27 #include "rcar_du_crtc.h" 28 #include "rcar_du_drv.h" 29 #include "rcar_du_encoder.h" 30 #include "rcar_du_kms.h" 31 #include "rcar_du_regs.h" 32 #include "rcar_du_vsp.h" 33 #include "rcar_du_writeback.h" 34 35 /* ----------------------------------------------------------------------------- 36 * Format helpers 37 */ 38 39 static const struct rcar_du_format_info rcar_du_format_infos[] = { 40 { 41 .fourcc = DRM_FORMAT_RGB565, 42 .v4l2 = V4L2_PIX_FMT_RGB565, 43 .bpp = 16, 44 .planes = 1, 45 .hsub = 1, 46 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP, 47 .edf = PnDDCR4_EDF_NONE, 48 }, { 49 .fourcc = DRM_FORMAT_ARGB1555, 50 .v4l2 = V4L2_PIX_FMT_ARGB555, 51 .bpp = 16, 52 .planes = 1, 53 .hsub = 1, 54 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB, 55 .edf = PnDDCR4_EDF_NONE, 56 }, { 57 .fourcc = DRM_FORMAT_XRGB1555, 58 .v4l2 = V4L2_PIX_FMT_XRGB555, 59 .bpp = 16, 60 .planes = 1, 61 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB, 62 .edf = PnDDCR4_EDF_NONE, 63 }, { 64 .fourcc = DRM_FORMAT_XRGB8888, 65 .v4l2 = V4L2_PIX_FMT_XBGR32, 66 .bpp = 32, 67 .planes = 1, 68 .hsub = 1, 69 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP, 70 .edf = PnDDCR4_EDF_RGB888, 71 }, { 72 .fourcc = DRM_FORMAT_ARGB8888, 73 .v4l2 = V4L2_PIX_FMT_ABGR32, 74 .bpp = 32, 75 .planes = 1, 76 .hsub = 1, 77 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP, 78 .edf = PnDDCR4_EDF_ARGB8888, 79 }, { 80 .fourcc = DRM_FORMAT_UYVY, 81 .v4l2 = V4L2_PIX_FMT_UYVY, 82 .bpp = 16, 83 .planes = 1, 84 .hsub = 2, 85 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC, 86 .edf = PnDDCR4_EDF_NONE, 87 }, { 88 .fourcc = DRM_FORMAT_YUYV, 89 .v4l2 = V4L2_PIX_FMT_YUYV, 90 .bpp = 16, 91 .planes = 1, 92 .hsub = 2, 93 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC, 94 .edf = PnDDCR4_EDF_NONE, 95 }, { 96 .fourcc = DRM_FORMAT_NV12, 97 .v4l2 = V4L2_PIX_FMT_NV12M, 98 .bpp = 12, 99 .planes = 2, 100 .hsub = 2, 101 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC, 102 .edf = PnDDCR4_EDF_NONE, 103 }, { 104 .fourcc = DRM_FORMAT_NV21, 105 .v4l2 = V4L2_PIX_FMT_NV21M, 106 .bpp = 12, 107 .planes = 2, 108 .hsub = 2, 109 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC, 110 .edf = PnDDCR4_EDF_NONE, 111 }, { 112 .fourcc = DRM_FORMAT_NV16, 113 .v4l2 = V4L2_PIX_FMT_NV16M, 114 .bpp = 16, 115 .planes = 2, 116 .hsub = 2, 117 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC, 118 .edf = PnDDCR4_EDF_NONE, 119 }, 120 /* 121 * The following formats are not supported on Gen2 and thus have no 122 * associated .pnmr or .edf settings. 123 */ 124 { 125 .fourcc = DRM_FORMAT_RGB332, 126 .v4l2 = V4L2_PIX_FMT_RGB332, 127 .bpp = 8, 128 .planes = 1, 129 .hsub = 1, 130 }, { 131 .fourcc = DRM_FORMAT_ARGB4444, 132 .v4l2 = V4L2_PIX_FMT_ARGB444, 133 .bpp = 16, 134 .planes = 1, 135 .hsub = 1, 136 }, { 137 .fourcc = DRM_FORMAT_XRGB4444, 138 .v4l2 = V4L2_PIX_FMT_XRGB444, 139 .bpp = 16, 140 .planes = 1, 141 .hsub = 1, 142 }, { 143 .fourcc = DRM_FORMAT_RGBA4444, 144 .v4l2 = V4L2_PIX_FMT_RGBA444, 145 .bpp = 16, 146 .planes = 1, 147 .hsub = 1, 148 }, { 149 .fourcc = DRM_FORMAT_RGBX4444, 150 .v4l2 = V4L2_PIX_FMT_RGBX444, 151 .bpp = 16, 152 .planes = 1, 153 .hsub = 1, 154 }, { 155 .fourcc = DRM_FORMAT_ABGR4444, 156 .v4l2 = V4L2_PIX_FMT_ABGR444, 157 .bpp = 16, 158 .planes = 1, 159 .hsub = 1, 160 }, { 161 .fourcc = DRM_FORMAT_XBGR4444, 162 .v4l2 = V4L2_PIX_FMT_XBGR444, 163 .bpp = 16, 164 .planes = 1, 165 .hsub = 1, 166 }, { 167 .fourcc = DRM_FORMAT_BGRA4444, 168 .v4l2 = V4L2_PIX_FMT_BGRA444, 169 .bpp = 16, 170 .planes = 1, 171 .hsub = 1, 172 }, { 173 .fourcc = DRM_FORMAT_BGRX4444, 174 .v4l2 = V4L2_PIX_FMT_BGRX444, 175 .bpp = 16, 176 .planes = 1, 177 .hsub = 1, 178 }, { 179 .fourcc = DRM_FORMAT_RGBA5551, 180 .v4l2 = V4L2_PIX_FMT_RGBA555, 181 .bpp = 16, 182 .planes = 1, 183 .hsub = 1, 184 }, { 185 .fourcc = DRM_FORMAT_RGBX5551, 186 .v4l2 = V4L2_PIX_FMT_RGBX555, 187 .bpp = 16, 188 .planes = 1, 189 .hsub = 1, 190 }, { 191 .fourcc = DRM_FORMAT_ABGR1555, 192 .v4l2 = V4L2_PIX_FMT_ABGR555, 193 .bpp = 16, 194 .planes = 1, 195 .hsub = 1, 196 }, { 197 .fourcc = DRM_FORMAT_XBGR1555, 198 .v4l2 = V4L2_PIX_FMT_XBGR555, 199 .bpp = 16, 200 .planes = 1, 201 .hsub = 1, 202 }, { 203 .fourcc = DRM_FORMAT_BGRA5551, 204 .v4l2 = V4L2_PIX_FMT_BGRA555, 205 .bpp = 16, 206 .planes = 1, 207 .hsub = 1, 208 }, { 209 .fourcc = DRM_FORMAT_BGRX5551, 210 .v4l2 = V4L2_PIX_FMT_BGRX555, 211 .bpp = 16, 212 .planes = 1, 213 .hsub = 1, 214 }, { 215 .fourcc = DRM_FORMAT_BGR888, 216 .v4l2 = V4L2_PIX_FMT_RGB24, 217 .bpp = 24, 218 .planes = 1, 219 .hsub = 1, 220 }, { 221 .fourcc = DRM_FORMAT_RGB888, 222 .v4l2 = V4L2_PIX_FMT_BGR24, 223 .bpp = 24, 224 .planes = 1, 225 .hsub = 1, 226 }, { 227 .fourcc = DRM_FORMAT_RGBA8888, 228 .v4l2 = V4L2_PIX_FMT_BGRA32, 229 .bpp = 32, 230 .planes = 1, 231 .hsub = 1, 232 }, { 233 .fourcc = DRM_FORMAT_RGBX8888, 234 .v4l2 = V4L2_PIX_FMT_BGRX32, 235 .bpp = 32, 236 .planes = 1, 237 .hsub = 1, 238 }, { 239 .fourcc = DRM_FORMAT_ABGR8888, 240 .v4l2 = V4L2_PIX_FMT_RGBA32, 241 .bpp = 32, 242 .planes = 1, 243 .hsub = 1, 244 }, { 245 .fourcc = DRM_FORMAT_XBGR8888, 246 .v4l2 = V4L2_PIX_FMT_RGBX32, 247 .bpp = 32, 248 .planes = 1, 249 .hsub = 1, 250 }, { 251 .fourcc = DRM_FORMAT_BGRA8888, 252 .v4l2 = V4L2_PIX_FMT_ARGB32, 253 .bpp = 32, 254 .planes = 1, 255 .hsub = 1, 256 }, { 257 .fourcc = DRM_FORMAT_BGRX8888, 258 .v4l2 = V4L2_PIX_FMT_XRGB32, 259 .bpp = 32, 260 .planes = 1, 261 .hsub = 1, 262 }, { 263 .fourcc = DRM_FORMAT_RGBX1010102, 264 .v4l2 = V4L2_PIX_FMT_RGBX1010102, 265 .bpp = 32, 266 .planes = 1, 267 .hsub = 1, 268 }, { 269 .fourcc = DRM_FORMAT_RGBA1010102, 270 .v4l2 = V4L2_PIX_FMT_RGBA1010102, 271 .bpp = 32, 272 .planes = 1, 273 .hsub = 1, 274 }, { 275 .fourcc = DRM_FORMAT_ARGB2101010, 276 .v4l2 = V4L2_PIX_FMT_ARGB2101010, 277 .bpp = 32, 278 .planes = 1, 279 .hsub = 1, 280 }, { 281 .fourcc = DRM_FORMAT_YVYU, 282 .v4l2 = V4L2_PIX_FMT_YVYU, 283 .bpp = 16, 284 .planes = 1, 285 .hsub = 2, 286 }, { 287 .fourcc = DRM_FORMAT_NV61, 288 .v4l2 = V4L2_PIX_FMT_NV61M, 289 .bpp = 16, 290 .planes = 2, 291 .hsub = 2, 292 }, { 293 .fourcc = DRM_FORMAT_YUV420, 294 .v4l2 = V4L2_PIX_FMT_YUV420M, 295 .bpp = 12, 296 .planes = 3, 297 .hsub = 2, 298 }, { 299 .fourcc = DRM_FORMAT_YVU420, 300 .v4l2 = V4L2_PIX_FMT_YVU420M, 301 .bpp = 12, 302 .planes = 3, 303 .hsub = 2, 304 }, { 305 .fourcc = DRM_FORMAT_YUV422, 306 .v4l2 = V4L2_PIX_FMT_YUV422M, 307 .bpp = 16, 308 .planes = 3, 309 .hsub = 2, 310 }, { 311 .fourcc = DRM_FORMAT_YVU422, 312 .v4l2 = V4L2_PIX_FMT_YVU422M, 313 .bpp = 16, 314 .planes = 3, 315 .hsub = 2, 316 }, { 317 .fourcc = DRM_FORMAT_YUV444, 318 .v4l2 = V4L2_PIX_FMT_YUV444M, 319 .bpp = 24, 320 .planes = 3, 321 .hsub = 1, 322 }, { 323 .fourcc = DRM_FORMAT_YVU444, 324 .v4l2 = V4L2_PIX_FMT_YVU444M, 325 .bpp = 24, 326 .planes = 3, 327 .hsub = 1, 328 }, { 329 .fourcc = DRM_FORMAT_Y210, 330 .v4l2 = V4L2_PIX_FMT_Y210, 331 .bpp = 32, 332 .planes = 1, 333 .hsub = 2, 334 }, { 335 .fourcc = DRM_FORMAT_Y212, 336 .v4l2 = V4L2_PIX_FMT_Y212, 337 .bpp = 32, 338 .planes = 1, 339 .hsub = 2, 340 }, 341 }; 342 343 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc) 344 { 345 unsigned int i; 346 347 for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) { 348 if (rcar_du_format_infos[i].fourcc == fourcc) 349 return &rcar_du_format_infos[i]; 350 } 351 352 return NULL; 353 } 354 355 /* ----------------------------------------------------------------------------- 356 * Frame buffer 357 */ 358 359 static const struct drm_gem_object_funcs rcar_du_gem_funcs = { 360 .free = drm_gem_dma_object_free, 361 .print_info = drm_gem_dma_object_print_info, 362 .get_sg_table = drm_gem_dma_object_get_sg_table, 363 .vmap = drm_gem_dma_object_vmap, 364 .mmap = drm_gem_dma_object_mmap, 365 .vm_ops = &drm_gem_dma_vm_ops, 366 }; 367 368 struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device *dev, 369 struct dma_buf_attachment *attach, 370 struct sg_table *sgt) 371 { 372 struct rcar_du_device *rcdu = to_rcar_du_device(dev); 373 struct drm_gem_dma_object *dma_obj; 374 struct drm_gem_object *gem_obj; 375 int ret; 376 377 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) 378 return drm_gem_dma_prime_import_sg_table(dev, attach, sgt); 379 380 /* Create a DMA GEM buffer. */ 381 dma_obj = kzalloc(sizeof(*dma_obj), GFP_KERNEL); 382 if (!dma_obj) 383 return ERR_PTR(-ENOMEM); 384 385 gem_obj = &dma_obj->base; 386 gem_obj->funcs = &rcar_du_gem_funcs; 387 388 drm_gem_private_object_init(dev, gem_obj, attach->dmabuf->size); 389 dma_obj->map_noncoherent = false; 390 391 ret = drm_gem_create_mmap_offset(gem_obj); 392 if (ret) { 393 drm_gem_object_release(gem_obj); 394 kfree(dma_obj); 395 return ERR_PTR(ret); 396 } 397 398 dma_obj->dma_addr = 0; 399 dma_obj->sgt = sgt; 400 401 return gem_obj; 402 } 403 404 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev, 405 struct drm_mode_create_dumb *args) 406 { 407 struct rcar_du_device *rcdu = to_rcar_du_device(dev); 408 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); 409 unsigned int align; 410 411 /* 412 * The R8A7779 DU requires a 16 pixels pitch alignment as documented, 413 * but the R8A7790 DU seems to require a 128 bytes pitch alignment. 414 */ 415 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B)) 416 align = 128; 417 else 418 align = 16 * args->bpp / 8; 419 420 args->pitch = roundup(min_pitch, align); 421 422 return drm_gem_dma_dumb_create_internal(file, dev, args); 423 } 424 425 static struct drm_framebuffer * 426 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, 427 const struct drm_mode_fb_cmd2 *mode_cmd) 428 { 429 struct rcar_du_device *rcdu = to_rcar_du_device(dev); 430 const struct rcar_du_format_info *format; 431 unsigned int chroma_pitch; 432 unsigned int max_pitch; 433 unsigned int align; 434 unsigned int i; 435 436 format = rcar_du_format_info(mode_cmd->pixel_format); 437 if (format == NULL) { 438 dev_dbg(dev->dev, "unsupported pixel format %p4cc\n", 439 &mode_cmd->pixel_format); 440 return ERR_PTR(-EINVAL); 441 } 442 443 if (rcdu->info->gen < 3) { 444 /* 445 * On Gen2 the DU limits the pitch to 4095 pixels and requires 446 * buffers to be aligned to a 16 pixels boundary (or 128 bytes 447 * on some platforms). 448 */ 449 unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1; 450 451 max_pitch = 4095 * bpp; 452 453 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B)) 454 align = 128; 455 else 456 align = 16 * bpp; 457 } else { 458 /* 459 * On Gen3 the memory interface is handled by the VSP that 460 * limits the pitch to 65535 bytes and has no alignment 461 * constraint. 462 */ 463 max_pitch = 65535; 464 align = 1; 465 } 466 467 if (mode_cmd->pitches[0] & (align - 1) || 468 mode_cmd->pitches[0] > max_pitch) { 469 dev_dbg(dev->dev, "invalid pitch value %u\n", 470 mode_cmd->pitches[0]); 471 return ERR_PTR(-EINVAL); 472 } 473 474 /* 475 * Calculate the chroma plane(s) pitch using the horizontal subsampling 476 * factor. For semi-planar formats, the U and V planes are combined, the 477 * pitch must thus be doubled. 478 */ 479 chroma_pitch = mode_cmd->pitches[0] / format->hsub; 480 if (format->planes == 2) 481 chroma_pitch *= 2; 482 483 for (i = 1; i < format->planes; ++i) { 484 if (mode_cmd->pitches[i] != chroma_pitch) { 485 dev_dbg(dev->dev, 486 "luma and chroma pitches are not compatible\n"); 487 return ERR_PTR(-EINVAL); 488 } 489 } 490 491 return drm_gem_fb_create(dev, file_priv, mode_cmd); 492 } 493 494 /* ----------------------------------------------------------------------------- 495 * Atomic Check and Update 496 */ 497 498 static int rcar_du_atomic_check(struct drm_device *dev, 499 struct drm_atomic_state *state) 500 { 501 struct rcar_du_device *rcdu = to_rcar_du_device(dev); 502 int ret; 503 504 ret = drm_atomic_helper_check(dev, state); 505 if (ret) 506 return ret; 507 508 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) 509 return 0; 510 511 return rcar_du_atomic_check_planes(dev, state); 512 } 513 514 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state) 515 { 516 struct drm_device *dev = old_state->dev; 517 struct rcar_du_device *rcdu = to_rcar_du_device(dev); 518 struct drm_crtc_state *crtc_state; 519 struct drm_crtc *crtc; 520 unsigned int i; 521 522 /* 523 * Store RGB routing to DPAD0 and DPAD1, the hardware will be configured 524 * when starting the CRTCs. 525 */ 526 rcdu->dpad1_source = -1; 527 528 for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) { 529 struct rcar_du_crtc_state *rcrtc_state = 530 to_rcar_crtc_state(crtc_state); 531 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); 532 533 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0)) 534 rcdu->dpad0_source = rcrtc->index; 535 536 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1)) 537 rcdu->dpad1_source = rcrtc->index; 538 } 539 540 /* Apply the atomic update. */ 541 drm_atomic_helper_commit_modeset_disables(dev, old_state); 542 drm_atomic_helper_commit_planes(dev, old_state, 543 DRM_PLANE_COMMIT_ACTIVE_ONLY); 544 drm_atomic_helper_commit_modeset_enables(dev, old_state); 545 546 drm_atomic_helper_commit_hw_done(old_state); 547 drm_atomic_helper_wait_for_flip_done(dev, old_state); 548 549 drm_atomic_helper_cleanup_planes(dev, old_state); 550 } 551 552 /* ----------------------------------------------------------------------------- 553 * Initialization 554 */ 555 556 static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = { 557 .atomic_commit_tail = rcar_du_atomic_commit_tail, 558 }; 559 560 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = { 561 .fb_create = rcar_du_fb_create, 562 .atomic_check = rcar_du_atomic_check, 563 .atomic_commit = drm_atomic_helper_commit, 564 }; 565 566 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu, 567 enum rcar_du_output output, 568 struct of_endpoint *ep) 569 { 570 struct device_node *entity; 571 int ret; 572 573 /* Locate the connected entity and initialize the encoder. */ 574 entity = of_graph_get_remote_port_parent(ep->local_node); 575 if (!entity) { 576 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n", 577 ep->local_node); 578 return -ENODEV; 579 } 580 581 if (!of_device_is_available(entity)) { 582 dev_dbg(rcdu->dev, 583 "connected entity %pOF is disabled, skipping\n", 584 entity); 585 of_node_put(entity); 586 return -ENODEV; 587 } 588 589 ret = rcar_du_encoder_init(rcdu, output, entity); 590 if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK) 591 dev_warn(rcdu->dev, 592 "failed to initialize encoder %pOF on output %s (%d), skipping\n", 593 entity, rcar_du_output_name(output), ret); 594 595 of_node_put(entity); 596 597 return ret; 598 } 599 600 static int rcar_du_encoders_init(struct rcar_du_device *rcdu) 601 { 602 struct device_node *np = rcdu->dev->of_node; 603 struct device_node *ep_node; 604 unsigned int num_encoders = 0; 605 606 /* 607 * Iterate over the endpoints and create one encoder for each output 608 * pipeline. 609 */ 610 for_each_endpoint_of_node(np, ep_node) { 611 enum rcar_du_output output; 612 struct of_endpoint ep; 613 unsigned int i; 614 int ret; 615 616 ret = of_graph_parse_endpoint(ep_node, &ep); 617 if (ret < 0) { 618 of_node_put(ep_node); 619 return ret; 620 } 621 622 /* Find the output route corresponding to the port number. */ 623 for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) { 624 if (rcdu->info->routes[i].possible_crtcs && 625 rcdu->info->routes[i].port == ep.port) { 626 output = i; 627 break; 628 } 629 } 630 631 if (i == RCAR_DU_OUTPUT_MAX) { 632 dev_warn(rcdu->dev, 633 "port %u references unexisting output, skipping\n", 634 ep.port); 635 continue; 636 } 637 638 /* Process the output pipeline. */ 639 ret = rcar_du_encoders_init_one(rcdu, output, &ep); 640 if (ret < 0) { 641 if (ret == -EPROBE_DEFER) { 642 of_node_put(ep_node); 643 return ret; 644 } 645 646 continue; 647 } 648 649 num_encoders++; 650 } 651 652 return num_encoders; 653 } 654 655 static int rcar_du_properties_init(struct rcar_du_device *rcdu) 656 { 657 /* 658 * The color key is expressed as an RGB888 triplet stored in a 32-bit 659 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0) 660 * or enable source color keying (1). 661 */ 662 rcdu->props.colorkey = 663 drm_property_create_range(&rcdu->ddev, 0, "colorkey", 664 0, 0x01ffffff); 665 if (rcdu->props.colorkey == NULL) 666 return -ENOMEM; 667 668 return 0; 669 } 670 671 static int rcar_du_vsps_init(struct rcar_du_device *rcdu) 672 { 673 const struct device_node *np = rcdu->dev->of_node; 674 const char *vsps_prop_name = "renesas,vsps"; 675 struct of_phandle_args args; 676 struct { 677 struct device_node *np; 678 unsigned int crtcs_mask; 679 } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, }; 680 unsigned int vsps_count = 0; 681 unsigned int cells; 682 unsigned int i; 683 int ret; 684 685 /* 686 * First parse the DT vsps property to populate the list of VSPs. Each 687 * entry contains a pointer to the VSP DT node and a bitmask of the 688 * connected DU CRTCs. 689 */ 690 ret = of_property_count_u32_elems(np, vsps_prop_name); 691 if (ret < 0) { 692 /* Backward compatibility with old DTBs. */ 693 vsps_prop_name = "vsps"; 694 ret = of_property_count_u32_elems(np, vsps_prop_name); 695 } 696 cells = ret / rcdu->num_crtcs - 1; 697 if (cells > 1) 698 return -EINVAL; 699 700 for (i = 0; i < rcdu->num_crtcs; ++i) { 701 unsigned int j; 702 703 ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name, 704 cells, i, &args); 705 if (ret < 0) 706 goto error; 707 708 /* 709 * Add the VSP to the list or update the corresponding existing 710 * entry if the VSP has already been added. 711 */ 712 for (j = 0; j < vsps_count; ++j) { 713 if (vsps[j].np == args.np) 714 break; 715 } 716 717 if (j < vsps_count) 718 of_node_put(args.np); 719 else 720 vsps[vsps_count++].np = args.np; 721 722 vsps[j].crtcs_mask |= BIT(i); 723 724 /* 725 * Store the VSP pointer and pipe index in the CRTC. If the 726 * second cell of the 'renesas,vsps' specifier isn't present, 727 * default to 0 to remain compatible with older DT bindings. 728 */ 729 rcdu->crtcs[i].vsp = &rcdu->vsps[j]; 730 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; 731 } 732 733 /* 734 * Then initialize all the VSPs from the node pointers and CRTCs bitmask 735 * computed previously. 736 */ 737 for (i = 0; i < vsps_count; ++i) { 738 struct rcar_du_vsp *vsp = &rcdu->vsps[i]; 739 740 vsp->index = i; 741 vsp->dev = rcdu; 742 743 ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask); 744 if (ret < 0) 745 goto error; 746 } 747 748 return 0; 749 750 error: 751 for (i = 0; i < ARRAY_SIZE(vsps); ++i) 752 of_node_put(vsps[i].np); 753 754 return ret; 755 } 756 757 static int rcar_du_cmm_init(struct rcar_du_device *rcdu) 758 { 759 const struct device_node *np = rcdu->dev->of_node; 760 unsigned int i; 761 int cells; 762 763 cells = of_property_count_u32_elems(np, "renesas,cmms"); 764 if (cells == -EINVAL) 765 return 0; 766 767 if (cells > rcdu->num_crtcs) { 768 dev_err(rcdu->dev, 769 "Invalid number of entries in 'renesas,cmms'\n"); 770 return -EINVAL; 771 } 772 773 for (i = 0; i < cells; ++i) { 774 struct platform_device *pdev; 775 struct device_link *link; 776 struct device_node *cmm; 777 int ret; 778 779 cmm = of_parse_phandle(np, "renesas,cmms", i); 780 if (!cmm) { 781 dev_err(rcdu->dev, 782 "Failed to parse 'renesas,cmms' property\n"); 783 return -EINVAL; 784 } 785 786 if (!of_device_is_available(cmm)) { 787 /* It's fine to have a phandle to a non-enabled CMM. */ 788 of_node_put(cmm); 789 continue; 790 } 791 792 pdev = of_find_device_by_node(cmm); 793 if (!pdev) { 794 dev_err(rcdu->dev, "No device found for CMM%u\n", i); 795 of_node_put(cmm); 796 return -EINVAL; 797 } 798 799 of_node_put(cmm); 800 801 /* 802 * -ENODEV is used to report that the CMM config option is 803 * disabled: return 0 and let the DU continue probing. 804 */ 805 ret = rcar_cmm_init(pdev); 806 if (ret) { 807 platform_device_put(pdev); 808 return ret == -ENODEV ? 0 : ret; 809 } 810 811 rcdu->cmms[i] = pdev; 812 813 /* 814 * Enforce suspend/resume ordering by making the CMM a provider 815 * of the DU: CMM is suspended after and resumed before the DU. 816 */ 817 link = device_link_add(rcdu->dev, &pdev->dev, DL_FLAG_STATELESS); 818 if (!link) { 819 dev_err(rcdu->dev, 820 "Failed to create device link to CMM%u\n", i); 821 return -EINVAL; 822 } 823 } 824 825 return 0; 826 } 827 828 static void rcar_du_modeset_cleanup(struct drm_device *dev, void *res) 829 { 830 struct rcar_du_device *rcdu = to_rcar_du_device(dev); 831 unsigned int i; 832 833 for (i = 0; i < ARRAY_SIZE(rcdu->cmms); ++i) 834 platform_device_put(rcdu->cmms[i]); 835 } 836 837 int rcar_du_modeset_init(struct rcar_du_device *rcdu) 838 { 839 static const unsigned int mmio_offsets[] = { 840 DU0_REG_OFFSET, DU2_REG_OFFSET 841 }; 842 843 struct drm_device *dev = &rcdu->ddev; 844 struct drm_encoder *encoder; 845 unsigned int dpad0_sources; 846 unsigned int num_encoders; 847 unsigned int num_groups; 848 unsigned int swindex; 849 unsigned int hwindex; 850 unsigned int i; 851 int ret; 852 853 ret = drmm_mode_config_init(dev); 854 if (ret) 855 return ret; 856 857 ret = drmm_add_action(&rcdu->ddev, rcar_du_modeset_cleanup, NULL); 858 if (ret) 859 return ret; 860 861 dev->mode_config.min_width = 0; 862 dev->mode_config.min_height = 0; 863 dev->mode_config.normalize_zpos = true; 864 dev->mode_config.funcs = &rcar_du_mode_config_funcs; 865 dev->mode_config.helper_private = &rcar_du_mode_config_helper; 866 867 if (rcdu->info->gen < 3) { 868 dev->mode_config.max_width = 4095; 869 dev->mode_config.max_height = 2047; 870 } else { 871 /* 872 * The Gen3 DU uses the VSP1 for memory access, and is limited 873 * to frame sizes of 8190x8190. 874 */ 875 dev->mode_config.max_width = 8190; 876 dev->mode_config.max_height = 8190; 877 } 878 879 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask); 880 881 ret = rcar_du_properties_init(rcdu); 882 if (ret < 0) 883 return ret; 884 885 /* 886 * Initialize vertical blanking interrupts handling. Start with vblank 887 * disabled for all CRTCs. 888 */ 889 ret = drm_vblank_init(dev, rcdu->num_crtcs); 890 if (ret < 0) 891 return ret; 892 893 /* Initialize the groups. */ 894 num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2); 895 896 for (i = 0; i < num_groups; ++i) { 897 struct rcar_du_group *rgrp = &rcdu->groups[i]; 898 899 mutex_init(&rgrp->lock); 900 901 rgrp->dev = rcdu; 902 rgrp->mmio_offset = mmio_offsets[i]; 903 rgrp->index = i; 904 /* Extract the channel mask for this group only. */ 905 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i)) 906 & GENMASK(1, 0); 907 rgrp->num_crtcs = hweight8(rgrp->channels_mask); 908 909 /* 910 * If we have more than one CRTCs in this group pre-associate 911 * the low-order planes with CRTC 0 and the high-order planes 912 * with CRTC 1 to minimize flicker occurring when the 913 * association is changed. 914 */ 915 rgrp->dptsr_planes = rgrp->num_crtcs > 1 916 ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0) 917 : 0; 918 919 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) { 920 ret = rcar_du_planes_init(rgrp); 921 if (ret < 0) 922 return ret; 923 } 924 } 925 926 /* Initialize the compositors. */ 927 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) { 928 ret = rcar_du_vsps_init(rcdu); 929 if (ret < 0) 930 return ret; 931 } 932 933 /* Initialize the Color Management Modules. */ 934 ret = rcar_du_cmm_init(rcdu); 935 if (ret) 936 return ret; 937 938 /* Create the CRTCs. */ 939 for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) { 940 struct rcar_du_group *rgrp; 941 942 /* Skip unpopulated DU channels. */ 943 if (!(rcdu->info->channels_mask & BIT(hwindex))) 944 continue; 945 946 rgrp = &rcdu->groups[hwindex / 2]; 947 948 ret = rcar_du_crtc_create(rgrp, swindex++, hwindex); 949 if (ret < 0) 950 return ret; 951 } 952 953 /* Initialize the encoders. */ 954 ret = rcar_du_encoders_init(rcdu); 955 if (ret < 0) 956 return ret; 957 958 if (ret == 0) { 959 dev_err(rcdu->dev, "error: no encoder could be initialized\n"); 960 return -EINVAL; 961 } 962 963 num_encoders = ret; 964 965 /* 966 * Set the possible CRTCs and possible clones. There's always at least 967 * one way for all encoders to clone each other, set all bits in the 968 * possible clones field. 969 */ 970 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 971 struct rcar_du_encoder *renc = to_rcar_encoder(encoder); 972 const struct rcar_du_output_routing *route = 973 &rcdu->info->routes[renc->output]; 974 975 encoder->possible_crtcs = route->possible_crtcs; 976 encoder->possible_clones = (1 << num_encoders) - 1; 977 } 978 979 /* Create the writeback connectors. */ 980 if (rcdu->info->gen >= 3) { 981 for (i = 0; i < rcdu->num_crtcs; ++i) { 982 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i]; 983 984 ret = rcar_du_writeback_init(rcdu, rcrtc); 985 if (ret < 0) 986 return ret; 987 } 988 } 989 990 /* 991 * Initialize the default DPAD0 source to the index of the first DU 992 * channel that can be connected to DPAD0. The exact value doesn't 993 * matter as it should be overwritten by mode setting for the RGB 994 * output, but it is nonetheless required to ensure a valid initial 995 * hardware configuration on Gen3 where DU0 can't always be connected to 996 * DPAD0. 997 */ 998 dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs; 999 rcdu->dpad0_source = ffs(dpad0_sources) - 1; 1000 1001 drm_mode_config_reset(dev); 1002 1003 drm_kms_helper_poll_init(dev); 1004 1005 return 0; 1006 } 1007