1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "radeon.h" 28 #include "radeon_asic.h" 29 #include "rv770d.h" 30 31 /** 32 * uvd_v2_2_fence_emit - emit an fence & trap command 33 * 34 * @rdev: radeon_device pointer 35 * @fence: fence to emit 36 * 37 * Write a fence and a trap command to the ring. 38 */ 39 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 40 struct radeon_fence *fence) 41 { 42 struct radeon_ring *ring = &rdev->ring[fence->ring]; 43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; 44 45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 46 radeon_ring_write(ring, fence->seq); 47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 48 radeon_ring_write(ring, lower_32_bits(addr)); 49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 52 radeon_ring_write(ring, 0); 53 54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 55 radeon_ring_write(ring, 0); 56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 57 radeon_ring_write(ring, 0); 58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 59 radeon_ring_write(ring, 2); 60 } 61 62 /** 63 * uvd_v2_2_resume - memory controller programming 64 * 65 * @rdev: radeon_device pointer 66 * 67 * Let the UVD memory controller know it's offsets 68 */ 69 int uvd_v2_2_resume(struct radeon_device *rdev) 70 { 71 uint64_t addr; 72 uint32_t chip_id, size; 73 int r; 74 75 r = radeon_uvd_resume(rdev); 76 if (r) 77 return r; 78 79 /* programm the VCPU memory controller bits 0-27 */ 80 addr = rdev->uvd.gpu_addr >> 3; 81 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3; 82 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); 83 WREG32(UVD_VCPU_CACHE_SIZE0, size); 84 85 addr += size; 86 size = RADEON_UVD_STACK_SIZE >> 3; 87 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); 88 WREG32(UVD_VCPU_CACHE_SIZE1, size); 89 90 addr += size; 91 size = RADEON_UVD_HEAP_SIZE >> 3; 92 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); 93 WREG32(UVD_VCPU_CACHE_SIZE2, size); 94 95 /* bits 28-31 */ 96 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; 97 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 98 99 /* bits 32-39 */ 100 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; 101 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 102 103 /* tell firmware which hardware it is running on */ 104 switch (rdev->family) { 105 default: 106 return -EINVAL; 107 case CHIP_RV710: 108 chip_id = 0x01000005; 109 break; 110 case CHIP_RV730: 111 chip_id = 0x01000006; 112 break; 113 case CHIP_RV740: 114 chip_id = 0x01000007; 115 break; 116 case CHIP_CYPRESS: 117 case CHIP_HEMLOCK: 118 chip_id = 0x01000008; 119 break; 120 case CHIP_JUNIPER: 121 chip_id = 0x01000009; 122 break; 123 case CHIP_REDWOOD: 124 chip_id = 0x0100000a; 125 break; 126 case CHIP_CEDAR: 127 chip_id = 0x0100000b; 128 break; 129 case CHIP_SUMO: 130 case CHIP_SUMO2: 131 chip_id = 0x0100000c; 132 break; 133 case CHIP_PALM: 134 chip_id = 0x0100000e; 135 break; 136 case CHIP_CAYMAN: 137 chip_id = 0x0100000f; 138 break; 139 case CHIP_BARTS: 140 chip_id = 0x01000010; 141 break; 142 case CHIP_TURKS: 143 chip_id = 0x01000011; 144 break; 145 case CHIP_CAICOS: 146 chip_id = 0x01000012; 147 break; 148 case CHIP_TAHITI: 149 chip_id = 0x01000014; 150 break; 151 case CHIP_VERDE: 152 chip_id = 0x01000015; 153 break; 154 case CHIP_PITCAIRN: 155 case CHIP_OLAND: 156 chip_id = 0x01000016; 157 break; 158 case CHIP_ARUBA: 159 chip_id = 0x01000017; 160 break; 161 } 162 WREG32(UVD_VCPU_CHIP_ID, chip_id); 163 164 return 0; 165 } 166