141a524abSAlex Deucher /* 241a524abSAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 341a524abSAlex Deucher * 441a524abSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 541a524abSAlex Deucher * copy of this software and associated documentation files (the "Software"), 641a524abSAlex Deucher * to deal in the Software without restriction, including without limitation 741a524abSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 841a524abSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 941a524abSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1041a524abSAlex Deucher * 1141a524abSAlex Deucher * The above copyright notice and this permission notice shall be included in 1241a524abSAlex Deucher * all copies or substantial portions of the Software. 1341a524abSAlex Deucher * 1441a524abSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1541a524abSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1641a524abSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1741a524abSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1841a524abSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1941a524abSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2041a524abSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2141a524abSAlex Deucher * 2241a524abSAlex Deucher */ 2341a524abSAlex Deucher 2441a524abSAlex Deucher #ifndef SMU7_FUSION_H 2541a524abSAlex Deucher #define SMU7_FUSION_H 2641a524abSAlex Deucher 2741a524abSAlex Deucher #include "smu7.h" 2841a524abSAlex Deucher 2941a524abSAlex Deucher #pragma pack(push, 1) 3041a524abSAlex Deucher 3141a524abSAlex Deucher #define SMU7_DTE_ITERATIONS 5 3241a524abSAlex Deucher #define SMU7_DTE_SOURCES 5 3341a524abSAlex Deucher #define SMU7_DTE_SINKS 3 3441a524abSAlex Deucher #define SMU7_NUM_CPU_TES 2 3541a524abSAlex Deucher #define SMU7_NUM_GPU_TES 1 3641a524abSAlex Deucher #define SMU7_NUM_NON_TES 2 3741a524abSAlex Deucher 3841a524abSAlex Deucher // All 'soft registers' should be uint32_t. 3941a524abSAlex Deucher struct SMU7_SoftRegisters 4041a524abSAlex Deucher { 4141a524abSAlex Deucher uint32_t RefClockFrequency; 4241a524abSAlex Deucher uint32_t PmTimerP; 4341a524abSAlex Deucher uint32_t FeatureEnables; 4441a524abSAlex Deucher uint32_t HandshakeDisables; 4541a524abSAlex Deucher 4641a524abSAlex Deucher uint8_t DisplayPhy1Config; 4741a524abSAlex Deucher uint8_t DisplayPhy2Config; 4841a524abSAlex Deucher uint8_t DisplayPhy3Config; 4941a524abSAlex Deucher uint8_t DisplayPhy4Config; 5041a524abSAlex Deucher 5141a524abSAlex Deucher uint8_t DisplayPhy5Config; 5241a524abSAlex Deucher uint8_t DisplayPhy6Config; 5341a524abSAlex Deucher uint8_t DisplayPhy7Config; 5441a524abSAlex Deucher uint8_t DisplayPhy8Config; 5541a524abSAlex Deucher 5641a524abSAlex Deucher uint32_t AverageGraphicsA; 5741a524abSAlex Deucher uint32_t AverageMemoryA; 5841a524abSAlex Deucher uint32_t AverageGioA; 5941a524abSAlex Deucher 6041a524abSAlex Deucher uint8_t SClkDpmEnabledLevels; 6141a524abSAlex Deucher uint8_t MClkDpmEnabledLevels; 6241a524abSAlex Deucher uint8_t LClkDpmEnabledLevels; 6341a524abSAlex Deucher uint8_t PCIeDpmEnabledLevels; 6441a524abSAlex Deucher 6541a524abSAlex Deucher uint8_t UVDDpmEnabledLevels; 6641a524abSAlex Deucher uint8_t SAMUDpmEnabledLevels; 6741a524abSAlex Deucher uint8_t ACPDpmEnabledLevels; 6841a524abSAlex Deucher uint8_t VCEDpmEnabledLevels; 6941a524abSAlex Deucher 7041a524abSAlex Deucher uint32_t DRAM_LOG_ADDR_H; 7141a524abSAlex Deucher uint32_t DRAM_LOG_ADDR_L; 7241a524abSAlex Deucher uint32_t DRAM_LOG_PHY_ADDR_H; 7341a524abSAlex Deucher uint32_t DRAM_LOG_PHY_ADDR_L; 7441a524abSAlex Deucher uint32_t DRAM_LOG_BUFF_SIZE; 7541a524abSAlex Deucher uint32_t UlvEnterC; 7641a524abSAlex Deucher uint32_t UlvTime; 7741a524abSAlex Deucher uint32_t Reserved[3]; 7841a524abSAlex Deucher 7941a524abSAlex Deucher }; 8041a524abSAlex Deucher 8141a524abSAlex Deucher typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 8241a524abSAlex Deucher 8341a524abSAlex Deucher struct SMU7_Fusion_GraphicsLevel 8441a524abSAlex Deucher { 8541a524abSAlex Deucher uint32_t MinVddNb; 8641a524abSAlex Deucher 8741a524abSAlex Deucher uint32_t SclkFrequency; 8841a524abSAlex Deucher 8941a524abSAlex Deucher uint8_t Vid; 9041a524abSAlex Deucher uint8_t VidOffset; 9141a524abSAlex Deucher uint16_t AT; 9241a524abSAlex Deucher 9341a524abSAlex Deucher uint8_t PowerThrottle; 9441a524abSAlex Deucher uint8_t GnbSlow; 9541a524abSAlex Deucher uint8_t ForceNbPs1; 9641a524abSAlex Deucher uint8_t SclkDid; 9741a524abSAlex Deucher 9841a524abSAlex Deucher uint8_t DisplayWatermark; 9941a524abSAlex Deucher uint8_t EnabledForActivity; 10041a524abSAlex Deucher uint8_t EnabledForThrottle; 10141a524abSAlex Deucher uint8_t UpH; 10241a524abSAlex Deucher 10341a524abSAlex Deucher uint8_t DownH; 10441a524abSAlex Deucher uint8_t VoltageDownH; 10541a524abSAlex Deucher uint8_t DeepSleepDivId; 10641a524abSAlex Deucher 10741a524abSAlex Deucher uint8_t ClkBypassCntl; 10841a524abSAlex Deucher 10941a524abSAlex Deucher uint32_t reserved; 11041a524abSAlex Deucher }; 11141a524abSAlex Deucher 11241a524abSAlex Deucher typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel; 11341a524abSAlex Deucher 11441a524abSAlex Deucher struct SMU7_Fusion_GIOLevel 11541a524abSAlex Deucher { 11641a524abSAlex Deucher uint8_t EnabledForActivity; 11741a524abSAlex Deucher uint8_t LclkDid; 11841a524abSAlex Deucher uint8_t Vid; 11941a524abSAlex Deucher uint8_t VoltageDownH; 12041a524abSAlex Deucher 12141a524abSAlex Deucher uint32_t MinVddNb; 12241a524abSAlex Deucher 12341a524abSAlex Deucher uint16_t ResidencyCounter; 12441a524abSAlex Deucher uint8_t UpH; 12541a524abSAlex Deucher uint8_t DownH; 12641a524abSAlex Deucher 12741a524abSAlex Deucher uint32_t LclkFrequency; 12841a524abSAlex Deucher 12941a524abSAlex Deucher uint8_t ActivityLevel; 13041a524abSAlex Deucher uint8_t EnabledForThrottle; 13141a524abSAlex Deucher 13241a524abSAlex Deucher uint8_t ClkBypassCntl; 13341a524abSAlex Deucher 13441a524abSAlex Deucher uint8_t padding; 13541a524abSAlex Deucher }; 13641a524abSAlex Deucher 13741a524abSAlex Deucher typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel; 13841a524abSAlex Deucher 13941a524abSAlex Deucher // UVD VCLK/DCLK state (level) definition. 14041a524abSAlex Deucher struct SMU7_Fusion_UvdLevel 14141a524abSAlex Deucher { 14241a524abSAlex Deucher uint32_t VclkFrequency; 14341a524abSAlex Deucher uint32_t DclkFrequency; 14441a524abSAlex Deucher uint16_t MinVddNb; 14541a524abSAlex Deucher uint8_t VclkDivider; 14641a524abSAlex Deucher uint8_t DclkDivider; 14741a524abSAlex Deucher 14841a524abSAlex Deucher uint8_t VClkBypassCntl; 14941a524abSAlex Deucher uint8_t DClkBypassCntl; 15041a524abSAlex Deucher 15141a524abSAlex Deucher uint8_t padding[2]; 15241a524abSAlex Deucher 15341a524abSAlex Deucher }; 15441a524abSAlex Deucher 15541a524abSAlex Deucher typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel; 15641a524abSAlex Deucher 15741a524abSAlex Deucher // Clocks for other external blocks (VCE, ACP, SAMU). 15841a524abSAlex Deucher struct SMU7_Fusion_ExtClkLevel 15941a524abSAlex Deucher { 16041a524abSAlex Deucher uint32_t Frequency; 16141a524abSAlex Deucher uint16_t MinVoltage; 16241a524abSAlex Deucher uint8_t Divider; 16341a524abSAlex Deucher uint8_t ClkBypassCntl; 16441a524abSAlex Deucher 16541a524abSAlex Deucher uint32_t Reserved; 16641a524abSAlex Deucher }; 16741a524abSAlex Deucher typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel; 16841a524abSAlex Deucher 16941a524abSAlex Deucher struct SMU7_Fusion_ACPILevel 17041a524abSAlex Deucher { 17141a524abSAlex Deucher uint32_t Flags; 17241a524abSAlex Deucher uint32_t MinVddNb; 17341a524abSAlex Deucher uint32_t SclkFrequency; 17441a524abSAlex Deucher uint8_t SclkDid; 17541a524abSAlex Deucher uint8_t GnbSlow; 17641a524abSAlex Deucher uint8_t ForceNbPs1; 17741a524abSAlex Deucher uint8_t DisplayWatermark; 17841a524abSAlex Deucher uint8_t DeepSleepDivId; 17941a524abSAlex Deucher uint8_t padding[3]; 18041a524abSAlex Deucher }; 18141a524abSAlex Deucher 18241a524abSAlex Deucher typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel; 18341a524abSAlex Deucher 18441a524abSAlex Deucher struct SMU7_Fusion_NbDpm 18541a524abSAlex Deucher { 18641a524abSAlex Deucher uint8_t DpmXNbPsHi; 18741a524abSAlex Deucher uint8_t DpmXNbPsLo; 18841a524abSAlex Deucher uint8_t Dpm0PgNbPsHi; 18941a524abSAlex Deucher uint8_t Dpm0PgNbPsLo; 19041a524abSAlex Deucher uint8_t EnablePsi1; 19141a524abSAlex Deucher uint8_t SkipDPM0; 19241a524abSAlex Deucher uint8_t SkipPG; 19341a524abSAlex Deucher uint8_t Hysteresis; 19441a524abSAlex Deucher uint8_t EnableDpmPstatePoll; 19541a524abSAlex Deucher uint8_t padding[3]; 19641a524abSAlex Deucher }; 19741a524abSAlex Deucher 19841a524abSAlex Deucher typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm; 19941a524abSAlex Deucher 20041a524abSAlex Deucher struct SMU7_Fusion_StateInfo 20141a524abSAlex Deucher { 20241a524abSAlex Deucher uint32_t SclkFrequency; 20341a524abSAlex Deucher uint32_t LclkFrequency; 20441a524abSAlex Deucher uint32_t VclkFrequency; 20541a524abSAlex Deucher uint32_t DclkFrequency; 20641a524abSAlex Deucher uint32_t SamclkFrequency; 20741a524abSAlex Deucher uint32_t AclkFrequency; 20841a524abSAlex Deucher uint32_t EclkFrequency; 20941a524abSAlex Deucher uint8_t DisplayWatermark; 21041a524abSAlex Deucher uint8_t McArbIndex; 21141a524abSAlex Deucher int8_t SclkIndex; 21241a524abSAlex Deucher int8_t MclkIndex; 21341a524abSAlex Deucher }; 21441a524abSAlex Deucher 21541a524abSAlex Deucher typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo; 21641a524abSAlex Deucher 21741a524abSAlex Deucher struct SMU7_Fusion_DpmTable 21841a524abSAlex Deucher { 21941a524abSAlex Deucher uint32_t SystemFlags; 22041a524abSAlex Deucher 22141a524abSAlex Deucher SMU7_PIDController GraphicsPIDController; 22241a524abSAlex Deucher SMU7_PIDController GioPIDController; 22341a524abSAlex Deucher 22441a524abSAlex Deucher uint8_t GraphicsDpmLevelCount; 22541a524abSAlex Deucher uint8_t GIOLevelCount; 22641a524abSAlex Deucher uint8_t UvdLevelCount; 22741a524abSAlex Deucher uint8_t VceLevelCount; 22841a524abSAlex Deucher 22941a524abSAlex Deucher uint8_t AcpLevelCount; 23041a524abSAlex Deucher uint8_t SamuLevelCount; 23141a524abSAlex Deucher uint16_t FpsHighT; 23241a524abSAlex Deucher 23341a524abSAlex Deucher SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; 23441a524abSAlex Deucher SMU7_Fusion_ACPILevel ACPILevel; 23541a524abSAlex Deucher SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; 23641a524abSAlex Deucher SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; 23741a524abSAlex Deucher SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; 23841a524abSAlex Deucher SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; 23941a524abSAlex Deucher 24041a524abSAlex Deucher uint8_t UvdBootLevel; 24141a524abSAlex Deucher uint8_t VceBootLevel; 24241a524abSAlex Deucher uint8_t AcpBootLevel; 24341a524abSAlex Deucher uint8_t SamuBootLevel; 24441a524abSAlex Deucher uint8_t UVDInterval; 24541a524abSAlex Deucher uint8_t VCEInterval; 24641a524abSAlex Deucher uint8_t ACPInterval; 24741a524abSAlex Deucher uint8_t SAMUInterval; 24841a524abSAlex Deucher 24941a524abSAlex Deucher uint8_t GraphicsBootLevel; 25041a524abSAlex Deucher uint8_t GraphicsInterval; 25141a524abSAlex Deucher uint8_t GraphicsThermThrottleEnable; 25241a524abSAlex Deucher uint8_t GraphicsVoltageChangeEnable; 25341a524abSAlex Deucher 25441a524abSAlex Deucher uint8_t GraphicsClkSlowEnable; 25541a524abSAlex Deucher uint8_t GraphicsClkSlowDivider; 25641a524abSAlex Deucher uint16_t FpsLowT; 25741a524abSAlex Deucher 25841a524abSAlex Deucher uint32_t DisplayCac; 25941a524abSAlex Deucher uint32_t LowSclkInterruptT; 26041a524abSAlex Deucher 26141a524abSAlex Deucher uint32_t DRAM_LOG_ADDR_H; 26241a524abSAlex Deucher uint32_t DRAM_LOG_ADDR_L; 26341a524abSAlex Deucher uint32_t DRAM_LOG_PHY_ADDR_H; 26441a524abSAlex Deucher uint32_t DRAM_LOG_PHY_ADDR_L; 26541a524abSAlex Deucher uint32_t DRAM_LOG_BUFF_SIZE; 26641a524abSAlex Deucher 26741a524abSAlex Deucher }; 26841a524abSAlex Deucher 26941a524abSAlex Deucher struct SMU7_Fusion_GIODpmTable 27041a524abSAlex Deucher { 27141a524abSAlex Deucher 27241a524abSAlex Deucher SMU7_Fusion_GIOLevel GIOLevel [SMU7_MAX_LEVELS_GIO]; 27341a524abSAlex Deucher 27441a524abSAlex Deucher SMU7_PIDController GioPIDController; 27541a524abSAlex Deucher 27641a524abSAlex Deucher uint32_t GIOLevelCount; 27741a524abSAlex Deucher 27841a524abSAlex Deucher uint8_t Enable; 27941a524abSAlex Deucher uint8_t GIOVoltageChangeEnable; 28041a524abSAlex Deucher uint8_t GIOBootLevel; 28141a524abSAlex Deucher uint8_t padding; 28241a524abSAlex Deucher uint8_t padding1[2]; 28341a524abSAlex Deucher uint8_t TargetState; 28441a524abSAlex Deucher uint8_t CurrenttState; 28541a524abSAlex Deucher uint8_t ThrottleOnHtc; 28641a524abSAlex Deucher uint8_t ThermThrottleStatus; 28741a524abSAlex Deucher uint8_t ThermThrottleTempSelect; 28841a524abSAlex Deucher uint8_t ThermThrottleEnable; 28941a524abSAlex Deucher uint16_t TemperatureLimitHigh; 29041a524abSAlex Deucher uint16_t TemperatureLimitLow; 29141a524abSAlex Deucher 29241a524abSAlex Deucher }; 29341a524abSAlex Deucher 29441a524abSAlex Deucher typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable; 29541a524abSAlex Deucher typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable; 29641a524abSAlex Deucher 29741a524abSAlex Deucher #pragma pack(pop) 29841a524abSAlex Deucher 29941a524abSAlex Deucher #endif 30041a524abSAlex Deucher 301