1cc8dbbb4SAlex Deucher /* 2cc8dbbb4SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3cc8dbbb4SAlex Deucher * 4cc8dbbb4SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5cc8dbbb4SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6cc8dbbb4SAlex Deucher * to deal in the Software without restriction, including without limitation 7cc8dbbb4SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8cc8dbbb4SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9cc8dbbb4SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10cc8dbbb4SAlex Deucher * 11cc8dbbb4SAlex Deucher * The above copyright notice and this permission notice shall be included in 12cc8dbbb4SAlex Deucher * all copies or substantial portions of the Software. 13cc8dbbb4SAlex Deucher * 14cc8dbbb4SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15cc8dbbb4SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16cc8dbbb4SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17cc8dbbb4SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18cc8dbbb4SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19cc8dbbb4SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20cc8dbbb4SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21cc8dbbb4SAlex Deucher * 22cc8dbbb4SAlex Deucher */ 23cc8dbbb4SAlex Deucher 24cc8dbbb4SAlex Deucher #ifndef SMU7_DISCRETE_H 25cc8dbbb4SAlex Deucher #define SMU7_DISCRETE_H 26cc8dbbb4SAlex Deucher 27cc8dbbb4SAlex Deucher #include "smu7.h" 28cc8dbbb4SAlex Deucher 29cc8dbbb4SAlex Deucher #pragma pack(push, 1) 30cc8dbbb4SAlex Deucher 31cc8dbbb4SAlex Deucher #define SMU7_DTE_ITERATIONS 5 32cc8dbbb4SAlex Deucher #define SMU7_DTE_SOURCES 3 33cc8dbbb4SAlex Deucher #define SMU7_DTE_SINKS 1 34cc8dbbb4SAlex Deucher #define SMU7_NUM_CPU_TES 0 35cc8dbbb4SAlex Deucher #define SMU7_NUM_GPU_TES 1 36cc8dbbb4SAlex Deucher #define SMU7_NUM_NON_TES 2 37cc8dbbb4SAlex Deucher 38cc8dbbb4SAlex Deucher struct SMU7_SoftRegisters 39cc8dbbb4SAlex Deucher { 40cc8dbbb4SAlex Deucher uint32_t RefClockFrequency; 41cc8dbbb4SAlex Deucher uint32_t PmTimerP; 42cc8dbbb4SAlex Deucher uint32_t FeatureEnables; 43cc8dbbb4SAlex Deucher uint32_t PreVBlankGap; 44cc8dbbb4SAlex Deucher uint32_t VBlankTimeout; 45cc8dbbb4SAlex Deucher uint32_t TrainTimeGap; 46cc8dbbb4SAlex Deucher 47cc8dbbb4SAlex Deucher uint32_t MvddSwitchTime; 48cc8dbbb4SAlex Deucher uint32_t LongestAcpiTrainTime; 49cc8dbbb4SAlex Deucher uint32_t AcpiDelay; 50cc8dbbb4SAlex Deucher uint32_t G5TrainTime; 51cc8dbbb4SAlex Deucher uint32_t DelayMpllPwron; 52cc8dbbb4SAlex Deucher uint32_t VoltageChangeTimeout; 53cc8dbbb4SAlex Deucher uint32_t HandshakeDisables; 54cc8dbbb4SAlex Deucher 55cc8dbbb4SAlex Deucher uint8_t DisplayPhy1Config; 56cc8dbbb4SAlex Deucher uint8_t DisplayPhy2Config; 57cc8dbbb4SAlex Deucher uint8_t DisplayPhy3Config; 58cc8dbbb4SAlex Deucher uint8_t DisplayPhy4Config; 59cc8dbbb4SAlex Deucher 60cc8dbbb4SAlex Deucher uint8_t DisplayPhy5Config; 61cc8dbbb4SAlex Deucher uint8_t DisplayPhy6Config; 62cc8dbbb4SAlex Deucher uint8_t DisplayPhy7Config; 63cc8dbbb4SAlex Deucher uint8_t DisplayPhy8Config; 64cc8dbbb4SAlex Deucher 65cc8dbbb4SAlex Deucher uint32_t AverageGraphicsA; 66cc8dbbb4SAlex Deucher uint32_t AverageMemoryA; 67cc8dbbb4SAlex Deucher uint32_t AverageGioA; 68cc8dbbb4SAlex Deucher 69cc8dbbb4SAlex Deucher uint8_t SClkDpmEnabledLevels; 70cc8dbbb4SAlex Deucher uint8_t MClkDpmEnabledLevels; 71cc8dbbb4SAlex Deucher uint8_t LClkDpmEnabledLevels; 72cc8dbbb4SAlex Deucher uint8_t PCIeDpmEnabledLevels; 73cc8dbbb4SAlex Deucher 74cc8dbbb4SAlex Deucher uint8_t UVDDpmEnabledLevels; 75cc8dbbb4SAlex Deucher uint8_t SAMUDpmEnabledLevels; 76cc8dbbb4SAlex Deucher uint8_t ACPDpmEnabledLevels; 77cc8dbbb4SAlex Deucher uint8_t VCEDpmEnabledLevels; 78cc8dbbb4SAlex Deucher 79cc8dbbb4SAlex Deucher uint32_t DRAM_LOG_ADDR_H; 80cc8dbbb4SAlex Deucher uint32_t DRAM_LOG_ADDR_L; 81cc8dbbb4SAlex Deucher uint32_t DRAM_LOG_PHY_ADDR_H; 82cc8dbbb4SAlex Deucher uint32_t DRAM_LOG_PHY_ADDR_L; 83cc8dbbb4SAlex Deucher uint32_t DRAM_LOG_BUFF_SIZE; 84cc8dbbb4SAlex Deucher uint32_t UlvEnterC; 85cc8dbbb4SAlex Deucher uint32_t UlvTime; 86cc8dbbb4SAlex Deucher uint32_t Reserved[3]; 87cc8dbbb4SAlex Deucher 88cc8dbbb4SAlex Deucher }; 89cc8dbbb4SAlex Deucher 90cc8dbbb4SAlex Deucher typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 91cc8dbbb4SAlex Deucher 92cc8dbbb4SAlex Deucher struct SMU7_Discrete_VoltageLevel 93cc8dbbb4SAlex Deucher { 94cc8dbbb4SAlex Deucher uint16_t Voltage; 95cc8dbbb4SAlex Deucher uint16_t StdVoltageHiSidd; 96cc8dbbb4SAlex Deucher uint16_t StdVoltageLoSidd; 97cc8dbbb4SAlex Deucher uint8_t Smio; 98cc8dbbb4SAlex Deucher uint8_t padding; 99cc8dbbb4SAlex Deucher }; 100cc8dbbb4SAlex Deucher 101cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; 102cc8dbbb4SAlex Deucher 103cc8dbbb4SAlex Deucher struct SMU7_Discrete_GraphicsLevel 104cc8dbbb4SAlex Deucher { 105cc8dbbb4SAlex Deucher uint32_t Flags; 106cc8dbbb4SAlex Deucher uint32_t MinVddc; 107cc8dbbb4SAlex Deucher uint32_t MinVddcPhases; 108cc8dbbb4SAlex Deucher 109cc8dbbb4SAlex Deucher uint32_t SclkFrequency; 110cc8dbbb4SAlex Deucher 111cc8dbbb4SAlex Deucher uint8_t padding1[2]; 112cc8dbbb4SAlex Deucher uint16_t ActivityLevel; 113cc8dbbb4SAlex Deucher 114cc8dbbb4SAlex Deucher uint32_t CgSpllFuncCntl3; 115cc8dbbb4SAlex Deucher uint32_t CgSpllFuncCntl4; 116cc8dbbb4SAlex Deucher uint32_t SpllSpreadSpectrum; 117cc8dbbb4SAlex Deucher uint32_t SpllSpreadSpectrum2; 118cc8dbbb4SAlex Deucher uint32_t CcPwrDynRm; 119cc8dbbb4SAlex Deucher uint32_t CcPwrDynRm1; 120cc8dbbb4SAlex Deucher uint8_t SclkDid; 121cc8dbbb4SAlex Deucher uint8_t DisplayWatermark; 122cc8dbbb4SAlex Deucher uint8_t EnabledForActivity; 123cc8dbbb4SAlex Deucher uint8_t EnabledForThrottle; 124cc8dbbb4SAlex Deucher uint8_t UpH; 125cc8dbbb4SAlex Deucher uint8_t DownH; 126cc8dbbb4SAlex Deucher uint8_t VoltageDownH; 127cc8dbbb4SAlex Deucher uint8_t PowerThrottle; 128cc8dbbb4SAlex Deucher uint8_t DeepSleepDivId; 129cc8dbbb4SAlex Deucher uint8_t padding[3]; 130cc8dbbb4SAlex Deucher }; 131cc8dbbb4SAlex Deucher 132cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; 133cc8dbbb4SAlex Deucher 134cc8dbbb4SAlex Deucher struct SMU7_Discrete_ACPILevel 135cc8dbbb4SAlex Deucher { 136cc8dbbb4SAlex Deucher uint32_t Flags; 137cc8dbbb4SAlex Deucher uint32_t MinVddc; 138cc8dbbb4SAlex Deucher uint32_t MinVddcPhases; 139cc8dbbb4SAlex Deucher uint32_t SclkFrequency; 140cc8dbbb4SAlex Deucher uint8_t SclkDid; 141cc8dbbb4SAlex Deucher uint8_t DisplayWatermark; 142cc8dbbb4SAlex Deucher uint8_t DeepSleepDivId; 143cc8dbbb4SAlex Deucher uint8_t padding; 144cc8dbbb4SAlex Deucher uint32_t CgSpllFuncCntl; 145cc8dbbb4SAlex Deucher uint32_t CgSpllFuncCntl2; 146cc8dbbb4SAlex Deucher uint32_t CgSpllFuncCntl3; 147cc8dbbb4SAlex Deucher uint32_t CgSpllFuncCntl4; 148cc8dbbb4SAlex Deucher uint32_t SpllSpreadSpectrum; 149cc8dbbb4SAlex Deucher uint32_t SpllSpreadSpectrum2; 150cc8dbbb4SAlex Deucher uint32_t CcPwrDynRm; 151cc8dbbb4SAlex Deucher uint32_t CcPwrDynRm1; 152cc8dbbb4SAlex Deucher }; 153cc8dbbb4SAlex Deucher 154cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; 155cc8dbbb4SAlex Deucher 156cc8dbbb4SAlex Deucher struct SMU7_Discrete_Ulv 157cc8dbbb4SAlex Deucher { 158cc8dbbb4SAlex Deucher uint32_t CcPwrDynRm; 159cc8dbbb4SAlex Deucher uint32_t CcPwrDynRm1; 160cc8dbbb4SAlex Deucher uint16_t VddcOffset; 161cc8dbbb4SAlex Deucher uint8_t VddcOffsetVid; 162cc8dbbb4SAlex Deucher uint8_t VddcPhase; 163cc8dbbb4SAlex Deucher uint32_t Reserved; 164cc8dbbb4SAlex Deucher }; 165cc8dbbb4SAlex Deucher 166cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; 167cc8dbbb4SAlex Deucher 168cc8dbbb4SAlex Deucher struct SMU7_Discrete_MemoryLevel 169cc8dbbb4SAlex Deucher { 170cc8dbbb4SAlex Deucher uint32_t MinVddc; 171cc8dbbb4SAlex Deucher uint32_t MinVddcPhases; 172cc8dbbb4SAlex Deucher uint32_t MinVddci; 173cc8dbbb4SAlex Deucher uint32_t MinMvdd; 174cc8dbbb4SAlex Deucher 175cc8dbbb4SAlex Deucher uint32_t MclkFrequency; 176cc8dbbb4SAlex Deucher 177cc8dbbb4SAlex Deucher uint8_t EdcReadEnable; 178cc8dbbb4SAlex Deucher uint8_t EdcWriteEnable; 179cc8dbbb4SAlex Deucher uint8_t RttEnable; 180cc8dbbb4SAlex Deucher uint8_t StutterEnable; 181cc8dbbb4SAlex Deucher 182cc8dbbb4SAlex Deucher uint8_t StrobeEnable; 183cc8dbbb4SAlex Deucher uint8_t StrobeRatio; 184cc8dbbb4SAlex Deucher uint8_t EnabledForThrottle; 185cc8dbbb4SAlex Deucher uint8_t EnabledForActivity; 186cc8dbbb4SAlex Deucher 187cc8dbbb4SAlex Deucher uint8_t UpH; 188cc8dbbb4SAlex Deucher uint8_t DownH; 189cc8dbbb4SAlex Deucher uint8_t VoltageDownH; 190cc8dbbb4SAlex Deucher uint8_t padding; 191cc8dbbb4SAlex Deucher 192cc8dbbb4SAlex Deucher uint16_t ActivityLevel; 193cc8dbbb4SAlex Deucher uint8_t DisplayWatermark; 194cc8dbbb4SAlex Deucher uint8_t padding1; 195cc8dbbb4SAlex Deucher 196cc8dbbb4SAlex Deucher uint32_t MpllFuncCntl; 197cc8dbbb4SAlex Deucher uint32_t MpllFuncCntl_1; 198cc8dbbb4SAlex Deucher uint32_t MpllFuncCntl_2; 199cc8dbbb4SAlex Deucher uint32_t MpllAdFuncCntl; 200cc8dbbb4SAlex Deucher uint32_t MpllDqFuncCntl; 201cc8dbbb4SAlex Deucher uint32_t MclkPwrmgtCntl; 202cc8dbbb4SAlex Deucher uint32_t DllCntl; 203cc8dbbb4SAlex Deucher uint32_t MpllSs1; 204cc8dbbb4SAlex Deucher uint32_t MpllSs2; 205cc8dbbb4SAlex Deucher }; 206cc8dbbb4SAlex Deucher 207cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; 208cc8dbbb4SAlex Deucher 209cc8dbbb4SAlex Deucher struct SMU7_Discrete_LinkLevel 210cc8dbbb4SAlex Deucher { 211cc8dbbb4SAlex Deucher uint8_t PcieGenSpeed; 212cc8dbbb4SAlex Deucher uint8_t PcieLaneCount; 213cc8dbbb4SAlex Deucher uint8_t EnabledForActivity; 214cc8dbbb4SAlex Deucher uint8_t Padding; 215cc8dbbb4SAlex Deucher uint32_t DownT; 216cc8dbbb4SAlex Deucher uint32_t UpT; 217cc8dbbb4SAlex Deucher uint32_t Reserved; 218cc8dbbb4SAlex Deucher }; 219cc8dbbb4SAlex Deucher 220cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; 221cc8dbbb4SAlex Deucher 222cc8dbbb4SAlex Deucher 223cc8dbbb4SAlex Deucher struct SMU7_Discrete_MCArbDramTimingTableEntry 224cc8dbbb4SAlex Deucher { 225cc8dbbb4SAlex Deucher uint32_t McArbDramTiming; 226cc8dbbb4SAlex Deucher uint32_t McArbDramTiming2; 227cc8dbbb4SAlex Deucher uint8_t McArbBurstTime; 228cc8dbbb4SAlex Deucher uint8_t padding[3]; 229cc8dbbb4SAlex Deucher }; 230cc8dbbb4SAlex Deucher 231cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; 232cc8dbbb4SAlex Deucher 233cc8dbbb4SAlex Deucher struct SMU7_Discrete_MCArbDramTimingTable 234cc8dbbb4SAlex Deucher { 235cc8dbbb4SAlex Deucher SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 236cc8dbbb4SAlex Deucher }; 237cc8dbbb4SAlex Deucher 238cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; 239cc8dbbb4SAlex Deucher 240cc8dbbb4SAlex Deucher struct SMU7_Discrete_UvdLevel 241cc8dbbb4SAlex Deucher { 242cc8dbbb4SAlex Deucher uint32_t VclkFrequency; 243cc8dbbb4SAlex Deucher uint32_t DclkFrequency; 244cc8dbbb4SAlex Deucher uint16_t MinVddc; 245cc8dbbb4SAlex Deucher uint8_t MinVddcPhases; 246cc8dbbb4SAlex Deucher uint8_t VclkDivider; 247cc8dbbb4SAlex Deucher uint8_t DclkDivider; 248cc8dbbb4SAlex Deucher uint8_t padding[3]; 249cc8dbbb4SAlex Deucher }; 250cc8dbbb4SAlex Deucher 251cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; 252cc8dbbb4SAlex Deucher 253cc8dbbb4SAlex Deucher struct SMU7_Discrete_ExtClkLevel 254cc8dbbb4SAlex Deucher { 255cc8dbbb4SAlex Deucher uint32_t Frequency; 256cc8dbbb4SAlex Deucher uint16_t MinVoltage; 257cc8dbbb4SAlex Deucher uint8_t MinPhases; 258cc8dbbb4SAlex Deucher uint8_t Divider; 259cc8dbbb4SAlex Deucher }; 260cc8dbbb4SAlex Deucher 261cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; 262cc8dbbb4SAlex Deucher 263cc8dbbb4SAlex Deucher struct SMU7_Discrete_StateInfo 264cc8dbbb4SAlex Deucher { 265cc8dbbb4SAlex Deucher uint32_t SclkFrequency; 266cc8dbbb4SAlex Deucher uint32_t MclkFrequency; 267cc8dbbb4SAlex Deucher uint32_t VclkFrequency; 268cc8dbbb4SAlex Deucher uint32_t DclkFrequency; 269cc8dbbb4SAlex Deucher uint32_t SamclkFrequency; 270cc8dbbb4SAlex Deucher uint32_t AclkFrequency; 271cc8dbbb4SAlex Deucher uint32_t EclkFrequency; 272cc8dbbb4SAlex Deucher uint16_t MvddVoltage; 273cc8dbbb4SAlex Deucher uint16_t padding16; 274cc8dbbb4SAlex Deucher uint8_t DisplayWatermark; 275cc8dbbb4SAlex Deucher uint8_t McArbIndex; 276cc8dbbb4SAlex Deucher uint8_t McRegIndex; 277cc8dbbb4SAlex Deucher uint8_t SeqIndex; 278cc8dbbb4SAlex Deucher uint8_t SclkDid; 279cc8dbbb4SAlex Deucher int8_t SclkIndex; 280cc8dbbb4SAlex Deucher int8_t MclkIndex; 281cc8dbbb4SAlex Deucher uint8_t PCIeGen; 282cc8dbbb4SAlex Deucher 283cc8dbbb4SAlex Deucher }; 284cc8dbbb4SAlex Deucher 285cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; 286cc8dbbb4SAlex Deucher 287cc8dbbb4SAlex Deucher 288cc8dbbb4SAlex Deucher struct SMU7_Discrete_DpmTable 289cc8dbbb4SAlex Deucher { 290cc8dbbb4SAlex Deucher SMU7_PIDController GraphicsPIDController; 291cc8dbbb4SAlex Deucher SMU7_PIDController MemoryPIDController; 292cc8dbbb4SAlex Deucher SMU7_PIDController LinkPIDController; 293cc8dbbb4SAlex Deucher 294cc8dbbb4SAlex Deucher uint32_t SystemFlags; 295cc8dbbb4SAlex Deucher 296cc8dbbb4SAlex Deucher 297cc8dbbb4SAlex Deucher uint32_t SmioMaskVddcVid; 298cc8dbbb4SAlex Deucher uint32_t SmioMaskVddcPhase; 299cc8dbbb4SAlex Deucher uint32_t SmioMaskVddciVid; 300cc8dbbb4SAlex Deucher uint32_t SmioMaskMvddVid; 301cc8dbbb4SAlex Deucher 302cc8dbbb4SAlex Deucher uint32_t VddcLevelCount; 303cc8dbbb4SAlex Deucher uint32_t VddciLevelCount; 304cc8dbbb4SAlex Deucher uint32_t MvddLevelCount; 305cc8dbbb4SAlex Deucher 306cc8dbbb4SAlex Deucher SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC]; 307cc8dbbb4SAlex Deucher // SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC]; 308cc8dbbb4SAlex Deucher SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI]; 309cc8dbbb4SAlex Deucher SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD]; 310cc8dbbb4SAlex Deucher 311cc8dbbb4SAlex Deucher uint8_t GraphicsDpmLevelCount; 312cc8dbbb4SAlex Deucher uint8_t MemoryDpmLevelCount; 313cc8dbbb4SAlex Deucher uint8_t LinkLevelCount; 314cc8dbbb4SAlex Deucher uint8_t UvdLevelCount; 315cc8dbbb4SAlex Deucher uint8_t VceLevelCount; 316cc8dbbb4SAlex Deucher uint8_t AcpLevelCount; 317cc8dbbb4SAlex Deucher uint8_t SamuLevelCount; 318cc8dbbb4SAlex Deucher uint8_t MasterDeepSleepControl; 319cc8dbbb4SAlex Deucher uint32_t Reserved[5]; 320cc8dbbb4SAlex Deucher // uint32_t SamuDefaultLevel; 321cc8dbbb4SAlex Deucher 322cc8dbbb4SAlex Deucher SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; 323cc8dbbb4SAlex Deucher SMU7_Discrete_MemoryLevel MemoryACPILevel; 324cc8dbbb4SAlex Deucher SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; 325cc8dbbb4SAlex Deucher SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; 326cc8dbbb4SAlex Deucher SMU7_Discrete_ACPILevel ACPILevel; 327cc8dbbb4SAlex Deucher SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; 328cc8dbbb4SAlex Deucher SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; 329cc8dbbb4SAlex Deucher SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; 330cc8dbbb4SAlex Deucher SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; 331cc8dbbb4SAlex Deucher SMU7_Discrete_Ulv Ulv; 332cc8dbbb4SAlex Deucher 333cc8dbbb4SAlex Deucher uint32_t SclkStepSize; 334cc8dbbb4SAlex Deucher uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; 335cc8dbbb4SAlex Deucher 336cc8dbbb4SAlex Deucher uint8_t UvdBootLevel; 337cc8dbbb4SAlex Deucher uint8_t VceBootLevel; 338cc8dbbb4SAlex Deucher uint8_t AcpBootLevel; 339cc8dbbb4SAlex Deucher uint8_t SamuBootLevel; 340cc8dbbb4SAlex Deucher 341cc8dbbb4SAlex Deucher uint8_t UVDInterval; 342cc8dbbb4SAlex Deucher uint8_t VCEInterval; 343cc8dbbb4SAlex Deucher uint8_t ACPInterval; 344cc8dbbb4SAlex Deucher uint8_t SAMUInterval; 345cc8dbbb4SAlex Deucher 346cc8dbbb4SAlex Deucher uint8_t GraphicsBootLevel; 347cc8dbbb4SAlex Deucher uint8_t GraphicsVoltageChangeEnable; 348cc8dbbb4SAlex Deucher uint8_t GraphicsThermThrottleEnable; 349cc8dbbb4SAlex Deucher uint8_t GraphicsInterval; 350cc8dbbb4SAlex Deucher 351cc8dbbb4SAlex Deucher uint8_t VoltageInterval; 352cc8dbbb4SAlex Deucher uint8_t ThermalInterval; 353cc8dbbb4SAlex Deucher uint16_t TemperatureLimitHigh; 354cc8dbbb4SAlex Deucher 355cc8dbbb4SAlex Deucher uint16_t TemperatureLimitLow; 356cc8dbbb4SAlex Deucher uint8_t MemoryBootLevel; 357cc8dbbb4SAlex Deucher uint8_t MemoryVoltageChangeEnable; 358cc8dbbb4SAlex Deucher 359cc8dbbb4SAlex Deucher uint8_t MemoryInterval; 360cc8dbbb4SAlex Deucher uint8_t MemoryThermThrottleEnable; 361cc8dbbb4SAlex Deucher uint16_t VddcVddciDelta; 362cc8dbbb4SAlex Deucher 363cc8dbbb4SAlex Deucher uint16_t VoltageResponseTime; 364cc8dbbb4SAlex Deucher uint16_t PhaseResponseTime; 365cc8dbbb4SAlex Deucher 366cc8dbbb4SAlex Deucher uint8_t PCIeBootLinkLevel; 367cc8dbbb4SAlex Deucher uint8_t PCIeGenInterval; 368cc8dbbb4SAlex Deucher uint8_t DTEInterval; 369cc8dbbb4SAlex Deucher uint8_t DTEMode; 370cc8dbbb4SAlex Deucher 371cc8dbbb4SAlex Deucher uint8_t SVI2Enable; 372cc8dbbb4SAlex Deucher uint8_t VRHotGpio; 373cc8dbbb4SAlex Deucher uint8_t AcDcGpio; 374cc8dbbb4SAlex Deucher uint8_t ThermGpio; 375cc8dbbb4SAlex Deucher 376cc8dbbb4SAlex Deucher uint16_t PPM_PkgPwrLimit; 377cc8dbbb4SAlex Deucher uint16_t PPM_TemperatureLimit; 378cc8dbbb4SAlex Deucher 379cc8dbbb4SAlex Deucher uint16_t DefaultTdp; 380cc8dbbb4SAlex Deucher uint16_t TargetTdp; 381cc8dbbb4SAlex Deucher 382cc8dbbb4SAlex Deucher uint16_t FpsHighT; 383cc8dbbb4SAlex Deucher uint16_t FpsLowT; 384cc8dbbb4SAlex Deucher 385cc8dbbb4SAlex Deucher uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 386cc8dbbb4SAlex Deucher uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 387cc8dbbb4SAlex Deucher 388cc8dbbb4SAlex Deucher uint8_t DTEAmbientTempBase; 389cc8dbbb4SAlex Deucher uint8_t DTETjOffset; 390cc8dbbb4SAlex Deucher uint8_t GpuTjMax; 391cc8dbbb4SAlex Deucher uint8_t GpuTjHyst; 392cc8dbbb4SAlex Deucher 393cc8dbbb4SAlex Deucher uint16_t BootVddc; 394cc8dbbb4SAlex Deucher uint16_t BootVddci; 395cc8dbbb4SAlex Deucher 396cc8dbbb4SAlex Deucher uint16_t BootMVdd; 397cc8dbbb4SAlex Deucher uint16_t padding; 398cc8dbbb4SAlex Deucher 399cc8dbbb4SAlex Deucher uint32_t BAPM_TEMP_GRADIENT; 400cc8dbbb4SAlex Deucher 401cc8dbbb4SAlex Deucher uint32_t LowSclkInterruptT; 402cc8dbbb4SAlex Deucher }; 403cc8dbbb4SAlex Deucher 404cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable; 405cc8dbbb4SAlex Deucher 406cc8dbbb4SAlex Deucher #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 407cc8dbbb4SAlex Deucher #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY 408cc8dbbb4SAlex Deucher 409cc8dbbb4SAlex Deucher struct SMU7_Discrete_MCRegisterAddress 410cc8dbbb4SAlex Deucher { 411cc8dbbb4SAlex Deucher uint16_t s0; 412cc8dbbb4SAlex Deucher uint16_t s1; 413cc8dbbb4SAlex Deucher }; 414cc8dbbb4SAlex Deucher 415cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; 416cc8dbbb4SAlex Deucher 417cc8dbbb4SAlex Deucher struct SMU7_Discrete_MCRegisterSet 418cc8dbbb4SAlex Deucher { 419cc8dbbb4SAlex Deucher uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 420cc8dbbb4SAlex Deucher }; 421cc8dbbb4SAlex Deucher 422cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; 423cc8dbbb4SAlex Deucher 424cc8dbbb4SAlex Deucher struct SMU7_Discrete_MCRegisters 425cc8dbbb4SAlex Deucher { 426cc8dbbb4SAlex Deucher uint8_t last; 427cc8dbbb4SAlex Deucher uint8_t reserved[3]; 428cc8dbbb4SAlex Deucher SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 429cc8dbbb4SAlex Deucher SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 430cc8dbbb4SAlex Deucher }; 431cc8dbbb4SAlex Deucher 432cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; 433cc8dbbb4SAlex Deucher 434e03cea36SAlex Deucher struct SMU7_Discrete_FanTable 435e03cea36SAlex Deucher { 436e03cea36SAlex Deucher uint16_t FdoMode; 437e03cea36SAlex Deucher int16_t TempMin; 438e03cea36SAlex Deucher int16_t TempMed; 439e03cea36SAlex Deucher int16_t TempMax; 440e03cea36SAlex Deucher int16_t Slope1; 441e03cea36SAlex Deucher int16_t Slope2; 442e03cea36SAlex Deucher int16_t FdoMin; 443e03cea36SAlex Deucher int16_t HystUp; 444e03cea36SAlex Deucher int16_t HystDown; 445e03cea36SAlex Deucher int16_t HystSlope; 446e03cea36SAlex Deucher int16_t TempRespLim; 447e03cea36SAlex Deucher int16_t TempCurr; 448e03cea36SAlex Deucher int16_t SlopeCurr; 449e03cea36SAlex Deucher int16_t PwmCurr; 450e03cea36SAlex Deucher uint32_t RefreshPeriod; 451e03cea36SAlex Deucher int16_t FdoMax; 452e03cea36SAlex Deucher uint8_t TempSrc; 453e03cea36SAlex Deucher int8_t Padding; 454e03cea36SAlex Deucher }; 455e03cea36SAlex Deucher 456e03cea36SAlex Deucher typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable; 457e03cea36SAlex Deucher 458e03cea36SAlex Deucher 459cc8dbbb4SAlex Deucher struct SMU7_Discrete_PmFuses { 460cc8dbbb4SAlex Deucher // dw0-dw1 461cc8dbbb4SAlex Deucher uint8_t BapmVddCVidHiSidd[8]; 462cc8dbbb4SAlex Deucher 463cc8dbbb4SAlex Deucher // dw2-dw3 464cc8dbbb4SAlex Deucher uint8_t BapmVddCVidLoSidd[8]; 465cc8dbbb4SAlex Deucher 466cc8dbbb4SAlex Deucher // dw4-dw5 467cc8dbbb4SAlex Deucher uint8_t VddCVid[8]; 468cc8dbbb4SAlex Deucher 469cc8dbbb4SAlex Deucher // dw6 470cc8dbbb4SAlex Deucher uint8_t SviLoadLineEn; 471cc8dbbb4SAlex Deucher uint8_t SviLoadLineVddC; 472cc8dbbb4SAlex Deucher uint8_t SviLoadLineTrimVddC; 473cc8dbbb4SAlex Deucher uint8_t SviLoadLineOffsetVddC; 474cc8dbbb4SAlex Deucher 475cc8dbbb4SAlex Deucher // dw7 476cc8dbbb4SAlex Deucher uint16_t TDC_VDDC_PkgLimit; 477cc8dbbb4SAlex Deucher uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 478cc8dbbb4SAlex Deucher uint8_t TDC_MAWt; 479cc8dbbb4SAlex Deucher 480cc8dbbb4SAlex Deucher // dw8 481cc8dbbb4SAlex Deucher uint8_t TdcWaterfallCtl; 482cc8dbbb4SAlex Deucher uint8_t LPMLTemperatureMin; 483cc8dbbb4SAlex Deucher uint8_t LPMLTemperatureMax; 484cc8dbbb4SAlex Deucher uint8_t Reserved; 485cc8dbbb4SAlex Deucher 486cc8dbbb4SAlex Deucher // dw9-dw10 487cc8dbbb4SAlex Deucher uint8_t BapmVddCVidHiSidd2[8]; 488cc8dbbb4SAlex Deucher 489cc8dbbb4SAlex Deucher // dw11-dw12 490e03cea36SAlex Deucher int16_t FuzzyFan_ErrorSetDelta; 491e03cea36SAlex Deucher int16_t FuzzyFan_ErrorRateSetDelta; 492e03cea36SAlex Deucher int16_t FuzzyFan_PwmSetDelta; 493e03cea36SAlex Deucher uint16_t CalcMeasPowerBlend; 494cc8dbbb4SAlex Deucher 495cc8dbbb4SAlex Deucher // dw13-dw16 496cc8dbbb4SAlex Deucher uint8_t GnbLPML[16]; 497cc8dbbb4SAlex Deucher 498cc8dbbb4SAlex Deucher // dw17 499cc8dbbb4SAlex Deucher uint8_t GnbLPMLMaxVid; 500cc8dbbb4SAlex Deucher uint8_t GnbLPMLMinVid; 501cc8dbbb4SAlex Deucher uint8_t Reserved1[2]; 502cc8dbbb4SAlex Deucher 503cc8dbbb4SAlex Deucher // dw18 504cc8dbbb4SAlex Deucher uint16_t BapmVddCBaseLeakageHiSidd; 505cc8dbbb4SAlex Deucher uint16_t BapmVddCBaseLeakageLoSidd; 506cc8dbbb4SAlex Deucher }; 507cc8dbbb4SAlex Deucher 508cc8dbbb4SAlex Deucher typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses; 509cc8dbbb4SAlex Deucher 510cc8dbbb4SAlex Deucher 511cc8dbbb4SAlex Deucher #pragma pack(pop) 512cc8dbbb4SAlex Deucher 513cc8dbbb4SAlex Deucher #endif 514cc8dbbb4SAlex Deucher 515