1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 28 29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 32 33 #define SI_MAX_SH_GPRS 256 34 #define SI_MAX_TEMP_GPRS 16 35 #define SI_MAX_SH_THREADS 256 36 #define SI_MAX_SH_STACK_ENTRIES 4096 37 #define SI_MAX_FRC_EOV_CNT 16384 38 #define SI_MAX_BACKENDS 8 39 #define SI_MAX_BACKENDS_MASK 0xFF 40 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 41 #define SI_MAX_SIMDS 12 42 #define SI_MAX_SIMDS_MASK 0x0FFF 43 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 44 #define SI_MAX_PIPES 8 45 #define SI_MAX_PIPES_MASK 0xFF 46 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 47 #define SI_MAX_LDS_NUM 0xFFFF 48 #define SI_MAX_TCC 16 49 #define SI_MAX_TCC_MASK 0xFFFF 50 51 /* SMC IND accessor regs */ 52 #define SMC_IND_INDEX_0 0x200 53 #define SMC_IND_DATA_0 0x204 54 55 #define SMC_IND_ACCESS_CNTL 0x228 56 # define AUTO_INCREMENT_IND_0 (1 << 0) 57 #define SMC_MESSAGE_0 0x22c 58 #define SMC_RESP_0 0x230 59 60 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 61 #define SMC_CG_IND_START 0xc0030000 62 #define SMC_CG_IND_END 0xc0040000 63 64 #define CG_CGTT_LOCAL_0 0x400 65 #define CG_CGTT_LOCAL_1 0x401 66 67 /* SMC IND registers */ 68 #define SMC_SYSCON_RESET_CNTL 0x80000000 69 # define RST_REG (1 << 0) 70 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 71 # define CK_DISABLE (1 << 0) 72 # define CKEN (1 << 24) 73 74 #define VGA_HDP_CONTROL 0x328 75 #define VGA_MEMORY_DISABLE (1 << 4) 76 77 #define DCCG_DISP_SLOW_SELECT_REG 0x4fc 78 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 79 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 80 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 81 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 82 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 83 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 84 85 #define CG_SPLL_FUNC_CNTL 0x600 86 #define SPLL_RESET (1 << 0) 87 #define SPLL_SLEEP (1 << 1) 88 #define SPLL_BYPASS_EN (1 << 3) 89 #define SPLL_REF_DIV(x) ((x) << 4) 90 #define SPLL_REF_DIV_MASK (0x3f << 4) 91 #define SPLL_PDIV_A(x) ((x) << 20) 92 #define SPLL_PDIV_A_MASK (0x7f << 20) 93 #define SPLL_PDIV_A_SHIFT 20 94 #define CG_SPLL_FUNC_CNTL_2 0x604 95 #define SCLK_MUX_SEL(x) ((x) << 0) 96 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 97 #define CG_SPLL_FUNC_CNTL_3 0x608 98 #define SPLL_FB_DIV(x) ((x) << 0) 99 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 100 #define SPLL_FB_DIV_SHIFT 0 101 #define SPLL_DITHEN (1 << 28) 102 #define CG_SPLL_FUNC_CNTL_4 0x60c 103 104 #define SPLL_CNTL_MODE 0x618 105 # define SPLL_REFCLK_SEL(x) ((x) << 8) 106 # define SPLL_REFCLK_SEL_MASK 0xFF00 107 108 #define CG_SPLL_SPREAD_SPECTRUM 0x620 109 #define SSEN (1 << 0) 110 #define CLK_S(x) ((x) << 4) 111 #define CLK_S_MASK (0xfff << 4) 112 #define CLK_S_SHIFT 4 113 #define CG_SPLL_SPREAD_SPECTRUM_2 0x624 114 #define CLK_V(x) ((x) << 0) 115 #define CLK_V_MASK (0x3ffffff << 0) 116 #define CLK_V_SHIFT 0 117 118 #define CG_SPLL_AUTOSCALE_CNTL 0x62c 119 # define AUTOSCALE_ON_SS_CLEAR (1 << 9) 120 121 /* discrete uvd clocks */ 122 #define CG_UPLL_FUNC_CNTL 0x634 123 # define UPLL_RESET_MASK 0x00000001 124 # define UPLL_SLEEP_MASK 0x00000002 125 # define UPLL_BYPASS_EN_MASK 0x00000004 126 # define UPLL_CTLREQ_MASK 0x00000008 127 # define UPLL_VCO_MODE_MASK 0x00000600 128 # define UPLL_REF_DIV_MASK 0x003F0000 129 # define UPLL_CTLACK_MASK 0x40000000 130 # define UPLL_CTLACK2_MASK 0x80000000 131 #define CG_UPLL_FUNC_CNTL_2 0x638 132 # define UPLL_PDIV_A(x) ((x) << 0) 133 # define UPLL_PDIV_A_MASK 0x0000007F 134 # define UPLL_PDIV_B(x) ((x) << 8) 135 # define UPLL_PDIV_B_MASK 0x00007F00 136 # define VCLK_SRC_SEL(x) ((x) << 20) 137 # define VCLK_SRC_SEL_MASK 0x01F00000 138 # define DCLK_SRC_SEL(x) ((x) << 25) 139 # define DCLK_SRC_SEL_MASK 0x3E000000 140 #define CG_UPLL_FUNC_CNTL_3 0x63C 141 # define UPLL_FB_DIV(x) ((x) << 0) 142 # define UPLL_FB_DIV_MASK 0x01FFFFFF 143 #define CG_UPLL_FUNC_CNTL_4 0x644 144 # define UPLL_SPARE_ISPARE9 0x00020000 145 #define CG_UPLL_FUNC_CNTL_5 0x648 146 # define RESET_ANTI_MUX_MASK 0x00000200 147 #define CG_UPLL_SPREAD_SPECTRUM 0x650 148 # define SSEN_MASK 0x00000001 149 150 #define MPLL_BYPASSCLK_SEL 0x65c 151 # define MPLL_CLKOUT_SEL(x) ((x) << 8) 152 # define MPLL_CLKOUT_SEL_MASK 0xFF00 153 154 #define CG_CLKPIN_CNTL 0x660 155 # define XTALIN_DIVIDE (1 << 1) 156 # define BCLK_AS_XCLK (1 << 2) 157 #define CG_CLKPIN_CNTL_2 0x664 158 # define FORCE_BIF_REFCLK_EN (1 << 3) 159 # define MUX_TCLK_TO_XCLK (1 << 8) 160 161 #define THM_CLK_CNTL 0x66c 162 # define CMON_CLK_SEL(x) ((x) << 0) 163 # define CMON_CLK_SEL_MASK 0xFF 164 # define TMON_CLK_SEL(x) ((x) << 8) 165 # define TMON_CLK_SEL_MASK 0xFF00 166 #define MISC_CLK_CNTL 0x670 167 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 168 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 169 # define ZCLK_SEL(x) ((x) << 8) 170 # define ZCLK_SEL_MASK 0xFF00 171 172 #define CG_THERMAL_CTRL 0x700 173 #define DPM_EVENT_SRC(x) ((x) << 0) 174 #define DPM_EVENT_SRC_MASK (7 << 0) 175 #define DIG_THERM_DPM(x) ((x) << 14) 176 #define DIG_THERM_DPM_MASK 0x003FC000 177 #define DIG_THERM_DPM_SHIFT 14 178 179 #define CG_THERMAL_INT 0x708 180 #define DIG_THERM_INTH(x) ((x) << 8) 181 #define DIG_THERM_INTH_MASK 0x0000FF00 182 #define DIG_THERM_INTH_SHIFT 8 183 #define DIG_THERM_INTL(x) ((x) << 16) 184 #define DIG_THERM_INTL_MASK 0x00FF0000 185 #define DIG_THERM_INTL_SHIFT 16 186 #define THERM_INT_MASK_HIGH (1 << 24) 187 #define THERM_INT_MASK_LOW (1 << 25) 188 189 #define CG_MULT_THERMAL_STATUS 0x714 190 #define ASIC_MAX_TEMP(x) ((x) << 0) 191 #define ASIC_MAX_TEMP_MASK 0x000001ff 192 #define ASIC_MAX_TEMP_SHIFT 0 193 #define CTF_TEMP(x) ((x) << 9) 194 #define CTF_TEMP_MASK 0x0003fe00 195 #define CTF_TEMP_SHIFT 9 196 197 #define GENERAL_PWRMGT 0x780 198 # define GLOBAL_PWRMGT_EN (1 << 0) 199 # define STATIC_PM_EN (1 << 1) 200 # define THERMAL_PROTECTION_DIS (1 << 2) 201 # define THERMAL_PROTECTION_TYPE (1 << 3) 202 # define SW_SMIO_INDEX(x) ((x) << 6) 203 # define SW_SMIO_INDEX_MASK (1 << 6) 204 # define SW_SMIO_INDEX_SHIFT 6 205 # define VOLT_PWRMGT_EN (1 << 10) 206 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 207 #define CG_TPC 0x784 208 #define SCLK_PWRMGT_CNTL 0x788 209 # define SCLK_PWRMGT_OFF (1 << 0) 210 # define SCLK_LOW_D1 (1 << 1) 211 # define FIR_RESET (1 << 4) 212 # define FIR_FORCE_TREND_SEL (1 << 5) 213 # define FIR_TREND_MODE (1 << 6) 214 # define DYN_GFX_CLK_OFF_EN (1 << 7) 215 # define GFX_CLK_FORCE_ON (1 << 8) 216 # define GFX_CLK_REQUEST_OFF (1 << 9) 217 # define GFX_CLK_FORCE_OFF (1 << 10) 218 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 219 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 220 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 221 # define DYN_LIGHT_SLEEP_EN (1 << 14) 222 223 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x798 224 # define CURRENT_STATE_INDEX_MASK (0xf << 4) 225 # define CURRENT_STATE_INDEX_SHIFT 4 226 227 #define CG_FTV 0x7bc 228 229 #define CG_FFCT_0 0x7c0 230 # define UTC_0(x) ((x) << 0) 231 # define UTC_0_MASK (0x3ff << 0) 232 # define DTC_0(x) ((x) << 10) 233 # define DTC_0_MASK (0x3ff << 10) 234 235 #define CG_BSP 0x7fc 236 # define BSP(x) ((x) << 0) 237 # define BSP_MASK (0xffff << 0) 238 # define BSU(x) ((x) << 16) 239 # define BSU_MASK (0xf << 16) 240 #define CG_AT 0x800 241 # define CG_R(x) ((x) << 0) 242 # define CG_R_MASK (0xffff << 0) 243 # define CG_L(x) ((x) << 16) 244 # define CG_L_MASK (0xffff << 16) 245 246 #define CG_GIT 0x804 247 # define CG_GICST(x) ((x) << 0) 248 # define CG_GICST_MASK (0xffff << 0) 249 # define CG_GIPOT(x) ((x) << 16) 250 # define CG_GIPOT_MASK (0xffff << 16) 251 252 #define CG_SSP 0x80c 253 # define SST(x) ((x) << 0) 254 # define SST_MASK (0xffff << 0) 255 # define SSTU(x) ((x) << 16) 256 # define SSTU_MASK (0xf << 16) 257 258 #define CG_DISPLAY_GAP_CNTL 0x828 259 # define DISP1_GAP(x) ((x) << 0) 260 # define DISP1_GAP_MASK (3 << 0) 261 # define DISP2_GAP(x) ((x) << 2) 262 # define DISP2_GAP_MASK (3 << 2) 263 # define VBI_TIMER_COUNT(x) ((x) << 4) 264 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 265 # define VBI_TIMER_UNIT(x) ((x) << 20) 266 # define VBI_TIMER_UNIT_MASK (7 << 20) 267 # define DISP1_GAP_MCHG(x) ((x) << 24) 268 # define DISP1_GAP_MCHG_MASK (3 << 24) 269 # define DISP2_GAP_MCHG(x) ((x) << 26) 270 # define DISP2_GAP_MCHG_MASK (3 << 26) 271 272 #define CG_ULV_CONTROL 0x878 273 #define CG_ULV_PARAMETER 0x87c 274 275 #define SMC_SCRATCH0 0x884 276 277 #define CG_CAC_CTRL 0x8b8 278 # define CAC_WINDOW(x) ((x) << 0) 279 # define CAC_WINDOW_MASK 0x00ffffff 280 281 #define DMIF_ADDR_CONFIG 0xBD4 282 283 #define DMIF_ADDR_CALC 0xC00 284 285 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 286 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 287 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 288 289 #define SRBM_STATUS 0xE50 290 #define GRBM_RQ_PENDING (1 << 5) 291 #define VMC_BUSY (1 << 8) 292 #define MCB_BUSY (1 << 9) 293 #define MCB_NON_DISPLAY_BUSY (1 << 10) 294 #define MCC_BUSY (1 << 11) 295 #define MCD_BUSY (1 << 12) 296 #define SEM_BUSY (1 << 14) 297 #define IH_BUSY (1 << 17) 298 299 #define SRBM_SOFT_RESET 0x0E60 300 #define SOFT_RESET_BIF (1 << 1) 301 #define SOFT_RESET_DC (1 << 5) 302 #define SOFT_RESET_DMA1 (1 << 6) 303 #define SOFT_RESET_GRBM (1 << 8) 304 #define SOFT_RESET_HDP (1 << 9) 305 #define SOFT_RESET_IH (1 << 10) 306 #define SOFT_RESET_MC (1 << 11) 307 #define SOFT_RESET_ROM (1 << 14) 308 #define SOFT_RESET_SEM (1 << 15) 309 #define SOFT_RESET_VMC (1 << 17) 310 #define SOFT_RESET_DMA (1 << 20) 311 #define SOFT_RESET_TST (1 << 21) 312 #define SOFT_RESET_REGBB (1 << 22) 313 #define SOFT_RESET_ORB (1 << 23) 314 315 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 316 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 317 318 #define SRBM_STATUS2 0x0EC4 319 #define DMA_BUSY (1 << 5) 320 #define DMA1_BUSY (1 << 6) 321 322 #define VM_L2_CNTL 0x1400 323 #define ENABLE_L2_CACHE (1 << 0) 324 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 325 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 326 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 327 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 328 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 329 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 330 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 331 #define VM_L2_CNTL2 0x1404 332 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 333 #define INVALIDATE_L2_CACHE (1 << 1) 334 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 335 #define INVALIDATE_PTE_AND_PDE_CACHES 0 336 #define INVALIDATE_ONLY_PTE_CACHES 1 337 #define INVALIDATE_ONLY_PDE_CACHES 2 338 #define VM_L2_CNTL3 0x1408 339 #define BANK_SELECT(x) ((x) << 0) 340 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 341 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 342 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 343 #define VM_L2_STATUS 0x140C 344 #define L2_BUSY (1 << 0) 345 #define VM_CONTEXT0_CNTL 0x1410 346 #define ENABLE_CONTEXT (1 << 0) 347 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 348 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 349 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 350 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 351 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 352 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 353 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 354 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 355 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 356 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 357 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 358 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 359 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 360 #define VM_CONTEXT1_CNTL 0x1414 361 #define VM_CONTEXT0_CNTL2 0x1430 362 #define VM_CONTEXT1_CNTL2 0x1434 363 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 364 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 365 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 366 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 367 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 368 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 369 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 370 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 371 372 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 373 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 374 #define PROTECTIONS_MASK (0xf << 0) 375 #define PROTECTIONS_SHIFT 0 376 /* bit 0: range 377 * bit 1: pde0 378 * bit 2: valid 379 * bit 3: read 380 * bit 4: write 381 */ 382 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 383 #define MEMORY_CLIENT_ID_SHIFT 12 384 #define MEMORY_CLIENT_RW_MASK (1 << 24) 385 #define MEMORY_CLIENT_RW_SHIFT 24 386 #define FAULT_VMID_MASK (0xf << 25) 387 #define FAULT_VMID_SHIFT 25 388 389 #define VM_INVALIDATE_REQUEST 0x1478 390 #define VM_INVALIDATE_RESPONSE 0x147c 391 392 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 393 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 394 395 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 396 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 397 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 398 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 399 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 400 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 401 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 402 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 403 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 404 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 405 406 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 407 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 408 409 #define VM_L2_CG 0x15c0 410 #define MC_CG_ENABLE (1 << 18) 411 #define MC_LS_ENABLE (1 << 19) 412 413 #define MC_SHARED_CHMAP 0x2004 414 #define NOOFCHAN_SHIFT 12 415 #define NOOFCHAN_MASK 0x0000f000 416 #define MC_SHARED_CHREMAP 0x2008 417 418 #define MC_VM_FB_LOCATION 0x2024 419 #define MC_VM_AGP_TOP 0x2028 420 #define MC_VM_AGP_BOT 0x202C 421 #define MC_VM_AGP_BASE 0x2030 422 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 423 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 424 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 425 426 #define MC_VM_MX_L1_TLB_CNTL 0x2064 427 #define ENABLE_L1_TLB (1 << 0) 428 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 429 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 430 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 431 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 432 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 433 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 434 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 435 436 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 437 438 #define MC_HUB_MISC_HUB_CG 0x20b8 439 #define MC_HUB_MISC_VM_CG 0x20bc 440 441 #define MC_HUB_MISC_SIP_CG 0x20c0 442 443 #define MC_XPB_CLK_GAT 0x2478 444 445 #define MC_CITF_MISC_RD_CG 0x2648 446 #define MC_CITF_MISC_WR_CG 0x264c 447 #define MC_CITF_MISC_VM_CG 0x2650 448 449 #define MC_ARB_RAMCFG 0x2760 450 #define NOOFBANK_SHIFT 0 451 #define NOOFBANK_MASK 0x00000003 452 #define NOOFRANK_SHIFT 2 453 #define NOOFRANK_MASK 0x00000004 454 #define NOOFROWS_SHIFT 3 455 #define NOOFROWS_MASK 0x00000038 456 #define NOOFCOLS_SHIFT 6 457 #define NOOFCOLS_MASK 0x000000C0 458 #define CHANSIZE_SHIFT 8 459 #define CHANSIZE_MASK 0x00000100 460 #define CHANSIZE_OVERRIDE (1 << 11) 461 #define NOOFGROUPS_SHIFT 12 462 #define NOOFGROUPS_MASK 0x00001000 463 464 #define MC_ARB_DRAM_TIMING 0x2774 465 #define MC_ARB_DRAM_TIMING2 0x2778 466 467 #define MC_ARB_BURST_TIME 0x2808 468 #define STATE0(x) ((x) << 0) 469 #define STATE0_MASK (0x1f << 0) 470 #define STATE0_SHIFT 0 471 #define STATE1(x) ((x) << 5) 472 #define STATE1_MASK (0x1f << 5) 473 #define STATE1_SHIFT 5 474 #define STATE2(x) ((x) << 10) 475 #define STATE2_MASK (0x1f << 10) 476 #define STATE2_SHIFT 10 477 #define STATE3(x) ((x) << 15) 478 #define STATE3_MASK (0x1f << 15) 479 #define STATE3_SHIFT 15 480 481 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 482 #define TRAIN_DONE_D0 (1 << 30) 483 #define TRAIN_DONE_D1 (1 << 31) 484 485 #define MC_SEQ_SUP_CNTL 0x28c8 486 #define RUN_MASK (1 << 0) 487 #define MC_SEQ_SUP_PGM 0x28cc 488 #define MC_PMG_AUTO_CMD 0x28d0 489 490 #define MC_IO_PAD_CNTL_D0 0x29d0 491 #define MEM_FALL_OUT_CMD (1 << 8) 492 493 #define MC_SEQ_RAS_TIMING 0x28a0 494 #define MC_SEQ_CAS_TIMING 0x28a4 495 #define MC_SEQ_MISC_TIMING 0x28a8 496 #define MC_SEQ_MISC_TIMING2 0x28ac 497 #define MC_SEQ_PMG_TIMING 0x28b0 498 #define MC_SEQ_RD_CTL_D0 0x28b4 499 #define MC_SEQ_RD_CTL_D1 0x28b8 500 #define MC_SEQ_WR_CTL_D0 0x28bc 501 #define MC_SEQ_WR_CTL_D1 0x28c0 502 503 #define MC_SEQ_MISC0 0x2a00 504 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 505 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 506 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 507 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 508 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 509 #define MC_SEQ_MISC0_REV_ID_VALUE 1 510 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 511 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 512 #define MC_SEQ_MISC0_GDDR5_VALUE 5 513 #define MC_SEQ_MISC1 0x2a04 514 #define MC_SEQ_RESERVE_M 0x2a08 515 #define MC_PMG_CMD_EMRS 0x2a0c 516 517 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 518 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 519 520 #define MC_SEQ_MISC5 0x2a54 521 #define MC_SEQ_MISC6 0x2a58 522 523 #define MC_SEQ_MISC7 0x2a64 524 525 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 526 #define MC_SEQ_CAS_TIMING_LP 0x2a70 527 #define MC_SEQ_MISC_TIMING_LP 0x2a74 528 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 529 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 530 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 531 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 532 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 533 534 #define MC_PMG_CMD_MRS 0x2aac 535 536 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 537 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 538 539 #define MC_PMG_CMD_MRS1 0x2b44 540 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 541 #define MC_SEQ_PMG_TIMING_LP 0x2b4c 542 543 #define MC_SEQ_WR_CTL_2 0x2b54 544 #define MC_SEQ_WR_CTL_2_LP 0x2b58 545 #define MC_PMG_CMD_MRS2 0x2b5c 546 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 547 548 #define MCLK_PWRMGT_CNTL 0x2ba0 549 # define DLL_SPEED(x) ((x) << 0) 550 # define DLL_SPEED_MASK (0x1f << 0) 551 # define DLL_READY (1 << 6) 552 # define MC_INT_CNTL (1 << 7) 553 # define MRDCK0_PDNB (1 << 8) 554 # define MRDCK1_PDNB (1 << 9) 555 # define MRDCK0_RESET (1 << 16) 556 # define MRDCK1_RESET (1 << 17) 557 # define DLL_READY_READ (1 << 24) 558 #define DLL_CNTL 0x2ba4 559 # define MRDCK0_BYPASS (1 << 24) 560 # define MRDCK1_BYPASS (1 << 25) 561 562 #define MPLL_FUNC_CNTL 0x2bb4 563 #define BWCTRL(x) ((x) << 20) 564 #define BWCTRL_MASK (0xff << 20) 565 #define MPLL_FUNC_CNTL_1 0x2bb8 566 #define VCO_MODE(x) ((x) << 0) 567 #define VCO_MODE_MASK (3 << 0) 568 #define CLKFRAC(x) ((x) << 4) 569 #define CLKFRAC_MASK (0xfff << 4) 570 #define CLKF(x) ((x) << 16) 571 #define CLKF_MASK (0xfff << 16) 572 #define MPLL_FUNC_CNTL_2 0x2bbc 573 #define MPLL_AD_FUNC_CNTL 0x2bc0 574 #define YCLK_POST_DIV(x) ((x) << 0) 575 #define YCLK_POST_DIV_MASK (7 << 0) 576 #define MPLL_DQ_FUNC_CNTL 0x2bc4 577 #define YCLK_SEL(x) ((x) << 4) 578 #define YCLK_SEL_MASK (1 << 4) 579 580 #define MPLL_SS1 0x2bcc 581 #define CLKV(x) ((x) << 0) 582 #define CLKV_MASK (0x3ffffff << 0) 583 #define MPLL_SS2 0x2bd0 584 #define CLKS(x) ((x) << 0) 585 #define CLKS_MASK (0xfff << 0) 586 587 #define HDP_HOST_PATH_CNTL 0x2C00 588 #define CLOCK_GATING_DIS (1 << 23) 589 #define HDP_NONSURFACE_BASE 0x2C04 590 #define HDP_NONSURFACE_INFO 0x2C08 591 #define HDP_NONSURFACE_SIZE 0x2C0C 592 593 #define HDP_ADDR_CONFIG 0x2F48 594 #define HDP_MISC_CNTL 0x2F4C 595 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 596 #define HDP_MEM_POWER_LS 0x2F50 597 #define HDP_LS_ENABLE (1 << 0) 598 599 #define ATC_MISC_CG 0x3350 600 601 #define IH_RB_CNTL 0x3e00 602 # define IH_RB_ENABLE (1 << 0) 603 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 604 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 605 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 606 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 607 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 608 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 609 #define IH_RB_BASE 0x3e04 610 #define IH_RB_RPTR 0x3e08 611 #define IH_RB_WPTR 0x3e0c 612 # define RB_OVERFLOW (1 << 0) 613 # define WPTR_OFFSET_MASK 0x3fffc 614 #define IH_RB_WPTR_ADDR_HI 0x3e10 615 #define IH_RB_WPTR_ADDR_LO 0x3e14 616 #define IH_CNTL 0x3e18 617 # define ENABLE_INTR (1 << 0) 618 # define IH_MC_SWAP(x) ((x) << 1) 619 # define IH_MC_SWAP_NONE 0 620 # define IH_MC_SWAP_16BIT 1 621 # define IH_MC_SWAP_32BIT 2 622 # define IH_MC_SWAP_64BIT 3 623 # define RPTR_REARM (1 << 4) 624 # define MC_WRREQ_CREDIT(x) ((x) << 15) 625 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 626 # define MC_VMID(x) ((x) << 25) 627 628 #define CONFIG_MEMSIZE 0x5428 629 630 #define INTERRUPT_CNTL 0x5468 631 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 632 # define IH_DUMMY_RD_EN (1 << 1) 633 # define IH_REQ_NONSNOOP_EN (1 << 3) 634 # define GEN_IH_INT_EN (1 << 8) 635 #define INTERRUPT_CNTL2 0x546c 636 637 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 638 639 #define BIF_FB_EN 0x5490 640 #define FB_READ_EN (1 << 0) 641 #define FB_WRITE_EN (1 << 1) 642 643 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 644 645 /* DCE6 ELD audio interface */ 646 #define AZ_F0_CODEC_ENDPOINT_INDEX 0x5E00 647 # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0) 648 # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8) 649 #define AZ_F0_CODEC_ENDPOINT_DATA 0x5E04 650 651 #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 652 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 653 #define SPEAKER_ALLOCATION_MASK (0x7f << 0) 654 #define SPEAKER_ALLOCATION_SHIFT 0 655 #define HDMI_CONNECTION (1 << 16) 656 #define DP_CONNECTION (1 << 17) 657 658 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */ 659 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */ 660 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */ 661 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */ 662 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */ 663 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */ 664 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */ 665 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */ 666 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */ 667 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */ 668 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */ 669 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */ 670 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */ 671 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */ 672 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 673 /* max channels minus one. 7 = 8 channels */ 674 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 675 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 676 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 677 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 678 * bit0 = 32 kHz 679 * bit1 = 44.1 kHz 680 * bit2 = 48 kHz 681 * bit3 = 88.2 kHz 682 * bit4 = 96 kHz 683 * bit5 = 176.4 kHz 684 * bit6 = 192 kHz 685 */ 686 #define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL 0x54 687 # define AUDIO_ENABLED (1 << 31) 688 689 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 690 #define PORT_CONNECTIVITY_MASK (3 << 30) 691 #define PORT_CONNECTIVITY_SHIFT 30 692 693 #define DC_LB_MEMORY_SPLIT 0x6b0c 694 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 695 696 #define PRIORITY_A_CNT 0x6b18 697 #define PRIORITY_MARK_MASK 0x7fff 698 #define PRIORITY_OFF (1 << 16) 699 #define PRIORITY_ALWAYS_ON (1 << 20) 700 #define PRIORITY_B_CNT 0x6b1c 701 702 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 703 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 704 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 705 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 706 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 707 708 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 709 #define VLINE_STATUS 0x6bb8 710 # define VLINE_OCCURRED (1 << 0) 711 # define VLINE_ACK (1 << 4) 712 # define VLINE_STAT (1 << 12) 713 # define VLINE_INTERRUPT (1 << 16) 714 # define VLINE_INTERRUPT_TYPE (1 << 17) 715 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 716 #define VBLANK_STATUS 0x6bbc 717 # define VBLANK_OCCURRED (1 << 0) 718 # define VBLANK_ACK (1 << 4) 719 # define VBLANK_STAT (1 << 12) 720 # define VBLANK_INTERRUPT (1 << 16) 721 # define VBLANK_INTERRUPT_TYPE (1 << 17) 722 723 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 724 #define INT_MASK 0x6b40 725 # define VBLANK_INT_MASK (1 << 0) 726 # define VLINE_INT_MASK (1 << 4) 727 728 #define DISP_INTERRUPT_STATUS 0x60f4 729 # define LB_D1_VLINE_INTERRUPT (1 << 2) 730 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 731 # define DC_HPD1_INTERRUPT (1 << 17) 732 # define DC_HPD1_RX_INTERRUPT (1 << 18) 733 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 734 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 735 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 736 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 737 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 738 # define LB_D2_VLINE_INTERRUPT (1 << 2) 739 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 740 # define DC_HPD2_INTERRUPT (1 << 17) 741 # define DC_HPD2_RX_INTERRUPT (1 << 18) 742 # define DISP_TIMER_INTERRUPT (1 << 24) 743 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 744 # define LB_D3_VLINE_INTERRUPT (1 << 2) 745 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 746 # define DC_HPD3_INTERRUPT (1 << 17) 747 # define DC_HPD3_RX_INTERRUPT (1 << 18) 748 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 749 # define LB_D4_VLINE_INTERRUPT (1 << 2) 750 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 751 # define DC_HPD4_INTERRUPT (1 << 17) 752 # define DC_HPD4_RX_INTERRUPT (1 << 18) 753 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 754 # define LB_D5_VLINE_INTERRUPT (1 << 2) 755 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 756 # define DC_HPD5_INTERRUPT (1 << 17) 757 # define DC_HPD5_RX_INTERRUPT (1 << 18) 758 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 759 # define LB_D6_VLINE_INTERRUPT (1 << 2) 760 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 761 # define DC_HPD6_INTERRUPT (1 << 17) 762 # define DC_HPD6_RX_INTERRUPT (1 << 18) 763 764 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 765 #define GRPH_INT_STATUS 0x6858 766 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 767 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 768 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 769 #define GRPH_INT_CONTROL 0x685c 770 # define GRPH_PFLIP_INT_MASK (1 << 0) 771 # define GRPH_PFLIP_INT_TYPE (1 << 8) 772 773 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 774 775 #define DC_HPD1_INT_STATUS 0x601c 776 #define DC_HPD2_INT_STATUS 0x6028 777 #define DC_HPD3_INT_STATUS 0x6034 778 #define DC_HPD4_INT_STATUS 0x6040 779 #define DC_HPD5_INT_STATUS 0x604c 780 #define DC_HPD6_INT_STATUS 0x6058 781 # define DC_HPDx_INT_STATUS (1 << 0) 782 # define DC_HPDx_SENSE (1 << 1) 783 # define DC_HPDx_RX_INT_STATUS (1 << 8) 784 785 #define DC_HPD1_INT_CONTROL 0x6020 786 #define DC_HPD2_INT_CONTROL 0x602c 787 #define DC_HPD3_INT_CONTROL 0x6038 788 #define DC_HPD4_INT_CONTROL 0x6044 789 #define DC_HPD5_INT_CONTROL 0x6050 790 #define DC_HPD6_INT_CONTROL 0x605c 791 # define DC_HPDx_INT_ACK (1 << 0) 792 # define DC_HPDx_INT_POLARITY (1 << 8) 793 # define DC_HPDx_INT_EN (1 << 16) 794 # define DC_HPDx_RX_INT_ACK (1 << 20) 795 # define DC_HPDx_RX_INT_EN (1 << 24) 796 797 #define DC_HPD1_CONTROL 0x6024 798 #define DC_HPD2_CONTROL 0x6030 799 #define DC_HPD3_CONTROL 0x603c 800 #define DC_HPD4_CONTROL 0x6048 801 #define DC_HPD5_CONTROL 0x6054 802 #define DC_HPD6_CONTROL 0x6060 803 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 804 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 805 # define DC_HPDx_EN (1 << 28) 806 807 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 808 # define STUTTER_ENABLE (1 << 0) 809 810 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 811 #define CRTC_STATUS_FRAME_COUNT 0x6e98 812 813 #define AFMT_AUDIO_SRC_CONTROL 0x713c 814 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) 815 /* AFMT_AUDIO_SRC_SELECT 816 * 0 = stream0 817 * 1 = stream1 818 * 2 = stream2 819 * 3 = stream3 820 * 4 = stream4 821 * 5 = stream5 822 */ 823 824 #define GRBM_CNTL 0x8000 825 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 826 827 #define GRBM_STATUS2 0x8008 828 #define RLC_RQ_PENDING (1 << 0) 829 #define RLC_BUSY (1 << 8) 830 #define TC_BUSY (1 << 9) 831 832 #define GRBM_STATUS 0x8010 833 #define CMDFIFO_AVAIL_MASK 0x0000000F 834 #define RING2_RQ_PENDING (1 << 4) 835 #define SRBM_RQ_PENDING (1 << 5) 836 #define RING1_RQ_PENDING (1 << 6) 837 #define CF_RQ_PENDING (1 << 7) 838 #define PF_RQ_PENDING (1 << 8) 839 #define GDS_DMA_RQ_PENDING (1 << 9) 840 #define GRBM_EE_BUSY (1 << 10) 841 #define DB_CLEAN (1 << 12) 842 #define CB_CLEAN (1 << 13) 843 #define TA_BUSY (1 << 14) 844 #define GDS_BUSY (1 << 15) 845 #define VGT_BUSY (1 << 17) 846 #define IA_BUSY_NO_DMA (1 << 18) 847 #define IA_BUSY (1 << 19) 848 #define SX_BUSY (1 << 20) 849 #define SPI_BUSY (1 << 22) 850 #define BCI_BUSY (1 << 23) 851 #define SC_BUSY (1 << 24) 852 #define PA_BUSY (1 << 25) 853 #define DB_BUSY (1 << 26) 854 #define CP_COHERENCY_BUSY (1 << 28) 855 #define CP_BUSY (1 << 29) 856 #define CB_BUSY (1 << 30) 857 #define GUI_ACTIVE (1 << 31) 858 #define GRBM_STATUS_SE0 0x8014 859 #define GRBM_STATUS_SE1 0x8018 860 #define SE_DB_CLEAN (1 << 1) 861 #define SE_CB_CLEAN (1 << 2) 862 #define SE_BCI_BUSY (1 << 22) 863 #define SE_VGT_BUSY (1 << 23) 864 #define SE_PA_BUSY (1 << 24) 865 #define SE_TA_BUSY (1 << 25) 866 #define SE_SX_BUSY (1 << 26) 867 #define SE_SPI_BUSY (1 << 27) 868 #define SE_SC_BUSY (1 << 29) 869 #define SE_DB_BUSY (1 << 30) 870 #define SE_CB_BUSY (1 << 31) 871 872 #define GRBM_SOFT_RESET 0x8020 873 #define SOFT_RESET_CP (1 << 0) 874 #define SOFT_RESET_CB (1 << 1) 875 #define SOFT_RESET_RLC (1 << 2) 876 #define SOFT_RESET_DB (1 << 3) 877 #define SOFT_RESET_GDS (1 << 4) 878 #define SOFT_RESET_PA (1 << 5) 879 #define SOFT_RESET_SC (1 << 6) 880 #define SOFT_RESET_BCI (1 << 7) 881 #define SOFT_RESET_SPI (1 << 8) 882 #define SOFT_RESET_SX (1 << 10) 883 #define SOFT_RESET_TC (1 << 11) 884 #define SOFT_RESET_TA (1 << 12) 885 #define SOFT_RESET_VGT (1 << 14) 886 #define SOFT_RESET_IA (1 << 15) 887 888 #define GRBM_GFX_INDEX 0x802C 889 #define INSTANCE_INDEX(x) ((x) << 0) 890 #define SH_INDEX(x) ((x) << 8) 891 #define SE_INDEX(x) ((x) << 16) 892 #define SH_BROADCAST_WRITES (1 << 29) 893 #define INSTANCE_BROADCAST_WRITES (1 << 30) 894 #define SE_BROADCAST_WRITES (1 << 31) 895 896 #define GRBM_INT_CNTL 0x8060 897 # define RDERR_INT_ENABLE (1 << 0) 898 # define GUI_IDLE_INT_ENABLE (1 << 19) 899 900 #define CP_STRMOUT_CNTL 0x84FC 901 #define SCRATCH_REG0 0x8500 902 #define SCRATCH_REG1 0x8504 903 #define SCRATCH_REG2 0x8508 904 #define SCRATCH_REG3 0x850C 905 #define SCRATCH_REG4 0x8510 906 #define SCRATCH_REG5 0x8514 907 #define SCRATCH_REG6 0x8518 908 #define SCRATCH_REG7 0x851C 909 910 #define SCRATCH_UMSK 0x8540 911 #define SCRATCH_ADDR 0x8544 912 913 #define CP_SEM_WAIT_TIMER 0x85BC 914 915 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 916 917 #define CP_ME_CNTL 0x86D8 918 #define CP_CE_HALT (1 << 24) 919 #define CP_PFP_HALT (1 << 26) 920 #define CP_ME_HALT (1 << 28) 921 922 #define CP_COHER_CNTL2 0x85E8 923 924 #define CP_RB2_RPTR 0x86f8 925 #define CP_RB1_RPTR 0x86fc 926 #define CP_RB0_RPTR 0x8700 927 #define CP_RB_WPTR_DELAY 0x8704 928 929 #define CP_QUEUE_THRESHOLDS 0x8760 930 #define ROQ_IB1_START(x) ((x) << 0) 931 #define ROQ_IB2_START(x) ((x) << 8) 932 #define CP_MEQ_THRESHOLDS 0x8764 933 #define MEQ1_START(x) ((x) << 0) 934 #define MEQ2_START(x) ((x) << 8) 935 936 #define CP_PERFMON_CNTL 0x87FC 937 938 #define VGT_VTX_VECT_EJECT_REG 0x88B0 939 940 #define VGT_CACHE_INVALIDATION 0x88C4 941 #define CACHE_INVALIDATION(x) ((x) << 0) 942 #define VC_ONLY 0 943 #define TC_ONLY 1 944 #define VC_AND_TC 2 945 #define AUTO_INVLD_EN(x) ((x) << 6) 946 #define NO_AUTO 0 947 #define ES_AUTO 1 948 #define GS_AUTO 2 949 #define ES_AND_GS_AUTO 3 950 #define VGT_ESGS_RING_SIZE 0x88C8 951 #define VGT_GSVS_RING_SIZE 0x88CC 952 953 #define VGT_GS_VERTEX_REUSE 0x88D4 954 955 #define VGT_PRIMITIVE_TYPE 0x8958 956 #define VGT_INDEX_TYPE 0x895C 957 958 #define VGT_NUM_INDICES 0x8970 959 #define VGT_NUM_INSTANCES 0x8974 960 961 #define VGT_TF_RING_SIZE 0x8988 962 963 #define VGT_HS_OFFCHIP_PARAM 0x89B0 964 965 #define VGT_TF_MEMORY_BASE 0x89B8 966 967 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 968 #define INACTIVE_CUS_MASK 0xFFFF0000 969 #define INACTIVE_CUS_SHIFT 16 970 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 971 972 #define PA_CL_ENHANCE 0x8A14 973 #define CLIP_VTX_REORDER_ENA (1 << 0) 974 #define NUM_CLIP_SEQ(x) ((x) << 1) 975 976 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 977 978 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 979 980 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 981 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 982 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 983 984 #define PA_SC_FIFO_SIZE 0x8BCC 985 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 986 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 987 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 988 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 989 990 #define PA_SC_ENHANCE 0x8BF0 991 992 #define SQ_CONFIG 0x8C00 993 994 #define SQC_CACHES 0x8C08 995 996 #define SQ_POWER_THROTTLE 0x8e58 997 #define MIN_POWER(x) ((x) << 0) 998 #define MIN_POWER_MASK (0x3fff << 0) 999 #define MIN_POWER_SHIFT 0 1000 #define MAX_POWER(x) ((x) << 16) 1001 #define MAX_POWER_MASK (0x3fff << 16) 1002 #define MAX_POWER_SHIFT 0 1003 #define SQ_POWER_THROTTLE2 0x8e5c 1004 #define MAX_POWER_DELTA(x) ((x) << 0) 1005 #define MAX_POWER_DELTA_MASK (0x3fff << 0) 1006 #define MAX_POWER_DELTA_SHIFT 0 1007 #define STI_SIZE(x) ((x) << 16) 1008 #define STI_SIZE_MASK (0x3ff << 16) 1009 #define STI_SIZE_SHIFT 16 1010 #define LTI_RATIO(x) ((x) << 27) 1011 #define LTI_RATIO_MASK (0xf << 27) 1012 #define LTI_RATIO_SHIFT 27 1013 1014 #define SX_DEBUG_1 0x9060 1015 1016 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 1017 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 1018 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 1019 #define SPI_PS_MAX_WAVE_ID 0x90EC 1020 1021 #define SPI_CONFIG_CNTL 0x9100 1022 1023 #define SPI_CONFIG_CNTL_1 0x913C 1024 #define VTX_DONE_DELAY(x) ((x) << 0) 1025 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1026 1027 #define CGTS_TCC_DISABLE 0x9148 1028 #define CGTS_USER_TCC_DISABLE 0x914C 1029 #define TCC_DISABLE_MASK 0xFFFF0000 1030 #define TCC_DISABLE_SHIFT 16 1031 #define CGTS_SM_CTRL_REG 0x9150 1032 #define OVERRIDE (1 << 21) 1033 #define LS_OVERRIDE (1 << 22) 1034 1035 #define SPI_LB_CU_MASK 0x9354 1036 1037 #define TA_CNTL_AUX 0x9508 1038 1039 #define CC_RB_BACKEND_DISABLE 0x98F4 1040 #define BACKEND_DISABLE(x) ((x) << 16) 1041 #define GB_ADDR_CONFIG 0x98F8 1042 #define NUM_PIPES(x) ((x) << 0) 1043 #define NUM_PIPES_MASK 0x00000007 1044 #define NUM_PIPES_SHIFT 0 1045 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1046 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1047 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 1048 #define NUM_SHADER_ENGINES(x) ((x) << 12) 1049 #define NUM_SHADER_ENGINES_MASK 0x00003000 1050 #define NUM_SHADER_ENGINES_SHIFT 12 1051 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1052 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1053 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1054 #define NUM_GPUS(x) ((x) << 20) 1055 #define NUM_GPUS_MASK 0x00700000 1056 #define NUM_GPUS_SHIFT 20 1057 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 1058 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 1059 #define MULTI_GPU_TILE_SIZE_SHIFT 24 1060 #define ROW_SIZE(x) ((x) << 28) 1061 #define ROW_SIZE_MASK 0x30000000 1062 #define ROW_SIZE_SHIFT 28 1063 1064 #define GB_TILE_MODE0 0x9910 1065 # define MICRO_TILE_MODE(x) ((x) << 0) 1066 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 1067 # define ADDR_SURF_THIN_MICRO_TILING 1 1068 # define ADDR_SURF_DEPTH_MICRO_TILING 2 1069 # define ARRAY_MODE(x) ((x) << 2) 1070 # define ARRAY_LINEAR_GENERAL 0 1071 # define ARRAY_LINEAR_ALIGNED 1 1072 # define ARRAY_1D_TILED_THIN1 2 1073 # define ARRAY_2D_TILED_THIN1 4 1074 # define PIPE_CONFIG(x) ((x) << 6) 1075 # define ADDR_SURF_P2 0 1076 # define ADDR_SURF_P4_8x16 4 1077 # define ADDR_SURF_P4_16x16 5 1078 # define ADDR_SURF_P4_16x32 6 1079 # define ADDR_SURF_P4_32x32 7 1080 # define ADDR_SURF_P8_16x16_8x16 8 1081 # define ADDR_SURF_P8_16x32_8x16 9 1082 # define ADDR_SURF_P8_32x32_8x16 10 1083 # define ADDR_SURF_P8_16x32_16x16 11 1084 # define ADDR_SURF_P8_32x32_16x16 12 1085 # define ADDR_SURF_P8_32x32_16x32 13 1086 # define ADDR_SURF_P8_32x64_32x32 14 1087 # define TILE_SPLIT(x) ((x) << 11) 1088 # define ADDR_SURF_TILE_SPLIT_64B 0 1089 # define ADDR_SURF_TILE_SPLIT_128B 1 1090 # define ADDR_SURF_TILE_SPLIT_256B 2 1091 # define ADDR_SURF_TILE_SPLIT_512B 3 1092 # define ADDR_SURF_TILE_SPLIT_1KB 4 1093 # define ADDR_SURF_TILE_SPLIT_2KB 5 1094 # define ADDR_SURF_TILE_SPLIT_4KB 6 1095 # define BANK_WIDTH(x) ((x) << 14) 1096 # define ADDR_SURF_BANK_WIDTH_1 0 1097 # define ADDR_SURF_BANK_WIDTH_2 1 1098 # define ADDR_SURF_BANK_WIDTH_4 2 1099 # define ADDR_SURF_BANK_WIDTH_8 3 1100 # define BANK_HEIGHT(x) ((x) << 16) 1101 # define ADDR_SURF_BANK_HEIGHT_1 0 1102 # define ADDR_SURF_BANK_HEIGHT_2 1 1103 # define ADDR_SURF_BANK_HEIGHT_4 2 1104 # define ADDR_SURF_BANK_HEIGHT_8 3 1105 # define MACRO_TILE_ASPECT(x) ((x) << 18) 1106 # define ADDR_SURF_MACRO_ASPECT_1 0 1107 # define ADDR_SURF_MACRO_ASPECT_2 1 1108 # define ADDR_SURF_MACRO_ASPECT_4 2 1109 # define ADDR_SURF_MACRO_ASPECT_8 3 1110 # define NUM_BANKS(x) ((x) << 20) 1111 # define ADDR_SURF_2_BANK 0 1112 # define ADDR_SURF_4_BANK 1 1113 # define ADDR_SURF_8_BANK 2 1114 # define ADDR_SURF_16_BANK 3 1115 1116 #define CB_PERFCOUNTER0_SELECT0 0x9a20 1117 #define CB_PERFCOUNTER0_SELECT1 0x9a24 1118 #define CB_PERFCOUNTER1_SELECT0 0x9a28 1119 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 1120 #define CB_PERFCOUNTER2_SELECT0 0x9a30 1121 #define CB_PERFCOUNTER2_SELECT1 0x9a34 1122 #define CB_PERFCOUNTER3_SELECT0 0x9a38 1123 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 1124 1125 #define CB_CGTT_SCLK_CTRL 0x9a60 1126 1127 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 1128 #define BACKEND_DISABLE_MASK 0x00FF0000 1129 #define BACKEND_DISABLE_SHIFT 16 1130 1131 #define TCP_CHAN_STEER_LO 0xac0c 1132 #define TCP_CHAN_STEER_HI 0xac10 1133 1134 #define CP_RB0_BASE 0xC100 1135 #define CP_RB0_CNTL 0xC104 1136 #define RB_BUFSZ(x) ((x) << 0) 1137 #define RB_BLKSZ(x) ((x) << 8) 1138 #define BUF_SWAP_32BIT (2 << 16) 1139 #define RB_NO_UPDATE (1 << 27) 1140 #define RB_RPTR_WR_ENA (1 << 31) 1141 1142 #define CP_RB0_RPTR_ADDR 0xC10C 1143 #define CP_RB0_RPTR_ADDR_HI 0xC110 1144 #define CP_RB0_WPTR 0xC114 1145 1146 #define CP_PFP_UCODE_ADDR 0xC150 1147 #define CP_PFP_UCODE_DATA 0xC154 1148 #define CP_ME_RAM_RADDR 0xC158 1149 #define CP_ME_RAM_WADDR 0xC15C 1150 #define CP_ME_RAM_DATA 0xC160 1151 1152 #define CP_CE_UCODE_ADDR 0xC168 1153 #define CP_CE_UCODE_DATA 0xC16C 1154 1155 #define CP_RB1_BASE 0xC180 1156 #define CP_RB1_CNTL 0xC184 1157 #define CP_RB1_RPTR_ADDR 0xC188 1158 #define CP_RB1_RPTR_ADDR_HI 0xC18C 1159 #define CP_RB1_WPTR 0xC190 1160 #define CP_RB2_BASE 0xC194 1161 #define CP_RB2_CNTL 0xC198 1162 #define CP_RB2_RPTR_ADDR 0xC19C 1163 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 1164 #define CP_RB2_WPTR 0xC1A4 1165 #define CP_INT_CNTL_RING0 0xC1A8 1166 #define CP_INT_CNTL_RING1 0xC1AC 1167 #define CP_INT_CNTL_RING2 0xC1B0 1168 # define CNTX_BUSY_INT_ENABLE (1 << 19) 1169 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1170 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 1171 # define TIME_STAMP_INT_ENABLE (1 << 26) 1172 # define CP_RINGID2_INT_ENABLE (1 << 29) 1173 # define CP_RINGID1_INT_ENABLE (1 << 30) 1174 # define CP_RINGID0_INT_ENABLE (1 << 31) 1175 #define CP_INT_STATUS_RING0 0xC1B4 1176 #define CP_INT_STATUS_RING1 0xC1B8 1177 #define CP_INT_STATUS_RING2 0xC1BC 1178 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 1179 # define TIME_STAMP_INT_STAT (1 << 26) 1180 # define CP_RINGID2_INT_STAT (1 << 29) 1181 # define CP_RINGID1_INT_STAT (1 << 30) 1182 # define CP_RINGID0_INT_STAT (1 << 31) 1183 1184 #define CP_MEM_SLP_CNTL 0xC1E4 1185 # define CP_MEM_LS_EN (1 << 0) 1186 1187 #define CP_DEBUG 0xC1FC 1188 1189 #define RLC_CNTL 0xC300 1190 # define RLC_ENABLE (1 << 0) 1191 #define RLC_RL_BASE 0xC304 1192 #define RLC_RL_SIZE 0xC308 1193 #define RLC_LB_CNTL 0xC30C 1194 # define LOAD_BALANCE_ENABLE (1 << 0) 1195 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 1196 #define RLC_LB_CNTR_MAX 0xC314 1197 #define RLC_LB_CNTR_INIT 0xC318 1198 1199 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 1200 1201 #define RLC_UCODE_ADDR 0xC32C 1202 #define RLC_UCODE_DATA 0xC330 1203 1204 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 1205 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 1206 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 1207 #define RLC_MC_CNTL 0xC344 1208 #define RLC_UCODE_CNTL 0xC348 1209 #define RLC_STAT 0xC34C 1210 # define RLC_BUSY_STATUS (1 << 0) 1211 # define GFX_POWER_STATUS (1 << 1) 1212 # define GFX_CLOCK_STATUS (1 << 2) 1213 # define GFX_LS_STATUS (1 << 3) 1214 1215 #define RLC_PG_CNTL 0xC35C 1216 # define GFX_PG_ENABLE (1 << 0) 1217 # define GFX_PG_SRC (1 << 1) 1218 1219 #define RLC_CGTT_MGCG_OVERRIDE 0xC400 1220 #define RLC_CGCG_CGLS_CTRL 0xC404 1221 # define CGCG_EN (1 << 0) 1222 # define CGLS_EN (1 << 1) 1223 1224 #define RLC_TTOP_D 0xC414 1225 # define RLC_PUD(x) ((x) << 0) 1226 # define RLC_PUD_MASK (0xff << 0) 1227 # define RLC_PDD(x) ((x) << 8) 1228 # define RLC_PDD_MASK (0xff << 8) 1229 # define RLC_TTPD(x) ((x) << 16) 1230 # define RLC_TTPD_MASK (0xff << 16) 1231 # define RLC_MSD(x) ((x) << 24) 1232 # define RLC_MSD_MASK (0xff << 24) 1233 1234 #define RLC_LB_INIT_CU_MASK 0xC41C 1235 1236 #define RLC_PG_AO_CU_MASK 0xC42C 1237 #define RLC_MAX_PG_CU 0xC430 1238 # define MAX_PU_CU(x) ((x) << 0) 1239 # define MAX_PU_CU_MASK (0xff << 0) 1240 #define RLC_AUTO_PG_CTRL 0xC434 1241 # define AUTO_PG_EN (1 << 0) 1242 # define GRBM_REG_SGIT(x) ((x) << 3) 1243 # define GRBM_REG_SGIT_MASK (0xffff << 3) 1244 # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19) 1245 # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19) 1246 1247 #define RLC_SERDES_WR_MASTER_MASK_0 0xC454 1248 #define RLC_SERDES_WR_MASTER_MASK_1 0xC458 1249 #define RLC_SERDES_WR_CTRL 0xC45C 1250 1251 #define RLC_SERDES_MASTER_BUSY_0 0xC464 1252 #define RLC_SERDES_MASTER_BUSY_1 0xC468 1253 1254 #define RLC_GCPM_GENERAL_3 0xC478 1255 1256 #define DB_RENDER_CONTROL 0x28000 1257 1258 #define DB_DEPTH_INFO 0x2803c 1259 1260 #define PA_SC_RASTER_CONFIG 0x28350 1261 # define RASTER_CONFIG_RB_MAP_0 0 1262 # define RASTER_CONFIG_RB_MAP_1 1 1263 # define RASTER_CONFIG_RB_MAP_2 2 1264 # define RASTER_CONFIG_RB_MAP_3 3 1265 1266 #define VGT_EVENT_INITIATOR 0x28a90 1267 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1268 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 1269 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 1270 # define CACHE_FLUSH_TS (4 << 0) 1271 # define CACHE_FLUSH (6 << 0) 1272 # define CS_PARTIAL_FLUSH (7 << 0) 1273 # define VGT_STREAMOUT_RESET (10 << 0) 1274 # define END_OF_PIPE_INCR_DE (11 << 0) 1275 # define END_OF_PIPE_IB_END (12 << 0) 1276 # define RST_PIX_CNT (13 << 0) 1277 # define VS_PARTIAL_FLUSH (15 << 0) 1278 # define PS_PARTIAL_FLUSH (16 << 0) 1279 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 1280 # define ZPASS_DONE (21 << 0) 1281 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 1282 # define PERFCOUNTER_START (23 << 0) 1283 # define PERFCOUNTER_STOP (24 << 0) 1284 # define PIPELINESTAT_START (25 << 0) 1285 # define PIPELINESTAT_STOP (26 << 0) 1286 # define PERFCOUNTER_SAMPLE (27 << 0) 1287 # define SAMPLE_PIPELINESTAT (30 << 0) 1288 # define SAMPLE_STREAMOUTSTATS (32 << 0) 1289 # define RESET_VTX_CNT (33 << 0) 1290 # define VGT_FLUSH (36 << 0) 1291 # define BOTTOM_OF_PIPE_TS (40 << 0) 1292 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 1293 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 1294 # define FLUSH_AND_INV_DB_META (44 << 0) 1295 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 1296 # define FLUSH_AND_INV_CB_META (46 << 0) 1297 # define CS_DONE (47 << 0) 1298 # define PS_DONE (48 << 0) 1299 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 1300 # define THREAD_TRACE_START (51 << 0) 1301 # define THREAD_TRACE_STOP (52 << 0) 1302 # define THREAD_TRACE_FLUSH (54 << 0) 1303 # define THREAD_TRACE_FINISH (55 << 0) 1304 1305 /* PIF PHY0 registers idx/data 0x8/0xc */ 1306 #define PB0_PIF_CNTL 0x10 1307 # define LS2_EXIT_TIME(x) ((x) << 17) 1308 # define LS2_EXIT_TIME_MASK (0x7 << 17) 1309 # define LS2_EXIT_TIME_SHIFT 17 1310 #define PB0_PIF_PAIRING 0x11 1311 # define MULTI_PIF (1 << 25) 1312 #define PB0_PIF_PWRDOWN_0 0x12 1313 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 1314 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 1315 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 1316 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 1317 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 1318 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 1319 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 1320 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 1321 # define PLL_RAMP_UP_TIME_0_SHIFT 24 1322 #define PB0_PIF_PWRDOWN_1 0x13 1323 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 1324 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 1325 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 1326 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 1327 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 1328 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 1329 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 1330 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 1331 # define PLL_RAMP_UP_TIME_1_SHIFT 24 1332 1333 #define PB0_PIF_PWRDOWN_2 0x17 1334 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) 1335 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7) 1336 # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7 1337 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) 1338 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10) 1339 # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10 1340 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) 1341 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24) 1342 # define PLL_RAMP_UP_TIME_2_SHIFT 24 1343 #define PB0_PIF_PWRDOWN_3 0x18 1344 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) 1345 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7) 1346 # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7 1347 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) 1348 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10) 1349 # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10 1350 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) 1351 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24) 1352 # define PLL_RAMP_UP_TIME_3_SHIFT 24 1353 /* PIF PHY1 registers idx/data 0x10/0x14 */ 1354 #define PB1_PIF_CNTL 0x10 1355 #define PB1_PIF_PAIRING 0x11 1356 #define PB1_PIF_PWRDOWN_0 0x12 1357 #define PB1_PIF_PWRDOWN_1 0x13 1358 1359 #define PB1_PIF_PWRDOWN_2 0x17 1360 #define PB1_PIF_PWRDOWN_3 0x18 1361 /* PCIE registers idx/data 0x30/0x34 */ 1362 #define PCIE_CNTL2 0x1c /* PCIE */ 1363 # define SLV_MEM_LS_EN (1 << 16) 1364 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 1365 # define MST_MEM_LS_EN (1 << 18) 1366 # define REPLAY_MEM_LS_EN (1 << 19) 1367 #define PCIE_LC_STATUS1 0x28 /* PCIE */ 1368 # define LC_REVERSE_RCVR (1 << 0) 1369 # define LC_REVERSE_XMIT (1 << 1) 1370 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 1371 # define LC_OPERATING_LINK_WIDTH_SHIFT 2 1372 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 1373 # define LC_DETECTED_LINK_WIDTH_SHIFT 5 1374 1375 #define PCIE_P_CNTL 0x40 /* PCIE */ 1376 # define P_IGNORE_EDB_ERR (1 << 6) 1377 1378 /* PCIE PORT registers idx/data 0x38/0x3c */ 1379 #define PCIE_LC_CNTL 0xa0 1380 # define LC_L0S_INACTIVITY(x) ((x) << 8) 1381 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 1382 # define LC_L0S_INACTIVITY_SHIFT 8 1383 # define LC_L1_INACTIVITY(x) ((x) << 12) 1384 # define LC_L1_INACTIVITY_MASK (0xf << 12) 1385 # define LC_L1_INACTIVITY_SHIFT 12 1386 # define LC_PMI_TO_L1_DIS (1 << 16) 1387 # define LC_ASPM_TO_L1_DIS (1 << 24) 1388 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1389 # define LC_LINK_WIDTH_SHIFT 0 1390 # define LC_LINK_WIDTH_MASK 0x7 1391 # define LC_LINK_WIDTH_X0 0 1392 # define LC_LINK_WIDTH_X1 1 1393 # define LC_LINK_WIDTH_X2 2 1394 # define LC_LINK_WIDTH_X4 3 1395 # define LC_LINK_WIDTH_X8 4 1396 # define LC_LINK_WIDTH_X16 6 1397 # define LC_LINK_WIDTH_RD_SHIFT 4 1398 # define LC_LINK_WIDTH_RD_MASK 0x70 1399 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1400 # define LC_RECONFIG_NOW (1 << 8) 1401 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1402 # define LC_RENEGOTIATE_EN (1 << 10) 1403 # define LC_SHORT_RECONFIG_EN (1 << 11) 1404 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1405 # define LC_UPCONFIGURE_DIS (1 << 13) 1406 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 1407 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 1408 # define LC_DYN_LANES_PWR_STATE_SHIFT 21 1409 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */ 1410 # define LC_XMIT_N_FTS(x) ((x) << 0) 1411 # define LC_XMIT_N_FTS_MASK (0xff << 0) 1412 # define LC_XMIT_N_FTS_SHIFT 0 1413 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 1414 # define LC_N_FTS_MASK (0xff << 24) 1415 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1416 # define LC_GEN2_EN_STRAP (1 << 0) 1417 # define LC_GEN3_EN_STRAP (1 << 1) 1418 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 1419 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 1420 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 1421 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 1422 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 1423 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 1424 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 1425 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 1426 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 1427 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 1428 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 1429 # define LC_CURRENT_DATA_RATE_SHIFT 13 1430 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 1431 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 1432 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 1433 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 1434 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 1435 1436 #define PCIE_LC_CNTL2 0xb1 1437 # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 1438 # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 1439 1440 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */ 1441 # define LC_GO_TO_RECOVERY (1 << 30) 1442 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */ 1443 # define LC_REDO_EQ (1 << 5) 1444 # define LC_SET_QUIESCE (1 << 13) 1445 1446 /* 1447 * UVD 1448 */ 1449 #define UVD_UDEC_ADDR_CONFIG 0xEF4C 1450 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 1451 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 1452 #define UVD_RBC_RB_RPTR 0xF690 1453 #define UVD_RBC_RB_WPTR 0xF694 1454 1455 #define UVD_CGC_CTRL 0xF4B0 1456 # define DCM (1 << 0) 1457 # define CG_DT(x) ((x) << 2) 1458 # define CG_DT_MASK (0xf << 2) 1459 # define CLK_OD(x) ((x) << 6) 1460 # define CLK_OD_MASK (0x1f << 6) 1461 1462 /* UVD CTX indirect */ 1463 #define UVD_CGC_MEM_CTRL 0xC0 1464 #define UVD_CGC_CTRL2 0xC1 1465 # define DYN_OR_EN (1 << 0) 1466 # define DYN_RR_EN (1 << 1) 1467 # define G_DIV_ID(x) ((x) << 2) 1468 # define G_DIV_ID_MASK (0x7 << 2) 1469 1470 /* 1471 * PM4 1472 */ 1473 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1474 (((reg) >> 2) & 0xFFFF) | \ 1475 ((n) & 0x3FFF) << 16) 1476 #define CP_PACKET2 0x80000000 1477 #define PACKET2_PAD_SHIFT 0 1478 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1479 1480 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1481 1482 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1483 (((op) & 0xFF) << 8) | \ 1484 ((n) & 0x3FFF) << 16) 1485 1486 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1487 1488 /* Packet 3 types */ 1489 #define PACKET3_NOP 0x10 1490 #define PACKET3_SET_BASE 0x11 1491 #define PACKET3_BASE_INDEX(x) ((x) << 0) 1492 #define GDS_PARTITION_BASE 2 1493 #define CE_PARTITION_BASE 3 1494 #define PACKET3_CLEAR_STATE 0x12 1495 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1496 #define PACKET3_DISPATCH_DIRECT 0x15 1497 #define PACKET3_DISPATCH_INDIRECT 0x16 1498 #define PACKET3_ALLOC_GDS 0x1B 1499 #define PACKET3_WRITE_GDS_RAM 0x1C 1500 #define PACKET3_ATOMIC_GDS 0x1D 1501 #define PACKET3_ATOMIC 0x1E 1502 #define PACKET3_OCCLUSION_QUERY 0x1F 1503 #define PACKET3_SET_PREDICATION 0x20 1504 #define PACKET3_REG_RMW 0x21 1505 #define PACKET3_COND_EXEC 0x22 1506 #define PACKET3_PRED_EXEC 0x23 1507 #define PACKET3_DRAW_INDIRECT 0x24 1508 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1509 #define PACKET3_INDEX_BASE 0x26 1510 #define PACKET3_DRAW_INDEX_2 0x27 1511 #define PACKET3_CONTEXT_CONTROL 0x28 1512 #define PACKET3_INDEX_TYPE 0x2A 1513 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1514 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1515 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1516 #define PACKET3_NUM_INSTANCES 0x2F 1517 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1518 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 1519 #define PACKET3_INDIRECT_BUFFER 0x32 1520 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1521 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1522 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1523 #define PACKET3_WRITE_DATA 0x37 1524 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1525 /* 0 - register 1526 * 1 - memory (sync - via GRBM) 1527 * 2 - tc/l2 1528 * 3 - gds 1529 * 4 - reserved 1530 * 5 - memory (async - direct) 1531 */ 1532 #define WR_ONE_ADDR (1 << 16) 1533 #define WR_CONFIRM (1 << 20) 1534 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1535 /* 0 - me 1536 * 1 - pfp 1537 * 2 - ce 1538 */ 1539 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1540 #define PACKET3_MEM_SEMAPHORE 0x39 1541 #define PACKET3_MPEG_INDEX 0x3A 1542 #define PACKET3_COPY_DW 0x3B 1543 #define PACKET3_WAIT_REG_MEM 0x3C 1544 #define PACKET3_MEM_WRITE 0x3D 1545 #define PACKET3_COPY_DATA 0x40 1546 #define PACKET3_CP_DMA 0x41 1547 /* 1. header 1548 * 2. SRC_ADDR_LO or DATA [31:0] 1549 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1550 * SRC_ADDR_HI [7:0] 1551 * 4. DST_ADDR_LO [31:0] 1552 * 5. DST_ADDR_HI [7:0] 1553 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1554 */ 1555 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1556 /* 0 - DST_ADDR 1557 * 1 - GDS 1558 */ 1559 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1560 /* 0 - ME 1561 * 1 - PFP 1562 */ 1563 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1564 /* 0 - SRC_ADDR 1565 * 1 - GDS 1566 * 2 - DATA 1567 */ 1568 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1569 /* COMMAND */ 1570 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1571 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1572 /* 0 - none 1573 * 1 - 8 in 16 1574 * 2 - 8 in 32 1575 * 3 - 8 in 64 1576 */ 1577 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1578 /* 0 - none 1579 * 1 - 8 in 16 1580 * 2 - 8 in 32 1581 * 3 - 8 in 64 1582 */ 1583 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1584 /* 0 - memory 1585 * 1 - register 1586 */ 1587 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1588 /* 0 - memory 1589 * 1 - register 1590 */ 1591 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1592 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1593 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 1594 #define PACKET3_PFP_SYNC_ME 0x42 1595 #define PACKET3_SURFACE_SYNC 0x43 1596 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1597 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1598 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1599 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1600 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1601 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1602 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1603 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1604 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1605 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1606 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1607 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1608 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1609 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1610 # define PACKET3_TC_ACTION_ENA (1 << 23) 1611 # define PACKET3_CB_ACTION_ENA (1 << 25) 1612 # define PACKET3_DB_ACTION_ENA (1 << 26) 1613 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1614 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1615 #define PACKET3_ME_INITIALIZE 0x44 1616 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1617 #define PACKET3_COND_WRITE 0x45 1618 #define PACKET3_EVENT_WRITE 0x46 1619 #define EVENT_TYPE(x) ((x) << 0) 1620 #define EVENT_INDEX(x) ((x) << 8) 1621 /* 0 - any non-TS event 1622 * 1 - ZPASS_DONE 1623 * 2 - SAMPLE_PIPELINESTAT 1624 * 3 - SAMPLE_STREAMOUTSTAT* 1625 * 4 - *S_PARTIAL_FLUSH 1626 * 5 - EOP events 1627 * 6 - EOS events 1628 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 1629 */ 1630 #define INV_L2 (1 << 20) 1631 /* INV TC L2 cache when EVENT_INDEX = 7 */ 1632 #define PACKET3_EVENT_WRITE_EOP 0x47 1633 #define DATA_SEL(x) ((x) << 29) 1634 /* 0 - discard 1635 * 1 - send low 32bit data 1636 * 2 - send 64bit data 1637 * 3 - send 64bit counter value 1638 */ 1639 #define INT_SEL(x) ((x) << 24) 1640 /* 0 - none 1641 * 1 - interrupt only (DATA_SEL = 0) 1642 * 2 - interrupt when data write is confirmed 1643 */ 1644 #define PACKET3_EVENT_WRITE_EOS 0x48 1645 #define PACKET3_PREAMBLE_CNTL 0x4A 1646 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1647 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1648 #define PACKET3_ONE_REG_WRITE 0x57 1649 #define PACKET3_LOAD_CONFIG_REG 0x5F 1650 #define PACKET3_LOAD_CONTEXT_REG 0x60 1651 #define PACKET3_LOAD_SH_REG 0x61 1652 #define PACKET3_SET_CONFIG_REG 0x68 1653 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1654 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1655 #define PACKET3_SET_CONTEXT_REG 0x69 1656 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1657 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1658 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1659 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1660 #define PACKET3_SET_SH_REG 0x76 1661 #define PACKET3_SET_SH_REG_START 0x0000b000 1662 #define PACKET3_SET_SH_REG_END 0x0000c000 1663 #define PACKET3_SET_SH_REG_OFFSET 0x77 1664 #define PACKET3_ME_WRITE 0x7A 1665 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1666 #define PACKET3_SCRATCH_RAM_READ 0x7E 1667 #define PACKET3_CE_WRITE 0x7F 1668 #define PACKET3_LOAD_CONST_RAM 0x80 1669 #define PACKET3_WRITE_CONST_RAM 0x81 1670 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 1671 #define PACKET3_DUMP_CONST_RAM 0x83 1672 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1673 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1674 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1675 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1676 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1677 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1678 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1679 #define PACKET3_SWITCH_BUFFER 0x8B 1680 1681 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1682 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1683 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1684 1685 #define DMA_RB_CNTL 0xd000 1686 # define DMA_RB_ENABLE (1 << 0) 1687 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1688 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1689 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1690 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1691 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1692 #define DMA_RB_BASE 0xd004 1693 #define DMA_RB_RPTR 0xd008 1694 #define DMA_RB_WPTR 0xd00c 1695 1696 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1697 #define DMA_RB_RPTR_ADDR_LO 0xd020 1698 1699 #define DMA_IB_CNTL 0xd024 1700 # define DMA_IB_ENABLE (1 << 0) 1701 # define DMA_IB_SWAP_ENABLE (1 << 4) 1702 #define DMA_IB_RPTR 0xd028 1703 #define DMA_CNTL 0xd02c 1704 # define TRAP_ENABLE (1 << 0) 1705 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1706 # define SEM_WAIT_INT_ENABLE (1 << 2) 1707 # define DATA_SWAP_ENABLE (1 << 3) 1708 # define FENCE_SWAP_ENABLE (1 << 4) 1709 # define CTXEMPTY_INT_ENABLE (1 << 28) 1710 #define DMA_STATUS_REG 0xd034 1711 # define DMA_IDLE (1 << 0) 1712 #define DMA_TILING_CONFIG 0xd0b8 1713 1714 #define DMA_POWER_CNTL 0xd0bc 1715 # define MEM_POWER_OVERRIDE (1 << 8) 1716 #define DMA_CLK_CTRL 0xd0c0 1717 1718 #define DMA_PG 0xd0d4 1719 # define PG_CNTL_ENABLE (1 << 0) 1720 #define DMA_PGFSM_CONFIG 0xd0d8 1721 #define DMA_PGFSM_WRITE 0xd0dc 1722 1723 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1724 (((b) & 0x1) << 26) | \ 1725 (((t) & 0x1) << 23) | \ 1726 (((s) & 0x1) << 22) | \ 1727 (((n) & 0xFFFFF) << 0)) 1728 1729 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1730 (((vmid) & 0xF) << 20) | \ 1731 (((n) & 0xFFFFF) << 0)) 1732 1733 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1734 (1 << 26) | \ 1735 (1 << 21) | \ 1736 (((n) & 0xFFFFF) << 0)) 1737 1738 /* async DMA Packet types */ 1739 #define DMA_PACKET_WRITE 0x2 1740 #define DMA_PACKET_COPY 0x3 1741 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1742 #define DMA_PACKET_SEMAPHORE 0x5 1743 #define DMA_PACKET_FENCE 0x6 1744 #define DMA_PACKET_TRAP 0x7 1745 #define DMA_PACKET_SRBM_WRITE 0x9 1746 #define DMA_PACKET_CONSTANT_FILL 0xd 1747 #define DMA_PACKET_NOP 0xf 1748 1749 #endif 1750