1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 28 29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 31 32 #define CG_MULT_THERMAL_STATUS 0x714 33 #define ASIC_MAX_TEMP(x) ((x) << 0) 34 #define ASIC_MAX_TEMP_MASK 0x000001ff 35 #define ASIC_MAX_TEMP_SHIFT 0 36 #define CTF_TEMP(x) ((x) << 9) 37 #define CTF_TEMP_MASK 0x0003fe00 38 #define CTF_TEMP_SHIFT 9 39 40 #define SI_MAX_SH_GPRS 256 41 #define SI_MAX_TEMP_GPRS 16 42 #define SI_MAX_SH_THREADS 256 43 #define SI_MAX_SH_STACK_ENTRIES 4096 44 #define SI_MAX_FRC_EOV_CNT 16384 45 #define SI_MAX_BACKENDS 8 46 #define SI_MAX_BACKENDS_MASK 0xFF 47 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 48 #define SI_MAX_SIMDS 12 49 #define SI_MAX_SIMDS_MASK 0x0FFF 50 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 51 #define SI_MAX_PIPES 8 52 #define SI_MAX_PIPES_MASK 0xFF 53 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 54 #define SI_MAX_LDS_NUM 0xFFFF 55 #define SI_MAX_TCC 16 56 #define SI_MAX_TCC_MASK 0xFFFF 57 58 #define VGA_HDP_CONTROL 0x328 59 #define VGA_MEMORY_DISABLE (1 << 4) 60 61 #define CG_CLKPIN_CNTL 0x660 62 # define XTALIN_DIVIDE (1 << 1) 63 #define CG_CLKPIN_CNTL_2 0x664 64 # define MUX_TCLK_TO_XCLK (1 << 8) 65 66 #define DMIF_ADDR_CONFIG 0xBD4 67 68 #define SRBM_STATUS 0xE50 69 #define GRBM_RQ_PENDING (1 << 5) 70 #define VMC_BUSY (1 << 8) 71 #define MCB_BUSY (1 << 9) 72 #define MCB_NON_DISPLAY_BUSY (1 << 10) 73 #define MCC_BUSY (1 << 11) 74 #define MCD_BUSY (1 << 12) 75 #define SEM_BUSY (1 << 14) 76 #define IH_BUSY (1 << 17) 77 78 #define SRBM_SOFT_RESET 0x0E60 79 #define SOFT_RESET_BIF (1 << 1) 80 #define SOFT_RESET_DC (1 << 5) 81 #define SOFT_RESET_DMA1 (1 << 6) 82 #define SOFT_RESET_GRBM (1 << 8) 83 #define SOFT_RESET_HDP (1 << 9) 84 #define SOFT_RESET_IH (1 << 10) 85 #define SOFT_RESET_MC (1 << 11) 86 #define SOFT_RESET_ROM (1 << 14) 87 #define SOFT_RESET_SEM (1 << 15) 88 #define SOFT_RESET_VMC (1 << 17) 89 #define SOFT_RESET_DMA (1 << 20) 90 #define SOFT_RESET_TST (1 << 21) 91 #define SOFT_RESET_REGBB (1 << 22) 92 #define SOFT_RESET_ORB (1 << 23) 93 94 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 95 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 96 97 #define SRBM_STATUS2 0x0EC4 98 #define DMA_BUSY (1 << 5) 99 #define DMA1_BUSY (1 << 6) 100 101 #define VM_L2_CNTL 0x1400 102 #define ENABLE_L2_CACHE (1 << 0) 103 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 104 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 105 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 106 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 107 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 108 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 109 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 110 #define VM_L2_CNTL2 0x1404 111 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 112 #define INVALIDATE_L2_CACHE (1 << 1) 113 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 114 #define INVALIDATE_PTE_AND_PDE_CACHES 0 115 #define INVALIDATE_ONLY_PTE_CACHES 1 116 #define INVALIDATE_ONLY_PDE_CACHES 2 117 #define VM_L2_CNTL3 0x1408 118 #define BANK_SELECT(x) ((x) << 0) 119 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 120 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 121 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 122 #define VM_L2_STATUS 0x140C 123 #define L2_BUSY (1 << 0) 124 #define VM_CONTEXT0_CNTL 0x1410 125 #define ENABLE_CONTEXT (1 << 0) 126 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 127 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 128 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 129 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 130 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 131 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 132 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 133 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 134 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 135 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 136 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 137 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 138 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 139 #define VM_CONTEXT1_CNTL 0x1414 140 #define VM_CONTEXT0_CNTL2 0x1430 141 #define VM_CONTEXT1_CNTL2 0x1434 142 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 143 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 144 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 145 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 146 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 147 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 148 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 149 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 150 151 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 152 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 153 154 #define VM_INVALIDATE_REQUEST 0x1478 155 #define VM_INVALIDATE_RESPONSE 0x147c 156 157 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 158 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 159 160 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 161 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 162 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 163 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 164 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 165 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 166 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 167 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 168 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 169 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 170 171 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 172 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 173 174 #define MC_SHARED_CHMAP 0x2004 175 #define NOOFCHAN_SHIFT 12 176 #define NOOFCHAN_MASK 0x0000f000 177 #define MC_SHARED_CHREMAP 0x2008 178 179 #define MC_VM_FB_LOCATION 0x2024 180 #define MC_VM_AGP_TOP 0x2028 181 #define MC_VM_AGP_BOT 0x202C 182 #define MC_VM_AGP_BASE 0x2030 183 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 184 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 185 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 186 187 #define MC_VM_MX_L1_TLB_CNTL 0x2064 188 #define ENABLE_L1_TLB (1 << 0) 189 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 190 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 191 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 192 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 193 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 194 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 195 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 196 197 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 198 199 #define MC_ARB_RAMCFG 0x2760 200 #define NOOFBANK_SHIFT 0 201 #define NOOFBANK_MASK 0x00000003 202 #define NOOFRANK_SHIFT 2 203 #define NOOFRANK_MASK 0x00000004 204 #define NOOFROWS_SHIFT 3 205 #define NOOFROWS_MASK 0x00000038 206 #define NOOFCOLS_SHIFT 6 207 #define NOOFCOLS_MASK 0x000000C0 208 #define CHANSIZE_SHIFT 8 209 #define CHANSIZE_MASK 0x00000100 210 #define CHANSIZE_OVERRIDE (1 << 11) 211 #define NOOFGROUPS_SHIFT 12 212 #define NOOFGROUPS_MASK 0x00001000 213 214 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 215 #define TRAIN_DONE_D0 (1 << 30) 216 #define TRAIN_DONE_D1 (1 << 31) 217 218 #define MC_SEQ_SUP_CNTL 0x28c8 219 #define RUN_MASK (1 << 0) 220 #define MC_SEQ_SUP_PGM 0x28cc 221 222 #define MC_IO_PAD_CNTL_D0 0x29d0 223 #define MEM_FALL_OUT_CMD (1 << 8) 224 225 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 226 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 227 228 #define HDP_HOST_PATH_CNTL 0x2C00 229 #define HDP_NONSURFACE_BASE 0x2C04 230 #define HDP_NONSURFACE_INFO 0x2C08 231 #define HDP_NONSURFACE_SIZE 0x2C0C 232 233 #define HDP_ADDR_CONFIG 0x2F48 234 #define HDP_MISC_CNTL 0x2F4C 235 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 236 237 #define IH_RB_CNTL 0x3e00 238 # define IH_RB_ENABLE (1 << 0) 239 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 240 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 241 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 242 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 243 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 244 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 245 #define IH_RB_BASE 0x3e04 246 #define IH_RB_RPTR 0x3e08 247 #define IH_RB_WPTR 0x3e0c 248 # define RB_OVERFLOW (1 << 0) 249 # define WPTR_OFFSET_MASK 0x3fffc 250 #define IH_RB_WPTR_ADDR_HI 0x3e10 251 #define IH_RB_WPTR_ADDR_LO 0x3e14 252 #define IH_CNTL 0x3e18 253 # define ENABLE_INTR (1 << 0) 254 # define IH_MC_SWAP(x) ((x) << 1) 255 # define IH_MC_SWAP_NONE 0 256 # define IH_MC_SWAP_16BIT 1 257 # define IH_MC_SWAP_32BIT 2 258 # define IH_MC_SWAP_64BIT 3 259 # define RPTR_REARM (1 << 4) 260 # define MC_WRREQ_CREDIT(x) ((x) << 15) 261 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 262 # define MC_VMID(x) ((x) << 25) 263 264 #define CONFIG_MEMSIZE 0x5428 265 266 #define INTERRUPT_CNTL 0x5468 267 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 268 # define IH_DUMMY_RD_EN (1 << 1) 269 # define IH_REQ_NONSNOOP_EN (1 << 3) 270 # define GEN_IH_INT_EN (1 << 8) 271 #define INTERRUPT_CNTL2 0x546c 272 273 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 274 275 #define BIF_FB_EN 0x5490 276 #define FB_READ_EN (1 << 0) 277 #define FB_WRITE_EN (1 << 1) 278 279 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 280 281 #define DC_LB_MEMORY_SPLIT 0x6b0c 282 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 283 284 #define PRIORITY_A_CNT 0x6b18 285 #define PRIORITY_MARK_MASK 0x7fff 286 #define PRIORITY_OFF (1 << 16) 287 #define PRIORITY_ALWAYS_ON (1 << 20) 288 #define PRIORITY_B_CNT 0x6b1c 289 290 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 291 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 292 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 293 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 294 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 295 296 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 297 #define VLINE_STATUS 0x6bb8 298 # define VLINE_OCCURRED (1 << 0) 299 # define VLINE_ACK (1 << 4) 300 # define VLINE_STAT (1 << 12) 301 # define VLINE_INTERRUPT (1 << 16) 302 # define VLINE_INTERRUPT_TYPE (1 << 17) 303 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 304 #define VBLANK_STATUS 0x6bbc 305 # define VBLANK_OCCURRED (1 << 0) 306 # define VBLANK_ACK (1 << 4) 307 # define VBLANK_STAT (1 << 12) 308 # define VBLANK_INTERRUPT (1 << 16) 309 # define VBLANK_INTERRUPT_TYPE (1 << 17) 310 311 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 312 #define INT_MASK 0x6b40 313 # define VBLANK_INT_MASK (1 << 0) 314 # define VLINE_INT_MASK (1 << 4) 315 316 #define DISP_INTERRUPT_STATUS 0x60f4 317 # define LB_D1_VLINE_INTERRUPT (1 << 2) 318 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 319 # define DC_HPD1_INTERRUPT (1 << 17) 320 # define DC_HPD1_RX_INTERRUPT (1 << 18) 321 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 322 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 323 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 324 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 325 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 326 # define LB_D2_VLINE_INTERRUPT (1 << 2) 327 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 328 # define DC_HPD2_INTERRUPT (1 << 17) 329 # define DC_HPD2_RX_INTERRUPT (1 << 18) 330 # define DISP_TIMER_INTERRUPT (1 << 24) 331 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 332 # define LB_D3_VLINE_INTERRUPT (1 << 2) 333 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 334 # define DC_HPD3_INTERRUPT (1 << 17) 335 # define DC_HPD3_RX_INTERRUPT (1 << 18) 336 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 337 # define LB_D4_VLINE_INTERRUPT (1 << 2) 338 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 339 # define DC_HPD4_INTERRUPT (1 << 17) 340 # define DC_HPD4_RX_INTERRUPT (1 << 18) 341 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 342 # define LB_D5_VLINE_INTERRUPT (1 << 2) 343 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 344 # define DC_HPD5_INTERRUPT (1 << 17) 345 # define DC_HPD5_RX_INTERRUPT (1 << 18) 346 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 347 # define LB_D6_VLINE_INTERRUPT (1 << 2) 348 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 349 # define DC_HPD6_INTERRUPT (1 << 17) 350 # define DC_HPD6_RX_INTERRUPT (1 << 18) 351 352 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 353 #define GRPH_INT_STATUS 0x6858 354 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 355 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 356 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 357 #define GRPH_INT_CONTROL 0x685c 358 # define GRPH_PFLIP_INT_MASK (1 << 0) 359 # define GRPH_PFLIP_INT_TYPE (1 << 8) 360 361 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 362 363 #define DC_HPD1_INT_STATUS 0x601c 364 #define DC_HPD2_INT_STATUS 0x6028 365 #define DC_HPD3_INT_STATUS 0x6034 366 #define DC_HPD4_INT_STATUS 0x6040 367 #define DC_HPD5_INT_STATUS 0x604c 368 #define DC_HPD6_INT_STATUS 0x6058 369 # define DC_HPDx_INT_STATUS (1 << 0) 370 # define DC_HPDx_SENSE (1 << 1) 371 # define DC_HPDx_RX_INT_STATUS (1 << 8) 372 373 #define DC_HPD1_INT_CONTROL 0x6020 374 #define DC_HPD2_INT_CONTROL 0x602c 375 #define DC_HPD3_INT_CONTROL 0x6038 376 #define DC_HPD4_INT_CONTROL 0x6044 377 #define DC_HPD5_INT_CONTROL 0x6050 378 #define DC_HPD6_INT_CONTROL 0x605c 379 # define DC_HPDx_INT_ACK (1 << 0) 380 # define DC_HPDx_INT_POLARITY (1 << 8) 381 # define DC_HPDx_INT_EN (1 << 16) 382 # define DC_HPDx_RX_INT_ACK (1 << 20) 383 # define DC_HPDx_RX_INT_EN (1 << 24) 384 385 #define DC_HPD1_CONTROL 0x6024 386 #define DC_HPD2_CONTROL 0x6030 387 #define DC_HPD3_CONTROL 0x603c 388 #define DC_HPD4_CONTROL 0x6048 389 #define DC_HPD5_CONTROL 0x6054 390 #define DC_HPD6_CONTROL 0x6060 391 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 392 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 393 # define DC_HPDx_EN (1 << 28) 394 395 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 396 #define CRTC_STATUS_FRAME_COUNT 0x6e98 397 398 #define GRBM_CNTL 0x8000 399 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 400 401 #define GRBM_STATUS2 0x8008 402 #define RLC_RQ_PENDING (1 << 0) 403 #define RLC_BUSY (1 << 8) 404 #define TC_BUSY (1 << 9) 405 406 #define GRBM_STATUS 0x8010 407 #define CMDFIFO_AVAIL_MASK 0x0000000F 408 #define RING2_RQ_PENDING (1 << 4) 409 #define SRBM_RQ_PENDING (1 << 5) 410 #define RING1_RQ_PENDING (1 << 6) 411 #define CF_RQ_PENDING (1 << 7) 412 #define PF_RQ_PENDING (1 << 8) 413 #define GDS_DMA_RQ_PENDING (1 << 9) 414 #define GRBM_EE_BUSY (1 << 10) 415 #define DB_CLEAN (1 << 12) 416 #define CB_CLEAN (1 << 13) 417 #define TA_BUSY (1 << 14) 418 #define GDS_BUSY (1 << 15) 419 #define VGT_BUSY (1 << 17) 420 #define IA_BUSY_NO_DMA (1 << 18) 421 #define IA_BUSY (1 << 19) 422 #define SX_BUSY (1 << 20) 423 #define SPI_BUSY (1 << 22) 424 #define BCI_BUSY (1 << 23) 425 #define SC_BUSY (1 << 24) 426 #define PA_BUSY (1 << 25) 427 #define DB_BUSY (1 << 26) 428 #define CP_COHERENCY_BUSY (1 << 28) 429 #define CP_BUSY (1 << 29) 430 #define CB_BUSY (1 << 30) 431 #define GUI_ACTIVE (1 << 31) 432 #define GRBM_STATUS_SE0 0x8014 433 #define GRBM_STATUS_SE1 0x8018 434 #define SE_DB_CLEAN (1 << 1) 435 #define SE_CB_CLEAN (1 << 2) 436 #define SE_BCI_BUSY (1 << 22) 437 #define SE_VGT_BUSY (1 << 23) 438 #define SE_PA_BUSY (1 << 24) 439 #define SE_TA_BUSY (1 << 25) 440 #define SE_SX_BUSY (1 << 26) 441 #define SE_SPI_BUSY (1 << 27) 442 #define SE_SC_BUSY (1 << 29) 443 #define SE_DB_BUSY (1 << 30) 444 #define SE_CB_BUSY (1 << 31) 445 446 #define GRBM_SOFT_RESET 0x8020 447 #define SOFT_RESET_CP (1 << 0) 448 #define SOFT_RESET_CB (1 << 1) 449 #define SOFT_RESET_RLC (1 << 2) 450 #define SOFT_RESET_DB (1 << 3) 451 #define SOFT_RESET_GDS (1 << 4) 452 #define SOFT_RESET_PA (1 << 5) 453 #define SOFT_RESET_SC (1 << 6) 454 #define SOFT_RESET_BCI (1 << 7) 455 #define SOFT_RESET_SPI (1 << 8) 456 #define SOFT_RESET_SX (1 << 10) 457 #define SOFT_RESET_TC (1 << 11) 458 #define SOFT_RESET_TA (1 << 12) 459 #define SOFT_RESET_VGT (1 << 14) 460 #define SOFT_RESET_IA (1 << 15) 461 462 #define GRBM_GFX_INDEX 0x802C 463 #define INSTANCE_INDEX(x) ((x) << 0) 464 #define SH_INDEX(x) ((x) << 8) 465 #define SE_INDEX(x) ((x) << 16) 466 #define SH_BROADCAST_WRITES (1 << 29) 467 #define INSTANCE_BROADCAST_WRITES (1 << 30) 468 #define SE_BROADCAST_WRITES (1 << 31) 469 470 #define GRBM_INT_CNTL 0x8060 471 # define RDERR_INT_ENABLE (1 << 0) 472 # define GUI_IDLE_INT_ENABLE (1 << 19) 473 474 #define CP_STRMOUT_CNTL 0x84FC 475 #define SCRATCH_REG0 0x8500 476 #define SCRATCH_REG1 0x8504 477 #define SCRATCH_REG2 0x8508 478 #define SCRATCH_REG3 0x850C 479 #define SCRATCH_REG4 0x8510 480 #define SCRATCH_REG5 0x8514 481 #define SCRATCH_REG6 0x8518 482 #define SCRATCH_REG7 0x851C 483 484 #define SCRATCH_UMSK 0x8540 485 #define SCRATCH_ADDR 0x8544 486 487 #define CP_SEM_WAIT_TIMER 0x85BC 488 489 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 490 491 #define CP_ME_CNTL 0x86D8 492 #define CP_CE_HALT (1 << 24) 493 #define CP_PFP_HALT (1 << 26) 494 #define CP_ME_HALT (1 << 28) 495 496 #define CP_COHER_CNTL2 0x85E8 497 498 #define CP_RB2_RPTR 0x86f8 499 #define CP_RB1_RPTR 0x86fc 500 #define CP_RB0_RPTR 0x8700 501 #define CP_RB_WPTR_DELAY 0x8704 502 503 #define CP_QUEUE_THRESHOLDS 0x8760 504 #define ROQ_IB1_START(x) ((x) << 0) 505 #define ROQ_IB2_START(x) ((x) << 8) 506 #define CP_MEQ_THRESHOLDS 0x8764 507 #define MEQ1_START(x) ((x) << 0) 508 #define MEQ2_START(x) ((x) << 8) 509 510 #define CP_PERFMON_CNTL 0x87FC 511 512 #define VGT_VTX_VECT_EJECT_REG 0x88B0 513 514 #define VGT_CACHE_INVALIDATION 0x88C4 515 #define CACHE_INVALIDATION(x) ((x) << 0) 516 #define VC_ONLY 0 517 #define TC_ONLY 1 518 #define VC_AND_TC 2 519 #define AUTO_INVLD_EN(x) ((x) << 6) 520 #define NO_AUTO 0 521 #define ES_AUTO 1 522 #define GS_AUTO 2 523 #define ES_AND_GS_AUTO 3 524 #define VGT_ESGS_RING_SIZE 0x88C8 525 #define VGT_GSVS_RING_SIZE 0x88CC 526 527 #define VGT_GS_VERTEX_REUSE 0x88D4 528 529 #define VGT_PRIMITIVE_TYPE 0x8958 530 #define VGT_INDEX_TYPE 0x895C 531 532 #define VGT_NUM_INDICES 0x8970 533 #define VGT_NUM_INSTANCES 0x8974 534 535 #define VGT_TF_RING_SIZE 0x8988 536 537 #define VGT_HS_OFFCHIP_PARAM 0x89B0 538 539 #define VGT_TF_MEMORY_BASE 0x89B8 540 541 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 542 #define INACTIVE_CUS_MASK 0xFFFF0000 543 #define INACTIVE_CUS_SHIFT 16 544 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 545 546 #define PA_CL_ENHANCE 0x8A14 547 #define CLIP_VTX_REORDER_ENA (1 << 0) 548 #define NUM_CLIP_SEQ(x) ((x) << 1) 549 550 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 551 552 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 553 554 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 555 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 556 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 557 558 #define PA_SC_FIFO_SIZE 0x8BCC 559 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 560 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 561 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 562 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 563 564 #define PA_SC_ENHANCE 0x8BF0 565 566 #define SQ_CONFIG 0x8C00 567 568 #define SQC_CACHES 0x8C08 569 570 #define SX_DEBUG_1 0x9060 571 572 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 573 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 574 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 575 #define SPI_PS_MAX_WAVE_ID 0x90EC 576 577 #define SPI_CONFIG_CNTL 0x9100 578 579 #define SPI_CONFIG_CNTL_1 0x913C 580 #define VTX_DONE_DELAY(x) ((x) << 0) 581 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 582 583 #define CGTS_TCC_DISABLE 0x9148 584 #define CGTS_USER_TCC_DISABLE 0x914C 585 #define TCC_DISABLE_MASK 0xFFFF0000 586 #define TCC_DISABLE_SHIFT 16 587 588 #define TA_CNTL_AUX 0x9508 589 590 #define CC_RB_BACKEND_DISABLE 0x98F4 591 #define BACKEND_DISABLE(x) ((x) << 16) 592 #define GB_ADDR_CONFIG 0x98F8 593 #define NUM_PIPES(x) ((x) << 0) 594 #define NUM_PIPES_MASK 0x00000007 595 #define NUM_PIPES_SHIFT 0 596 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 597 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 598 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 599 #define NUM_SHADER_ENGINES(x) ((x) << 12) 600 #define NUM_SHADER_ENGINES_MASK 0x00003000 601 #define NUM_SHADER_ENGINES_SHIFT 12 602 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 603 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 604 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 605 #define NUM_GPUS(x) ((x) << 20) 606 #define NUM_GPUS_MASK 0x00700000 607 #define NUM_GPUS_SHIFT 20 608 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 609 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 610 #define MULTI_GPU_TILE_SIZE_SHIFT 24 611 #define ROW_SIZE(x) ((x) << 28) 612 #define ROW_SIZE_MASK 0x30000000 613 #define ROW_SIZE_SHIFT 28 614 615 #define GB_TILE_MODE0 0x9910 616 # define MICRO_TILE_MODE(x) ((x) << 0) 617 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 618 # define ADDR_SURF_THIN_MICRO_TILING 1 619 # define ADDR_SURF_DEPTH_MICRO_TILING 2 620 # define ARRAY_MODE(x) ((x) << 2) 621 # define ARRAY_LINEAR_GENERAL 0 622 # define ARRAY_LINEAR_ALIGNED 1 623 # define ARRAY_1D_TILED_THIN1 2 624 # define ARRAY_2D_TILED_THIN1 4 625 # define PIPE_CONFIG(x) ((x) << 6) 626 # define ADDR_SURF_P2 0 627 # define ADDR_SURF_P4_8x16 4 628 # define ADDR_SURF_P4_16x16 5 629 # define ADDR_SURF_P4_16x32 6 630 # define ADDR_SURF_P4_32x32 7 631 # define ADDR_SURF_P8_16x16_8x16 8 632 # define ADDR_SURF_P8_16x32_8x16 9 633 # define ADDR_SURF_P8_32x32_8x16 10 634 # define ADDR_SURF_P8_16x32_16x16 11 635 # define ADDR_SURF_P8_32x32_16x16 12 636 # define ADDR_SURF_P8_32x32_16x32 13 637 # define ADDR_SURF_P8_32x64_32x32 14 638 # define TILE_SPLIT(x) ((x) << 11) 639 # define ADDR_SURF_TILE_SPLIT_64B 0 640 # define ADDR_SURF_TILE_SPLIT_128B 1 641 # define ADDR_SURF_TILE_SPLIT_256B 2 642 # define ADDR_SURF_TILE_SPLIT_512B 3 643 # define ADDR_SURF_TILE_SPLIT_1KB 4 644 # define ADDR_SURF_TILE_SPLIT_2KB 5 645 # define ADDR_SURF_TILE_SPLIT_4KB 6 646 # define BANK_WIDTH(x) ((x) << 14) 647 # define ADDR_SURF_BANK_WIDTH_1 0 648 # define ADDR_SURF_BANK_WIDTH_2 1 649 # define ADDR_SURF_BANK_WIDTH_4 2 650 # define ADDR_SURF_BANK_WIDTH_8 3 651 # define BANK_HEIGHT(x) ((x) << 16) 652 # define ADDR_SURF_BANK_HEIGHT_1 0 653 # define ADDR_SURF_BANK_HEIGHT_2 1 654 # define ADDR_SURF_BANK_HEIGHT_4 2 655 # define ADDR_SURF_BANK_HEIGHT_8 3 656 # define MACRO_TILE_ASPECT(x) ((x) << 18) 657 # define ADDR_SURF_MACRO_ASPECT_1 0 658 # define ADDR_SURF_MACRO_ASPECT_2 1 659 # define ADDR_SURF_MACRO_ASPECT_4 2 660 # define ADDR_SURF_MACRO_ASPECT_8 3 661 # define NUM_BANKS(x) ((x) << 20) 662 # define ADDR_SURF_2_BANK 0 663 # define ADDR_SURF_4_BANK 1 664 # define ADDR_SURF_8_BANK 2 665 # define ADDR_SURF_16_BANK 3 666 667 #define CB_PERFCOUNTER0_SELECT0 0x9a20 668 #define CB_PERFCOUNTER0_SELECT1 0x9a24 669 #define CB_PERFCOUNTER1_SELECT0 0x9a28 670 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 671 #define CB_PERFCOUNTER2_SELECT0 0x9a30 672 #define CB_PERFCOUNTER2_SELECT1 0x9a34 673 #define CB_PERFCOUNTER3_SELECT0 0x9a38 674 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 675 676 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 677 #define BACKEND_DISABLE_MASK 0x00FF0000 678 #define BACKEND_DISABLE_SHIFT 16 679 680 #define TCP_CHAN_STEER_LO 0xac0c 681 #define TCP_CHAN_STEER_HI 0xac10 682 683 #define CP_RB0_BASE 0xC100 684 #define CP_RB0_CNTL 0xC104 685 #define RB_BUFSZ(x) ((x) << 0) 686 #define RB_BLKSZ(x) ((x) << 8) 687 #define BUF_SWAP_32BIT (2 << 16) 688 #define RB_NO_UPDATE (1 << 27) 689 #define RB_RPTR_WR_ENA (1 << 31) 690 691 #define CP_RB0_RPTR_ADDR 0xC10C 692 #define CP_RB0_RPTR_ADDR_HI 0xC110 693 #define CP_RB0_WPTR 0xC114 694 695 #define CP_PFP_UCODE_ADDR 0xC150 696 #define CP_PFP_UCODE_DATA 0xC154 697 #define CP_ME_RAM_RADDR 0xC158 698 #define CP_ME_RAM_WADDR 0xC15C 699 #define CP_ME_RAM_DATA 0xC160 700 701 #define CP_CE_UCODE_ADDR 0xC168 702 #define CP_CE_UCODE_DATA 0xC16C 703 704 #define CP_RB1_BASE 0xC180 705 #define CP_RB1_CNTL 0xC184 706 #define CP_RB1_RPTR_ADDR 0xC188 707 #define CP_RB1_RPTR_ADDR_HI 0xC18C 708 #define CP_RB1_WPTR 0xC190 709 #define CP_RB2_BASE 0xC194 710 #define CP_RB2_CNTL 0xC198 711 #define CP_RB2_RPTR_ADDR 0xC19C 712 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 713 #define CP_RB2_WPTR 0xC1A4 714 #define CP_INT_CNTL_RING0 0xC1A8 715 #define CP_INT_CNTL_RING1 0xC1AC 716 #define CP_INT_CNTL_RING2 0xC1B0 717 # define CNTX_BUSY_INT_ENABLE (1 << 19) 718 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 719 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 720 # define TIME_STAMP_INT_ENABLE (1 << 26) 721 # define CP_RINGID2_INT_ENABLE (1 << 29) 722 # define CP_RINGID1_INT_ENABLE (1 << 30) 723 # define CP_RINGID0_INT_ENABLE (1 << 31) 724 #define CP_INT_STATUS_RING0 0xC1B4 725 #define CP_INT_STATUS_RING1 0xC1B8 726 #define CP_INT_STATUS_RING2 0xC1BC 727 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 728 # define TIME_STAMP_INT_STAT (1 << 26) 729 # define CP_RINGID2_INT_STAT (1 << 29) 730 # define CP_RINGID1_INT_STAT (1 << 30) 731 # define CP_RINGID0_INT_STAT (1 << 31) 732 733 #define CP_DEBUG 0xC1FC 734 735 #define RLC_CNTL 0xC300 736 # define RLC_ENABLE (1 << 0) 737 #define RLC_RL_BASE 0xC304 738 #define RLC_RL_SIZE 0xC308 739 #define RLC_LB_CNTL 0xC30C 740 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 741 #define RLC_LB_CNTR_MAX 0xC314 742 #define RLC_LB_CNTR_INIT 0xC318 743 744 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 745 746 #define RLC_UCODE_ADDR 0xC32C 747 #define RLC_UCODE_DATA 0xC330 748 749 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 750 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 751 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 752 #define RLC_MC_CNTL 0xC344 753 #define RLC_UCODE_CNTL 0xC348 754 755 #define PA_SC_RASTER_CONFIG 0x28350 756 # define RASTER_CONFIG_RB_MAP_0 0 757 # define RASTER_CONFIG_RB_MAP_1 1 758 # define RASTER_CONFIG_RB_MAP_2 2 759 # define RASTER_CONFIG_RB_MAP_3 3 760 761 #define VGT_EVENT_INITIATOR 0x28a90 762 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 763 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 764 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 765 # define CACHE_FLUSH_TS (4 << 0) 766 # define CACHE_FLUSH (6 << 0) 767 # define CS_PARTIAL_FLUSH (7 << 0) 768 # define VGT_STREAMOUT_RESET (10 << 0) 769 # define END_OF_PIPE_INCR_DE (11 << 0) 770 # define END_OF_PIPE_IB_END (12 << 0) 771 # define RST_PIX_CNT (13 << 0) 772 # define VS_PARTIAL_FLUSH (15 << 0) 773 # define PS_PARTIAL_FLUSH (16 << 0) 774 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 775 # define ZPASS_DONE (21 << 0) 776 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 777 # define PERFCOUNTER_START (23 << 0) 778 # define PERFCOUNTER_STOP (24 << 0) 779 # define PIPELINESTAT_START (25 << 0) 780 # define PIPELINESTAT_STOP (26 << 0) 781 # define PERFCOUNTER_SAMPLE (27 << 0) 782 # define SAMPLE_PIPELINESTAT (30 << 0) 783 # define SAMPLE_STREAMOUTSTATS (32 << 0) 784 # define RESET_VTX_CNT (33 << 0) 785 # define VGT_FLUSH (36 << 0) 786 # define BOTTOM_OF_PIPE_TS (40 << 0) 787 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 788 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 789 # define FLUSH_AND_INV_DB_META (44 << 0) 790 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 791 # define FLUSH_AND_INV_CB_META (46 << 0) 792 # define CS_DONE (47 << 0) 793 # define PS_DONE (48 << 0) 794 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 795 # define THREAD_TRACE_START (51 << 0) 796 # define THREAD_TRACE_STOP (52 << 0) 797 # define THREAD_TRACE_FLUSH (54 << 0) 798 # define THREAD_TRACE_FINISH (55 << 0) 799 800 /* 801 * PM4 802 */ 803 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 804 (((reg) >> 2) & 0xFFFF) | \ 805 ((n) & 0x3FFF) << 16) 806 #define CP_PACKET2 0x80000000 807 #define PACKET2_PAD_SHIFT 0 808 #define PACKET2_PAD_MASK (0x3fffffff << 0) 809 810 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 811 812 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 813 (((op) & 0xFF) << 8) | \ 814 ((n) & 0x3FFF) << 16) 815 816 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 817 818 /* Packet 3 types */ 819 #define PACKET3_NOP 0x10 820 #define PACKET3_SET_BASE 0x11 821 #define PACKET3_BASE_INDEX(x) ((x) << 0) 822 #define GDS_PARTITION_BASE 2 823 #define CE_PARTITION_BASE 3 824 #define PACKET3_CLEAR_STATE 0x12 825 #define PACKET3_INDEX_BUFFER_SIZE 0x13 826 #define PACKET3_DISPATCH_DIRECT 0x15 827 #define PACKET3_DISPATCH_INDIRECT 0x16 828 #define PACKET3_ALLOC_GDS 0x1B 829 #define PACKET3_WRITE_GDS_RAM 0x1C 830 #define PACKET3_ATOMIC_GDS 0x1D 831 #define PACKET3_ATOMIC 0x1E 832 #define PACKET3_OCCLUSION_QUERY 0x1F 833 #define PACKET3_SET_PREDICATION 0x20 834 #define PACKET3_REG_RMW 0x21 835 #define PACKET3_COND_EXEC 0x22 836 #define PACKET3_PRED_EXEC 0x23 837 #define PACKET3_DRAW_INDIRECT 0x24 838 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 839 #define PACKET3_INDEX_BASE 0x26 840 #define PACKET3_DRAW_INDEX_2 0x27 841 #define PACKET3_CONTEXT_CONTROL 0x28 842 #define PACKET3_INDEX_TYPE 0x2A 843 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 844 #define PACKET3_DRAW_INDEX_AUTO 0x2D 845 #define PACKET3_DRAW_INDEX_IMMD 0x2E 846 #define PACKET3_NUM_INSTANCES 0x2F 847 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 848 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 849 #define PACKET3_INDIRECT_BUFFER 0x32 850 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 851 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 852 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 853 #define PACKET3_WRITE_DATA 0x37 854 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 855 /* 0 - register 856 * 1 - memory (sync - via GRBM) 857 * 2 - tc/l2 858 * 3 - gds 859 * 4 - reserved 860 * 5 - memory (async - direct) 861 */ 862 #define WR_ONE_ADDR (1 << 16) 863 #define WR_CONFIRM (1 << 20) 864 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 865 /* 0 - me 866 * 1 - pfp 867 * 2 - ce 868 */ 869 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 870 #define PACKET3_MEM_SEMAPHORE 0x39 871 #define PACKET3_MPEG_INDEX 0x3A 872 #define PACKET3_COPY_DW 0x3B 873 #define PACKET3_WAIT_REG_MEM 0x3C 874 #define PACKET3_MEM_WRITE 0x3D 875 #define PACKET3_COPY_DATA 0x40 876 #define PACKET3_CP_DMA 0x41 877 /* 1. header 878 * 2. SRC_ADDR_LO or DATA [31:0] 879 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 880 * SRC_ADDR_HI [7:0] 881 * 4. DST_ADDR_LO [31:0] 882 * 5. DST_ADDR_HI [7:0] 883 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 884 */ 885 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 886 /* 0 - SRC_ADDR 887 * 1 - GDS 888 */ 889 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 890 /* 0 - ME 891 * 1 - PFP 892 */ 893 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 894 /* 0 - SRC_ADDR 895 * 1 - GDS 896 * 2 - DATA 897 */ 898 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 899 /* COMMAND */ 900 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 901 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 902 /* 0 - none 903 * 1 - 8 in 16 904 * 2 - 8 in 32 905 * 3 - 8 in 64 906 */ 907 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 908 /* 0 - none 909 * 1 - 8 in 16 910 * 2 - 8 in 32 911 * 3 - 8 in 64 912 */ 913 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 914 /* 0 - memory 915 * 1 - register 916 */ 917 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 918 /* 0 - memory 919 * 1 - register 920 */ 921 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 922 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 923 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 924 #define PACKET3_PFP_SYNC_ME 0x42 925 #define PACKET3_SURFACE_SYNC 0x43 926 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 927 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 928 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 929 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 930 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 931 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 932 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 933 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 934 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 935 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 936 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 937 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 938 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 939 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 940 # define PACKET3_TC_ACTION_ENA (1 << 23) 941 # define PACKET3_CB_ACTION_ENA (1 << 25) 942 # define PACKET3_DB_ACTION_ENA (1 << 26) 943 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 944 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 945 #define PACKET3_ME_INITIALIZE 0x44 946 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 947 #define PACKET3_COND_WRITE 0x45 948 #define PACKET3_EVENT_WRITE 0x46 949 #define EVENT_TYPE(x) ((x) << 0) 950 #define EVENT_INDEX(x) ((x) << 8) 951 /* 0 - any non-TS event 952 * 1 - ZPASS_DONE 953 * 2 - SAMPLE_PIPELINESTAT 954 * 3 - SAMPLE_STREAMOUTSTAT* 955 * 4 - *S_PARTIAL_FLUSH 956 * 5 - EOP events 957 * 6 - EOS events 958 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 959 */ 960 #define INV_L2 (1 << 20) 961 /* INV TC L2 cache when EVENT_INDEX = 7 */ 962 #define PACKET3_EVENT_WRITE_EOP 0x47 963 #define DATA_SEL(x) ((x) << 29) 964 /* 0 - discard 965 * 1 - send low 32bit data 966 * 2 - send 64bit data 967 * 3 - send 64bit counter value 968 */ 969 #define INT_SEL(x) ((x) << 24) 970 /* 0 - none 971 * 1 - interrupt only (DATA_SEL = 0) 972 * 2 - interrupt when data write is confirmed 973 */ 974 #define PACKET3_EVENT_WRITE_EOS 0x48 975 #define PACKET3_PREAMBLE_CNTL 0x4A 976 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 977 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 978 #define PACKET3_ONE_REG_WRITE 0x57 979 #define PACKET3_LOAD_CONFIG_REG 0x5F 980 #define PACKET3_LOAD_CONTEXT_REG 0x60 981 #define PACKET3_LOAD_SH_REG 0x61 982 #define PACKET3_SET_CONFIG_REG 0x68 983 #define PACKET3_SET_CONFIG_REG_START 0x00008000 984 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 985 #define PACKET3_SET_CONTEXT_REG 0x69 986 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 987 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 988 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 989 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 990 #define PACKET3_SET_SH_REG 0x76 991 #define PACKET3_SET_SH_REG_START 0x0000b000 992 #define PACKET3_SET_SH_REG_END 0x0000c000 993 #define PACKET3_SET_SH_REG_OFFSET 0x77 994 #define PACKET3_ME_WRITE 0x7A 995 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 996 #define PACKET3_SCRATCH_RAM_READ 0x7E 997 #define PACKET3_CE_WRITE 0x7F 998 #define PACKET3_LOAD_CONST_RAM 0x80 999 #define PACKET3_WRITE_CONST_RAM 0x81 1000 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 1001 #define PACKET3_DUMP_CONST_RAM 0x83 1002 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1003 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1004 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1005 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1006 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1007 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1008 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1009 #define PACKET3_SWITCH_BUFFER 0x8B 1010 1011 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1012 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1013 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1014 1015 #define DMA_RB_CNTL 0xd000 1016 # define DMA_RB_ENABLE (1 << 0) 1017 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1018 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1019 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1020 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1021 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1022 #define DMA_RB_BASE 0xd004 1023 #define DMA_RB_RPTR 0xd008 1024 #define DMA_RB_WPTR 0xd00c 1025 1026 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1027 #define DMA_RB_RPTR_ADDR_LO 0xd020 1028 1029 #define DMA_IB_CNTL 0xd024 1030 # define DMA_IB_ENABLE (1 << 0) 1031 # define DMA_IB_SWAP_ENABLE (1 << 4) 1032 #define DMA_IB_RPTR 0xd028 1033 #define DMA_CNTL 0xd02c 1034 # define TRAP_ENABLE (1 << 0) 1035 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1036 # define SEM_WAIT_INT_ENABLE (1 << 2) 1037 # define DATA_SWAP_ENABLE (1 << 3) 1038 # define FENCE_SWAP_ENABLE (1 << 4) 1039 # define CTXEMPTY_INT_ENABLE (1 << 28) 1040 #define DMA_STATUS_REG 0xd034 1041 # define DMA_IDLE (1 << 0) 1042 #define DMA_TILING_CONFIG 0xd0b8 1043 1044 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1045 (((b) & 0x1) << 26) | \ 1046 (((t) & 0x1) << 23) | \ 1047 (((s) & 0x1) << 22) | \ 1048 (((n) & 0xFFFFF) << 0)) 1049 1050 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1051 (((vmid) & 0xF) << 20) | \ 1052 (((n) & 0xFFFFF) << 0)) 1053 1054 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1055 (1 << 26) | \ 1056 (1 << 21) | \ 1057 (((n) & 0xFFFFF) << 0)) 1058 1059 /* async DMA Packet types */ 1060 #define DMA_PACKET_WRITE 0x2 1061 #define DMA_PACKET_COPY 0x3 1062 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1063 #define DMA_PACKET_SEMAPHORE 0x5 1064 #define DMA_PACKET_FENCE 0x6 1065 #define DMA_PACKET_TRAP 0x7 1066 #define DMA_PACKET_SRBM_WRITE 0x9 1067 #define DMA_PACKET_CONSTANT_FILL 0xd 1068 #define DMA_PACKET_NOP 0xf 1069 1070 #endif 1071