1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define CG_MULT_THERMAL_STATUS 0x714 28 #define ASIC_MAX_TEMP(x) ((x) << 0) 29 #define ASIC_MAX_TEMP_MASK 0x000001ff 30 #define ASIC_MAX_TEMP_SHIFT 0 31 #define CTF_TEMP(x) ((x) << 9) 32 #define CTF_TEMP_MASK 0x0003fe00 33 #define CTF_TEMP_SHIFT 9 34 35 #define SI_MAX_SH_GPRS 256 36 #define SI_MAX_TEMP_GPRS 16 37 #define SI_MAX_SH_THREADS 256 38 #define SI_MAX_SH_STACK_ENTRIES 4096 39 #define SI_MAX_FRC_EOV_CNT 16384 40 #define SI_MAX_BACKENDS 8 41 #define SI_MAX_BACKENDS_MASK 0xFF 42 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 43 #define SI_MAX_SIMDS 12 44 #define SI_MAX_SIMDS_MASK 0x0FFF 45 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 46 #define SI_MAX_PIPES 8 47 #define SI_MAX_PIPES_MASK 0xFF 48 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 49 #define SI_MAX_LDS_NUM 0xFFFF 50 #define SI_MAX_TCC 16 51 #define SI_MAX_TCC_MASK 0xFFFF 52 53 #define VGA_HDP_CONTROL 0x328 54 #define VGA_MEMORY_DISABLE (1 << 4) 55 56 #define DMIF_ADDR_CONFIG 0xBD4 57 58 #define SRBM_STATUS 0xE50 59 60 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 61 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 62 63 #define VM_L2_CNTL 0x1400 64 #define ENABLE_L2_CACHE (1 << 0) 65 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 66 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 67 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 68 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 69 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 70 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 71 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 72 #define VM_L2_CNTL2 0x1404 73 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 74 #define INVALIDATE_L2_CACHE (1 << 1) 75 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 76 #define INVALIDATE_PTE_AND_PDE_CACHES 0 77 #define INVALIDATE_ONLY_PTE_CACHES 1 78 #define INVALIDATE_ONLY_PDE_CACHES 2 79 #define VM_L2_CNTL3 0x1408 80 #define BANK_SELECT(x) ((x) << 0) 81 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 82 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 83 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 84 #define VM_L2_STATUS 0x140C 85 #define L2_BUSY (1 << 0) 86 #define VM_CONTEXT0_CNTL 0x1410 87 #define ENABLE_CONTEXT (1 << 0) 88 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 89 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 90 #define VM_CONTEXT1_CNTL 0x1414 91 #define VM_CONTEXT0_CNTL2 0x1430 92 #define VM_CONTEXT1_CNTL2 0x1434 93 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 94 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 95 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 96 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 97 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 98 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 99 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 100 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 101 102 #define VM_INVALIDATE_REQUEST 0x1478 103 #define VM_INVALIDATE_RESPONSE 0x147c 104 105 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 106 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 107 108 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 109 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 110 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 111 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 112 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 113 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 114 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 115 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 116 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 117 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 118 119 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 120 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 121 122 #define MC_SHARED_CHMAP 0x2004 123 #define NOOFCHAN_SHIFT 12 124 #define NOOFCHAN_MASK 0x0000f000 125 #define MC_SHARED_CHREMAP 0x2008 126 127 #define MC_VM_FB_LOCATION 0x2024 128 #define MC_VM_AGP_TOP 0x2028 129 #define MC_VM_AGP_BOT 0x202C 130 #define MC_VM_AGP_BASE 0x2030 131 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 132 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 133 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 134 135 #define MC_VM_MX_L1_TLB_CNTL 0x2064 136 #define ENABLE_L1_TLB (1 << 0) 137 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 138 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 139 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 140 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 141 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 142 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 143 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 144 145 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 146 147 #define MC_ARB_RAMCFG 0x2760 148 #define NOOFBANK_SHIFT 0 149 #define NOOFBANK_MASK 0x00000003 150 #define NOOFRANK_SHIFT 2 151 #define NOOFRANK_MASK 0x00000004 152 #define NOOFROWS_SHIFT 3 153 #define NOOFROWS_MASK 0x00000038 154 #define NOOFCOLS_SHIFT 6 155 #define NOOFCOLS_MASK 0x000000C0 156 #define CHANSIZE_SHIFT 8 157 #define CHANSIZE_MASK 0x00000100 158 #define CHANSIZE_OVERRIDE (1 << 11) 159 #define NOOFGROUPS_SHIFT 12 160 #define NOOFGROUPS_MASK 0x00001000 161 162 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 163 #define TRAIN_DONE_D0 (1 << 30) 164 #define TRAIN_DONE_D1 (1 << 31) 165 166 #define MC_SEQ_SUP_CNTL 0x28c8 167 #define RUN_MASK (1 << 0) 168 #define MC_SEQ_SUP_PGM 0x28cc 169 170 #define MC_IO_PAD_CNTL_D0 0x29d0 171 #define MEM_FALL_OUT_CMD (1 << 8) 172 173 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 174 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 175 176 #define HDP_HOST_PATH_CNTL 0x2C00 177 #define HDP_NONSURFACE_BASE 0x2C04 178 #define HDP_NONSURFACE_INFO 0x2C08 179 #define HDP_NONSURFACE_SIZE 0x2C0C 180 181 #define HDP_ADDR_CONFIG 0x2F48 182 #define HDP_MISC_CNTL 0x2F4C 183 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 184 185 #define IH_RB_CNTL 0x3e00 186 # define IH_RB_ENABLE (1 << 0) 187 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 188 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 189 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 190 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 191 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 192 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 193 #define IH_RB_BASE 0x3e04 194 #define IH_RB_RPTR 0x3e08 195 #define IH_RB_WPTR 0x3e0c 196 # define RB_OVERFLOW (1 << 0) 197 # define WPTR_OFFSET_MASK 0x3fffc 198 #define IH_RB_WPTR_ADDR_HI 0x3e10 199 #define IH_RB_WPTR_ADDR_LO 0x3e14 200 #define IH_CNTL 0x3e18 201 # define ENABLE_INTR (1 << 0) 202 # define IH_MC_SWAP(x) ((x) << 1) 203 # define IH_MC_SWAP_NONE 0 204 # define IH_MC_SWAP_16BIT 1 205 # define IH_MC_SWAP_32BIT 2 206 # define IH_MC_SWAP_64BIT 3 207 # define RPTR_REARM (1 << 4) 208 # define MC_WRREQ_CREDIT(x) ((x) << 15) 209 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 210 # define MC_VMID(x) ((x) << 25) 211 212 #define CONFIG_MEMSIZE 0x5428 213 214 #define INTERRUPT_CNTL 0x5468 215 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 216 # define IH_DUMMY_RD_EN (1 << 1) 217 # define IH_REQ_NONSNOOP_EN (1 << 3) 218 # define GEN_IH_INT_EN (1 << 8) 219 #define INTERRUPT_CNTL2 0x546c 220 221 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 222 223 #define BIF_FB_EN 0x5490 224 #define FB_READ_EN (1 << 0) 225 #define FB_WRITE_EN (1 << 1) 226 227 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 228 229 #define DC_LB_MEMORY_SPLIT 0x6b0c 230 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 231 232 #define PRIORITY_A_CNT 0x6b18 233 #define PRIORITY_MARK_MASK 0x7fff 234 #define PRIORITY_OFF (1 << 16) 235 #define PRIORITY_ALWAYS_ON (1 << 20) 236 #define PRIORITY_B_CNT 0x6b1c 237 238 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 239 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 240 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 241 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 242 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 243 244 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 245 #define VLINE_STATUS 0x6bb8 246 # define VLINE_OCCURRED (1 << 0) 247 # define VLINE_ACK (1 << 4) 248 # define VLINE_STAT (1 << 12) 249 # define VLINE_INTERRUPT (1 << 16) 250 # define VLINE_INTERRUPT_TYPE (1 << 17) 251 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 252 #define VBLANK_STATUS 0x6bbc 253 # define VBLANK_OCCURRED (1 << 0) 254 # define VBLANK_ACK (1 << 4) 255 # define VBLANK_STAT (1 << 12) 256 # define VBLANK_INTERRUPT (1 << 16) 257 # define VBLANK_INTERRUPT_TYPE (1 << 17) 258 259 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 260 #define INT_MASK 0x6b40 261 # define VBLANK_INT_MASK (1 << 0) 262 # define VLINE_INT_MASK (1 << 4) 263 264 #define DISP_INTERRUPT_STATUS 0x60f4 265 # define LB_D1_VLINE_INTERRUPT (1 << 2) 266 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 267 # define DC_HPD1_INTERRUPT (1 << 17) 268 # define DC_HPD1_RX_INTERRUPT (1 << 18) 269 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 270 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 271 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 272 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 273 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 274 # define LB_D2_VLINE_INTERRUPT (1 << 2) 275 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 276 # define DC_HPD2_INTERRUPT (1 << 17) 277 # define DC_HPD2_RX_INTERRUPT (1 << 18) 278 # define DISP_TIMER_INTERRUPT (1 << 24) 279 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 280 # define LB_D3_VLINE_INTERRUPT (1 << 2) 281 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 282 # define DC_HPD3_INTERRUPT (1 << 17) 283 # define DC_HPD3_RX_INTERRUPT (1 << 18) 284 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 285 # define LB_D4_VLINE_INTERRUPT (1 << 2) 286 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 287 # define DC_HPD4_INTERRUPT (1 << 17) 288 # define DC_HPD4_RX_INTERRUPT (1 << 18) 289 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 290 # define LB_D5_VLINE_INTERRUPT (1 << 2) 291 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 292 # define DC_HPD5_INTERRUPT (1 << 17) 293 # define DC_HPD5_RX_INTERRUPT (1 << 18) 294 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 295 # define LB_D6_VLINE_INTERRUPT (1 << 2) 296 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 297 # define DC_HPD6_INTERRUPT (1 << 17) 298 # define DC_HPD6_RX_INTERRUPT (1 << 18) 299 300 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 301 #define GRPH_INT_STATUS 0x6858 302 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 303 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 304 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 305 #define GRPH_INT_CONTROL 0x685c 306 # define GRPH_PFLIP_INT_MASK (1 << 0) 307 # define GRPH_PFLIP_INT_TYPE (1 << 8) 308 309 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 310 311 #define DC_HPD1_INT_STATUS 0x601c 312 #define DC_HPD2_INT_STATUS 0x6028 313 #define DC_HPD3_INT_STATUS 0x6034 314 #define DC_HPD4_INT_STATUS 0x6040 315 #define DC_HPD5_INT_STATUS 0x604c 316 #define DC_HPD6_INT_STATUS 0x6058 317 # define DC_HPDx_INT_STATUS (1 << 0) 318 # define DC_HPDx_SENSE (1 << 1) 319 # define DC_HPDx_RX_INT_STATUS (1 << 8) 320 321 #define DC_HPD1_INT_CONTROL 0x6020 322 #define DC_HPD2_INT_CONTROL 0x602c 323 #define DC_HPD3_INT_CONTROL 0x6038 324 #define DC_HPD4_INT_CONTROL 0x6044 325 #define DC_HPD5_INT_CONTROL 0x6050 326 #define DC_HPD6_INT_CONTROL 0x605c 327 # define DC_HPDx_INT_ACK (1 << 0) 328 # define DC_HPDx_INT_POLARITY (1 << 8) 329 # define DC_HPDx_INT_EN (1 << 16) 330 # define DC_HPDx_RX_INT_ACK (1 << 20) 331 # define DC_HPDx_RX_INT_EN (1 << 24) 332 333 #define DC_HPD1_CONTROL 0x6024 334 #define DC_HPD2_CONTROL 0x6030 335 #define DC_HPD3_CONTROL 0x603c 336 #define DC_HPD4_CONTROL 0x6048 337 #define DC_HPD5_CONTROL 0x6054 338 #define DC_HPD6_CONTROL 0x6060 339 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 340 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 341 # define DC_HPDx_EN (1 << 28) 342 343 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 344 #define CRTC_STATUS_FRAME_COUNT 0x6e98 345 346 #define GRBM_CNTL 0x8000 347 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 348 349 #define GRBM_STATUS2 0x8008 350 #define RLC_RQ_PENDING (1 << 0) 351 #define RLC_BUSY (1 << 8) 352 #define TC_BUSY (1 << 9) 353 354 #define GRBM_STATUS 0x8010 355 #define CMDFIFO_AVAIL_MASK 0x0000000F 356 #define RING2_RQ_PENDING (1 << 4) 357 #define SRBM_RQ_PENDING (1 << 5) 358 #define RING1_RQ_PENDING (1 << 6) 359 #define CF_RQ_PENDING (1 << 7) 360 #define PF_RQ_PENDING (1 << 8) 361 #define GDS_DMA_RQ_PENDING (1 << 9) 362 #define GRBM_EE_BUSY (1 << 10) 363 #define DB_CLEAN (1 << 12) 364 #define CB_CLEAN (1 << 13) 365 #define TA_BUSY (1 << 14) 366 #define GDS_BUSY (1 << 15) 367 #define VGT_BUSY (1 << 17) 368 #define IA_BUSY_NO_DMA (1 << 18) 369 #define IA_BUSY (1 << 19) 370 #define SX_BUSY (1 << 20) 371 #define SPI_BUSY (1 << 22) 372 #define BCI_BUSY (1 << 23) 373 #define SC_BUSY (1 << 24) 374 #define PA_BUSY (1 << 25) 375 #define DB_BUSY (1 << 26) 376 #define CP_COHERENCY_BUSY (1 << 28) 377 #define CP_BUSY (1 << 29) 378 #define CB_BUSY (1 << 30) 379 #define GUI_ACTIVE (1 << 31) 380 #define GRBM_STATUS_SE0 0x8014 381 #define GRBM_STATUS_SE1 0x8018 382 #define SE_DB_CLEAN (1 << 1) 383 #define SE_CB_CLEAN (1 << 2) 384 #define SE_BCI_BUSY (1 << 22) 385 #define SE_VGT_BUSY (1 << 23) 386 #define SE_PA_BUSY (1 << 24) 387 #define SE_TA_BUSY (1 << 25) 388 #define SE_SX_BUSY (1 << 26) 389 #define SE_SPI_BUSY (1 << 27) 390 #define SE_SC_BUSY (1 << 29) 391 #define SE_DB_BUSY (1 << 30) 392 #define SE_CB_BUSY (1 << 31) 393 394 #define GRBM_SOFT_RESET 0x8020 395 #define SOFT_RESET_CP (1 << 0) 396 #define SOFT_RESET_CB (1 << 1) 397 #define SOFT_RESET_RLC (1 << 2) 398 #define SOFT_RESET_DB (1 << 3) 399 #define SOFT_RESET_GDS (1 << 4) 400 #define SOFT_RESET_PA (1 << 5) 401 #define SOFT_RESET_SC (1 << 6) 402 #define SOFT_RESET_BCI (1 << 7) 403 #define SOFT_RESET_SPI (1 << 8) 404 #define SOFT_RESET_SX (1 << 10) 405 #define SOFT_RESET_TC (1 << 11) 406 #define SOFT_RESET_TA (1 << 12) 407 #define SOFT_RESET_VGT (1 << 14) 408 #define SOFT_RESET_IA (1 << 15) 409 410 #define GRBM_GFX_INDEX 0x802C 411 412 #define GRBM_INT_CNTL 0x8060 413 # define RDERR_INT_ENABLE (1 << 0) 414 # define GUI_IDLE_INT_ENABLE (1 << 19) 415 416 #define SCRATCH_REG0 0x8500 417 #define SCRATCH_REG1 0x8504 418 #define SCRATCH_REG2 0x8508 419 #define SCRATCH_REG3 0x850C 420 #define SCRATCH_REG4 0x8510 421 #define SCRATCH_REG5 0x8514 422 #define SCRATCH_REG6 0x8518 423 #define SCRATCH_REG7 0x851C 424 425 #define SCRATCH_UMSK 0x8540 426 #define SCRATCH_ADDR 0x8544 427 428 #define CP_SEM_WAIT_TIMER 0x85BC 429 430 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 431 432 #define CP_ME_CNTL 0x86D8 433 #define CP_CE_HALT (1 << 24) 434 #define CP_PFP_HALT (1 << 26) 435 #define CP_ME_HALT (1 << 28) 436 437 #define CP_COHER_CNTL2 0x85E8 438 439 #define CP_RB2_RPTR 0x86f8 440 #define CP_RB1_RPTR 0x86fc 441 #define CP_RB0_RPTR 0x8700 442 #define CP_RB_WPTR_DELAY 0x8704 443 444 #define CP_QUEUE_THRESHOLDS 0x8760 445 #define ROQ_IB1_START(x) ((x) << 0) 446 #define ROQ_IB2_START(x) ((x) << 8) 447 #define CP_MEQ_THRESHOLDS 0x8764 448 #define MEQ1_START(x) ((x) << 0) 449 #define MEQ2_START(x) ((x) << 8) 450 451 #define CP_PERFMON_CNTL 0x87FC 452 453 #define VGT_VTX_VECT_EJECT_REG 0x88B0 454 455 #define VGT_CACHE_INVALIDATION 0x88C4 456 #define CACHE_INVALIDATION(x) ((x) << 0) 457 #define VC_ONLY 0 458 #define TC_ONLY 1 459 #define VC_AND_TC 2 460 #define AUTO_INVLD_EN(x) ((x) << 6) 461 #define NO_AUTO 0 462 #define ES_AUTO 1 463 #define GS_AUTO 2 464 #define ES_AND_GS_AUTO 3 465 #define VGT_ESGS_RING_SIZE 0x88C8 466 #define VGT_GSVS_RING_SIZE 0x88CC 467 468 #define VGT_GS_VERTEX_REUSE 0x88D4 469 470 #define VGT_PRIMITIVE_TYPE 0x8958 471 #define VGT_INDEX_TYPE 0x895C 472 473 #define VGT_NUM_INDICES 0x8970 474 #define VGT_NUM_INSTANCES 0x8974 475 476 #define VGT_TF_RING_SIZE 0x8988 477 478 #define VGT_HS_OFFCHIP_PARAM 0x89B0 479 480 #define VGT_TF_MEMORY_BASE 0x89B8 481 482 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 483 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 484 485 #define PA_CL_ENHANCE 0x8A14 486 #define CLIP_VTX_REORDER_ENA (1 << 0) 487 #define NUM_CLIP_SEQ(x) ((x) << 1) 488 489 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 490 491 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 492 493 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 494 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 495 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 496 497 #define PA_SC_FIFO_SIZE 0x8BCC 498 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 499 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 500 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 501 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 502 503 #define PA_SC_ENHANCE 0x8BF0 504 505 #define SQ_CONFIG 0x8C00 506 507 #define SQC_CACHES 0x8C08 508 509 #define SX_DEBUG_1 0x9060 510 511 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 512 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 513 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 514 #define SPI_PS_MAX_WAVE_ID 0x90EC 515 516 #define SPI_CONFIG_CNTL 0x9100 517 518 #define SPI_CONFIG_CNTL_1 0x913C 519 #define VTX_DONE_DELAY(x) ((x) << 0) 520 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 521 522 #define CGTS_TCC_DISABLE 0x9148 523 #define CGTS_USER_TCC_DISABLE 0x914C 524 #define TCC_DISABLE_MASK 0xFFFF0000 525 #define TCC_DISABLE_SHIFT 16 526 527 #define TA_CNTL_AUX 0x9508 528 529 #define CC_RB_BACKEND_DISABLE 0x98F4 530 #define BACKEND_DISABLE(x) ((x) << 16) 531 #define GB_ADDR_CONFIG 0x98F8 532 #define NUM_PIPES(x) ((x) << 0) 533 #define NUM_PIPES_MASK 0x00000007 534 #define NUM_PIPES_SHIFT 0 535 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 536 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 537 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 538 #define NUM_SHADER_ENGINES(x) ((x) << 12) 539 #define NUM_SHADER_ENGINES_MASK 0x00003000 540 #define NUM_SHADER_ENGINES_SHIFT 12 541 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 542 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 543 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 544 #define NUM_GPUS(x) ((x) << 20) 545 #define NUM_GPUS_MASK 0x00700000 546 #define NUM_GPUS_SHIFT 20 547 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 548 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 549 #define MULTI_GPU_TILE_SIZE_SHIFT 24 550 #define ROW_SIZE(x) ((x) << 28) 551 #define ROW_SIZE_MASK 0x30000000 552 #define ROW_SIZE_SHIFT 28 553 554 #define GB_TILE_MODE0 0x9910 555 # define MICRO_TILE_MODE(x) ((x) << 0) 556 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 557 # define ADDR_SURF_THIN_MICRO_TILING 1 558 # define ADDR_SURF_DEPTH_MICRO_TILING 2 559 # define ARRAY_MODE(x) ((x) << 2) 560 # define ARRAY_LINEAR_GENERAL 0 561 # define ARRAY_LINEAR_ALIGNED 1 562 # define ARRAY_1D_TILED_THIN1 2 563 # define ARRAY_2D_TILED_THIN1 4 564 # define PIPE_CONFIG(x) ((x) << 6) 565 # define ADDR_SURF_P2 0 566 # define ADDR_SURF_P4_8x16 4 567 # define ADDR_SURF_P4_16x16 5 568 # define ADDR_SURF_P4_16x32 6 569 # define ADDR_SURF_P4_32x32 7 570 # define ADDR_SURF_P8_16x16_8x16 8 571 # define ADDR_SURF_P8_16x32_8x16 9 572 # define ADDR_SURF_P8_32x32_8x16 10 573 # define ADDR_SURF_P8_16x32_16x16 11 574 # define ADDR_SURF_P8_32x32_16x16 12 575 # define ADDR_SURF_P8_32x32_16x32 13 576 # define ADDR_SURF_P8_32x64_32x32 14 577 # define TILE_SPLIT(x) ((x) << 11) 578 # define ADDR_SURF_TILE_SPLIT_64B 0 579 # define ADDR_SURF_TILE_SPLIT_128B 1 580 # define ADDR_SURF_TILE_SPLIT_256B 2 581 # define ADDR_SURF_TILE_SPLIT_512B 3 582 # define ADDR_SURF_TILE_SPLIT_1KB 4 583 # define ADDR_SURF_TILE_SPLIT_2KB 5 584 # define ADDR_SURF_TILE_SPLIT_4KB 6 585 # define BANK_WIDTH(x) ((x) << 14) 586 # define ADDR_SURF_BANK_WIDTH_1 0 587 # define ADDR_SURF_BANK_WIDTH_2 1 588 # define ADDR_SURF_BANK_WIDTH_4 2 589 # define ADDR_SURF_BANK_WIDTH_8 3 590 # define BANK_HEIGHT(x) ((x) << 16) 591 # define ADDR_SURF_BANK_HEIGHT_1 0 592 # define ADDR_SURF_BANK_HEIGHT_2 1 593 # define ADDR_SURF_BANK_HEIGHT_4 2 594 # define ADDR_SURF_BANK_HEIGHT_8 3 595 # define MACRO_TILE_ASPECT(x) ((x) << 18) 596 # define ADDR_SURF_MACRO_ASPECT_1 0 597 # define ADDR_SURF_MACRO_ASPECT_2 1 598 # define ADDR_SURF_MACRO_ASPECT_4 2 599 # define ADDR_SURF_MACRO_ASPECT_8 3 600 # define NUM_BANKS(x) ((x) << 20) 601 # define ADDR_SURF_2_BANK 0 602 # define ADDR_SURF_4_BANK 1 603 # define ADDR_SURF_8_BANK 2 604 # define ADDR_SURF_16_BANK 3 605 606 #define CB_PERFCOUNTER0_SELECT0 0x9a20 607 #define CB_PERFCOUNTER0_SELECT1 0x9a24 608 #define CB_PERFCOUNTER1_SELECT0 0x9a28 609 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 610 #define CB_PERFCOUNTER2_SELECT0 0x9a30 611 #define CB_PERFCOUNTER2_SELECT1 0x9a34 612 #define CB_PERFCOUNTER3_SELECT0 0x9a38 613 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 614 615 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 616 #define BACKEND_DISABLE_MASK 0x00FF0000 617 #define BACKEND_DISABLE_SHIFT 16 618 619 #define TCP_CHAN_STEER_LO 0xac0c 620 #define TCP_CHAN_STEER_HI 0xac10 621 622 #define CP_RB0_BASE 0xC100 623 #define CP_RB0_CNTL 0xC104 624 #define RB_BUFSZ(x) ((x) << 0) 625 #define RB_BLKSZ(x) ((x) << 8) 626 #define BUF_SWAP_32BIT (2 << 16) 627 #define RB_NO_UPDATE (1 << 27) 628 #define RB_RPTR_WR_ENA (1 << 31) 629 630 #define CP_RB0_RPTR_ADDR 0xC10C 631 #define CP_RB0_RPTR_ADDR_HI 0xC110 632 #define CP_RB0_WPTR 0xC114 633 634 #define CP_PFP_UCODE_ADDR 0xC150 635 #define CP_PFP_UCODE_DATA 0xC154 636 #define CP_ME_RAM_RADDR 0xC158 637 #define CP_ME_RAM_WADDR 0xC15C 638 #define CP_ME_RAM_DATA 0xC160 639 640 #define CP_CE_UCODE_ADDR 0xC168 641 #define CP_CE_UCODE_DATA 0xC16C 642 643 #define CP_RB1_BASE 0xC180 644 #define CP_RB1_CNTL 0xC184 645 #define CP_RB1_RPTR_ADDR 0xC188 646 #define CP_RB1_RPTR_ADDR_HI 0xC18C 647 #define CP_RB1_WPTR 0xC190 648 #define CP_RB2_BASE 0xC194 649 #define CP_RB2_CNTL 0xC198 650 #define CP_RB2_RPTR_ADDR 0xC19C 651 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 652 #define CP_RB2_WPTR 0xC1A4 653 #define CP_INT_CNTL_RING0 0xC1A8 654 #define CP_INT_CNTL_RING1 0xC1AC 655 #define CP_INT_CNTL_RING2 0xC1B0 656 # define CNTX_BUSY_INT_ENABLE (1 << 19) 657 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 658 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 659 # define TIME_STAMP_INT_ENABLE (1 << 26) 660 # define CP_RINGID2_INT_ENABLE (1 << 29) 661 # define CP_RINGID1_INT_ENABLE (1 << 30) 662 # define CP_RINGID0_INT_ENABLE (1 << 31) 663 #define CP_INT_STATUS_RING0 0xC1B4 664 #define CP_INT_STATUS_RING1 0xC1B8 665 #define CP_INT_STATUS_RING2 0xC1BC 666 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 667 # define TIME_STAMP_INT_STAT (1 << 26) 668 # define CP_RINGID2_INT_STAT (1 << 29) 669 # define CP_RINGID1_INT_STAT (1 << 30) 670 # define CP_RINGID0_INT_STAT (1 << 31) 671 672 #define CP_DEBUG 0xC1FC 673 674 #define RLC_CNTL 0xC300 675 # define RLC_ENABLE (1 << 0) 676 #define RLC_RL_BASE 0xC304 677 #define RLC_RL_SIZE 0xC308 678 #define RLC_LB_CNTL 0xC30C 679 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 680 #define RLC_LB_CNTR_MAX 0xC314 681 #define RLC_LB_CNTR_INIT 0xC318 682 683 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 684 685 #define RLC_UCODE_ADDR 0xC32C 686 #define RLC_UCODE_DATA 0xC330 687 688 #define RLC_MC_CNTL 0xC344 689 #define RLC_UCODE_CNTL 0xC348 690 691 #define VGT_EVENT_INITIATOR 0x28a90 692 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 693 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 694 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 695 # define CACHE_FLUSH_TS (4 << 0) 696 # define CACHE_FLUSH (6 << 0) 697 # define CS_PARTIAL_FLUSH (7 << 0) 698 # define VGT_STREAMOUT_RESET (10 << 0) 699 # define END_OF_PIPE_INCR_DE (11 << 0) 700 # define END_OF_PIPE_IB_END (12 << 0) 701 # define RST_PIX_CNT (13 << 0) 702 # define VS_PARTIAL_FLUSH (15 << 0) 703 # define PS_PARTIAL_FLUSH (16 << 0) 704 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 705 # define ZPASS_DONE (21 << 0) 706 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 707 # define PERFCOUNTER_START (23 << 0) 708 # define PERFCOUNTER_STOP (24 << 0) 709 # define PIPELINESTAT_START (25 << 0) 710 # define PIPELINESTAT_STOP (26 << 0) 711 # define PERFCOUNTER_SAMPLE (27 << 0) 712 # define SAMPLE_PIPELINESTAT (30 << 0) 713 # define SAMPLE_STREAMOUTSTATS (32 << 0) 714 # define RESET_VTX_CNT (33 << 0) 715 # define VGT_FLUSH (36 << 0) 716 # define BOTTOM_OF_PIPE_TS (40 << 0) 717 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 718 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 719 # define FLUSH_AND_INV_DB_META (44 << 0) 720 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 721 # define FLUSH_AND_INV_CB_META (46 << 0) 722 # define CS_DONE (47 << 0) 723 # define PS_DONE (48 << 0) 724 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 725 # define THREAD_TRACE_START (51 << 0) 726 # define THREAD_TRACE_STOP (52 << 0) 727 # define THREAD_TRACE_FLUSH (54 << 0) 728 # define THREAD_TRACE_FINISH (55 << 0) 729 730 /* 731 * PM4 732 */ 733 #define PACKET_TYPE0 0 734 #define PACKET_TYPE1 1 735 #define PACKET_TYPE2 2 736 #define PACKET_TYPE3 3 737 738 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 739 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 740 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 741 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 742 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 743 (((reg) >> 2) & 0xFFFF) | \ 744 ((n) & 0x3FFF) << 16) 745 #define CP_PACKET2 0x80000000 746 #define PACKET2_PAD_SHIFT 0 747 #define PACKET2_PAD_MASK (0x3fffffff << 0) 748 749 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 750 751 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 752 (((op) & 0xFF) << 8) | \ 753 ((n) & 0x3FFF) << 16) 754 755 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 756 757 /* Packet 3 types */ 758 #define PACKET3_NOP 0x10 759 #define PACKET3_SET_BASE 0x11 760 #define PACKET3_BASE_INDEX(x) ((x) << 0) 761 #define GDS_PARTITION_BASE 2 762 #define CE_PARTITION_BASE 3 763 #define PACKET3_CLEAR_STATE 0x12 764 #define PACKET3_INDEX_BUFFER_SIZE 0x13 765 #define PACKET3_DISPATCH_DIRECT 0x15 766 #define PACKET3_DISPATCH_INDIRECT 0x16 767 #define PACKET3_ALLOC_GDS 0x1B 768 #define PACKET3_WRITE_GDS_RAM 0x1C 769 #define PACKET3_ATOMIC_GDS 0x1D 770 #define PACKET3_ATOMIC 0x1E 771 #define PACKET3_OCCLUSION_QUERY 0x1F 772 #define PACKET3_SET_PREDICATION 0x20 773 #define PACKET3_REG_RMW 0x21 774 #define PACKET3_COND_EXEC 0x22 775 #define PACKET3_PRED_EXEC 0x23 776 #define PACKET3_DRAW_INDIRECT 0x24 777 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 778 #define PACKET3_INDEX_BASE 0x26 779 #define PACKET3_DRAW_INDEX_2 0x27 780 #define PACKET3_CONTEXT_CONTROL 0x28 781 #define PACKET3_INDEX_TYPE 0x2A 782 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 783 #define PACKET3_DRAW_INDEX_AUTO 0x2D 784 #define PACKET3_DRAW_INDEX_IMMD 0x2E 785 #define PACKET3_NUM_INSTANCES 0x2F 786 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 787 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 788 #define PACKET3_INDIRECT_BUFFER 0x32 789 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 790 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 791 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 792 #define PACKET3_WRITE_DATA 0x37 793 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 794 #define PACKET3_MEM_SEMAPHORE 0x39 795 #define PACKET3_MPEG_INDEX 0x3A 796 #define PACKET3_COPY_DW 0x3B 797 #define PACKET3_WAIT_REG_MEM 0x3C 798 #define PACKET3_MEM_WRITE 0x3D 799 #define PACKET3_COPY_DATA 0x40 800 #define PACKET3_PFP_SYNC_ME 0x42 801 #define PACKET3_SURFACE_SYNC 0x43 802 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 803 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 804 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 805 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 806 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 807 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 808 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 809 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 810 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 811 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 812 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 813 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 814 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 815 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 816 # define PACKET3_TC_ACTION_ENA (1 << 23) 817 # define PACKET3_CB_ACTION_ENA (1 << 25) 818 # define PACKET3_DB_ACTION_ENA (1 << 26) 819 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 820 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 821 #define PACKET3_ME_INITIALIZE 0x44 822 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 823 #define PACKET3_COND_WRITE 0x45 824 #define PACKET3_EVENT_WRITE 0x46 825 #define EVENT_TYPE(x) ((x) << 0) 826 #define EVENT_INDEX(x) ((x) << 8) 827 /* 0 - any non-TS event 828 * 1 - ZPASS_DONE 829 * 2 - SAMPLE_PIPELINESTAT 830 * 3 - SAMPLE_STREAMOUTSTAT* 831 * 4 - *S_PARTIAL_FLUSH 832 * 5 - EOP events 833 * 6 - EOS events 834 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 835 */ 836 #define INV_L2 (1 << 20) 837 /* INV TC L2 cache when EVENT_INDEX = 7 */ 838 #define PACKET3_EVENT_WRITE_EOP 0x47 839 #define DATA_SEL(x) ((x) << 29) 840 /* 0 - discard 841 * 1 - send low 32bit data 842 * 2 - send 64bit data 843 * 3 - send 64bit counter value 844 */ 845 #define INT_SEL(x) ((x) << 24) 846 /* 0 - none 847 * 1 - interrupt only (DATA_SEL = 0) 848 * 2 - interrupt when data write is confirmed 849 */ 850 #define PACKET3_EVENT_WRITE_EOS 0x48 851 #define PACKET3_PREAMBLE_CNTL 0x4A 852 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 853 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 854 #define PACKET3_ONE_REG_WRITE 0x57 855 #define PACKET3_LOAD_CONFIG_REG 0x5F 856 #define PACKET3_LOAD_CONTEXT_REG 0x60 857 #define PACKET3_LOAD_SH_REG 0x61 858 #define PACKET3_SET_CONFIG_REG 0x68 859 #define PACKET3_SET_CONFIG_REG_START 0x00008000 860 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 861 #define PACKET3_SET_CONTEXT_REG 0x69 862 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 863 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 864 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 865 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 866 #define PACKET3_SET_SH_REG 0x76 867 #define PACKET3_SET_SH_REG_START 0x0000b000 868 #define PACKET3_SET_SH_REG_END 0x0000c000 869 #define PACKET3_SET_SH_REG_OFFSET 0x77 870 #define PACKET3_ME_WRITE 0x7A 871 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 872 #define PACKET3_SCRATCH_RAM_READ 0x7E 873 #define PACKET3_CE_WRITE 0x7F 874 #define PACKET3_LOAD_CONST_RAM 0x80 875 #define PACKET3_WRITE_CONST_RAM 0x81 876 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 877 #define PACKET3_DUMP_CONST_RAM 0x83 878 #define PACKET3_INCREMENT_CE_COUNTER 0x84 879 #define PACKET3_INCREMENT_DE_COUNTER 0x85 880 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 881 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 882 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 883 #define PACKET3_SET_CE_DE_COUNTERS 0x89 884 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 885 886 #endif 887