xref: /openbmc/linux/drivers/gpu/drm/radeon/si_smc.c (revision fee4b700) 
1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 
25 #include <linux/firmware.h>
26 #include "drmP.h"
27 #include "radeon.h"
28 #include "sid.h"
29 #include "ppsmc.h"
30 #include "radeon_ucode.h"
31 
32 int si_set_smc_sram_address(struct radeon_device *rdev,
33 			    u32 smc_address, u32 limit)
34 {
35 	if (smc_address & 3)
36 		return -EINVAL;
37 	if ((smc_address + 3) > limit)
38 		return -EINVAL;
39 
40 	WREG32(SMC_IND_INDEX_0, smc_address);
41 	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
42 
43 	return 0;
44 }
45 
46 int si_copy_bytes_to_smc(struct radeon_device *rdev,
47 			 u32 smc_start_address,
48 			 const u8 *src, u32 byte_count, u32 limit)
49 {
50 	int ret;
51 	u32 data, original_data, addr, extra_shift;
52 
53 	if (smc_start_address & 3)
54 		return -EINVAL;
55 	if ((smc_start_address + byte_count) > limit)
56 		return -EINVAL;
57 
58 	addr = smc_start_address;
59 
60 	while (byte_count >= 4) {
61 		/* SMC address space is BE */
62 		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
63 
64 		ret = si_set_smc_sram_address(rdev, addr, limit);
65 		if (ret)
66 			return ret;
67 
68 		WREG32(SMC_IND_DATA_0, data);
69 
70 		src += 4;
71 		byte_count -= 4;
72 		addr += 4;
73 	}
74 
75 	/* RMW for the final bytes */
76 	if (byte_count > 0) {
77 		data = 0;
78 
79 		ret = si_set_smc_sram_address(rdev, addr, limit);
80 		if (ret)
81 			return ret;
82 
83 		original_data = RREG32(SMC_IND_DATA_0);
84 
85 		extra_shift = 8 * (4 - byte_count);
86 
87 		while (byte_count > 0) {
88 			/* SMC address space is BE */
89 			data = (data << 8) + *src++;
90 			byte_count--;
91 		}
92 
93 		data <<= extra_shift;
94 
95 		data |= (original_data & ~((~0UL) << extra_shift));
96 
97 		ret = si_set_smc_sram_address(rdev, addr, limit);
98 		if (ret)
99 			return ret;
100 
101 		WREG32(SMC_IND_DATA_0, data);
102 	}
103 	return 0;
104 }
105 
106 void si_start_smc(struct radeon_device *rdev)
107 {
108 	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
109 
110 	tmp &= ~RST_REG;
111 
112 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
113 }
114 
115 void si_reset_smc(struct radeon_device *rdev)
116 {
117 	u32 tmp;
118 
119 	RREG32(CB_CGTT_SCLK_CTRL);
120 	RREG32(CB_CGTT_SCLK_CTRL);
121 	RREG32(CB_CGTT_SCLK_CTRL);
122 	RREG32(CB_CGTT_SCLK_CTRL);
123 
124 	tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
125 	tmp |= RST_REG;
126 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
127 }
128 
129 int si_program_jump_on_start(struct radeon_device *rdev)
130 {
131 	static u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
132 
133 	return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
134 }
135 
136 void si_stop_smc_clock(struct radeon_device *rdev)
137 {
138 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
139 
140 	tmp |= CK_DISABLE;
141 
142 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
143 }
144 
145 void si_start_smc_clock(struct radeon_device *rdev)
146 {
147 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
148 
149 	tmp &= ~CK_DISABLE;
150 
151 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
152 }
153 
154 bool si_is_smc_running(struct radeon_device *rdev)
155 {
156 	u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
157 	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
158 
159 	if (!(rst & RST_REG) && !(clk & CK_DISABLE))
160 		return true;
161 
162 	return false;
163 }
164 
165 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
166 {
167 	u32 tmp;
168 	int i;
169 
170 	if (!si_is_smc_running(rdev))
171 		return PPSMC_Result_Failed;
172 
173 	WREG32(SMC_MESSAGE_0, msg);
174 
175 	for (i = 0; i < rdev->usec_timeout; i++) {
176 		tmp = RREG32(SMC_RESP_0);
177 		if (tmp != 0)
178 			break;
179 		udelay(1);
180 	}
181 	tmp = RREG32(SMC_RESP_0);
182 
183 	return (PPSMC_Result)tmp;
184 }
185 
186 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
187 {
188 	u32 tmp;
189 	int i;
190 
191 	if (!si_is_smc_running(rdev))
192 		return PPSMC_Result_OK;
193 
194 	for (i = 0; i < rdev->usec_timeout; i++) {
195 		tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
196 		if ((tmp & CKEN) == 0)
197 			break;
198 		udelay(1);
199 	}
200 
201 	return PPSMC_Result_OK;
202 }
203 
204 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
205 {
206 	u32 ucode_start_address;
207 	u32 ucode_size;
208 	const u8 *src;
209 	u32 data;
210 
211 	if (!rdev->smc_fw)
212 		return -EINVAL;
213 
214 	switch (rdev->family) {
215 	case CHIP_TAHITI:
216 		ucode_start_address = TAHITI_SMC_UCODE_START;
217 		ucode_size = TAHITI_SMC_UCODE_SIZE;
218 		break;
219 	case CHIP_PITCAIRN:
220 		ucode_start_address = PITCAIRN_SMC_UCODE_START;
221 		ucode_size = PITCAIRN_SMC_UCODE_SIZE;
222 		break;
223 	case CHIP_VERDE:
224 		ucode_start_address = VERDE_SMC_UCODE_START;
225 		ucode_size = VERDE_SMC_UCODE_SIZE;
226 		break;
227 	case CHIP_OLAND:
228 		ucode_start_address = OLAND_SMC_UCODE_START;
229 		ucode_size = OLAND_SMC_UCODE_SIZE;
230 		break;
231 	case CHIP_HAINAN:
232 		ucode_start_address = HAINAN_SMC_UCODE_START;
233 		ucode_size = HAINAN_SMC_UCODE_SIZE;
234 		break;
235 	default:
236 		DRM_ERROR("unknown asic in smc ucode loader\n");
237 		BUG();
238 	}
239 
240 	if (ucode_size & 3)
241 		return -EINVAL;
242 
243 	src = (const u8 *)rdev->smc_fw->data;
244 	WREG32(SMC_IND_INDEX_0, ucode_start_address);
245 	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
246 	while (ucode_size >= 4) {
247 		/* SMC address space is BE */
248 		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
249 
250 		WREG32(SMC_IND_DATA_0, data);
251 
252 		src += 4;
253 		ucode_size -= 4;
254 	}
255 	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
256 
257 	return 0;
258 }
259 
260 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
261 			   u32 *value, u32 limit)
262 {
263 	int ret;
264 
265 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
266 	if (ret)
267 		return ret;
268 
269 	*value = RREG32(SMC_IND_DATA_0);
270 	return 0;
271 }
272 
273 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
274 			    u32 value, u32 limit)
275 {
276 	int ret;
277 
278 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
279 	if (ret)
280 		return ret;
281 
282 	WREG32(SMC_IND_DATA_0, value);
283 	return 0;
284 }
285