1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "drmP.h" 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 static const struct si_dte_data dte_data_tahiti_le = 255 { 256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 258 0x5, 259 0xAFC8, 260 0x64, 261 0x32, 262 1, 263 0, 264 0x10, 265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 268 85, 269 true 270 }; 271 272 static const struct si_dte_data dte_data_tahiti_pro = 273 { 274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 275 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 276 5, 277 45000, 278 100, 279 0xA, 280 1, 281 0, 282 0x10, 283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 286 90, 287 true 288 }; 289 290 static const struct si_dte_data dte_data_new_zealand = 291 { 292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 294 0x5, 295 0xAFC8, 296 0x69, 297 0x32, 298 1, 299 0, 300 0x10, 301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 304 85, 305 true 306 }; 307 308 static const struct si_dte_data dte_data_aruba_pro = 309 { 310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 311 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 312 5, 313 45000, 314 100, 315 0xA, 316 1, 317 0, 318 0x10, 319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 322 90, 323 true 324 }; 325 326 static const struct si_dte_data dte_data_malta = 327 { 328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 329 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 330 5, 331 45000, 332 100, 333 0xA, 334 1, 335 0, 336 0x10, 337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 340 90, 341 true 342 }; 343 344 struct si_cac_config_reg cac_weights_pitcairn[] = 345 { 346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 406 { 0xFFFFFFFF } 407 }; 408 409 static const struct si_cac_config_reg lcac_pitcairn[] = 410 { 411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0xFFFFFFFF } 498 }; 499 500 static const struct si_cac_config_reg cac_override_pitcairn[] = 501 { 502 { 0xFFFFFFFF } 503 }; 504 505 static const struct si_powertune_data powertune_data_pitcairn = 506 { 507 ((1 << 16) | 27027), 508 5, 509 0, 510 6, 511 100, 512 { 513 51600000UL, 514 1800000UL, 515 7194395UL, 516 309631529UL, 517 -1270850L, 518 4513710L, 519 100 520 }, 521 117830498UL, 522 12, 523 { 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0 532 }, 533 true 534 }; 535 536 static const struct si_dte_data dte_data_pitcairn = 537 { 538 { 0, 0, 0, 0, 0 }, 539 { 0, 0, 0, 0, 0 }, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 0, 551 false 552 }; 553 554 static const struct si_dte_data dte_data_curacao_xt = 555 { 556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 557 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 558 5, 559 45000, 560 100, 561 0xA, 562 1, 563 0, 564 0x10, 565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 568 90, 569 true 570 }; 571 572 static const struct si_dte_data dte_data_curacao_pro = 573 { 574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 575 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 576 5, 577 45000, 578 100, 579 0xA, 580 1, 581 0, 582 0x10, 583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 586 90, 587 true 588 }; 589 590 static const struct si_dte_data dte_data_neptune_xt = 591 { 592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 593 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 594 5, 595 45000, 596 100, 597 0xA, 598 1, 599 0, 600 0x10, 601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 604 90, 605 true 606 }; 607 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 609 { 610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 670 { 0xFFFFFFFF } 671 }; 672 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 674 { 675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 735 { 0xFFFFFFFF } 736 }; 737 738 static const struct si_cac_config_reg cac_weights_heathrow[] = 739 { 740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 800 { 0xFFFFFFFF } 801 }; 802 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 804 { 805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 865 { 0xFFFFFFFF } 866 }; 867 868 static const struct si_cac_config_reg cac_weights_cape_verde[] = 869 { 870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 930 { 0xFFFFFFFF } 931 }; 932 933 static const struct si_cac_config_reg lcac_cape_verde[] = 934 { 935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0xFFFFFFFF } 990 }; 991 992 static const struct si_cac_config_reg cac_override_cape_verde[] = 993 { 994 { 0xFFFFFFFF } 995 }; 996 997 static const struct si_powertune_data powertune_data_cape_verde = 998 { 999 ((1 << 16) | 0x6993), 1000 5, 1001 0, 1002 7, 1003 105, 1004 { 1005 0UL, 1006 0UL, 1007 7194395UL, 1008 309631529UL, 1009 -1270850L, 1010 4513710L, 1011 100 1012 }, 1013 117830498UL, 1014 12, 1015 { 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0 1024 }, 1025 true 1026 }; 1027 1028 static const struct si_dte_data dte_data_cape_verde = 1029 { 1030 { 0, 0, 0, 0, 0 }, 1031 { 0, 0, 0, 0, 0 }, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 0, 1043 false 1044 }; 1045 1046 static const struct si_dte_data dte_data_venus_xtx = 1047 { 1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1050 5, 1051 55000, 1052 0x69, 1053 0xA, 1054 1, 1055 0, 1056 0x3, 1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 90, 1061 true 1062 }; 1063 1064 static const struct si_dte_data dte_data_venus_xt = 1065 { 1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1068 5, 1069 55000, 1070 0x69, 1071 0xA, 1072 1, 1073 0, 1074 0x3, 1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 90, 1079 true 1080 }; 1081 1082 static const struct si_dte_data dte_data_venus_pro = 1083 { 1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1086 5, 1087 55000, 1088 0x69, 1089 0xA, 1090 1, 1091 0, 1092 0x3, 1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 90, 1097 true 1098 }; 1099 1100 struct si_cac_config_reg cac_weights_oland[] = 1101 { 1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1162 { 0xFFFFFFFF } 1163 }; 1164 1165 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1166 { 1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1227 { 0xFFFFFFFF } 1228 }; 1229 1230 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1231 { 1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1292 { 0xFFFFFFFF } 1293 }; 1294 1295 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1296 { 1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1357 { 0xFFFFFFFF } 1358 }; 1359 1360 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1361 { 1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1422 { 0xFFFFFFFF } 1423 }; 1424 1425 static const struct si_cac_config_reg lcac_oland[] = 1426 { 1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0xFFFFFFFF } 1470 }; 1471 1472 static const struct si_cac_config_reg lcac_mars_pro[] = 1473 { 1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0xFFFFFFFF } 1517 }; 1518 1519 static const struct si_cac_config_reg cac_override_oland[] = 1520 { 1521 { 0xFFFFFFFF } 1522 }; 1523 1524 static const struct si_powertune_data powertune_data_oland = 1525 { 1526 ((1 << 16) | 0x6993), 1527 5, 1528 0, 1529 7, 1530 105, 1531 { 1532 0UL, 1533 0UL, 1534 7194395UL, 1535 309631529UL, 1536 -1270850L, 1537 4513710L, 1538 100 1539 }, 1540 117830498UL, 1541 12, 1542 { 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0 1551 }, 1552 true 1553 }; 1554 1555 static const struct si_powertune_data powertune_data_mars_pro = 1556 { 1557 ((1 << 16) | 0x6993), 1558 5, 1559 0, 1560 7, 1561 105, 1562 { 1563 0UL, 1564 0UL, 1565 7194395UL, 1566 309631529UL, 1567 -1270850L, 1568 4513710L, 1569 100 1570 }, 1571 117830498UL, 1572 12, 1573 { 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0 1582 }, 1583 true 1584 }; 1585 1586 static const struct si_dte_data dte_data_oland = 1587 { 1588 { 0, 0, 0, 0, 0 }, 1589 { 0, 0, 0, 0, 0 }, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 0, 1601 false 1602 }; 1603 1604 static const struct si_dte_data dte_data_mars_pro = 1605 { 1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1607 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1608 5, 1609 55000, 1610 105, 1611 0xA, 1612 1, 1613 0, 1614 0x10, 1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1618 90, 1619 true 1620 }; 1621 1622 static const struct si_dte_data dte_data_sun_xt = 1623 { 1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1625 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1626 5, 1627 55000, 1628 105, 1629 0xA, 1630 1, 1631 0, 1632 0x10, 1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1636 90, 1637 true 1638 }; 1639 1640 1641 static const struct si_cac_config_reg cac_weights_hainan[] = 1642 { 1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1703 { 0xFFFFFFFF } 1704 }; 1705 1706 static const struct si_powertune_data powertune_data_hainan = 1707 { 1708 ((1 << 16) | 0x6993), 1709 5, 1710 0, 1711 9, 1712 105, 1713 { 1714 0UL, 1715 0UL, 1716 7194395UL, 1717 309631529UL, 1718 -1270850L, 1719 4513710L, 1720 100 1721 }, 1722 117830498UL, 1723 12, 1724 { 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0 1733 }, 1734 true 1735 }; 1736 1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1741 1742 extern int si_mc_load_microcode(struct radeon_device *rdev); 1743 1744 static int si_populate_voltage_value(struct radeon_device *rdev, 1745 const struct atom_voltage_table *table, 1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1747 static int si_get_std_voltage_value(struct radeon_device *rdev, 1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1749 u16 *std_voltage); 1750 static int si_write_smc_soft_register(struct radeon_device *rdev, 1751 u16 reg_offset, u32 value); 1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1753 struct rv7xx_pl *pl, 1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1755 static int si_calculate_sclk_params(struct radeon_device *rdev, 1756 u32 engine_clock, 1757 SISLANDS_SMC_SCLK_VALUE *sclk); 1758 1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1760 { 1761 struct si_power_info *pi = rdev->pm.dpm.priv; 1762 1763 return pi; 1764 } 1765 1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1767 u16 v, s32 t, u32 ileakage, u32 *leakage) 1768 { 1769 s64 kt, kv, leakage_w, i_leakage, vddc; 1770 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1771 s64 tmp; 1772 1773 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1774 vddc = div64_s64(drm_int2fixp(v), 1000); 1775 temperature = div64_s64(drm_int2fixp(t), 1000); 1776 1777 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1778 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1779 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1780 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1781 t_ref = drm_int2fixp(coeff->t_ref); 1782 1783 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1784 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1785 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1786 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1787 1788 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1789 1790 *leakage = drm_fixp2int(leakage_w * 1000); 1791 } 1792 1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1794 const struct ni_leakage_coeffients *coeff, 1795 u16 v, 1796 s32 t, 1797 u32 i_leakage, 1798 u32 *leakage) 1799 { 1800 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1801 } 1802 1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1804 const u32 fixed_kt, u16 v, 1805 u32 ileakage, u32 *leakage) 1806 { 1807 s64 kt, kv, leakage_w, i_leakage, vddc; 1808 1809 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1810 vddc = div64_s64(drm_int2fixp(v), 1000); 1811 1812 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1813 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1814 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1815 1816 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1817 1818 *leakage = drm_fixp2int(leakage_w * 1000); 1819 } 1820 1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1822 const struct ni_leakage_coeffients *coeff, 1823 const u32 fixed_kt, 1824 u16 v, 1825 u32 i_leakage, 1826 u32 *leakage) 1827 { 1828 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1829 } 1830 1831 1832 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1833 struct si_dte_data *dte_data) 1834 { 1835 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1836 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1837 u32 k = dte_data->k; 1838 u32 t_max = dte_data->max_t; 1839 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1840 u32 t_0 = dte_data->t0; 1841 u32 i; 1842 1843 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1844 dte_data->tdep_count = 3; 1845 1846 for (i = 0; i < k; i++) { 1847 dte_data->r[i] = 1848 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1849 (p_limit2 * (u32)100); 1850 } 1851 1852 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1853 1854 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1855 dte_data->tdep_r[i] = dte_data->r[4]; 1856 } 1857 } else { 1858 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1859 } 1860 } 1861 1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1863 { 1864 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1865 struct si_power_info *si_pi = si_get_pi(rdev); 1866 bool update_dte_from_pl2 = false; 1867 1868 if (rdev->family == CHIP_TAHITI) { 1869 si_pi->cac_weights = cac_weights_tahiti; 1870 si_pi->lcac_config = lcac_tahiti; 1871 si_pi->cac_override = cac_override_tahiti; 1872 si_pi->powertune_data = &powertune_data_tahiti; 1873 si_pi->dte_data = dte_data_tahiti; 1874 1875 switch (rdev->pdev->device) { 1876 case 0x6798: 1877 si_pi->dte_data.enable_dte_by_default = true; 1878 break; 1879 case 0x6799: 1880 si_pi->dte_data = dte_data_new_zealand; 1881 break; 1882 case 0x6790: 1883 case 0x6791: 1884 case 0x6792: 1885 case 0x679E: 1886 si_pi->dte_data = dte_data_aruba_pro; 1887 update_dte_from_pl2 = true; 1888 break; 1889 case 0x679B: 1890 si_pi->dte_data = dte_data_malta; 1891 update_dte_from_pl2 = true; 1892 break; 1893 case 0x679A: 1894 si_pi->dte_data = dte_data_tahiti_pro; 1895 update_dte_from_pl2 = true; 1896 break; 1897 default: 1898 if (si_pi->dte_data.enable_dte_by_default == true) 1899 DRM_ERROR("DTE is not enabled!\n"); 1900 break; 1901 } 1902 } else if (rdev->family == CHIP_PITCAIRN) { 1903 switch (rdev->pdev->device) { 1904 case 0x6810: 1905 case 0x6818: 1906 si_pi->cac_weights = cac_weights_pitcairn; 1907 si_pi->lcac_config = lcac_pitcairn; 1908 si_pi->cac_override = cac_override_pitcairn; 1909 si_pi->powertune_data = &powertune_data_pitcairn; 1910 si_pi->dte_data = dte_data_curacao_xt; 1911 update_dte_from_pl2 = true; 1912 break; 1913 case 0x6819: 1914 case 0x6811: 1915 si_pi->cac_weights = cac_weights_pitcairn; 1916 si_pi->lcac_config = lcac_pitcairn; 1917 si_pi->cac_override = cac_override_pitcairn; 1918 si_pi->powertune_data = &powertune_data_pitcairn; 1919 si_pi->dte_data = dte_data_curacao_pro; 1920 update_dte_from_pl2 = true; 1921 break; 1922 case 0x6800: 1923 case 0x6806: 1924 si_pi->cac_weights = cac_weights_pitcairn; 1925 si_pi->lcac_config = lcac_pitcairn; 1926 si_pi->cac_override = cac_override_pitcairn; 1927 si_pi->powertune_data = &powertune_data_pitcairn; 1928 si_pi->dte_data = dte_data_neptune_xt; 1929 update_dte_from_pl2 = true; 1930 break; 1931 default: 1932 si_pi->cac_weights = cac_weights_pitcairn; 1933 si_pi->lcac_config = lcac_pitcairn; 1934 si_pi->cac_override = cac_override_pitcairn; 1935 si_pi->powertune_data = &powertune_data_pitcairn; 1936 si_pi->dte_data = dte_data_pitcairn; 1937 break; 1938 } 1939 } else if (rdev->family == CHIP_VERDE) { 1940 si_pi->lcac_config = lcac_cape_verde; 1941 si_pi->cac_override = cac_override_cape_verde; 1942 si_pi->powertune_data = &powertune_data_cape_verde; 1943 1944 switch (rdev->pdev->device) { 1945 case 0x683B: 1946 case 0x683F: 1947 case 0x6829: 1948 case 0x6835: 1949 si_pi->cac_weights = cac_weights_cape_verde_pro; 1950 si_pi->dte_data = dte_data_cape_verde; 1951 break; 1952 case 0x682C: 1953 si_pi->cac_weights = cac_weights_cape_verde_pro; 1954 si_pi->dte_data = dte_data_sun_xt; 1955 break; 1956 case 0x6825: 1957 case 0x6827: 1958 si_pi->cac_weights = cac_weights_heathrow; 1959 si_pi->dte_data = dte_data_cape_verde; 1960 break; 1961 case 0x6824: 1962 case 0x682D: 1963 si_pi->cac_weights = cac_weights_chelsea_xt; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x682F: 1967 si_pi->cac_weights = cac_weights_chelsea_pro; 1968 si_pi->dte_data = dte_data_cape_verde; 1969 break; 1970 case 0x6820: 1971 si_pi->cac_weights = cac_weights_heathrow; 1972 si_pi->dte_data = dte_data_venus_xtx; 1973 break; 1974 case 0x6821: 1975 si_pi->cac_weights = cac_weights_heathrow; 1976 si_pi->dte_data = dte_data_venus_xt; 1977 break; 1978 case 0x6823: 1979 case 0x682B: 1980 case 0x6822: 1981 case 0x682A: 1982 si_pi->cac_weights = cac_weights_chelsea_pro; 1983 si_pi->dte_data = dte_data_venus_pro; 1984 break; 1985 default: 1986 si_pi->cac_weights = cac_weights_cape_verde; 1987 si_pi->dte_data = dte_data_cape_verde; 1988 break; 1989 } 1990 } else if (rdev->family == CHIP_OLAND) { 1991 switch (rdev->pdev->device) { 1992 case 0x6601: 1993 case 0x6621: 1994 case 0x6603: 1995 case 0x6605: 1996 si_pi->cac_weights = cac_weights_mars_pro; 1997 si_pi->lcac_config = lcac_mars_pro; 1998 si_pi->cac_override = cac_override_oland; 1999 si_pi->powertune_data = &powertune_data_mars_pro; 2000 si_pi->dte_data = dte_data_mars_pro; 2001 update_dte_from_pl2 = true; 2002 break; 2003 case 0x6600: 2004 case 0x6606: 2005 case 0x6620: 2006 case 0x6604: 2007 si_pi->cac_weights = cac_weights_mars_xt; 2008 si_pi->lcac_config = lcac_mars_pro; 2009 si_pi->cac_override = cac_override_oland; 2010 si_pi->powertune_data = &powertune_data_mars_pro; 2011 si_pi->dte_data = dte_data_mars_pro; 2012 update_dte_from_pl2 = true; 2013 break; 2014 case 0x6611: 2015 case 0x6613: 2016 case 0x6608: 2017 si_pi->cac_weights = cac_weights_oland_pro; 2018 si_pi->lcac_config = lcac_mars_pro; 2019 si_pi->cac_override = cac_override_oland; 2020 si_pi->powertune_data = &powertune_data_mars_pro; 2021 si_pi->dte_data = dte_data_mars_pro; 2022 update_dte_from_pl2 = true; 2023 break; 2024 case 0x6610: 2025 si_pi->cac_weights = cac_weights_oland_xt; 2026 si_pi->lcac_config = lcac_mars_pro; 2027 si_pi->cac_override = cac_override_oland; 2028 si_pi->powertune_data = &powertune_data_mars_pro; 2029 si_pi->dte_data = dte_data_mars_pro; 2030 update_dte_from_pl2 = true; 2031 break; 2032 default: 2033 si_pi->cac_weights = cac_weights_oland; 2034 si_pi->lcac_config = lcac_oland; 2035 si_pi->cac_override = cac_override_oland; 2036 si_pi->powertune_data = &powertune_data_oland; 2037 si_pi->dte_data = dte_data_oland; 2038 break; 2039 } 2040 } else if (rdev->family == CHIP_HAINAN) { 2041 si_pi->cac_weights = cac_weights_hainan; 2042 si_pi->lcac_config = lcac_oland; 2043 si_pi->cac_override = cac_override_oland; 2044 si_pi->powertune_data = &powertune_data_hainan; 2045 si_pi->dte_data = dte_data_sun_xt; 2046 update_dte_from_pl2 = true; 2047 } else { 2048 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2049 return; 2050 } 2051 2052 ni_pi->enable_power_containment = false; 2053 ni_pi->enable_cac = false; 2054 ni_pi->enable_sq_ramping = false; 2055 si_pi->enable_dte = false; 2056 2057 if (si_pi->powertune_data->enable_powertune_by_default) { 2058 ni_pi->enable_power_containment= true; 2059 ni_pi->enable_cac = true; 2060 if (si_pi->dte_data.enable_dte_by_default) { 2061 si_pi->enable_dte = true; 2062 if (update_dte_from_pl2) 2063 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2064 2065 } 2066 ni_pi->enable_sq_ramping = true; 2067 } 2068 2069 ni_pi->driver_calculate_cac_leakage = true; 2070 ni_pi->cac_configuration_required = true; 2071 2072 if (ni_pi->cac_configuration_required) { 2073 ni_pi->support_cac_long_term_average = true; 2074 si_pi->dyn_powertune_data.l2_lta_window_size = 2075 si_pi->powertune_data->l2_lta_window_size_default; 2076 si_pi->dyn_powertune_data.lts_truncate = 2077 si_pi->powertune_data->lts_truncate_default; 2078 } else { 2079 ni_pi->support_cac_long_term_average = false; 2080 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2081 si_pi->dyn_powertune_data.lts_truncate = 0; 2082 } 2083 2084 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2085 } 2086 2087 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2088 { 2089 return 1; 2090 } 2091 2092 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2093 { 2094 u32 xclk; 2095 u32 wintime; 2096 u32 cac_window; 2097 u32 cac_window_size; 2098 2099 xclk = radeon_get_xclk(rdev); 2100 2101 if (xclk == 0) 2102 return 0; 2103 2104 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2105 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2106 2107 wintime = (cac_window_size * 100) / xclk; 2108 2109 return wintime; 2110 } 2111 2112 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2113 { 2114 return power_in_watts; 2115 } 2116 2117 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2118 bool adjust_polarity, 2119 u32 tdp_adjustment, 2120 u32 *tdp_limit, 2121 u32 *near_tdp_limit) 2122 { 2123 u32 adjustment_delta, max_tdp_limit; 2124 2125 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2126 return -EINVAL; 2127 2128 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2129 2130 if (adjust_polarity) { 2131 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2132 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2133 } else { 2134 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2135 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2136 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2138 else 2139 *near_tdp_limit = 0; 2140 } 2141 2142 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2143 return -EINVAL; 2144 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2145 return -EINVAL; 2146 2147 return 0; 2148 } 2149 2150 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2151 struct radeon_ps *radeon_state) 2152 { 2153 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2154 struct si_power_info *si_pi = si_get_pi(rdev); 2155 2156 if (ni_pi->enable_power_containment) { 2157 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2158 PP_SIslands_PAPMParameters *papm_parm; 2159 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2160 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2161 u32 tdp_limit; 2162 u32 near_tdp_limit; 2163 int ret; 2164 2165 if (scaling_factor == 0) 2166 return -EINVAL; 2167 2168 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2169 2170 ret = si_calculate_adjusted_tdp_limits(rdev, 2171 false, /* ??? */ 2172 rdev->pm.dpm.tdp_adjustment, 2173 &tdp_limit, 2174 &near_tdp_limit); 2175 if (ret) 2176 return ret; 2177 2178 smc_table->dpm2Params.TDPLimit = 2179 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2180 smc_table->dpm2Params.NearTDPLimit = 2181 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2182 smc_table->dpm2Params.SafePowerLimit = 2183 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2184 2185 ret = si_copy_bytes_to_smc(rdev, 2186 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2187 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2188 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2189 sizeof(u32) * 3, 2190 si_pi->sram_end); 2191 if (ret) 2192 return ret; 2193 2194 if (si_pi->enable_ppm) { 2195 papm_parm = &si_pi->papm_parm; 2196 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2197 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2198 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2199 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2200 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2201 papm_parm->PlatformPowerLimit = 0xffffffff; 2202 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2203 2204 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2205 (u8 *)papm_parm, 2206 sizeof(PP_SIslands_PAPMParameters), 2207 si_pi->sram_end); 2208 if (ret) 2209 return ret; 2210 } 2211 } 2212 return 0; 2213 } 2214 2215 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2216 struct radeon_ps *radeon_state) 2217 { 2218 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2219 struct si_power_info *si_pi = si_get_pi(rdev); 2220 2221 if (ni_pi->enable_power_containment) { 2222 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2223 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2224 int ret; 2225 2226 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2227 2228 smc_table->dpm2Params.NearTDPLimit = 2229 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2230 smc_table->dpm2Params.SafePowerLimit = 2231 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2232 2233 ret = si_copy_bytes_to_smc(rdev, 2234 (si_pi->state_table_start + 2235 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2236 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2237 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2238 sizeof(u32) * 2, 2239 si_pi->sram_end); 2240 if (ret) 2241 return ret; 2242 } 2243 2244 return 0; 2245 } 2246 2247 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2248 const u16 prev_std_vddc, 2249 const u16 curr_std_vddc) 2250 { 2251 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2252 u64 prev_vddc = (u64)prev_std_vddc; 2253 u64 curr_vddc = (u64)curr_std_vddc; 2254 u64 pwr_efficiency_ratio, n, d; 2255 2256 if ((prev_vddc == 0) || (curr_vddc == 0)) 2257 return 0; 2258 2259 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2260 d = prev_vddc * prev_vddc; 2261 pwr_efficiency_ratio = div64_u64(n, d); 2262 2263 if (pwr_efficiency_ratio > (u64)0xFFFF) 2264 return 0; 2265 2266 return (u16)pwr_efficiency_ratio; 2267 } 2268 2269 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2270 struct radeon_ps *radeon_state) 2271 { 2272 struct si_power_info *si_pi = si_get_pi(rdev); 2273 2274 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2275 radeon_state->vclk && radeon_state->dclk) 2276 return true; 2277 2278 return false; 2279 } 2280 2281 static int si_populate_power_containment_values(struct radeon_device *rdev, 2282 struct radeon_ps *radeon_state, 2283 SISLANDS_SMC_SWSTATE *smc_state) 2284 { 2285 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2286 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2287 struct ni_ps *state = ni_get_ps(radeon_state); 2288 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2289 u32 prev_sclk; 2290 u32 max_sclk; 2291 u32 min_sclk; 2292 u16 prev_std_vddc; 2293 u16 curr_std_vddc; 2294 int i; 2295 u16 pwr_efficiency_ratio; 2296 u8 max_ps_percent; 2297 bool disable_uvd_power_tune; 2298 int ret; 2299 2300 if (ni_pi->enable_power_containment == false) 2301 return 0; 2302 2303 if (state->performance_level_count == 0) 2304 return -EINVAL; 2305 2306 if (smc_state->levelCount != state->performance_level_count) 2307 return -EINVAL; 2308 2309 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2310 2311 smc_state->levels[0].dpm2.MaxPS = 0; 2312 smc_state->levels[0].dpm2.NearTDPDec = 0; 2313 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2314 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2315 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2316 2317 for (i = 1; i < state->performance_level_count; i++) { 2318 prev_sclk = state->performance_levels[i-1].sclk; 2319 max_sclk = state->performance_levels[i].sclk; 2320 if (i == 1) 2321 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2322 else 2323 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2324 2325 if (prev_sclk > max_sclk) 2326 return -EINVAL; 2327 2328 if ((max_ps_percent == 0) || 2329 (prev_sclk == max_sclk) || 2330 disable_uvd_power_tune) { 2331 min_sclk = max_sclk; 2332 } else if (i == 1) { 2333 min_sclk = prev_sclk; 2334 } else { 2335 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2336 } 2337 2338 if (min_sclk < state->performance_levels[0].sclk) 2339 min_sclk = state->performance_levels[0].sclk; 2340 2341 if (min_sclk == 0) 2342 return -EINVAL; 2343 2344 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2345 state->performance_levels[i-1].vddc, &vddc); 2346 if (ret) 2347 return ret; 2348 2349 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2350 if (ret) 2351 return ret; 2352 2353 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2354 state->performance_levels[i].vddc, &vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2359 if (ret) 2360 return ret; 2361 2362 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2363 prev_std_vddc, curr_std_vddc); 2364 2365 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2366 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2367 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2368 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2369 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2370 } 2371 2372 return 0; 2373 } 2374 2375 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2376 struct radeon_ps *radeon_state, 2377 SISLANDS_SMC_SWSTATE *smc_state) 2378 { 2379 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2380 struct ni_ps *state = ni_get_ps(radeon_state); 2381 u32 sq_power_throttle, sq_power_throttle2; 2382 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2383 int i; 2384 2385 if (state->performance_level_count == 0) 2386 return -EINVAL; 2387 2388 if (smc_state->levelCount != state->performance_level_count) 2389 return -EINVAL; 2390 2391 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2392 return -EINVAL; 2393 2394 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2395 enable_sq_ramping = false; 2396 2397 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2398 enable_sq_ramping = false; 2399 2400 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2401 enable_sq_ramping = false; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 for (i = 0; i < state->performance_level_count; i++) { 2410 sq_power_throttle = 0; 2411 sq_power_throttle2 = 0; 2412 2413 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2414 enable_sq_ramping) { 2415 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2416 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2417 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2418 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2419 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2420 } else { 2421 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2422 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2423 } 2424 2425 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2426 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2427 } 2428 2429 return 0; 2430 } 2431 2432 static int si_enable_power_containment(struct radeon_device *rdev, 2433 struct radeon_ps *radeon_new_state, 2434 bool enable) 2435 { 2436 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2437 PPSMC_Result smc_result; 2438 int ret = 0; 2439 2440 if (ni_pi->enable_power_containment) { 2441 if (enable) { 2442 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2443 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2444 if (smc_result != PPSMC_Result_OK) { 2445 ret = -EINVAL; 2446 ni_pi->pc_enabled = false; 2447 } else { 2448 ni_pi->pc_enabled = true; 2449 } 2450 } 2451 } else { 2452 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2453 if (smc_result != PPSMC_Result_OK) 2454 ret = -EINVAL; 2455 ni_pi->pc_enabled = false; 2456 } 2457 } 2458 2459 return ret; 2460 } 2461 2462 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2463 { 2464 struct si_power_info *si_pi = si_get_pi(rdev); 2465 int ret = 0; 2466 struct si_dte_data *dte_data = &si_pi->dte_data; 2467 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2468 u32 table_size; 2469 u8 tdep_count; 2470 u32 i; 2471 2472 if (dte_data == NULL) 2473 si_pi->enable_dte = false; 2474 2475 if (si_pi->enable_dte == false) 2476 return 0; 2477 2478 if (dte_data->k <= 0) 2479 return -EINVAL; 2480 2481 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2482 if (dte_tables == NULL) { 2483 si_pi->enable_dte = false; 2484 return -ENOMEM; 2485 } 2486 2487 table_size = dte_data->k; 2488 2489 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2490 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2491 2492 tdep_count = dte_data->tdep_count; 2493 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2494 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2495 2496 dte_tables->K = cpu_to_be32(table_size); 2497 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2498 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2499 dte_tables->WindowSize = dte_data->window_size; 2500 dte_tables->temp_select = dte_data->temp_select; 2501 dte_tables->DTE_mode = dte_data->dte_mode; 2502 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2503 2504 if (tdep_count > 0) 2505 table_size--; 2506 2507 for (i = 0; i < table_size; i++) { 2508 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2509 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2510 } 2511 2512 dte_tables->Tdep_count = tdep_count; 2513 2514 for (i = 0; i < (u32)tdep_count; i++) { 2515 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2516 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2517 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2518 } 2519 2520 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2521 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2522 kfree(dte_tables); 2523 2524 return ret; 2525 } 2526 2527 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2528 u16 *max, u16 *min) 2529 { 2530 struct si_power_info *si_pi = si_get_pi(rdev); 2531 struct radeon_cac_leakage_table *table = 2532 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2533 u32 i; 2534 u32 v0_loadline; 2535 2536 2537 if (table == NULL) 2538 return -EINVAL; 2539 2540 *max = 0; 2541 *min = 0xFFFF; 2542 2543 for (i = 0; i < table->count; i++) { 2544 if (table->entries[i].vddc > *max) 2545 *max = table->entries[i].vddc; 2546 if (table->entries[i].vddc < *min) 2547 *min = table->entries[i].vddc; 2548 } 2549 2550 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2551 return -EINVAL; 2552 2553 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2554 2555 if (v0_loadline > 0xFFFFUL) 2556 return -EINVAL; 2557 2558 *min = (u16)v0_loadline; 2559 2560 if ((*min > *max) || (*max == 0) || (*min == 0)) 2561 return -EINVAL; 2562 2563 return 0; 2564 } 2565 2566 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2567 { 2568 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2569 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2570 } 2571 2572 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2573 PP_SIslands_CacConfig *cac_tables, 2574 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2575 u16 t0, u16 t_step) 2576 { 2577 struct si_power_info *si_pi = si_get_pi(rdev); 2578 u32 leakage; 2579 unsigned int i, j; 2580 s32 t; 2581 u32 smc_leakage; 2582 u32 scaling_factor; 2583 u16 voltage; 2584 2585 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2586 2587 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2588 t = (1000 * (i * t_step + t0)); 2589 2590 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2591 voltage = vddc_max - (vddc_step * j); 2592 2593 si_calculate_leakage_for_v_and_t(rdev, 2594 &si_pi->powertune_data->leakage_coefficients, 2595 voltage, 2596 t, 2597 si_pi->dyn_powertune_data.cac_leakage, 2598 &leakage); 2599 2600 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2601 2602 if (smc_leakage > 0xFFFF) 2603 smc_leakage = 0xFFFF; 2604 2605 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2606 cpu_to_be16((u16)smc_leakage); 2607 } 2608 } 2609 return 0; 2610 } 2611 2612 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2613 PP_SIslands_CacConfig *cac_tables, 2614 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2615 { 2616 struct si_power_info *si_pi = si_get_pi(rdev); 2617 u32 leakage; 2618 unsigned int i, j; 2619 u32 smc_leakage; 2620 u32 scaling_factor; 2621 u16 voltage; 2622 2623 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2624 2625 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2626 voltage = vddc_max - (vddc_step * j); 2627 2628 si_calculate_leakage_for_v(rdev, 2629 &si_pi->powertune_data->leakage_coefficients, 2630 si_pi->powertune_data->fixed_kt, 2631 voltage, 2632 si_pi->dyn_powertune_data.cac_leakage, 2633 &leakage); 2634 2635 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2636 2637 if (smc_leakage > 0xFFFF) 2638 smc_leakage = 0xFFFF; 2639 2640 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2641 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2642 cpu_to_be16((u16)smc_leakage); 2643 } 2644 return 0; 2645 } 2646 2647 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2648 { 2649 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2650 struct si_power_info *si_pi = si_get_pi(rdev); 2651 PP_SIslands_CacConfig *cac_tables = NULL; 2652 u16 vddc_max, vddc_min, vddc_step; 2653 u16 t0, t_step; 2654 u32 load_line_slope, reg; 2655 int ret = 0; 2656 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2657 2658 if (ni_pi->enable_cac == false) 2659 return 0; 2660 2661 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2662 if (!cac_tables) 2663 return -ENOMEM; 2664 2665 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2666 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2667 WREG32(CG_CAC_CTRL, reg); 2668 2669 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2670 si_pi->dyn_powertune_data.dc_pwr_value = 2671 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2672 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2673 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2674 2675 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2676 2677 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2678 if (ret) 2679 goto done_free; 2680 2681 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2682 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2683 t_step = 4; 2684 t0 = 60; 2685 2686 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2687 ret = si_init_dte_leakage_table(rdev, cac_tables, 2688 vddc_max, vddc_min, vddc_step, 2689 t0, t_step); 2690 else 2691 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2692 vddc_max, vddc_min, vddc_step); 2693 if (ret) 2694 goto done_free; 2695 2696 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2697 2698 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2699 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2700 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2701 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2702 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2703 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2704 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2705 cac_tables->calculation_repeats = cpu_to_be32(2); 2706 cac_tables->dc_cac = cpu_to_be32(0); 2707 cac_tables->log2_PG_LKG_SCALE = 12; 2708 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2709 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2710 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2711 2712 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2713 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2714 2715 if (ret) 2716 goto done_free; 2717 2718 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2719 2720 done_free: 2721 if (ret) { 2722 ni_pi->enable_cac = false; 2723 ni_pi->enable_power_containment = false; 2724 } 2725 2726 kfree(cac_tables); 2727 2728 return 0; 2729 } 2730 2731 static int si_program_cac_config_registers(struct radeon_device *rdev, 2732 const struct si_cac_config_reg *cac_config_regs) 2733 { 2734 const struct si_cac_config_reg *config_regs = cac_config_regs; 2735 u32 data = 0, offset; 2736 2737 if (!config_regs) 2738 return -EINVAL; 2739 2740 while (config_regs->offset != 0xFFFFFFFF) { 2741 switch (config_regs->type) { 2742 case SISLANDS_CACCONFIG_CGIND: 2743 offset = SMC_CG_IND_START + config_regs->offset; 2744 if (offset < SMC_CG_IND_END) 2745 data = RREG32_SMC(offset); 2746 break; 2747 default: 2748 data = RREG32(config_regs->offset << 2); 2749 break; 2750 } 2751 2752 data &= ~config_regs->mask; 2753 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2754 2755 switch (config_regs->type) { 2756 case SISLANDS_CACCONFIG_CGIND: 2757 offset = SMC_CG_IND_START + config_regs->offset; 2758 if (offset < SMC_CG_IND_END) 2759 WREG32_SMC(offset, data); 2760 break; 2761 default: 2762 WREG32(config_regs->offset << 2, data); 2763 break; 2764 } 2765 config_regs++; 2766 } 2767 return 0; 2768 } 2769 2770 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2771 { 2772 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2773 struct si_power_info *si_pi = si_get_pi(rdev); 2774 int ret; 2775 2776 if ((ni_pi->enable_cac == false) || 2777 (ni_pi->cac_configuration_required == false)) 2778 return 0; 2779 2780 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2781 if (ret) 2782 return ret; 2783 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2784 if (ret) 2785 return ret; 2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2787 if (ret) 2788 return ret; 2789 2790 return 0; 2791 } 2792 2793 static int si_enable_smc_cac(struct radeon_device *rdev, 2794 struct radeon_ps *radeon_new_state, 2795 bool enable) 2796 { 2797 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2798 struct si_power_info *si_pi = si_get_pi(rdev); 2799 PPSMC_Result smc_result; 2800 int ret = 0; 2801 2802 if (ni_pi->enable_cac) { 2803 if (enable) { 2804 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2805 if (ni_pi->support_cac_long_term_average) { 2806 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2807 if (smc_result != PPSMC_Result_OK) 2808 ni_pi->support_cac_long_term_average = false; 2809 } 2810 2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2812 if (smc_result != PPSMC_Result_OK) { 2813 ret = -EINVAL; 2814 ni_pi->cac_enabled = false; 2815 } else { 2816 ni_pi->cac_enabled = true; 2817 } 2818 2819 if (si_pi->enable_dte) { 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2821 if (smc_result != PPSMC_Result_OK) 2822 ret = -EINVAL; 2823 } 2824 } 2825 } else if (ni_pi->cac_enabled) { 2826 if (si_pi->enable_dte) 2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2828 2829 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2830 2831 ni_pi->cac_enabled = false; 2832 2833 if (ni_pi->support_cac_long_term_average) 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2835 } 2836 } 2837 return ret; 2838 } 2839 2840 static int si_init_smc_spll_table(struct radeon_device *rdev) 2841 { 2842 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2843 struct si_power_info *si_pi = si_get_pi(rdev); 2844 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2845 SISLANDS_SMC_SCLK_VALUE sclk_params; 2846 u32 fb_div, p_div; 2847 u32 clk_s, clk_v; 2848 u32 sclk = 0; 2849 int ret = 0; 2850 u32 tmp; 2851 int i; 2852 2853 if (si_pi->spll_table_start == 0) 2854 return -EINVAL; 2855 2856 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2857 if (spll_table == NULL) 2858 return -ENOMEM; 2859 2860 for (i = 0; i < 256; i++) { 2861 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2862 if (ret) 2863 break; 2864 2865 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2866 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2867 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2868 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2869 2870 fb_div &= ~0x00001FFF; 2871 fb_div >>= 1; 2872 clk_v >>= 6; 2873 2874 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2875 ret = -EINVAL; 2876 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2877 ret = -EINVAL; 2878 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2879 ret = -EINVAL; 2880 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2881 ret = -EINVAL; 2882 2883 if (ret) 2884 break; 2885 2886 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2887 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2888 spll_table->freq[i] = cpu_to_be32(tmp); 2889 2890 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2891 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2892 spll_table->ss[i] = cpu_to_be32(tmp); 2893 2894 sclk += 512; 2895 } 2896 2897 2898 if (!ret) 2899 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2900 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2901 si_pi->sram_end); 2902 2903 if (ret) 2904 ni_pi->enable_power_containment = false; 2905 2906 kfree(spll_table); 2907 2908 return ret; 2909 } 2910 2911 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2912 struct radeon_ps *rps) 2913 { 2914 struct ni_ps *ps = ni_get_ps(rps); 2915 struct radeon_clock_and_voltage_limits *max_limits; 2916 bool disable_mclk_switching = false; 2917 bool disable_sclk_switching = false; 2918 u32 mclk, sclk; 2919 u16 vddc, vddci; 2920 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2921 int i; 2922 2923 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2924 ni_dpm_vblank_too_short(rdev)) 2925 disable_mclk_switching = true; 2926 2927 if (rps->vclk || rps->dclk) { 2928 disable_mclk_switching = true; 2929 disable_sclk_switching = true; 2930 } 2931 2932 if (rdev->pm.dpm.ac_power) 2933 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2934 else 2935 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2936 2937 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2938 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2939 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2940 } 2941 if (rdev->pm.dpm.ac_power == false) { 2942 for (i = 0; i < ps->performance_level_count; i++) { 2943 if (ps->performance_levels[i].mclk > max_limits->mclk) 2944 ps->performance_levels[i].mclk = max_limits->mclk; 2945 if (ps->performance_levels[i].sclk > max_limits->sclk) 2946 ps->performance_levels[i].sclk = max_limits->sclk; 2947 if (ps->performance_levels[i].vddc > max_limits->vddc) 2948 ps->performance_levels[i].vddc = max_limits->vddc; 2949 if (ps->performance_levels[i].vddci > max_limits->vddci) 2950 ps->performance_levels[i].vddci = max_limits->vddci; 2951 } 2952 } 2953 2954 /* limit clocks to max supported clocks based on voltage dependency tables */ 2955 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2956 &max_sclk_vddc); 2957 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2958 &max_mclk_vddci); 2959 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2960 &max_mclk_vddc); 2961 2962 for (i = 0; i < ps->performance_level_count; i++) { 2963 if (max_sclk_vddc) { 2964 if (ps->performance_levels[i].sclk > max_sclk_vddc) 2965 ps->performance_levels[i].sclk = max_sclk_vddc; 2966 } 2967 if (max_mclk_vddci) { 2968 if (ps->performance_levels[i].mclk > max_mclk_vddci) 2969 ps->performance_levels[i].mclk = max_mclk_vddci; 2970 } 2971 if (max_mclk_vddc) { 2972 if (ps->performance_levels[i].mclk > max_mclk_vddc) 2973 ps->performance_levels[i].mclk = max_mclk_vddc; 2974 } 2975 } 2976 2977 /* XXX validate the min clocks required for display */ 2978 2979 if (disable_mclk_switching) { 2980 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2981 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2982 } else { 2983 mclk = ps->performance_levels[0].mclk; 2984 vddci = ps->performance_levels[0].vddci; 2985 } 2986 2987 if (disable_sclk_switching) { 2988 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2989 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2990 } else { 2991 sclk = ps->performance_levels[0].sclk; 2992 vddc = ps->performance_levels[0].vddc; 2993 } 2994 2995 /* adjusted low state */ 2996 ps->performance_levels[0].sclk = sclk; 2997 ps->performance_levels[0].mclk = mclk; 2998 ps->performance_levels[0].vddc = vddc; 2999 ps->performance_levels[0].vddci = vddci; 3000 3001 if (disable_sclk_switching) { 3002 sclk = ps->performance_levels[0].sclk; 3003 for (i = 1; i < ps->performance_level_count; i++) { 3004 if (sclk < ps->performance_levels[i].sclk) 3005 sclk = ps->performance_levels[i].sclk; 3006 } 3007 for (i = 0; i < ps->performance_level_count; i++) { 3008 ps->performance_levels[i].sclk = sclk; 3009 ps->performance_levels[i].vddc = vddc; 3010 } 3011 } else { 3012 for (i = 1; i < ps->performance_level_count; i++) { 3013 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3014 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3015 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3016 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3017 } 3018 } 3019 3020 if (disable_mclk_switching) { 3021 mclk = ps->performance_levels[0].mclk; 3022 for (i = 1; i < ps->performance_level_count; i++) { 3023 if (mclk < ps->performance_levels[i].mclk) 3024 mclk = ps->performance_levels[i].mclk; 3025 } 3026 for (i = 0; i < ps->performance_level_count; i++) { 3027 ps->performance_levels[i].mclk = mclk; 3028 ps->performance_levels[i].vddci = vddci; 3029 } 3030 } else { 3031 for (i = 1; i < ps->performance_level_count; i++) { 3032 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3033 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3034 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3035 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3036 } 3037 } 3038 3039 for (i = 0; i < ps->performance_level_count; i++) 3040 btc_adjust_clock_combinations(rdev, max_limits, 3041 &ps->performance_levels[i]); 3042 3043 for (i = 0; i < ps->performance_level_count; i++) { 3044 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3045 ps->performance_levels[i].sclk, 3046 max_limits->vddc, &ps->performance_levels[i].vddc); 3047 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3048 ps->performance_levels[i].mclk, 3049 max_limits->vddci, &ps->performance_levels[i].vddci); 3050 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3051 ps->performance_levels[i].mclk, 3052 max_limits->vddc, &ps->performance_levels[i].vddc); 3053 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3054 rdev->clock.current_dispclk, 3055 max_limits->vddc, &ps->performance_levels[i].vddc); 3056 } 3057 3058 for (i = 0; i < ps->performance_level_count; i++) { 3059 btc_apply_voltage_delta_rules(rdev, 3060 max_limits->vddc, max_limits->vddci, 3061 &ps->performance_levels[i].vddc, 3062 &ps->performance_levels[i].vddci); 3063 } 3064 3065 ps->dc_compatible = true; 3066 for (i = 0; i < ps->performance_level_count; i++) { 3067 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3068 ps->dc_compatible = false; 3069 } 3070 3071 } 3072 3073 #if 0 3074 static int si_read_smc_soft_register(struct radeon_device *rdev, 3075 u16 reg_offset, u32 *value) 3076 { 3077 struct si_power_info *si_pi = si_get_pi(rdev); 3078 3079 return si_read_smc_sram_dword(rdev, 3080 si_pi->soft_regs_start + reg_offset, value, 3081 si_pi->sram_end); 3082 } 3083 #endif 3084 3085 static int si_write_smc_soft_register(struct radeon_device *rdev, 3086 u16 reg_offset, u32 value) 3087 { 3088 struct si_power_info *si_pi = si_get_pi(rdev); 3089 3090 return si_write_smc_sram_dword(rdev, 3091 si_pi->soft_regs_start + reg_offset, 3092 value, si_pi->sram_end); 3093 } 3094 3095 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3096 { 3097 bool ret = false; 3098 u32 tmp, width, row, column, bank, density; 3099 bool is_memory_gddr5, is_special; 3100 3101 tmp = RREG32(MC_SEQ_MISC0); 3102 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3103 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3104 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3105 3106 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3107 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3108 3109 tmp = RREG32(MC_ARB_RAMCFG); 3110 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3111 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3112 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3113 3114 density = (1 << (row + column - 20 + bank)) * width; 3115 3116 if ((rdev->pdev->device == 0x6819) && 3117 is_memory_gddr5 && is_special && (density == 0x400)) 3118 ret = true; 3119 3120 return ret; 3121 } 3122 3123 static void si_get_leakage_vddc(struct radeon_device *rdev) 3124 { 3125 struct si_power_info *si_pi = si_get_pi(rdev); 3126 u16 vddc, count = 0; 3127 int i, ret; 3128 3129 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3130 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3131 3132 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3133 si_pi->leakage_voltage.entries[count].voltage = vddc; 3134 si_pi->leakage_voltage.entries[count].leakage_index = 3135 SISLANDS_LEAKAGE_INDEX0 + i; 3136 count++; 3137 } 3138 } 3139 si_pi->leakage_voltage.count = count; 3140 } 3141 3142 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3143 u32 index, u16 *leakage_voltage) 3144 { 3145 struct si_power_info *si_pi = si_get_pi(rdev); 3146 int i; 3147 3148 if (leakage_voltage == NULL) 3149 return -EINVAL; 3150 3151 if ((index & 0xff00) != 0xff00) 3152 return -EINVAL; 3153 3154 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3155 return -EINVAL; 3156 3157 if (index < SISLANDS_LEAKAGE_INDEX0) 3158 return -EINVAL; 3159 3160 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3161 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3162 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3163 return 0; 3164 } 3165 } 3166 return -EAGAIN; 3167 } 3168 3169 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3170 { 3171 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3172 bool want_thermal_protection; 3173 enum radeon_dpm_event_src dpm_event_src; 3174 3175 switch (sources) { 3176 case 0: 3177 default: 3178 want_thermal_protection = false; 3179 break; 3180 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3181 want_thermal_protection = true; 3182 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3183 break; 3184 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3185 want_thermal_protection = true; 3186 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3187 break; 3188 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3189 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3190 want_thermal_protection = true; 3191 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3192 break; 3193 } 3194 3195 if (want_thermal_protection) { 3196 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3197 if (pi->thermal_protection) 3198 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3199 } else { 3200 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3201 } 3202 } 3203 3204 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3205 enum radeon_dpm_auto_throttle_src source, 3206 bool enable) 3207 { 3208 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3209 3210 if (enable) { 3211 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3212 pi->active_auto_throttle_sources |= 1 << source; 3213 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3214 } 3215 } else { 3216 if (pi->active_auto_throttle_sources & (1 << source)) { 3217 pi->active_auto_throttle_sources &= ~(1 << source); 3218 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3219 } 3220 } 3221 } 3222 3223 static void si_start_dpm(struct radeon_device *rdev) 3224 { 3225 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3226 } 3227 3228 static void si_stop_dpm(struct radeon_device *rdev) 3229 { 3230 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3231 } 3232 3233 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3234 { 3235 if (enable) 3236 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3237 else 3238 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3239 3240 } 3241 3242 #if 0 3243 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3244 u32 thermal_level) 3245 { 3246 PPSMC_Result ret; 3247 3248 if (thermal_level == 0) { 3249 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3250 if (ret == PPSMC_Result_OK) 3251 return 0; 3252 else 3253 return -EINVAL; 3254 } 3255 return 0; 3256 } 3257 3258 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3259 { 3260 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3261 } 3262 #endif 3263 3264 #if 0 3265 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3266 { 3267 if (ac_power) 3268 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3269 0 : -EINVAL; 3270 3271 return 0; 3272 } 3273 #endif 3274 3275 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3276 PPSMC_Msg msg, u32 parameter) 3277 { 3278 WREG32(SMC_SCRATCH0, parameter); 3279 return si_send_msg_to_smc(rdev, msg); 3280 } 3281 3282 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3283 { 3284 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3285 return -EINVAL; 3286 3287 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3288 0 : -EINVAL; 3289 } 3290 3291 int si_dpm_force_performance_level(struct radeon_device *rdev, 3292 enum radeon_dpm_forced_level level) 3293 { 3294 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3295 struct ni_ps *ps = ni_get_ps(rps); 3296 u32 levels = ps->performance_level_count; 3297 3298 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3299 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3300 return -EINVAL; 3301 3302 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3303 return -EINVAL; 3304 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3305 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3306 return -EINVAL; 3307 3308 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3309 return -EINVAL; 3310 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3311 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3312 return -EINVAL; 3313 3314 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3315 return -EINVAL; 3316 } 3317 3318 rdev->pm.dpm.forced_level = level; 3319 3320 return 0; 3321 } 3322 3323 static int si_set_boot_state(struct radeon_device *rdev) 3324 { 3325 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3326 0 : -EINVAL; 3327 } 3328 3329 static int si_set_sw_state(struct radeon_device *rdev) 3330 { 3331 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3332 0 : -EINVAL; 3333 } 3334 3335 static int si_halt_smc(struct radeon_device *rdev) 3336 { 3337 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3338 return -EINVAL; 3339 3340 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3341 0 : -EINVAL; 3342 } 3343 3344 static int si_resume_smc(struct radeon_device *rdev) 3345 { 3346 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3347 return -EINVAL; 3348 3349 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3350 0 : -EINVAL; 3351 } 3352 3353 static void si_dpm_start_smc(struct radeon_device *rdev) 3354 { 3355 si_program_jump_on_start(rdev); 3356 si_start_smc(rdev); 3357 si_start_smc_clock(rdev); 3358 } 3359 3360 static void si_dpm_stop_smc(struct radeon_device *rdev) 3361 { 3362 si_reset_smc(rdev); 3363 si_stop_smc_clock(rdev); 3364 } 3365 3366 static int si_process_firmware_header(struct radeon_device *rdev) 3367 { 3368 struct si_power_info *si_pi = si_get_pi(rdev); 3369 u32 tmp; 3370 int ret; 3371 3372 ret = si_read_smc_sram_dword(rdev, 3373 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3374 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3375 &tmp, si_pi->sram_end); 3376 if (ret) 3377 return ret; 3378 3379 si_pi->state_table_start = tmp; 3380 3381 ret = si_read_smc_sram_dword(rdev, 3382 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3383 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3384 &tmp, si_pi->sram_end); 3385 if (ret) 3386 return ret; 3387 3388 si_pi->soft_regs_start = tmp; 3389 3390 ret = si_read_smc_sram_dword(rdev, 3391 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3392 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3393 &tmp, si_pi->sram_end); 3394 if (ret) 3395 return ret; 3396 3397 si_pi->mc_reg_table_start = tmp; 3398 3399 ret = si_read_smc_sram_dword(rdev, 3400 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3401 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3402 &tmp, si_pi->sram_end); 3403 if (ret) 3404 return ret; 3405 3406 si_pi->fan_table_start = tmp; 3407 3408 ret = si_read_smc_sram_dword(rdev, 3409 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3410 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3411 &tmp, si_pi->sram_end); 3412 if (ret) 3413 return ret; 3414 3415 si_pi->arb_table_start = tmp; 3416 3417 ret = si_read_smc_sram_dword(rdev, 3418 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3419 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3420 &tmp, si_pi->sram_end); 3421 if (ret) 3422 return ret; 3423 3424 si_pi->cac_table_start = tmp; 3425 3426 ret = si_read_smc_sram_dword(rdev, 3427 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3428 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3429 &tmp, si_pi->sram_end); 3430 if (ret) 3431 return ret; 3432 3433 si_pi->dte_table_start = tmp; 3434 3435 ret = si_read_smc_sram_dword(rdev, 3436 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3437 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3438 &tmp, si_pi->sram_end); 3439 if (ret) 3440 return ret; 3441 3442 si_pi->spll_table_start = tmp; 3443 3444 ret = si_read_smc_sram_dword(rdev, 3445 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3446 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3447 &tmp, si_pi->sram_end); 3448 if (ret) 3449 return ret; 3450 3451 si_pi->papm_cfg_table_start = tmp; 3452 3453 return ret; 3454 } 3455 3456 static void si_read_clock_registers(struct radeon_device *rdev) 3457 { 3458 struct si_power_info *si_pi = si_get_pi(rdev); 3459 3460 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3461 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3462 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3463 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3464 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3465 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3466 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3467 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3468 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3469 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3470 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3471 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3472 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3473 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3474 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3475 } 3476 3477 static void si_enable_thermal_protection(struct radeon_device *rdev, 3478 bool enable) 3479 { 3480 if (enable) 3481 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3482 else 3483 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3484 } 3485 3486 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3487 { 3488 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3489 } 3490 3491 #if 0 3492 static int si_enter_ulp_state(struct radeon_device *rdev) 3493 { 3494 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3495 3496 udelay(25000); 3497 3498 return 0; 3499 } 3500 3501 static int si_exit_ulp_state(struct radeon_device *rdev) 3502 { 3503 int i; 3504 3505 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3506 3507 udelay(7000); 3508 3509 for (i = 0; i < rdev->usec_timeout; i++) { 3510 if (RREG32(SMC_RESP_0) == 1) 3511 break; 3512 udelay(1000); 3513 } 3514 3515 return 0; 3516 } 3517 #endif 3518 3519 static int si_notify_smc_display_change(struct radeon_device *rdev, 3520 bool has_display) 3521 { 3522 PPSMC_Msg msg = has_display ? 3523 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3524 3525 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3526 0 : -EINVAL; 3527 } 3528 3529 static void si_program_response_times(struct radeon_device *rdev) 3530 { 3531 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3532 u32 vddc_dly, acpi_dly, vbi_dly; 3533 u32 reference_clock; 3534 3535 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3536 3537 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3538 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3539 3540 if (voltage_response_time == 0) 3541 voltage_response_time = 1000; 3542 3543 acpi_delay_time = 15000; 3544 vbi_time_out = 100000; 3545 3546 reference_clock = radeon_get_xclk(rdev); 3547 3548 vddc_dly = (voltage_response_time * reference_clock) / 100; 3549 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3550 vbi_dly = (vbi_time_out * reference_clock) / 100; 3551 3552 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3553 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3554 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3555 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3556 } 3557 3558 static void si_program_ds_registers(struct radeon_device *rdev) 3559 { 3560 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3561 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3562 3563 if (eg_pi->sclk_deep_sleep) { 3564 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3565 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3566 ~AUTOSCALE_ON_SS_CLEAR); 3567 } 3568 } 3569 3570 static void si_program_display_gap(struct radeon_device *rdev) 3571 { 3572 u32 tmp, pipe; 3573 int i; 3574 3575 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3576 if (rdev->pm.dpm.new_active_crtc_count > 0) 3577 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3578 else 3579 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3580 3581 if (rdev->pm.dpm.new_active_crtc_count > 1) 3582 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3583 else 3584 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3585 3586 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3587 3588 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3589 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3590 3591 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3592 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3593 /* find the first active crtc */ 3594 for (i = 0; i < rdev->num_crtc; i++) { 3595 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3596 break; 3597 } 3598 if (i == rdev->num_crtc) 3599 pipe = 0; 3600 else 3601 pipe = i; 3602 3603 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3604 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3605 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3606 } 3607 3608 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3609 * This can be a problem on PowerXpress systems or if you want to use the card 3610 * for offscreen rendering or compute if there are no crtcs enabled. 3611 */ 3612 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3613 } 3614 3615 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3616 { 3617 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3618 3619 if (enable) { 3620 if (pi->sclk_ss) 3621 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3622 } else { 3623 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3624 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3625 } 3626 } 3627 3628 static void si_setup_bsp(struct radeon_device *rdev) 3629 { 3630 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3631 u32 xclk = radeon_get_xclk(rdev); 3632 3633 r600_calculate_u_and_p(pi->asi, 3634 xclk, 3635 16, 3636 &pi->bsp, 3637 &pi->bsu); 3638 3639 r600_calculate_u_and_p(pi->pasi, 3640 xclk, 3641 16, 3642 &pi->pbsp, 3643 &pi->pbsu); 3644 3645 3646 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3647 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3648 3649 WREG32(CG_BSP, pi->dsp); 3650 } 3651 3652 static void si_program_git(struct radeon_device *rdev) 3653 { 3654 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3655 } 3656 3657 static void si_program_tp(struct radeon_device *rdev) 3658 { 3659 int i; 3660 enum r600_td td = R600_TD_DFLT; 3661 3662 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3663 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3664 3665 if (td == R600_TD_AUTO) 3666 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3667 else 3668 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3669 3670 if (td == R600_TD_UP) 3671 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3672 3673 if (td == R600_TD_DOWN) 3674 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3675 } 3676 3677 static void si_program_tpp(struct radeon_device *rdev) 3678 { 3679 WREG32(CG_TPC, R600_TPC_DFLT); 3680 } 3681 3682 static void si_program_sstp(struct radeon_device *rdev) 3683 { 3684 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3685 } 3686 3687 static void si_enable_display_gap(struct radeon_device *rdev) 3688 { 3689 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3690 3691 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3692 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3693 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3694 3695 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3696 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3697 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3698 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3699 } 3700 3701 static void si_program_vc(struct radeon_device *rdev) 3702 { 3703 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3704 3705 WREG32(CG_FTV, pi->vrc); 3706 } 3707 3708 static void si_clear_vc(struct radeon_device *rdev) 3709 { 3710 WREG32(CG_FTV, 0); 3711 } 3712 3713 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3714 { 3715 u8 mc_para_index; 3716 3717 if (memory_clock < 10000) 3718 mc_para_index = 0; 3719 else if (memory_clock >= 80000) 3720 mc_para_index = 0x0f; 3721 else 3722 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3723 return mc_para_index; 3724 } 3725 3726 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3727 { 3728 u8 mc_para_index; 3729 3730 if (strobe_mode) { 3731 if (memory_clock < 12500) 3732 mc_para_index = 0x00; 3733 else if (memory_clock > 47500) 3734 mc_para_index = 0x0f; 3735 else 3736 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3737 } else { 3738 if (memory_clock < 65000) 3739 mc_para_index = 0x00; 3740 else if (memory_clock > 135000) 3741 mc_para_index = 0x0f; 3742 else 3743 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3744 } 3745 return mc_para_index; 3746 } 3747 3748 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3749 { 3750 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3751 bool strobe_mode = false; 3752 u8 result = 0; 3753 3754 if (mclk <= pi->mclk_strobe_mode_threshold) 3755 strobe_mode = true; 3756 3757 if (pi->mem_gddr5) 3758 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3759 else 3760 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3761 3762 if (strobe_mode) 3763 result |= SISLANDS_SMC_STROBE_ENABLE; 3764 3765 return result; 3766 } 3767 3768 static int si_upload_firmware(struct radeon_device *rdev) 3769 { 3770 struct si_power_info *si_pi = si_get_pi(rdev); 3771 int ret; 3772 3773 si_reset_smc(rdev); 3774 si_stop_smc_clock(rdev); 3775 3776 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3777 3778 return ret; 3779 } 3780 3781 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3782 const struct atom_voltage_table *table, 3783 const struct radeon_phase_shedding_limits_table *limits) 3784 { 3785 u32 data, num_bits, num_levels; 3786 3787 if ((table == NULL) || (limits == NULL)) 3788 return false; 3789 3790 data = table->mask_low; 3791 3792 num_bits = hweight32(data); 3793 3794 if (num_bits == 0) 3795 return false; 3796 3797 num_levels = (1 << num_bits); 3798 3799 if (table->count != num_levels) 3800 return false; 3801 3802 if (limits->count != (num_levels - 1)) 3803 return false; 3804 3805 return true; 3806 } 3807 3808 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3809 u32 max_voltage_steps, 3810 struct atom_voltage_table *voltage_table) 3811 { 3812 unsigned int i, diff; 3813 3814 if (voltage_table->count <= max_voltage_steps) 3815 return; 3816 3817 diff = voltage_table->count - max_voltage_steps; 3818 3819 for (i= 0; i < max_voltage_steps; i++) 3820 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3821 3822 voltage_table->count = max_voltage_steps; 3823 } 3824 3825 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3826 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3827 struct atom_voltage_table *voltage_table) 3828 { 3829 u32 i; 3830 3831 if (voltage_dependency_table == NULL) 3832 return -EINVAL; 3833 3834 voltage_table->mask_low = 0; 3835 voltage_table->phase_delay = 0; 3836 3837 voltage_table->count = voltage_dependency_table->count; 3838 for (i = 0; i < voltage_table->count; i++) { 3839 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3840 voltage_table->entries[i].smio_low = 0; 3841 } 3842 3843 return 0; 3844 } 3845 3846 static int si_construct_voltage_tables(struct radeon_device *rdev) 3847 { 3848 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3849 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3850 struct si_power_info *si_pi = si_get_pi(rdev); 3851 int ret; 3852 3853 if (pi->voltage_control) { 3854 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3855 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3856 if (ret) 3857 return ret; 3858 3859 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3860 si_trim_voltage_table_to_fit_state_table(rdev, 3861 SISLANDS_MAX_NO_VREG_STEPS, 3862 &eg_pi->vddc_voltage_table); 3863 } else if (si_pi->voltage_control_svi2) { 3864 ret = si_get_svi2_voltage_table(rdev, 3865 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3866 &eg_pi->vddc_voltage_table); 3867 if (ret) 3868 return ret; 3869 } else { 3870 return -EINVAL; 3871 } 3872 3873 if (eg_pi->vddci_control) { 3874 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3875 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3876 if (ret) 3877 return ret; 3878 3879 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3880 si_trim_voltage_table_to_fit_state_table(rdev, 3881 SISLANDS_MAX_NO_VREG_STEPS, 3882 &eg_pi->vddci_voltage_table); 3883 } 3884 if (si_pi->vddci_control_svi2) { 3885 ret = si_get_svi2_voltage_table(rdev, 3886 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3887 &eg_pi->vddci_voltage_table); 3888 if (ret) 3889 return ret; 3890 } 3891 3892 if (pi->mvdd_control) { 3893 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3894 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3895 3896 if (ret) { 3897 pi->mvdd_control = false; 3898 return ret; 3899 } 3900 3901 if (si_pi->mvdd_voltage_table.count == 0) { 3902 pi->mvdd_control = false; 3903 return -EINVAL; 3904 } 3905 3906 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3907 si_trim_voltage_table_to_fit_state_table(rdev, 3908 SISLANDS_MAX_NO_VREG_STEPS, 3909 &si_pi->mvdd_voltage_table); 3910 } 3911 3912 if (si_pi->vddc_phase_shed_control) { 3913 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3914 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3915 if (ret) 3916 si_pi->vddc_phase_shed_control = false; 3917 3918 if ((si_pi->vddc_phase_shed_table.count == 0) || 3919 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3920 si_pi->vddc_phase_shed_control = false; 3921 } 3922 3923 return 0; 3924 } 3925 3926 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3927 const struct atom_voltage_table *voltage_table, 3928 SISLANDS_SMC_STATETABLE *table) 3929 { 3930 unsigned int i; 3931 3932 for (i = 0; i < voltage_table->count; i++) 3933 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3934 } 3935 3936 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3937 SISLANDS_SMC_STATETABLE *table) 3938 { 3939 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3940 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3941 struct si_power_info *si_pi = si_get_pi(rdev); 3942 u8 i; 3943 3944 if (si_pi->voltage_control_svi2) { 3945 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 3946 si_pi->svc_gpio_id); 3947 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 3948 si_pi->svd_gpio_id); 3949 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 3950 2); 3951 } else { 3952 if (eg_pi->vddc_voltage_table.count) { 3953 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3954 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3955 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3956 3957 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3958 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3959 table->maxVDDCIndexInPPTable = i; 3960 break; 3961 } 3962 } 3963 } 3964 3965 if (eg_pi->vddci_voltage_table.count) { 3966 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3967 3968 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3969 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3970 } 3971 3972 3973 if (si_pi->mvdd_voltage_table.count) { 3974 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3975 3976 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3977 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3978 } 3979 3980 if (si_pi->vddc_phase_shed_control) { 3981 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3982 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3983 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3984 3985 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3986 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3987 3988 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3989 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3990 } else { 3991 si_pi->vddc_phase_shed_control = false; 3992 } 3993 } 3994 } 3995 3996 return 0; 3997 } 3998 3999 static int si_populate_voltage_value(struct radeon_device *rdev, 4000 const struct atom_voltage_table *table, 4001 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4002 { 4003 unsigned int i; 4004 4005 for (i = 0; i < table->count; i++) { 4006 if (value <= table->entries[i].value) { 4007 voltage->index = (u8)i; 4008 voltage->value = cpu_to_be16(table->entries[i].value); 4009 break; 4010 } 4011 } 4012 4013 if (i >= table->count) 4014 return -EINVAL; 4015 4016 return 0; 4017 } 4018 4019 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4020 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4021 { 4022 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4023 struct si_power_info *si_pi = si_get_pi(rdev); 4024 4025 if (pi->mvdd_control) { 4026 if (mclk <= pi->mvdd_split_frequency) 4027 voltage->index = 0; 4028 else 4029 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4030 4031 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4032 } 4033 return 0; 4034 } 4035 4036 static int si_get_std_voltage_value(struct radeon_device *rdev, 4037 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4038 u16 *std_voltage) 4039 { 4040 u16 v_index; 4041 bool voltage_found = false; 4042 *std_voltage = be16_to_cpu(voltage->value); 4043 4044 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4045 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4046 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4047 return -EINVAL; 4048 4049 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4050 if (be16_to_cpu(voltage->value) == 4051 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4052 voltage_found = true; 4053 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4054 *std_voltage = 4055 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4056 else 4057 *std_voltage = 4058 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4059 break; 4060 } 4061 } 4062 4063 if (!voltage_found) { 4064 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4065 if (be16_to_cpu(voltage->value) <= 4066 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4067 voltage_found = true; 4068 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4069 *std_voltage = 4070 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4071 else 4072 *std_voltage = 4073 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4074 break; 4075 } 4076 } 4077 } 4078 } else { 4079 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4080 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4081 } 4082 } 4083 4084 return 0; 4085 } 4086 4087 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4088 u16 value, u8 index, 4089 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4090 { 4091 voltage->index = index; 4092 voltage->value = cpu_to_be16(value); 4093 4094 return 0; 4095 } 4096 4097 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4098 const struct radeon_phase_shedding_limits_table *limits, 4099 u16 voltage, u32 sclk, u32 mclk, 4100 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4101 { 4102 unsigned int i; 4103 4104 for (i = 0; i < limits->count; i++) { 4105 if ((voltage <= limits->entries[i].voltage) && 4106 (sclk <= limits->entries[i].sclk) && 4107 (mclk <= limits->entries[i].mclk)) 4108 break; 4109 } 4110 4111 smc_voltage->phase_settings = (u8)i; 4112 4113 return 0; 4114 } 4115 4116 static int si_init_arb_table_index(struct radeon_device *rdev) 4117 { 4118 struct si_power_info *si_pi = si_get_pi(rdev); 4119 u32 tmp; 4120 int ret; 4121 4122 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4123 if (ret) 4124 return ret; 4125 4126 tmp &= 0x00FFFFFF; 4127 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4128 4129 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4130 } 4131 4132 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4133 { 4134 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4135 } 4136 4137 static int si_reset_to_default(struct radeon_device *rdev) 4138 { 4139 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4140 0 : -EINVAL; 4141 } 4142 4143 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4144 { 4145 struct si_power_info *si_pi = si_get_pi(rdev); 4146 u32 tmp; 4147 int ret; 4148 4149 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4150 &tmp, si_pi->sram_end); 4151 if (ret) 4152 return ret; 4153 4154 tmp = (tmp >> 24) & 0xff; 4155 4156 if (tmp == MC_CG_ARB_FREQ_F0) 4157 return 0; 4158 4159 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4160 } 4161 4162 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4163 u32 engine_clock) 4164 { 4165 u32 dram_rows; 4166 u32 dram_refresh_rate; 4167 u32 mc_arb_rfsh_rate; 4168 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4169 4170 if (tmp >= 4) 4171 dram_rows = 16384; 4172 else 4173 dram_rows = 1 << (tmp + 10); 4174 4175 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4176 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4177 4178 return mc_arb_rfsh_rate; 4179 } 4180 4181 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4182 struct rv7xx_pl *pl, 4183 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4184 { 4185 u32 dram_timing; 4186 u32 dram_timing2; 4187 u32 burst_time; 4188 4189 arb_regs->mc_arb_rfsh_rate = 4190 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4191 4192 radeon_atom_set_engine_dram_timings(rdev, 4193 pl->sclk, 4194 pl->mclk); 4195 4196 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4197 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4198 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4199 4200 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4201 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4202 arb_regs->mc_arb_burst_time = (u8)burst_time; 4203 4204 return 0; 4205 } 4206 4207 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4208 struct radeon_ps *radeon_state, 4209 unsigned int first_arb_set) 4210 { 4211 struct si_power_info *si_pi = si_get_pi(rdev); 4212 struct ni_ps *state = ni_get_ps(radeon_state); 4213 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4214 int i, ret = 0; 4215 4216 for (i = 0; i < state->performance_level_count; i++) { 4217 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4218 if (ret) 4219 break; 4220 ret = si_copy_bytes_to_smc(rdev, 4221 si_pi->arb_table_start + 4222 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4223 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4224 (u8 *)&arb_regs, 4225 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4226 si_pi->sram_end); 4227 if (ret) 4228 break; 4229 } 4230 4231 return ret; 4232 } 4233 4234 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4235 struct radeon_ps *radeon_new_state) 4236 { 4237 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4238 SISLANDS_DRIVER_STATE_ARB_INDEX); 4239 } 4240 4241 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4242 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4243 { 4244 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4245 struct si_power_info *si_pi = si_get_pi(rdev); 4246 4247 if (pi->mvdd_control) 4248 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4249 si_pi->mvdd_bootup_value, voltage); 4250 4251 return 0; 4252 } 4253 4254 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4255 struct radeon_ps *radeon_initial_state, 4256 SISLANDS_SMC_STATETABLE *table) 4257 { 4258 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4259 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4260 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4261 struct si_power_info *si_pi = si_get_pi(rdev); 4262 u32 reg; 4263 int ret; 4264 4265 table->initialState.levels[0].mclk.vDLL_CNTL = 4266 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4267 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4268 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4269 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4270 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4271 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4272 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4273 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4274 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4275 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4276 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4277 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4278 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4279 table->initialState.levels[0].mclk.vMPLL_SS = 4280 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4281 table->initialState.levels[0].mclk.vMPLL_SS2 = 4282 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4283 4284 table->initialState.levels[0].mclk.mclk_value = 4285 cpu_to_be32(initial_state->performance_levels[0].mclk); 4286 4287 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4288 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4289 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4290 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4291 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4292 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4293 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4294 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4295 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4296 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4297 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4298 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4299 4300 table->initialState.levels[0].sclk.sclk_value = 4301 cpu_to_be32(initial_state->performance_levels[0].sclk); 4302 4303 table->initialState.levels[0].arbRefreshState = 4304 SISLANDS_INITIAL_STATE_ARB_INDEX; 4305 4306 table->initialState.levels[0].ACIndex = 0; 4307 4308 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4309 initial_state->performance_levels[0].vddc, 4310 &table->initialState.levels[0].vddc); 4311 4312 if (!ret) { 4313 u16 std_vddc; 4314 4315 ret = si_get_std_voltage_value(rdev, 4316 &table->initialState.levels[0].vddc, 4317 &std_vddc); 4318 if (!ret) 4319 si_populate_std_voltage_value(rdev, std_vddc, 4320 table->initialState.levels[0].vddc.index, 4321 &table->initialState.levels[0].std_vddc); 4322 } 4323 4324 if (eg_pi->vddci_control) 4325 si_populate_voltage_value(rdev, 4326 &eg_pi->vddci_voltage_table, 4327 initial_state->performance_levels[0].vddci, 4328 &table->initialState.levels[0].vddci); 4329 4330 if (si_pi->vddc_phase_shed_control) 4331 si_populate_phase_shedding_value(rdev, 4332 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4333 initial_state->performance_levels[0].vddc, 4334 initial_state->performance_levels[0].sclk, 4335 initial_state->performance_levels[0].mclk, 4336 &table->initialState.levels[0].vddc); 4337 4338 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4339 4340 reg = CG_R(0xffff) | CG_L(0); 4341 table->initialState.levels[0].aT = cpu_to_be32(reg); 4342 4343 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4344 4345 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4346 4347 if (pi->mem_gddr5) { 4348 table->initialState.levels[0].strobeMode = 4349 si_get_strobe_mode_settings(rdev, 4350 initial_state->performance_levels[0].mclk); 4351 4352 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4353 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4354 else 4355 table->initialState.levels[0].mcFlags = 0; 4356 } 4357 4358 table->initialState.levelCount = 1; 4359 4360 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4361 4362 table->initialState.levels[0].dpm2.MaxPS = 0; 4363 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4364 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4365 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4366 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4367 4368 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4369 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4370 4371 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4372 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4373 4374 return 0; 4375 } 4376 4377 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4378 SISLANDS_SMC_STATETABLE *table) 4379 { 4380 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4381 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4382 struct si_power_info *si_pi = si_get_pi(rdev); 4383 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4384 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4385 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4386 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4387 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4388 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4389 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4390 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4391 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4392 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4393 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4394 u32 reg; 4395 int ret; 4396 4397 table->ACPIState = table->initialState; 4398 4399 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4400 4401 if (pi->acpi_vddc) { 4402 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4403 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4404 if (!ret) { 4405 u16 std_vddc; 4406 4407 ret = si_get_std_voltage_value(rdev, 4408 &table->ACPIState.levels[0].vddc, &std_vddc); 4409 if (!ret) 4410 si_populate_std_voltage_value(rdev, std_vddc, 4411 table->ACPIState.levels[0].vddc.index, 4412 &table->ACPIState.levels[0].std_vddc); 4413 } 4414 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4415 4416 if (si_pi->vddc_phase_shed_control) { 4417 si_populate_phase_shedding_value(rdev, 4418 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4419 pi->acpi_vddc, 4420 0, 4421 0, 4422 &table->ACPIState.levels[0].vddc); 4423 } 4424 } else { 4425 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4426 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4427 if (!ret) { 4428 u16 std_vddc; 4429 4430 ret = si_get_std_voltage_value(rdev, 4431 &table->ACPIState.levels[0].vddc, &std_vddc); 4432 4433 if (!ret) 4434 si_populate_std_voltage_value(rdev, std_vddc, 4435 table->ACPIState.levels[0].vddc.index, 4436 &table->ACPIState.levels[0].std_vddc); 4437 } 4438 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4439 si_pi->sys_pcie_mask, 4440 si_pi->boot_pcie_gen, 4441 RADEON_PCIE_GEN1); 4442 4443 if (si_pi->vddc_phase_shed_control) 4444 si_populate_phase_shedding_value(rdev, 4445 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4446 pi->min_vddc_in_table, 4447 0, 4448 0, 4449 &table->ACPIState.levels[0].vddc); 4450 } 4451 4452 if (pi->acpi_vddc) { 4453 if (eg_pi->acpi_vddci) 4454 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4455 eg_pi->acpi_vddci, 4456 &table->ACPIState.levels[0].vddci); 4457 } 4458 4459 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4460 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4461 4462 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4463 4464 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4465 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4466 4467 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4468 cpu_to_be32(dll_cntl); 4469 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4470 cpu_to_be32(mclk_pwrmgt_cntl); 4471 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4472 cpu_to_be32(mpll_ad_func_cntl); 4473 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4474 cpu_to_be32(mpll_dq_func_cntl); 4475 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4476 cpu_to_be32(mpll_func_cntl); 4477 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4478 cpu_to_be32(mpll_func_cntl_1); 4479 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4480 cpu_to_be32(mpll_func_cntl_2); 4481 table->ACPIState.levels[0].mclk.vMPLL_SS = 4482 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4483 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4484 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4485 4486 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4487 cpu_to_be32(spll_func_cntl); 4488 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4489 cpu_to_be32(spll_func_cntl_2); 4490 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4491 cpu_to_be32(spll_func_cntl_3); 4492 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4493 cpu_to_be32(spll_func_cntl_4); 4494 4495 table->ACPIState.levels[0].mclk.mclk_value = 0; 4496 table->ACPIState.levels[0].sclk.sclk_value = 0; 4497 4498 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4499 4500 if (eg_pi->dynamic_ac_timing) 4501 table->ACPIState.levels[0].ACIndex = 0; 4502 4503 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4504 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4505 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4506 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4507 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4508 4509 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4510 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4511 4512 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4513 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4514 4515 return 0; 4516 } 4517 4518 static int si_populate_ulv_state(struct radeon_device *rdev, 4519 SISLANDS_SMC_SWSTATE *state) 4520 { 4521 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4522 struct si_power_info *si_pi = si_get_pi(rdev); 4523 struct si_ulv_param *ulv = &si_pi->ulv; 4524 u32 sclk_in_sr = 1350; /* ??? */ 4525 int ret; 4526 4527 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4528 &state->levels[0]); 4529 if (!ret) { 4530 if (eg_pi->sclk_deep_sleep) { 4531 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4532 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4533 else 4534 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4535 } 4536 if (ulv->one_pcie_lane_in_ulv) 4537 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4538 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4539 state->levels[0].ACIndex = 1; 4540 state->levels[0].std_vddc = state->levels[0].vddc; 4541 state->levelCount = 1; 4542 4543 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4544 } 4545 4546 return ret; 4547 } 4548 4549 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4550 { 4551 struct si_power_info *si_pi = si_get_pi(rdev); 4552 struct si_ulv_param *ulv = &si_pi->ulv; 4553 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4554 int ret; 4555 4556 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4557 &arb_regs); 4558 if (ret) 4559 return ret; 4560 4561 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4562 ulv->volt_change_delay); 4563 4564 ret = si_copy_bytes_to_smc(rdev, 4565 si_pi->arb_table_start + 4566 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4567 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4568 (u8 *)&arb_regs, 4569 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4570 si_pi->sram_end); 4571 4572 return ret; 4573 } 4574 4575 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4576 { 4577 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4578 4579 pi->mvdd_split_frequency = 30000; 4580 } 4581 4582 static int si_init_smc_table(struct radeon_device *rdev) 4583 { 4584 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4585 struct si_power_info *si_pi = si_get_pi(rdev); 4586 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4587 const struct si_ulv_param *ulv = &si_pi->ulv; 4588 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4589 int ret; 4590 u32 lane_width; 4591 u32 vr_hot_gpio; 4592 4593 si_populate_smc_voltage_tables(rdev, table); 4594 4595 switch (rdev->pm.int_thermal_type) { 4596 case THERMAL_TYPE_SI: 4597 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4598 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4599 break; 4600 case THERMAL_TYPE_NONE: 4601 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4602 break; 4603 default: 4604 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4605 break; 4606 } 4607 4608 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4609 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4610 4611 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4612 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4613 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4614 } 4615 4616 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4617 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4618 4619 if (pi->mem_gddr5) 4620 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4621 4622 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4623 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4624 4625 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4626 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4627 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4628 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4629 vr_hot_gpio); 4630 } 4631 4632 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4633 if (ret) 4634 return ret; 4635 4636 ret = si_populate_smc_acpi_state(rdev, table); 4637 if (ret) 4638 return ret; 4639 4640 table->driverState = table->initialState; 4641 4642 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4643 SISLANDS_INITIAL_STATE_ARB_INDEX); 4644 if (ret) 4645 return ret; 4646 4647 if (ulv->supported && ulv->pl.vddc) { 4648 ret = si_populate_ulv_state(rdev, &table->ULVState); 4649 if (ret) 4650 return ret; 4651 4652 ret = si_program_ulv_memory_timing_parameters(rdev); 4653 if (ret) 4654 return ret; 4655 4656 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4657 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4658 4659 lane_width = radeon_get_pcie_lanes(rdev); 4660 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4661 } else { 4662 table->ULVState = table->initialState; 4663 } 4664 4665 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4666 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4667 si_pi->sram_end); 4668 } 4669 4670 static int si_calculate_sclk_params(struct radeon_device *rdev, 4671 u32 engine_clock, 4672 SISLANDS_SMC_SCLK_VALUE *sclk) 4673 { 4674 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4675 struct si_power_info *si_pi = si_get_pi(rdev); 4676 struct atom_clock_dividers dividers; 4677 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4678 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4679 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4680 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4681 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4682 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4683 u64 tmp; 4684 u32 reference_clock = rdev->clock.spll.reference_freq; 4685 u32 reference_divider; 4686 u32 fbdiv; 4687 int ret; 4688 4689 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4690 engine_clock, false, ÷rs); 4691 if (ret) 4692 return ret; 4693 4694 reference_divider = 1 + dividers.ref_div; 4695 4696 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4697 do_div(tmp, reference_clock); 4698 fbdiv = (u32) tmp; 4699 4700 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4701 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4702 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4703 4704 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4705 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4706 4707 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4708 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4709 spll_func_cntl_3 |= SPLL_DITHEN; 4710 4711 if (pi->sclk_ss) { 4712 struct radeon_atom_ss ss; 4713 u32 vco_freq = engine_clock * dividers.post_div; 4714 4715 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4716 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4717 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4718 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4719 4720 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4721 cg_spll_spread_spectrum |= CLK_S(clk_s); 4722 cg_spll_spread_spectrum |= SSEN; 4723 4724 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4725 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4726 } 4727 } 4728 4729 sclk->sclk_value = engine_clock; 4730 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4731 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4732 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4733 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4734 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4735 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4736 4737 return 0; 4738 } 4739 4740 static int si_populate_sclk_value(struct radeon_device *rdev, 4741 u32 engine_clock, 4742 SISLANDS_SMC_SCLK_VALUE *sclk) 4743 { 4744 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4745 int ret; 4746 4747 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4748 if (!ret) { 4749 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4750 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4751 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4752 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4753 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4754 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4755 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4756 } 4757 4758 return ret; 4759 } 4760 4761 static int si_populate_mclk_value(struct radeon_device *rdev, 4762 u32 engine_clock, 4763 u32 memory_clock, 4764 SISLANDS_SMC_MCLK_VALUE *mclk, 4765 bool strobe_mode, 4766 bool dll_state_on) 4767 { 4768 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4769 struct si_power_info *si_pi = si_get_pi(rdev); 4770 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4771 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4772 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4773 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4774 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4775 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4776 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4777 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4778 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4779 struct atom_mpll_param mpll_param; 4780 int ret; 4781 4782 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4783 if (ret) 4784 return ret; 4785 4786 mpll_func_cntl &= ~BWCTRL_MASK; 4787 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4788 4789 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4790 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4791 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4792 4793 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4794 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4795 4796 if (pi->mem_gddr5) { 4797 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4798 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4799 YCLK_POST_DIV(mpll_param.post_div); 4800 } 4801 4802 if (pi->mclk_ss) { 4803 struct radeon_atom_ss ss; 4804 u32 freq_nom; 4805 u32 tmp; 4806 u32 reference_clock = rdev->clock.mpll.reference_freq; 4807 4808 if (pi->mem_gddr5) 4809 freq_nom = memory_clock * 4; 4810 else 4811 freq_nom = memory_clock * 2; 4812 4813 tmp = freq_nom / reference_clock; 4814 tmp = tmp * tmp; 4815 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4816 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4817 u32 clks = reference_clock * 5 / ss.rate; 4818 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4819 4820 mpll_ss1 &= ~CLKV_MASK; 4821 mpll_ss1 |= CLKV(clkv); 4822 4823 mpll_ss2 &= ~CLKS_MASK; 4824 mpll_ss2 |= CLKS(clks); 4825 } 4826 } 4827 4828 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4829 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4830 4831 if (dll_state_on) 4832 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4833 else 4834 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4835 4836 mclk->mclk_value = cpu_to_be32(memory_clock); 4837 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4838 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4839 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4840 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4841 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4842 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4843 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4844 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4845 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4846 4847 return 0; 4848 } 4849 4850 static void si_populate_smc_sp(struct radeon_device *rdev, 4851 struct radeon_ps *radeon_state, 4852 SISLANDS_SMC_SWSTATE *smc_state) 4853 { 4854 struct ni_ps *ps = ni_get_ps(radeon_state); 4855 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4856 int i; 4857 4858 for (i = 0; i < ps->performance_level_count - 1; i++) 4859 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4860 4861 smc_state->levels[ps->performance_level_count - 1].bSP = 4862 cpu_to_be32(pi->psp); 4863 } 4864 4865 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4866 struct rv7xx_pl *pl, 4867 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4868 { 4869 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4870 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4871 struct si_power_info *si_pi = si_get_pi(rdev); 4872 int ret; 4873 bool dll_state_on; 4874 u16 std_vddc; 4875 bool gmc_pg = false; 4876 4877 if (eg_pi->pcie_performance_request && 4878 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4879 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4880 else 4881 level->gen2PCIE = (u8)pl->pcie_gen; 4882 4883 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4884 if (ret) 4885 return ret; 4886 4887 level->mcFlags = 0; 4888 4889 if (pi->mclk_stutter_mode_threshold && 4890 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4891 !eg_pi->uvd_enabled && 4892 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4893 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4894 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4895 4896 if (gmc_pg) 4897 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4898 } 4899 4900 if (pi->mem_gddr5) { 4901 if (pl->mclk > pi->mclk_edc_enable_threshold) 4902 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4903 4904 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4905 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4906 4907 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4908 4909 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4910 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4911 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4912 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4913 else 4914 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4915 } else { 4916 dll_state_on = false; 4917 } 4918 } else { 4919 level->strobeMode = si_get_strobe_mode_settings(rdev, 4920 pl->mclk); 4921 4922 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4923 } 4924 4925 ret = si_populate_mclk_value(rdev, 4926 pl->sclk, 4927 pl->mclk, 4928 &level->mclk, 4929 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4930 if (ret) 4931 return ret; 4932 4933 ret = si_populate_voltage_value(rdev, 4934 &eg_pi->vddc_voltage_table, 4935 pl->vddc, &level->vddc); 4936 if (ret) 4937 return ret; 4938 4939 4940 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4941 if (ret) 4942 return ret; 4943 4944 ret = si_populate_std_voltage_value(rdev, std_vddc, 4945 level->vddc.index, &level->std_vddc); 4946 if (ret) 4947 return ret; 4948 4949 if (eg_pi->vddci_control) { 4950 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4951 pl->vddci, &level->vddci); 4952 if (ret) 4953 return ret; 4954 } 4955 4956 if (si_pi->vddc_phase_shed_control) { 4957 ret = si_populate_phase_shedding_value(rdev, 4958 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4959 pl->vddc, 4960 pl->sclk, 4961 pl->mclk, 4962 &level->vddc); 4963 if (ret) 4964 return ret; 4965 } 4966 4967 level->MaxPoweredUpCU = si_pi->max_cu; 4968 4969 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4970 4971 return ret; 4972 } 4973 4974 static int si_populate_smc_t(struct radeon_device *rdev, 4975 struct radeon_ps *radeon_state, 4976 SISLANDS_SMC_SWSTATE *smc_state) 4977 { 4978 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4979 struct ni_ps *state = ni_get_ps(radeon_state); 4980 u32 a_t; 4981 u32 t_l, t_h; 4982 u32 high_bsp; 4983 int i, ret; 4984 4985 if (state->performance_level_count >= 9) 4986 return -EINVAL; 4987 4988 if (state->performance_level_count < 2) { 4989 a_t = CG_R(0xffff) | CG_L(0); 4990 smc_state->levels[0].aT = cpu_to_be32(a_t); 4991 return 0; 4992 } 4993 4994 smc_state->levels[0].aT = cpu_to_be32(0); 4995 4996 for (i = 0; i <= state->performance_level_count - 2; i++) { 4997 ret = r600_calculate_at( 4998 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4999 100 * R600_AH_DFLT, 5000 state->performance_levels[i + 1].sclk, 5001 state->performance_levels[i].sclk, 5002 &t_l, 5003 &t_h); 5004 5005 if (ret) { 5006 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5007 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5008 } 5009 5010 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5011 a_t |= CG_R(t_l * pi->bsp / 20000); 5012 smc_state->levels[i].aT = cpu_to_be32(a_t); 5013 5014 high_bsp = (i == state->performance_level_count - 2) ? 5015 pi->pbsp : pi->bsp; 5016 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5017 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5018 } 5019 5020 return 0; 5021 } 5022 5023 static int si_disable_ulv(struct radeon_device *rdev) 5024 { 5025 struct si_power_info *si_pi = si_get_pi(rdev); 5026 struct si_ulv_param *ulv = &si_pi->ulv; 5027 5028 if (ulv->supported) 5029 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5030 0 : -EINVAL; 5031 5032 return 0; 5033 } 5034 5035 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5036 struct radeon_ps *radeon_state) 5037 { 5038 const struct si_power_info *si_pi = si_get_pi(rdev); 5039 const struct si_ulv_param *ulv = &si_pi->ulv; 5040 const struct ni_ps *state = ni_get_ps(radeon_state); 5041 int i; 5042 5043 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5044 return false; 5045 5046 /* XXX validate against display requirements! */ 5047 5048 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5049 if (rdev->clock.current_dispclk <= 5050 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5051 if (ulv->pl.vddc < 5052 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5053 return false; 5054 } 5055 } 5056 5057 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5058 return false; 5059 5060 return true; 5061 } 5062 5063 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5064 struct radeon_ps *radeon_new_state) 5065 { 5066 const struct si_power_info *si_pi = si_get_pi(rdev); 5067 const struct si_ulv_param *ulv = &si_pi->ulv; 5068 5069 if (ulv->supported) { 5070 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5071 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5072 0 : -EINVAL; 5073 } 5074 return 0; 5075 } 5076 5077 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5078 struct radeon_ps *radeon_state, 5079 SISLANDS_SMC_SWSTATE *smc_state) 5080 { 5081 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5082 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5083 struct si_power_info *si_pi = si_get_pi(rdev); 5084 struct ni_ps *state = ni_get_ps(radeon_state); 5085 int i, ret; 5086 u32 threshold; 5087 u32 sclk_in_sr = 1350; /* ??? */ 5088 5089 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5090 return -EINVAL; 5091 5092 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5093 5094 if (radeon_state->vclk && radeon_state->dclk) { 5095 eg_pi->uvd_enabled = true; 5096 if (eg_pi->smu_uvd_hs) 5097 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5098 } else { 5099 eg_pi->uvd_enabled = false; 5100 } 5101 5102 if (state->dc_compatible) 5103 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5104 5105 smc_state->levelCount = 0; 5106 for (i = 0; i < state->performance_level_count; i++) { 5107 if (eg_pi->sclk_deep_sleep) { 5108 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5109 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5110 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5111 else 5112 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5113 } 5114 } 5115 5116 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5117 &smc_state->levels[i]); 5118 smc_state->levels[i].arbRefreshState = 5119 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5120 5121 if (ret) 5122 return ret; 5123 5124 if (ni_pi->enable_power_containment) 5125 smc_state->levels[i].displayWatermark = 5126 (state->performance_levels[i].sclk < threshold) ? 5127 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5128 else 5129 smc_state->levels[i].displayWatermark = (i < 2) ? 5130 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5131 5132 if (eg_pi->dynamic_ac_timing) 5133 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5134 else 5135 smc_state->levels[i].ACIndex = 0; 5136 5137 smc_state->levelCount++; 5138 } 5139 5140 si_write_smc_soft_register(rdev, 5141 SI_SMC_SOFT_REGISTER_watermark_threshold, 5142 threshold / 512); 5143 5144 si_populate_smc_sp(rdev, radeon_state, smc_state); 5145 5146 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5147 if (ret) 5148 ni_pi->enable_power_containment = false; 5149 5150 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5151 if (ret) 5152 ni_pi->enable_sq_ramping = false; 5153 5154 return si_populate_smc_t(rdev, radeon_state, smc_state); 5155 } 5156 5157 static int si_upload_sw_state(struct radeon_device *rdev, 5158 struct radeon_ps *radeon_new_state) 5159 { 5160 struct si_power_info *si_pi = si_get_pi(rdev); 5161 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5162 int ret; 5163 u32 address = si_pi->state_table_start + 5164 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5165 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5166 ((new_state->performance_level_count - 1) * 5167 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5168 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5169 5170 memset(smc_state, 0, state_size); 5171 5172 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5173 if (ret) 5174 return ret; 5175 5176 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5177 state_size, si_pi->sram_end); 5178 5179 return ret; 5180 } 5181 5182 static int si_upload_ulv_state(struct radeon_device *rdev) 5183 { 5184 struct si_power_info *si_pi = si_get_pi(rdev); 5185 struct si_ulv_param *ulv = &si_pi->ulv; 5186 int ret = 0; 5187 5188 if (ulv->supported && ulv->pl.vddc) { 5189 u32 address = si_pi->state_table_start + 5190 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5191 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5192 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5193 5194 memset(smc_state, 0, state_size); 5195 5196 ret = si_populate_ulv_state(rdev, smc_state); 5197 if (!ret) 5198 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5199 state_size, si_pi->sram_end); 5200 } 5201 5202 return ret; 5203 } 5204 5205 static int si_upload_smc_data(struct radeon_device *rdev) 5206 { 5207 struct radeon_crtc *radeon_crtc = NULL; 5208 int i; 5209 5210 if (rdev->pm.dpm.new_active_crtc_count == 0) 5211 return 0; 5212 5213 for (i = 0; i < rdev->num_crtc; i++) { 5214 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5215 radeon_crtc = rdev->mode_info.crtcs[i]; 5216 break; 5217 } 5218 } 5219 5220 if (radeon_crtc == NULL) 5221 return 0; 5222 5223 if (radeon_crtc->line_time <= 0) 5224 return 0; 5225 5226 if (si_write_smc_soft_register(rdev, 5227 SI_SMC_SOFT_REGISTER_crtc_index, 5228 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5229 return 0; 5230 5231 if (si_write_smc_soft_register(rdev, 5232 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5233 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5234 return 0; 5235 5236 if (si_write_smc_soft_register(rdev, 5237 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5238 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5239 return 0; 5240 5241 return 0; 5242 } 5243 5244 static int si_set_mc_special_registers(struct radeon_device *rdev, 5245 struct si_mc_reg_table *table) 5246 { 5247 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5248 u8 i, j, k; 5249 u32 temp_reg; 5250 5251 for (i = 0, j = table->last; i < table->last; i++) { 5252 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5253 return -EINVAL; 5254 switch (table->mc_reg_address[i].s1 << 2) { 5255 case MC_SEQ_MISC1: 5256 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5257 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5258 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5259 for (k = 0; k < table->num_entries; k++) 5260 table->mc_reg_table_entry[k].mc_data[j] = 5261 ((temp_reg & 0xffff0000)) | 5262 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5263 j++; 5264 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5265 return -EINVAL; 5266 5267 temp_reg = RREG32(MC_PMG_CMD_MRS); 5268 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5269 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5270 for (k = 0; k < table->num_entries; k++) { 5271 table->mc_reg_table_entry[k].mc_data[j] = 5272 (temp_reg & 0xffff0000) | 5273 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5274 if (!pi->mem_gddr5) 5275 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5276 } 5277 j++; 5278 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5279 return -EINVAL; 5280 5281 if (!pi->mem_gddr5) { 5282 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5283 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5284 for (k = 0; k < table->num_entries; k++) 5285 table->mc_reg_table_entry[k].mc_data[j] = 5286 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5287 j++; 5288 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5289 return -EINVAL; 5290 } 5291 break; 5292 case MC_SEQ_RESERVE_M: 5293 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5294 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5295 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5296 for(k = 0; k < table->num_entries; k++) 5297 table->mc_reg_table_entry[k].mc_data[j] = 5298 (temp_reg & 0xffff0000) | 5299 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5300 j++; 5301 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5302 return -EINVAL; 5303 break; 5304 default: 5305 break; 5306 } 5307 } 5308 5309 table->last = j; 5310 5311 return 0; 5312 } 5313 5314 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5315 { 5316 bool result = true; 5317 5318 switch (in_reg) { 5319 case MC_SEQ_RAS_TIMING >> 2: 5320 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5321 break; 5322 case MC_SEQ_CAS_TIMING >> 2: 5323 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5324 break; 5325 case MC_SEQ_MISC_TIMING >> 2: 5326 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5327 break; 5328 case MC_SEQ_MISC_TIMING2 >> 2: 5329 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5330 break; 5331 case MC_SEQ_RD_CTL_D0 >> 2: 5332 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5333 break; 5334 case MC_SEQ_RD_CTL_D1 >> 2: 5335 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5336 break; 5337 case MC_SEQ_WR_CTL_D0 >> 2: 5338 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5339 break; 5340 case MC_SEQ_WR_CTL_D1 >> 2: 5341 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5342 break; 5343 case MC_PMG_CMD_EMRS >> 2: 5344 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5345 break; 5346 case MC_PMG_CMD_MRS >> 2: 5347 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5348 break; 5349 case MC_PMG_CMD_MRS1 >> 2: 5350 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5351 break; 5352 case MC_SEQ_PMG_TIMING >> 2: 5353 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5354 break; 5355 case MC_PMG_CMD_MRS2 >> 2: 5356 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5357 break; 5358 case MC_SEQ_WR_CTL_2 >> 2: 5359 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5360 break; 5361 default: 5362 result = false; 5363 break; 5364 } 5365 5366 return result; 5367 } 5368 5369 static void si_set_valid_flag(struct si_mc_reg_table *table) 5370 { 5371 u8 i, j; 5372 5373 for (i = 0; i < table->last; i++) { 5374 for (j = 1; j < table->num_entries; j++) { 5375 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5376 table->valid_flag |= 1 << i; 5377 break; 5378 } 5379 } 5380 } 5381 } 5382 5383 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5384 { 5385 u32 i; 5386 u16 address; 5387 5388 for (i = 0; i < table->last; i++) 5389 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5390 address : table->mc_reg_address[i].s1; 5391 5392 } 5393 5394 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5395 struct si_mc_reg_table *si_table) 5396 { 5397 u8 i, j; 5398 5399 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5400 return -EINVAL; 5401 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5402 return -EINVAL; 5403 5404 for (i = 0; i < table->last; i++) 5405 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5406 si_table->last = table->last; 5407 5408 for (i = 0; i < table->num_entries; i++) { 5409 si_table->mc_reg_table_entry[i].mclk_max = 5410 table->mc_reg_table_entry[i].mclk_max; 5411 for (j = 0; j < table->last; j++) { 5412 si_table->mc_reg_table_entry[i].mc_data[j] = 5413 table->mc_reg_table_entry[i].mc_data[j]; 5414 } 5415 } 5416 si_table->num_entries = table->num_entries; 5417 5418 return 0; 5419 } 5420 5421 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5422 { 5423 struct si_power_info *si_pi = si_get_pi(rdev); 5424 struct atom_mc_reg_table *table; 5425 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5426 u8 module_index = rv770_get_memory_module_index(rdev); 5427 int ret; 5428 5429 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5430 if (!table) 5431 return -ENOMEM; 5432 5433 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5434 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5435 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5436 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5437 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5438 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5439 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5440 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5441 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5442 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5443 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5444 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5445 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5446 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5447 5448 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5449 if (ret) 5450 goto init_mc_done; 5451 5452 ret = si_copy_vbios_mc_reg_table(table, si_table); 5453 if (ret) 5454 goto init_mc_done; 5455 5456 si_set_s0_mc_reg_index(si_table); 5457 5458 ret = si_set_mc_special_registers(rdev, si_table); 5459 if (ret) 5460 goto init_mc_done; 5461 5462 si_set_valid_flag(si_table); 5463 5464 init_mc_done: 5465 kfree(table); 5466 5467 return ret; 5468 5469 } 5470 5471 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5472 SMC_SIslands_MCRegisters *mc_reg_table) 5473 { 5474 struct si_power_info *si_pi = si_get_pi(rdev); 5475 u32 i, j; 5476 5477 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5478 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5479 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5480 break; 5481 mc_reg_table->address[i].s0 = 5482 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5483 mc_reg_table->address[i].s1 = 5484 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5485 i++; 5486 } 5487 } 5488 mc_reg_table->last = (u8)i; 5489 } 5490 5491 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5492 SMC_SIslands_MCRegisterSet *data, 5493 u32 num_entries, u32 valid_flag) 5494 { 5495 u32 i, j; 5496 5497 for(i = 0, j = 0; j < num_entries; j++) { 5498 if (valid_flag & (1 << j)) { 5499 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5500 i++; 5501 } 5502 } 5503 } 5504 5505 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5506 struct rv7xx_pl *pl, 5507 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5508 { 5509 struct si_power_info *si_pi = si_get_pi(rdev); 5510 u32 i = 0; 5511 5512 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5513 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5514 break; 5515 } 5516 5517 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5518 --i; 5519 5520 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5521 mc_reg_table_data, si_pi->mc_reg_table.last, 5522 si_pi->mc_reg_table.valid_flag); 5523 } 5524 5525 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5526 struct radeon_ps *radeon_state, 5527 SMC_SIslands_MCRegisters *mc_reg_table) 5528 { 5529 struct ni_ps *state = ni_get_ps(radeon_state); 5530 int i; 5531 5532 for (i = 0; i < state->performance_level_count; i++) { 5533 si_convert_mc_reg_table_entry_to_smc(rdev, 5534 &state->performance_levels[i], 5535 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5536 } 5537 } 5538 5539 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5540 struct radeon_ps *radeon_boot_state) 5541 { 5542 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5543 struct si_power_info *si_pi = si_get_pi(rdev); 5544 struct si_ulv_param *ulv = &si_pi->ulv; 5545 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5546 5547 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5548 5549 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5550 5551 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5552 5553 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5554 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5555 5556 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5557 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5558 si_pi->mc_reg_table.last, 5559 si_pi->mc_reg_table.valid_flag); 5560 5561 if (ulv->supported && ulv->pl.vddc != 0) 5562 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5563 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5564 else 5565 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5566 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5567 si_pi->mc_reg_table.last, 5568 si_pi->mc_reg_table.valid_flag); 5569 5570 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5571 5572 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5573 (u8 *)smc_mc_reg_table, 5574 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5575 } 5576 5577 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5578 struct radeon_ps *radeon_new_state) 5579 { 5580 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5581 struct si_power_info *si_pi = si_get_pi(rdev); 5582 u32 address = si_pi->mc_reg_table_start + 5583 offsetof(SMC_SIslands_MCRegisters, 5584 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5585 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5586 5587 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5588 5589 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5590 5591 5592 return si_copy_bytes_to_smc(rdev, address, 5593 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5594 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5595 si_pi->sram_end); 5596 5597 } 5598 5599 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5600 { 5601 if (enable) 5602 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5603 else 5604 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5605 } 5606 5607 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5608 struct radeon_ps *radeon_state) 5609 { 5610 struct ni_ps *state = ni_get_ps(radeon_state); 5611 int i; 5612 u16 pcie_speed, max_speed = 0; 5613 5614 for (i = 0; i < state->performance_level_count; i++) { 5615 pcie_speed = state->performance_levels[i].pcie_gen; 5616 if (max_speed < pcie_speed) 5617 max_speed = pcie_speed; 5618 } 5619 return max_speed; 5620 } 5621 5622 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5623 { 5624 u32 speed_cntl; 5625 5626 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5627 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5628 5629 return (u16)speed_cntl; 5630 } 5631 5632 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5633 struct radeon_ps *radeon_new_state, 5634 struct radeon_ps *radeon_current_state) 5635 { 5636 struct si_power_info *si_pi = si_get_pi(rdev); 5637 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5638 enum radeon_pcie_gen current_link_speed; 5639 5640 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5641 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5642 else 5643 current_link_speed = si_pi->force_pcie_gen; 5644 5645 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5646 si_pi->pspp_notify_required = false; 5647 if (target_link_speed > current_link_speed) { 5648 switch (target_link_speed) { 5649 #if defined(CONFIG_ACPI) 5650 case RADEON_PCIE_GEN3: 5651 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5652 break; 5653 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5654 if (current_link_speed == RADEON_PCIE_GEN2) 5655 break; 5656 case RADEON_PCIE_GEN2: 5657 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5658 break; 5659 #endif 5660 default: 5661 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5662 break; 5663 } 5664 } else { 5665 if (target_link_speed < current_link_speed) 5666 si_pi->pspp_notify_required = true; 5667 } 5668 } 5669 5670 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5671 struct radeon_ps *radeon_new_state, 5672 struct radeon_ps *radeon_current_state) 5673 { 5674 struct si_power_info *si_pi = si_get_pi(rdev); 5675 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5676 u8 request; 5677 5678 if (si_pi->pspp_notify_required) { 5679 if (target_link_speed == RADEON_PCIE_GEN3) 5680 request = PCIE_PERF_REQ_PECI_GEN3; 5681 else if (target_link_speed == RADEON_PCIE_GEN2) 5682 request = PCIE_PERF_REQ_PECI_GEN2; 5683 else 5684 request = PCIE_PERF_REQ_PECI_GEN1; 5685 5686 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5687 (si_get_current_pcie_speed(rdev) > 0)) 5688 return; 5689 5690 #if defined(CONFIG_ACPI) 5691 radeon_acpi_pcie_performance_request(rdev, request, false); 5692 #endif 5693 } 5694 } 5695 5696 #if 0 5697 static int si_ds_request(struct radeon_device *rdev, 5698 bool ds_status_on, u32 count_write) 5699 { 5700 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5701 5702 if (eg_pi->sclk_deep_sleep) { 5703 if (ds_status_on) 5704 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5705 PPSMC_Result_OK) ? 5706 0 : -EINVAL; 5707 else 5708 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5709 PPSMC_Result_OK) ? 0 : -EINVAL; 5710 } 5711 return 0; 5712 } 5713 #endif 5714 5715 static void si_set_max_cu_value(struct radeon_device *rdev) 5716 { 5717 struct si_power_info *si_pi = si_get_pi(rdev); 5718 5719 if (rdev->family == CHIP_VERDE) { 5720 switch (rdev->pdev->device) { 5721 case 0x6820: 5722 case 0x6825: 5723 case 0x6821: 5724 case 0x6823: 5725 case 0x6827: 5726 si_pi->max_cu = 10; 5727 break; 5728 case 0x682D: 5729 case 0x6824: 5730 case 0x682F: 5731 case 0x6826: 5732 si_pi->max_cu = 8; 5733 break; 5734 case 0x6828: 5735 case 0x6830: 5736 case 0x6831: 5737 case 0x6838: 5738 case 0x6839: 5739 case 0x683D: 5740 si_pi->max_cu = 10; 5741 break; 5742 case 0x683B: 5743 case 0x683F: 5744 case 0x6829: 5745 si_pi->max_cu = 8; 5746 break; 5747 default: 5748 si_pi->max_cu = 0; 5749 break; 5750 } 5751 } else { 5752 si_pi->max_cu = 0; 5753 } 5754 } 5755 5756 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5757 struct radeon_clock_voltage_dependency_table *table) 5758 { 5759 u32 i; 5760 int j; 5761 u16 leakage_voltage; 5762 5763 if (table) { 5764 for (i = 0; i < table->count; i++) { 5765 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5766 table->entries[i].v, 5767 &leakage_voltage)) { 5768 case 0: 5769 table->entries[i].v = leakage_voltage; 5770 break; 5771 case -EAGAIN: 5772 return -EINVAL; 5773 case -EINVAL: 5774 default: 5775 break; 5776 } 5777 } 5778 5779 for (j = (table->count - 2); j >= 0; j--) { 5780 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5781 table->entries[j].v : table->entries[j + 1].v; 5782 } 5783 } 5784 return 0; 5785 } 5786 5787 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5788 { 5789 int ret = 0; 5790 5791 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5792 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5793 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5794 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5795 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5796 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5797 return ret; 5798 } 5799 5800 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5801 struct radeon_ps *radeon_new_state, 5802 struct radeon_ps *radeon_current_state) 5803 { 5804 u32 lane_width; 5805 u32 new_lane_width = 5806 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5807 u32 current_lane_width = 5808 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5809 5810 if (new_lane_width != current_lane_width) { 5811 radeon_set_pcie_lanes(rdev, new_lane_width); 5812 lane_width = radeon_get_pcie_lanes(rdev); 5813 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5814 } 5815 } 5816 5817 void si_dpm_setup_asic(struct radeon_device *rdev) 5818 { 5819 int r; 5820 5821 r = si_mc_load_microcode(rdev); 5822 if (r) 5823 DRM_ERROR("Failed to load MC firmware!\n"); 5824 rv770_get_memory_type(rdev); 5825 si_read_clock_registers(rdev); 5826 si_enable_acpi_power_management(rdev); 5827 } 5828 5829 static int si_thermal_enable_alert(struct radeon_device *rdev, 5830 bool enable) 5831 { 5832 u32 thermal_int = RREG32(CG_THERMAL_INT); 5833 5834 if (enable) { 5835 PPSMC_Result result; 5836 5837 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5838 WREG32(CG_THERMAL_INT, thermal_int); 5839 rdev->irq.dpm_thermal = false; 5840 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5841 if (result != PPSMC_Result_OK) { 5842 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5843 return -EINVAL; 5844 } 5845 } else { 5846 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5847 WREG32(CG_THERMAL_INT, thermal_int); 5848 rdev->irq.dpm_thermal = true; 5849 } 5850 5851 return 0; 5852 } 5853 5854 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5855 int min_temp, int max_temp) 5856 { 5857 int low_temp = 0 * 1000; 5858 int high_temp = 255 * 1000; 5859 5860 if (low_temp < min_temp) 5861 low_temp = min_temp; 5862 if (high_temp > max_temp) 5863 high_temp = max_temp; 5864 if (high_temp < low_temp) { 5865 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5866 return -EINVAL; 5867 } 5868 5869 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5870 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5871 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5872 5873 rdev->pm.dpm.thermal.min_temp = low_temp; 5874 rdev->pm.dpm.thermal.max_temp = high_temp; 5875 5876 return 0; 5877 } 5878 5879 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 5880 { 5881 struct si_power_info *si_pi = si_get_pi(rdev); 5882 u32 tmp; 5883 5884 if (si_pi->fan_ctrl_is_in_default_mode) { 5885 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 5886 si_pi->fan_ctrl_default_mode = tmp; 5887 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 5888 si_pi->t_min = tmp; 5889 si_pi->fan_ctrl_is_in_default_mode = false; 5890 } 5891 5892 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 5893 tmp |= TMIN(0); 5894 WREG32(CG_FDO_CTRL2, tmp); 5895 5896 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 5897 tmp |= FDO_PWM_MODE(mode); 5898 WREG32(CG_FDO_CTRL2, tmp); 5899 } 5900 5901 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 5902 { 5903 struct si_power_info *si_pi = si_get_pi(rdev); 5904 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 5905 u32 duty100; 5906 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 5907 u16 fdo_min, slope1, slope2; 5908 u32 reference_clock, tmp; 5909 int ret; 5910 u64 tmp64; 5911 5912 if (!si_pi->fan_table_start) { 5913 rdev->pm.dpm.fan.ucode_fan_control = false; 5914 return 0; 5915 } 5916 5917 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 5918 5919 if (duty100 == 0) { 5920 rdev->pm.dpm.fan.ucode_fan_control = false; 5921 return 0; 5922 } 5923 5924 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 5925 do_div(tmp64, 10000); 5926 fdo_min = (u16)tmp64; 5927 5928 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 5929 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 5930 5931 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 5932 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 5933 5934 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 5935 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 5936 5937 fan_table.slope1 = cpu_to_be16(slope1); 5938 fan_table.slope2 = cpu_to_be16(slope2); 5939 5940 fan_table.fdo_min = cpu_to_be16(fdo_min); 5941 5942 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 5943 5944 fan_table.hys_up = cpu_to_be16(1); 5945 5946 fan_table.hys_slope = cpu_to_be16(1); 5947 5948 fan_table.temp_resp_lim = cpu_to_be16(5); 5949 5950 reference_clock = radeon_get_xclk(rdev); 5951 5952 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 5953 reference_clock) / 1600); 5954 5955 fan_table.fdo_max = cpu_to_be16((u16)duty100); 5956 5957 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 5958 fan_table.temp_src = (uint8_t)tmp; 5959 5960 ret = si_copy_bytes_to_smc(rdev, 5961 si_pi->fan_table_start, 5962 (u8 *)(&fan_table), 5963 sizeof(fan_table), 5964 si_pi->sram_end); 5965 5966 if (ret) { 5967 DRM_ERROR("Failed to load fan table to the SMC."); 5968 rdev->pm.dpm.fan.ucode_fan_control = false; 5969 } 5970 5971 return 0; 5972 } 5973 5974 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 5975 { 5976 PPSMC_Result ret; 5977 5978 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 5979 if (ret == PPSMC_Result_OK) 5980 return 0; 5981 else 5982 return -EINVAL; 5983 } 5984 5985 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 5986 { 5987 PPSMC_Result ret; 5988 5989 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 5990 if (ret == PPSMC_Result_OK) 5991 return 0; 5992 else 5993 return -EINVAL; 5994 } 5995 5996 #if 0 5997 static int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 5998 u32 *speed) 5999 { 6000 u32 duty, duty100; 6001 u64 tmp64; 6002 6003 if (rdev->pm.no_fan) 6004 return -ENOENT; 6005 6006 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6007 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6008 6009 if (duty100 == 0) 6010 return -EINVAL; 6011 6012 tmp64 = (u64)duty * 100; 6013 do_div(tmp64, duty100); 6014 *speed = (u32)tmp64; 6015 6016 if (*speed > 100) 6017 *speed = 100; 6018 6019 return 0; 6020 } 6021 6022 static int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6023 u32 speed) 6024 { 6025 u32 tmp; 6026 u32 duty, duty100; 6027 u64 tmp64; 6028 6029 if (rdev->pm.no_fan) 6030 return -ENOENT; 6031 6032 if (speed > 100) 6033 return -EINVAL; 6034 6035 if (rdev->pm.dpm.fan.ucode_fan_control) 6036 si_fan_ctrl_stop_smc_fan_control(rdev); 6037 6038 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6039 6040 if (duty100 == 0) 6041 return -EINVAL; 6042 6043 tmp64 = (u64)speed * duty100; 6044 do_div(tmp64, 100); 6045 duty = (u32)tmp64; 6046 6047 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6048 tmp |= FDO_STATIC_DUTY(duty); 6049 WREG32(CG_FDO_CTRL0, tmp); 6050 6051 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6052 6053 return 0; 6054 } 6055 6056 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6057 u32 *speed) 6058 { 6059 u32 tach_period; 6060 u32 xclk = radeon_get_xclk(rdev); 6061 6062 if (rdev->pm.no_fan) 6063 return -ENOENT; 6064 6065 if (rdev->pm.fan_pulses_per_revolution == 0) 6066 return -ENOENT; 6067 6068 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6069 if (tach_period == 0) 6070 return -ENOENT; 6071 6072 *speed = 60 * xclk * 10000 / tach_period; 6073 6074 return 0; 6075 } 6076 6077 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6078 u32 speed) 6079 { 6080 u32 tach_period, tmp; 6081 u32 xclk = radeon_get_xclk(rdev); 6082 6083 if (rdev->pm.no_fan) 6084 return -ENOENT; 6085 6086 if (rdev->pm.fan_pulses_per_revolution == 0) 6087 return -ENOENT; 6088 6089 if ((speed < rdev->pm.fan_min_rpm) || 6090 (speed > rdev->pm.fan_max_rpm)) 6091 return -EINVAL; 6092 6093 if (rdev->pm.dpm.fan.ucode_fan_control) 6094 si_fan_ctrl_stop_smc_fan_control(rdev); 6095 6096 tach_period = 60 * xclk * 10000 / (8 * speed); 6097 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6098 tmp |= TARGET_PERIOD(tach_period); 6099 WREG32(CG_TACH_CTRL, tmp); 6100 6101 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6102 6103 return 0; 6104 } 6105 #endif 6106 6107 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6108 { 6109 struct si_power_info *si_pi = si_get_pi(rdev); 6110 u32 tmp; 6111 6112 if (!si_pi->fan_ctrl_is_in_default_mode) { 6113 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6114 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6115 WREG32(CG_FDO_CTRL2, tmp); 6116 6117 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6118 tmp |= TMIN(si_pi->t_min); 6119 WREG32(CG_FDO_CTRL2, tmp); 6120 si_pi->fan_ctrl_is_in_default_mode = true; 6121 } 6122 } 6123 6124 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6125 { 6126 if (rdev->pm.dpm.fan.ucode_fan_control) { 6127 si_fan_ctrl_start_smc_fan_control(rdev); 6128 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6129 } 6130 } 6131 6132 static void si_thermal_initialize(struct radeon_device *rdev) 6133 { 6134 u32 tmp; 6135 6136 if (rdev->pm.fan_pulses_per_revolution) { 6137 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6138 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6139 WREG32(CG_TACH_CTRL, tmp); 6140 } 6141 6142 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6143 tmp |= TACH_PWM_RESP_RATE(0x28); 6144 WREG32(CG_FDO_CTRL2, tmp); 6145 } 6146 6147 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6148 { 6149 int ret; 6150 6151 si_thermal_initialize(rdev); 6152 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6153 if (ret) 6154 return ret; 6155 ret = si_thermal_enable_alert(rdev, true); 6156 if (ret) 6157 return ret; 6158 if (rdev->pm.dpm.fan.ucode_fan_control) { 6159 ret = si_halt_smc(rdev); 6160 if (ret) 6161 return ret; 6162 ret = si_thermal_setup_fan_table(rdev); 6163 if (ret) 6164 return ret; 6165 ret = si_resume_smc(rdev); 6166 if (ret) 6167 return ret; 6168 si_thermal_start_smc_fan_control(rdev); 6169 } 6170 6171 return 0; 6172 } 6173 6174 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6175 { 6176 if (!rdev->pm.no_fan) { 6177 si_fan_ctrl_set_default_mode(rdev); 6178 si_fan_ctrl_stop_smc_fan_control(rdev); 6179 } 6180 } 6181 6182 int si_dpm_enable(struct radeon_device *rdev) 6183 { 6184 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6185 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6186 struct si_power_info *si_pi = si_get_pi(rdev); 6187 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6188 int ret; 6189 6190 if (si_is_smc_running(rdev)) 6191 return -EINVAL; 6192 if (pi->voltage_control || si_pi->voltage_control_svi2) 6193 si_enable_voltage_control(rdev, true); 6194 if (pi->mvdd_control) 6195 si_get_mvdd_configuration(rdev); 6196 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6197 ret = si_construct_voltage_tables(rdev); 6198 if (ret) { 6199 DRM_ERROR("si_construct_voltage_tables failed\n"); 6200 return ret; 6201 } 6202 } 6203 if (eg_pi->dynamic_ac_timing) { 6204 ret = si_initialize_mc_reg_table(rdev); 6205 if (ret) 6206 eg_pi->dynamic_ac_timing = false; 6207 } 6208 if (pi->dynamic_ss) 6209 si_enable_spread_spectrum(rdev, true); 6210 if (pi->thermal_protection) 6211 si_enable_thermal_protection(rdev, true); 6212 si_setup_bsp(rdev); 6213 si_program_git(rdev); 6214 si_program_tp(rdev); 6215 si_program_tpp(rdev); 6216 si_program_sstp(rdev); 6217 si_enable_display_gap(rdev); 6218 si_program_vc(rdev); 6219 ret = si_upload_firmware(rdev); 6220 if (ret) { 6221 DRM_ERROR("si_upload_firmware failed\n"); 6222 return ret; 6223 } 6224 ret = si_process_firmware_header(rdev); 6225 if (ret) { 6226 DRM_ERROR("si_process_firmware_header failed\n"); 6227 return ret; 6228 } 6229 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6230 if (ret) { 6231 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6232 return ret; 6233 } 6234 ret = si_init_smc_table(rdev); 6235 if (ret) { 6236 DRM_ERROR("si_init_smc_table failed\n"); 6237 return ret; 6238 } 6239 ret = si_init_smc_spll_table(rdev); 6240 if (ret) { 6241 DRM_ERROR("si_init_smc_spll_table failed\n"); 6242 return ret; 6243 } 6244 ret = si_init_arb_table_index(rdev); 6245 if (ret) { 6246 DRM_ERROR("si_init_arb_table_index failed\n"); 6247 return ret; 6248 } 6249 if (eg_pi->dynamic_ac_timing) { 6250 ret = si_populate_mc_reg_table(rdev, boot_ps); 6251 if (ret) { 6252 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6253 return ret; 6254 } 6255 } 6256 ret = si_initialize_smc_cac_tables(rdev); 6257 if (ret) { 6258 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6259 return ret; 6260 } 6261 ret = si_initialize_hardware_cac_manager(rdev); 6262 if (ret) { 6263 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6264 return ret; 6265 } 6266 ret = si_initialize_smc_dte_tables(rdev); 6267 if (ret) { 6268 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6269 return ret; 6270 } 6271 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6272 if (ret) { 6273 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6274 return ret; 6275 } 6276 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6277 if (ret) { 6278 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6279 return ret; 6280 } 6281 si_program_response_times(rdev); 6282 si_program_ds_registers(rdev); 6283 si_dpm_start_smc(rdev); 6284 ret = si_notify_smc_display_change(rdev, false); 6285 if (ret) { 6286 DRM_ERROR("si_notify_smc_display_change failed\n"); 6287 return ret; 6288 } 6289 si_enable_sclk_control(rdev, true); 6290 si_start_dpm(rdev); 6291 6292 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6293 6294 si_thermal_start_thermal_controller(rdev); 6295 6296 ni_update_current_ps(rdev, boot_ps); 6297 6298 return 0; 6299 } 6300 6301 static int si_set_temperature_range(struct radeon_device *rdev) 6302 { 6303 int ret; 6304 6305 ret = si_thermal_enable_alert(rdev, false); 6306 if (ret) 6307 return ret; 6308 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6309 if (ret) 6310 return ret; 6311 ret = si_thermal_enable_alert(rdev, true); 6312 if (ret) 6313 return ret; 6314 6315 return ret; 6316 } 6317 6318 int si_dpm_late_enable(struct radeon_device *rdev) 6319 { 6320 int ret; 6321 6322 ret = si_set_temperature_range(rdev); 6323 if (ret) 6324 return ret; 6325 6326 return ret; 6327 } 6328 6329 void si_dpm_disable(struct radeon_device *rdev) 6330 { 6331 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6332 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6333 6334 if (!si_is_smc_running(rdev)) 6335 return; 6336 si_thermal_stop_thermal_controller(rdev); 6337 si_disable_ulv(rdev); 6338 si_clear_vc(rdev); 6339 if (pi->thermal_protection) 6340 si_enable_thermal_protection(rdev, false); 6341 si_enable_power_containment(rdev, boot_ps, false); 6342 si_enable_smc_cac(rdev, boot_ps, false); 6343 si_enable_spread_spectrum(rdev, false); 6344 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6345 si_stop_dpm(rdev); 6346 si_reset_to_default(rdev); 6347 si_dpm_stop_smc(rdev); 6348 si_force_switch_to_arb_f0(rdev); 6349 6350 ni_update_current_ps(rdev, boot_ps); 6351 } 6352 6353 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6354 { 6355 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6356 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6357 struct radeon_ps *new_ps = &requested_ps; 6358 6359 ni_update_requested_ps(rdev, new_ps); 6360 6361 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6362 6363 return 0; 6364 } 6365 6366 static int si_power_control_set_level(struct radeon_device *rdev) 6367 { 6368 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6369 int ret; 6370 6371 ret = si_restrict_performance_levels_before_switch(rdev); 6372 if (ret) 6373 return ret; 6374 ret = si_halt_smc(rdev); 6375 if (ret) 6376 return ret; 6377 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6378 if (ret) 6379 return ret; 6380 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6381 if (ret) 6382 return ret; 6383 ret = si_resume_smc(rdev); 6384 if (ret) 6385 return ret; 6386 ret = si_set_sw_state(rdev); 6387 if (ret) 6388 return ret; 6389 return 0; 6390 } 6391 6392 int si_dpm_set_power_state(struct radeon_device *rdev) 6393 { 6394 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6395 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6396 struct radeon_ps *old_ps = &eg_pi->current_rps; 6397 int ret; 6398 6399 ret = si_disable_ulv(rdev); 6400 if (ret) { 6401 DRM_ERROR("si_disable_ulv failed\n"); 6402 return ret; 6403 } 6404 ret = si_restrict_performance_levels_before_switch(rdev); 6405 if (ret) { 6406 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6407 return ret; 6408 } 6409 if (eg_pi->pcie_performance_request) 6410 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6411 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6412 ret = si_enable_power_containment(rdev, new_ps, false); 6413 if (ret) { 6414 DRM_ERROR("si_enable_power_containment failed\n"); 6415 return ret; 6416 } 6417 ret = si_enable_smc_cac(rdev, new_ps, false); 6418 if (ret) { 6419 DRM_ERROR("si_enable_smc_cac failed\n"); 6420 return ret; 6421 } 6422 ret = si_halt_smc(rdev); 6423 if (ret) { 6424 DRM_ERROR("si_halt_smc failed\n"); 6425 return ret; 6426 } 6427 ret = si_upload_sw_state(rdev, new_ps); 6428 if (ret) { 6429 DRM_ERROR("si_upload_sw_state failed\n"); 6430 return ret; 6431 } 6432 ret = si_upload_smc_data(rdev); 6433 if (ret) { 6434 DRM_ERROR("si_upload_smc_data failed\n"); 6435 return ret; 6436 } 6437 ret = si_upload_ulv_state(rdev); 6438 if (ret) { 6439 DRM_ERROR("si_upload_ulv_state failed\n"); 6440 return ret; 6441 } 6442 if (eg_pi->dynamic_ac_timing) { 6443 ret = si_upload_mc_reg_table(rdev, new_ps); 6444 if (ret) { 6445 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6446 return ret; 6447 } 6448 } 6449 ret = si_program_memory_timing_parameters(rdev, new_ps); 6450 if (ret) { 6451 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6452 return ret; 6453 } 6454 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6455 6456 ret = si_resume_smc(rdev); 6457 if (ret) { 6458 DRM_ERROR("si_resume_smc failed\n"); 6459 return ret; 6460 } 6461 ret = si_set_sw_state(rdev); 6462 if (ret) { 6463 DRM_ERROR("si_set_sw_state failed\n"); 6464 return ret; 6465 } 6466 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6467 if (eg_pi->pcie_performance_request) 6468 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6469 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6470 if (ret) { 6471 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6472 return ret; 6473 } 6474 ret = si_enable_smc_cac(rdev, new_ps, true); 6475 if (ret) { 6476 DRM_ERROR("si_enable_smc_cac failed\n"); 6477 return ret; 6478 } 6479 ret = si_enable_power_containment(rdev, new_ps, true); 6480 if (ret) { 6481 DRM_ERROR("si_enable_power_containment failed\n"); 6482 return ret; 6483 } 6484 6485 ret = si_power_control_set_level(rdev); 6486 if (ret) { 6487 DRM_ERROR("si_power_control_set_level failed\n"); 6488 return ret; 6489 } 6490 6491 return 0; 6492 } 6493 6494 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6495 { 6496 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6497 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6498 6499 ni_update_current_ps(rdev, new_ps); 6500 } 6501 6502 6503 void si_dpm_reset_asic(struct radeon_device *rdev) 6504 { 6505 si_restrict_performance_levels_before_switch(rdev); 6506 si_disable_ulv(rdev); 6507 si_set_boot_state(rdev); 6508 } 6509 6510 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6511 { 6512 si_program_display_gap(rdev); 6513 } 6514 6515 union power_info { 6516 struct _ATOM_POWERPLAY_INFO info; 6517 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6518 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6519 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6520 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6521 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6522 }; 6523 6524 union pplib_clock_info { 6525 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6526 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6527 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6528 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6529 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6530 }; 6531 6532 union pplib_power_state { 6533 struct _ATOM_PPLIB_STATE v1; 6534 struct _ATOM_PPLIB_STATE_V2 v2; 6535 }; 6536 6537 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6538 struct radeon_ps *rps, 6539 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6540 u8 table_rev) 6541 { 6542 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6543 rps->class = le16_to_cpu(non_clock_info->usClassification); 6544 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6545 6546 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6547 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6548 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6549 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6550 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6551 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6552 } else { 6553 rps->vclk = 0; 6554 rps->dclk = 0; 6555 } 6556 6557 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6558 rdev->pm.dpm.boot_ps = rps; 6559 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6560 rdev->pm.dpm.uvd_ps = rps; 6561 } 6562 6563 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6564 struct radeon_ps *rps, int index, 6565 union pplib_clock_info *clock_info) 6566 { 6567 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6568 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6569 struct si_power_info *si_pi = si_get_pi(rdev); 6570 struct ni_ps *ps = ni_get_ps(rps); 6571 u16 leakage_voltage; 6572 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6573 int ret; 6574 6575 ps->performance_level_count = index + 1; 6576 6577 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6578 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6579 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6580 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6581 6582 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6583 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6584 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6585 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6586 si_pi->sys_pcie_mask, 6587 si_pi->boot_pcie_gen, 6588 clock_info->si.ucPCIEGen); 6589 6590 /* patch up vddc if necessary */ 6591 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6592 &leakage_voltage); 6593 if (ret == 0) 6594 pl->vddc = leakage_voltage; 6595 6596 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6597 pi->acpi_vddc = pl->vddc; 6598 eg_pi->acpi_vddci = pl->vddci; 6599 si_pi->acpi_pcie_gen = pl->pcie_gen; 6600 } 6601 6602 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6603 index == 0) { 6604 /* XXX disable for A0 tahiti */ 6605 si_pi->ulv.supported = false; 6606 si_pi->ulv.pl = *pl; 6607 si_pi->ulv.one_pcie_lane_in_ulv = false; 6608 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6609 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6610 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6611 } 6612 6613 if (pi->min_vddc_in_table > pl->vddc) 6614 pi->min_vddc_in_table = pl->vddc; 6615 6616 if (pi->max_vddc_in_table < pl->vddc) 6617 pi->max_vddc_in_table = pl->vddc; 6618 6619 /* patch up boot state */ 6620 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6621 u16 vddc, vddci, mvdd; 6622 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6623 pl->mclk = rdev->clock.default_mclk; 6624 pl->sclk = rdev->clock.default_sclk; 6625 pl->vddc = vddc; 6626 pl->vddci = vddci; 6627 si_pi->mvdd_bootup_value = mvdd; 6628 } 6629 6630 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6631 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6632 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6633 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6634 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6635 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6636 } 6637 } 6638 6639 static int si_parse_power_table(struct radeon_device *rdev) 6640 { 6641 struct radeon_mode_info *mode_info = &rdev->mode_info; 6642 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6643 union pplib_power_state *power_state; 6644 int i, j, k, non_clock_array_index, clock_array_index; 6645 union pplib_clock_info *clock_info; 6646 struct _StateArray *state_array; 6647 struct _ClockInfoArray *clock_info_array; 6648 struct _NonClockInfoArray *non_clock_info_array; 6649 union power_info *power_info; 6650 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6651 u16 data_offset; 6652 u8 frev, crev; 6653 u8 *power_state_offset; 6654 struct ni_ps *ps; 6655 6656 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6657 &frev, &crev, &data_offset)) 6658 return -EINVAL; 6659 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6660 6661 state_array = (struct _StateArray *) 6662 (mode_info->atom_context->bios + data_offset + 6663 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6664 clock_info_array = (struct _ClockInfoArray *) 6665 (mode_info->atom_context->bios + data_offset + 6666 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6667 non_clock_info_array = (struct _NonClockInfoArray *) 6668 (mode_info->atom_context->bios + data_offset + 6669 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6670 6671 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6672 state_array->ucNumEntries, GFP_KERNEL); 6673 if (!rdev->pm.dpm.ps) 6674 return -ENOMEM; 6675 power_state_offset = (u8 *)state_array->states; 6676 for (i = 0; i < state_array->ucNumEntries; i++) { 6677 u8 *idx; 6678 power_state = (union pplib_power_state *)power_state_offset; 6679 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6680 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6681 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6682 if (!rdev->pm.power_state[i].clock_info) 6683 return -EINVAL; 6684 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6685 if (ps == NULL) { 6686 kfree(rdev->pm.dpm.ps); 6687 return -ENOMEM; 6688 } 6689 rdev->pm.dpm.ps[i].ps_priv = ps; 6690 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6691 non_clock_info, 6692 non_clock_info_array->ucEntrySize); 6693 k = 0; 6694 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6695 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6696 clock_array_index = idx[j]; 6697 if (clock_array_index >= clock_info_array->ucNumEntries) 6698 continue; 6699 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6700 break; 6701 clock_info = (union pplib_clock_info *) 6702 ((u8 *)&clock_info_array->clockInfo[0] + 6703 (clock_array_index * clock_info_array->ucEntrySize)); 6704 si_parse_pplib_clock_info(rdev, 6705 &rdev->pm.dpm.ps[i], k, 6706 clock_info); 6707 k++; 6708 } 6709 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6710 } 6711 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6712 return 0; 6713 } 6714 6715 int si_dpm_init(struct radeon_device *rdev) 6716 { 6717 struct rv7xx_power_info *pi; 6718 struct evergreen_power_info *eg_pi; 6719 struct ni_power_info *ni_pi; 6720 struct si_power_info *si_pi; 6721 struct atom_clock_dividers dividers; 6722 int ret; 6723 u32 mask; 6724 6725 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6726 if (si_pi == NULL) 6727 return -ENOMEM; 6728 rdev->pm.dpm.priv = si_pi; 6729 ni_pi = &si_pi->ni; 6730 eg_pi = &ni_pi->eg; 6731 pi = &eg_pi->rv7xx; 6732 6733 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6734 if (ret) 6735 si_pi->sys_pcie_mask = 0; 6736 else 6737 si_pi->sys_pcie_mask = mask; 6738 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6739 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6740 6741 si_set_max_cu_value(rdev); 6742 6743 rv770_get_max_vddc(rdev); 6744 si_get_leakage_vddc(rdev); 6745 si_patch_dependency_tables_based_on_leakage(rdev); 6746 6747 pi->acpi_vddc = 0; 6748 eg_pi->acpi_vddci = 0; 6749 pi->min_vddc_in_table = 0; 6750 pi->max_vddc_in_table = 0; 6751 6752 ret = r600_get_platform_caps(rdev); 6753 if (ret) 6754 return ret; 6755 6756 ret = si_parse_power_table(rdev); 6757 if (ret) 6758 return ret; 6759 ret = r600_parse_extended_power_table(rdev); 6760 if (ret) 6761 return ret; 6762 6763 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6764 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6765 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6766 r600_free_extended_power_table(rdev); 6767 return -ENOMEM; 6768 } 6769 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6770 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6771 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6772 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6773 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6774 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6775 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6776 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6777 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6778 6779 if (rdev->pm.dpm.voltage_response_time == 0) 6780 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6781 if (rdev->pm.dpm.backbias_response_time == 0) 6782 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6783 6784 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6785 0, false, ÷rs); 6786 if (ret) 6787 pi->ref_div = dividers.ref_div + 1; 6788 else 6789 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6790 6791 eg_pi->smu_uvd_hs = false; 6792 6793 pi->mclk_strobe_mode_threshold = 40000; 6794 if (si_is_special_1gb_platform(rdev)) 6795 pi->mclk_stutter_mode_threshold = 0; 6796 else 6797 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6798 pi->mclk_edc_enable_threshold = 40000; 6799 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6800 6801 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6802 6803 pi->voltage_control = 6804 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6805 VOLTAGE_OBJ_GPIO_LUT); 6806 if (!pi->voltage_control) { 6807 si_pi->voltage_control_svi2 = 6808 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6809 VOLTAGE_OBJ_SVID2); 6810 if (si_pi->voltage_control_svi2) 6811 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6812 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6813 } 6814 6815 pi->mvdd_control = 6816 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6817 VOLTAGE_OBJ_GPIO_LUT); 6818 6819 eg_pi->vddci_control = 6820 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6821 VOLTAGE_OBJ_GPIO_LUT); 6822 if (!eg_pi->vddci_control) 6823 si_pi->vddci_control_svi2 = 6824 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6825 VOLTAGE_OBJ_SVID2); 6826 6827 si_pi->vddc_phase_shed_control = 6828 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6829 VOLTAGE_OBJ_PHASE_LUT); 6830 6831 rv770_get_engine_memory_ss(rdev); 6832 6833 pi->asi = RV770_ASI_DFLT; 6834 pi->pasi = CYPRESS_HASI_DFLT; 6835 pi->vrc = SISLANDS_VRC_DFLT; 6836 6837 pi->gfx_clock_gating = true; 6838 6839 eg_pi->sclk_deep_sleep = true; 6840 si_pi->sclk_deep_sleep_above_low = false; 6841 6842 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6843 pi->thermal_protection = true; 6844 else 6845 pi->thermal_protection = false; 6846 6847 eg_pi->dynamic_ac_timing = true; 6848 6849 eg_pi->light_sleep = true; 6850 #if defined(CONFIG_ACPI) 6851 eg_pi->pcie_performance_request = 6852 radeon_acpi_is_pcie_performance_request_supported(rdev); 6853 #else 6854 eg_pi->pcie_performance_request = false; 6855 #endif 6856 6857 si_pi->sram_end = SMC_RAM_END; 6858 6859 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6860 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6861 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6862 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6863 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6864 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6865 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6866 6867 si_initialize_powertune_defaults(rdev); 6868 6869 /* make sure dc limits are valid */ 6870 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6871 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6872 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6873 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6874 6875 si_pi->fan_ctrl_is_in_default_mode = true; 6876 rdev->pm.dpm.fan.ucode_fan_control = false; 6877 6878 return 0; 6879 } 6880 6881 void si_dpm_fini(struct radeon_device *rdev) 6882 { 6883 int i; 6884 6885 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6886 kfree(rdev->pm.dpm.ps[i].ps_priv); 6887 } 6888 kfree(rdev->pm.dpm.ps); 6889 kfree(rdev->pm.dpm.priv); 6890 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6891 r600_free_extended_power_table(rdev); 6892 } 6893 6894 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6895 struct seq_file *m) 6896 { 6897 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6898 struct radeon_ps *rps = &eg_pi->current_rps; 6899 struct ni_ps *ps = ni_get_ps(rps); 6900 struct rv7xx_pl *pl; 6901 u32 current_index = 6902 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6903 CURRENT_STATE_INDEX_SHIFT; 6904 6905 if (current_index >= ps->performance_level_count) { 6906 seq_printf(m, "invalid dpm profile %d\n", current_index); 6907 } else { 6908 pl = &ps->performance_levels[current_index]; 6909 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6910 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6911 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6912 } 6913 } 6914