1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/math64.h> 25 #include <linux/seq_file.h> 26 27 #include <drm/drm_pci.h> 28 29 #include "atom.h" 30 #include "r600_dpm.h" 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "si_dpm.h" 34 #include "sid.h" 35 36 #define MC_CG_ARB_FREQ_F0 0x0a 37 #define MC_CG_ARB_FREQ_F1 0x0b 38 #define MC_CG_ARB_FREQ_F2 0x0c 39 #define MC_CG_ARB_FREQ_F3 0x0d 40 41 #define SMC_RAM_END 0x20000 42 43 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 44 45 static const struct si_cac_config_reg cac_weights_tahiti[] = 46 { 47 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 50 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 51 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 57 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 58 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 59 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 60 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 61 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 62 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 65 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 66 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 67 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 68 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 69 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 78 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 82 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 85 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 87 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 106 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 107 { 0xFFFFFFFF } 108 }; 109 110 static const struct si_cac_config_reg lcac_tahiti[] = 111 { 112 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 119 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 135 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 159 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 171 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 185 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 197 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 198 { 0xFFFFFFFF } 199 200 }; 201 202 static const struct si_cac_config_reg cac_override_tahiti[] = 203 { 204 { 0xFFFFFFFF } 205 }; 206 207 static const struct si_powertune_data powertune_data_tahiti = 208 { 209 ((1 << 16) | 27027), 210 6, 211 0, 212 4, 213 95, 214 { 215 0UL, 216 0UL, 217 4521550UL, 218 309631529UL, 219 -1270850L, 220 4513710L, 221 40 222 }, 223 595000000UL, 224 12, 225 { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0 234 }, 235 true 236 }; 237 238 static const struct si_dte_data dte_data_tahiti = 239 { 240 { 1159409, 0, 0, 0, 0 }, 241 { 777, 0, 0, 0, 0 }, 242 2, 243 54000, 244 127000, 245 25, 246 2, 247 10, 248 13, 249 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 250 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 251 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 252 85, 253 false 254 }; 255 256 static const struct si_dte_data dte_data_tahiti_le = 257 { 258 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 259 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 260 0x5, 261 0xAFC8, 262 0x64, 263 0x32, 264 1, 265 0, 266 0x10, 267 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 268 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 269 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 270 85, 271 true 272 }; 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 extern int si_mc_load_microcode(struct radeon_device *rdev); 1745 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1746 1747 static int si_populate_voltage_value(struct radeon_device *rdev, 1748 const struct atom_voltage_table *table, 1749 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1750 static int si_get_std_voltage_value(struct radeon_device *rdev, 1751 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1752 u16 *std_voltage); 1753 static int si_write_smc_soft_register(struct radeon_device *rdev, 1754 u16 reg_offset, u32 value); 1755 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1756 struct rv7xx_pl *pl, 1757 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1758 static int si_calculate_sclk_params(struct radeon_device *rdev, 1759 u32 engine_clock, 1760 SISLANDS_SMC_SCLK_VALUE *sclk); 1761 1762 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1763 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1764 1765 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1766 { 1767 struct si_power_info *pi = rdev->pm.dpm.priv; 1768 1769 return pi; 1770 } 1771 1772 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1773 u16 v, s32 t, u32 ileakage, u32 *leakage) 1774 { 1775 s64 kt, kv, leakage_w, i_leakage, vddc; 1776 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1777 s64 tmp; 1778 1779 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1780 vddc = div64_s64(drm_int2fixp(v), 1000); 1781 temperature = div64_s64(drm_int2fixp(t), 1000); 1782 1783 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1784 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1785 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1786 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1787 t_ref = drm_int2fixp(coeff->t_ref); 1788 1789 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1790 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1791 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1792 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1793 1794 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1795 1796 *leakage = drm_fixp2int(leakage_w * 1000); 1797 } 1798 1799 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1800 const struct ni_leakage_coeffients *coeff, 1801 u16 v, 1802 s32 t, 1803 u32 i_leakage, 1804 u32 *leakage) 1805 { 1806 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1807 } 1808 1809 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1810 const u32 fixed_kt, u16 v, 1811 u32 ileakage, u32 *leakage) 1812 { 1813 s64 kt, kv, leakage_w, i_leakage, vddc; 1814 1815 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1816 vddc = div64_s64(drm_int2fixp(v), 1000); 1817 1818 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1819 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1820 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1821 1822 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1823 1824 *leakage = drm_fixp2int(leakage_w * 1000); 1825 } 1826 1827 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1828 const struct ni_leakage_coeffients *coeff, 1829 const u32 fixed_kt, 1830 u16 v, 1831 u32 i_leakage, 1832 u32 *leakage) 1833 { 1834 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1835 } 1836 1837 1838 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1839 struct si_dte_data *dte_data) 1840 { 1841 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1842 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1843 u32 k = dte_data->k; 1844 u32 t_max = dte_data->max_t; 1845 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1846 u32 t_0 = dte_data->t0; 1847 u32 i; 1848 1849 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1850 dte_data->tdep_count = 3; 1851 1852 for (i = 0; i < k; i++) { 1853 dte_data->r[i] = 1854 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1855 (p_limit2 * (u32)100); 1856 } 1857 1858 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1859 1860 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1861 dte_data->tdep_r[i] = dte_data->r[4]; 1862 } 1863 } else { 1864 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1865 } 1866 } 1867 1868 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1869 { 1870 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1871 struct si_power_info *si_pi = si_get_pi(rdev); 1872 bool update_dte_from_pl2 = false; 1873 1874 if (rdev->family == CHIP_TAHITI) { 1875 si_pi->cac_weights = cac_weights_tahiti; 1876 si_pi->lcac_config = lcac_tahiti; 1877 si_pi->cac_override = cac_override_tahiti; 1878 si_pi->powertune_data = &powertune_data_tahiti; 1879 si_pi->dte_data = dte_data_tahiti; 1880 1881 switch (rdev->pdev->device) { 1882 case 0x6798: 1883 si_pi->dte_data.enable_dte_by_default = true; 1884 break; 1885 case 0x6799: 1886 si_pi->dte_data = dte_data_new_zealand; 1887 break; 1888 case 0x6790: 1889 case 0x6791: 1890 case 0x6792: 1891 case 0x679E: 1892 si_pi->dte_data = dte_data_aruba_pro; 1893 update_dte_from_pl2 = true; 1894 break; 1895 case 0x679B: 1896 si_pi->dte_data = dte_data_malta; 1897 update_dte_from_pl2 = true; 1898 break; 1899 case 0x679A: 1900 si_pi->dte_data = dte_data_tahiti_pro; 1901 update_dte_from_pl2 = true; 1902 break; 1903 default: 1904 if (si_pi->dte_data.enable_dte_by_default == true) 1905 DRM_ERROR("DTE is not enabled!\n"); 1906 break; 1907 } 1908 } else if (rdev->family == CHIP_PITCAIRN) { 1909 switch (rdev->pdev->device) { 1910 case 0x6810: 1911 case 0x6818: 1912 si_pi->cac_weights = cac_weights_pitcairn; 1913 si_pi->lcac_config = lcac_pitcairn; 1914 si_pi->cac_override = cac_override_pitcairn; 1915 si_pi->powertune_data = &powertune_data_pitcairn; 1916 si_pi->dte_data = dte_data_curacao_xt; 1917 update_dte_from_pl2 = true; 1918 break; 1919 case 0x6819: 1920 case 0x6811: 1921 si_pi->cac_weights = cac_weights_pitcairn; 1922 si_pi->lcac_config = lcac_pitcairn; 1923 si_pi->cac_override = cac_override_pitcairn; 1924 si_pi->powertune_data = &powertune_data_pitcairn; 1925 si_pi->dte_data = dte_data_curacao_pro; 1926 update_dte_from_pl2 = true; 1927 break; 1928 case 0x6800: 1929 case 0x6806: 1930 si_pi->cac_weights = cac_weights_pitcairn; 1931 si_pi->lcac_config = lcac_pitcairn; 1932 si_pi->cac_override = cac_override_pitcairn; 1933 si_pi->powertune_data = &powertune_data_pitcairn; 1934 si_pi->dte_data = dte_data_neptune_xt; 1935 update_dte_from_pl2 = true; 1936 break; 1937 default: 1938 si_pi->cac_weights = cac_weights_pitcairn; 1939 si_pi->lcac_config = lcac_pitcairn; 1940 si_pi->cac_override = cac_override_pitcairn; 1941 si_pi->powertune_data = &powertune_data_pitcairn; 1942 si_pi->dte_data = dte_data_pitcairn; 1943 break; 1944 } 1945 } else if (rdev->family == CHIP_VERDE) { 1946 si_pi->lcac_config = lcac_cape_verde; 1947 si_pi->cac_override = cac_override_cape_verde; 1948 si_pi->powertune_data = &powertune_data_cape_verde; 1949 1950 switch (rdev->pdev->device) { 1951 case 0x683B: 1952 case 0x683F: 1953 case 0x6829: 1954 case 0x6835: 1955 si_pi->cac_weights = cac_weights_cape_verde_pro; 1956 si_pi->dte_data = dte_data_cape_verde; 1957 break; 1958 case 0x682C: 1959 si_pi->cac_weights = cac_weights_cape_verde_pro; 1960 si_pi->dte_data = dte_data_sun_xt; 1961 update_dte_from_pl2 = true; 1962 break; 1963 case 0x6825: 1964 case 0x6827: 1965 si_pi->cac_weights = cac_weights_heathrow; 1966 si_pi->dte_data = dte_data_cape_verde; 1967 break; 1968 case 0x6824: 1969 case 0x682D: 1970 si_pi->cac_weights = cac_weights_chelsea_xt; 1971 si_pi->dte_data = dte_data_cape_verde; 1972 break; 1973 case 0x682F: 1974 si_pi->cac_weights = cac_weights_chelsea_pro; 1975 si_pi->dte_data = dte_data_cape_verde; 1976 break; 1977 case 0x6820: 1978 si_pi->cac_weights = cac_weights_heathrow; 1979 si_pi->dte_data = dte_data_venus_xtx; 1980 break; 1981 case 0x6821: 1982 si_pi->cac_weights = cac_weights_heathrow; 1983 si_pi->dte_data = dte_data_venus_xt; 1984 break; 1985 case 0x6823: 1986 case 0x682B: 1987 case 0x6822: 1988 case 0x682A: 1989 si_pi->cac_weights = cac_weights_chelsea_pro; 1990 si_pi->dte_data = dte_data_venus_pro; 1991 break; 1992 default: 1993 si_pi->cac_weights = cac_weights_cape_verde; 1994 si_pi->dte_data = dte_data_cape_verde; 1995 break; 1996 } 1997 } else if (rdev->family == CHIP_OLAND) { 1998 switch (rdev->pdev->device) { 1999 case 0x6601: 2000 case 0x6621: 2001 case 0x6603: 2002 case 0x6605: 2003 si_pi->cac_weights = cac_weights_mars_pro; 2004 si_pi->lcac_config = lcac_mars_pro; 2005 si_pi->cac_override = cac_override_oland; 2006 si_pi->powertune_data = &powertune_data_mars_pro; 2007 si_pi->dte_data = dte_data_mars_pro; 2008 update_dte_from_pl2 = true; 2009 break; 2010 case 0x6600: 2011 case 0x6606: 2012 case 0x6620: 2013 case 0x6604: 2014 si_pi->cac_weights = cac_weights_mars_xt; 2015 si_pi->lcac_config = lcac_mars_pro; 2016 si_pi->cac_override = cac_override_oland; 2017 si_pi->powertune_data = &powertune_data_mars_pro; 2018 si_pi->dte_data = dte_data_mars_pro; 2019 update_dte_from_pl2 = true; 2020 break; 2021 case 0x6611: 2022 case 0x6613: 2023 case 0x6608: 2024 si_pi->cac_weights = cac_weights_oland_pro; 2025 si_pi->lcac_config = lcac_mars_pro; 2026 si_pi->cac_override = cac_override_oland; 2027 si_pi->powertune_data = &powertune_data_mars_pro; 2028 si_pi->dte_data = dte_data_mars_pro; 2029 update_dte_from_pl2 = true; 2030 break; 2031 case 0x6610: 2032 si_pi->cac_weights = cac_weights_oland_xt; 2033 si_pi->lcac_config = lcac_mars_pro; 2034 si_pi->cac_override = cac_override_oland; 2035 si_pi->powertune_data = &powertune_data_mars_pro; 2036 si_pi->dte_data = dte_data_mars_pro; 2037 update_dte_from_pl2 = true; 2038 break; 2039 default: 2040 si_pi->cac_weights = cac_weights_oland; 2041 si_pi->lcac_config = lcac_oland; 2042 si_pi->cac_override = cac_override_oland; 2043 si_pi->powertune_data = &powertune_data_oland; 2044 si_pi->dte_data = dte_data_oland; 2045 break; 2046 } 2047 } else if (rdev->family == CHIP_HAINAN) { 2048 si_pi->cac_weights = cac_weights_hainan; 2049 si_pi->lcac_config = lcac_oland; 2050 si_pi->cac_override = cac_override_oland; 2051 si_pi->powertune_data = &powertune_data_hainan; 2052 si_pi->dte_data = dte_data_sun_xt; 2053 update_dte_from_pl2 = true; 2054 } else { 2055 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2056 return; 2057 } 2058 2059 ni_pi->enable_power_containment = false; 2060 ni_pi->enable_cac = false; 2061 ni_pi->enable_sq_ramping = false; 2062 si_pi->enable_dte = false; 2063 2064 if (si_pi->powertune_data->enable_powertune_by_default) { 2065 ni_pi->enable_power_containment= true; 2066 ni_pi->enable_cac = true; 2067 if (si_pi->dte_data.enable_dte_by_default) { 2068 si_pi->enable_dte = true; 2069 if (update_dte_from_pl2) 2070 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2071 2072 } 2073 ni_pi->enable_sq_ramping = true; 2074 } 2075 2076 ni_pi->driver_calculate_cac_leakage = true; 2077 ni_pi->cac_configuration_required = true; 2078 2079 if (ni_pi->cac_configuration_required) { 2080 ni_pi->support_cac_long_term_average = true; 2081 si_pi->dyn_powertune_data.l2_lta_window_size = 2082 si_pi->powertune_data->l2_lta_window_size_default; 2083 si_pi->dyn_powertune_data.lts_truncate = 2084 si_pi->powertune_data->lts_truncate_default; 2085 } else { 2086 ni_pi->support_cac_long_term_average = false; 2087 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2088 si_pi->dyn_powertune_data.lts_truncate = 0; 2089 } 2090 2091 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2092 } 2093 2094 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2095 { 2096 return 1; 2097 } 2098 2099 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2100 { 2101 u32 xclk; 2102 u32 wintime; 2103 u32 cac_window; 2104 u32 cac_window_size; 2105 2106 xclk = radeon_get_xclk(rdev); 2107 2108 if (xclk == 0) 2109 return 0; 2110 2111 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2112 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2113 2114 wintime = (cac_window_size * 100) / xclk; 2115 2116 return wintime; 2117 } 2118 2119 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2120 { 2121 return power_in_watts; 2122 } 2123 2124 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2125 bool adjust_polarity, 2126 u32 tdp_adjustment, 2127 u32 *tdp_limit, 2128 u32 *near_tdp_limit) 2129 { 2130 u32 adjustment_delta, max_tdp_limit; 2131 2132 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2133 return -EINVAL; 2134 2135 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2136 2137 if (adjust_polarity) { 2138 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2139 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2140 } else { 2141 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2142 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2143 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2144 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2145 else 2146 *near_tdp_limit = 0; 2147 } 2148 2149 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2150 return -EINVAL; 2151 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2152 return -EINVAL; 2153 2154 return 0; 2155 } 2156 2157 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2158 struct radeon_ps *radeon_state) 2159 { 2160 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2161 struct si_power_info *si_pi = si_get_pi(rdev); 2162 2163 if (ni_pi->enable_power_containment) { 2164 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2165 PP_SIslands_PAPMParameters *papm_parm; 2166 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2167 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2168 u32 tdp_limit; 2169 u32 near_tdp_limit; 2170 int ret; 2171 2172 if (scaling_factor == 0) 2173 return -EINVAL; 2174 2175 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2176 2177 ret = si_calculate_adjusted_tdp_limits(rdev, 2178 false, /* ??? */ 2179 rdev->pm.dpm.tdp_adjustment, 2180 &tdp_limit, 2181 &near_tdp_limit); 2182 if (ret) 2183 return ret; 2184 2185 smc_table->dpm2Params.TDPLimit = 2186 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2187 smc_table->dpm2Params.NearTDPLimit = 2188 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2189 smc_table->dpm2Params.SafePowerLimit = 2190 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2191 2192 ret = si_copy_bytes_to_smc(rdev, 2193 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2194 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2195 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2196 sizeof(u32) * 3, 2197 si_pi->sram_end); 2198 if (ret) 2199 return ret; 2200 2201 if (si_pi->enable_ppm) { 2202 papm_parm = &si_pi->papm_parm; 2203 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2204 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2205 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2206 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2207 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2208 papm_parm->PlatformPowerLimit = 0xffffffff; 2209 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2210 2211 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2212 (u8 *)papm_parm, 2213 sizeof(PP_SIslands_PAPMParameters), 2214 si_pi->sram_end); 2215 if (ret) 2216 return ret; 2217 } 2218 } 2219 return 0; 2220 } 2221 2222 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2223 struct radeon_ps *radeon_state) 2224 { 2225 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2226 struct si_power_info *si_pi = si_get_pi(rdev); 2227 2228 if (ni_pi->enable_power_containment) { 2229 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2230 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2231 int ret; 2232 2233 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2234 2235 smc_table->dpm2Params.NearTDPLimit = 2236 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2237 smc_table->dpm2Params.SafePowerLimit = 2238 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2239 2240 ret = si_copy_bytes_to_smc(rdev, 2241 (si_pi->state_table_start + 2242 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2243 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2244 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2245 sizeof(u32) * 2, 2246 si_pi->sram_end); 2247 if (ret) 2248 return ret; 2249 } 2250 2251 return 0; 2252 } 2253 2254 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2255 const u16 prev_std_vddc, 2256 const u16 curr_std_vddc) 2257 { 2258 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2259 u64 prev_vddc = (u64)prev_std_vddc; 2260 u64 curr_vddc = (u64)curr_std_vddc; 2261 u64 pwr_efficiency_ratio, n, d; 2262 2263 if ((prev_vddc == 0) || (curr_vddc == 0)) 2264 return 0; 2265 2266 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2267 d = prev_vddc * prev_vddc; 2268 pwr_efficiency_ratio = div64_u64(n, d); 2269 2270 if (pwr_efficiency_ratio > (u64)0xFFFF) 2271 return 0; 2272 2273 return (u16)pwr_efficiency_ratio; 2274 } 2275 2276 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2277 struct radeon_ps *radeon_state) 2278 { 2279 struct si_power_info *si_pi = si_get_pi(rdev); 2280 2281 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2282 radeon_state->vclk && radeon_state->dclk) 2283 return true; 2284 2285 return false; 2286 } 2287 2288 static int si_populate_power_containment_values(struct radeon_device *rdev, 2289 struct radeon_ps *radeon_state, 2290 SISLANDS_SMC_SWSTATE *smc_state) 2291 { 2292 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2293 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2294 struct ni_ps *state = ni_get_ps(radeon_state); 2295 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2296 u32 prev_sclk; 2297 u32 max_sclk; 2298 u32 min_sclk; 2299 u16 prev_std_vddc; 2300 u16 curr_std_vddc; 2301 int i; 2302 u16 pwr_efficiency_ratio; 2303 u8 max_ps_percent; 2304 bool disable_uvd_power_tune; 2305 int ret; 2306 2307 if (ni_pi->enable_power_containment == false) 2308 return 0; 2309 2310 if (state->performance_level_count == 0) 2311 return -EINVAL; 2312 2313 if (smc_state->levelCount != state->performance_level_count) 2314 return -EINVAL; 2315 2316 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2317 2318 smc_state->levels[0].dpm2.MaxPS = 0; 2319 smc_state->levels[0].dpm2.NearTDPDec = 0; 2320 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2321 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2322 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2323 2324 for (i = 1; i < state->performance_level_count; i++) { 2325 prev_sclk = state->performance_levels[i-1].sclk; 2326 max_sclk = state->performance_levels[i].sclk; 2327 if (i == 1) 2328 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2329 else 2330 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2331 2332 if (prev_sclk > max_sclk) 2333 return -EINVAL; 2334 2335 if ((max_ps_percent == 0) || 2336 (prev_sclk == max_sclk) || 2337 disable_uvd_power_tune) { 2338 min_sclk = max_sclk; 2339 } else if (i == 1) { 2340 min_sclk = prev_sclk; 2341 } else { 2342 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2343 } 2344 2345 if (min_sclk < state->performance_levels[0].sclk) 2346 min_sclk = state->performance_levels[0].sclk; 2347 2348 if (min_sclk == 0) 2349 return -EINVAL; 2350 2351 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2352 state->performance_levels[i-1].vddc, &vddc); 2353 if (ret) 2354 return ret; 2355 2356 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2357 if (ret) 2358 return ret; 2359 2360 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2361 state->performance_levels[i].vddc, &vddc); 2362 if (ret) 2363 return ret; 2364 2365 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2366 if (ret) 2367 return ret; 2368 2369 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2370 prev_std_vddc, curr_std_vddc); 2371 2372 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2373 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2374 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2375 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2376 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2377 } 2378 2379 return 0; 2380 } 2381 2382 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2383 struct radeon_ps *radeon_state, 2384 SISLANDS_SMC_SWSTATE *smc_state) 2385 { 2386 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2387 struct ni_ps *state = ni_get_ps(radeon_state); 2388 u32 sq_power_throttle, sq_power_throttle2; 2389 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2390 int i; 2391 2392 if (state->performance_level_count == 0) 2393 return -EINVAL; 2394 2395 if (smc_state->levelCount != state->performance_level_count) 2396 return -EINVAL; 2397 2398 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2399 return -EINVAL; 2400 2401 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2402 enable_sq_ramping = false; 2403 2404 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2405 enable_sq_ramping = false; 2406 2407 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2408 enable_sq_ramping = false; 2409 2410 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2411 enable_sq_ramping = false; 2412 2413 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2414 enable_sq_ramping = false; 2415 2416 for (i = 0; i < state->performance_level_count; i++) { 2417 sq_power_throttle = 0; 2418 sq_power_throttle2 = 0; 2419 2420 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2421 enable_sq_ramping) { 2422 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2423 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2424 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2425 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2426 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2427 } else { 2428 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2429 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2430 } 2431 2432 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2433 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2434 } 2435 2436 return 0; 2437 } 2438 2439 static int si_enable_power_containment(struct radeon_device *rdev, 2440 struct radeon_ps *radeon_new_state, 2441 bool enable) 2442 { 2443 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2444 PPSMC_Result smc_result; 2445 int ret = 0; 2446 2447 if (ni_pi->enable_power_containment) { 2448 if (enable) { 2449 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2450 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2451 if (smc_result != PPSMC_Result_OK) { 2452 ret = -EINVAL; 2453 ni_pi->pc_enabled = false; 2454 } else { 2455 ni_pi->pc_enabled = true; 2456 } 2457 } 2458 } else { 2459 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2460 if (smc_result != PPSMC_Result_OK) 2461 ret = -EINVAL; 2462 ni_pi->pc_enabled = false; 2463 } 2464 } 2465 2466 return ret; 2467 } 2468 2469 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2470 { 2471 struct si_power_info *si_pi = si_get_pi(rdev); 2472 int ret = 0; 2473 struct si_dte_data *dte_data = &si_pi->dte_data; 2474 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2475 u32 table_size; 2476 u8 tdep_count; 2477 u32 i; 2478 2479 if (dte_data == NULL) 2480 si_pi->enable_dte = false; 2481 2482 if (si_pi->enable_dte == false) 2483 return 0; 2484 2485 if (dte_data->k <= 0) 2486 return -EINVAL; 2487 2488 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2489 if (dte_tables == NULL) { 2490 si_pi->enable_dte = false; 2491 return -ENOMEM; 2492 } 2493 2494 table_size = dte_data->k; 2495 2496 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2497 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2498 2499 tdep_count = dte_data->tdep_count; 2500 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2501 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2502 2503 dte_tables->K = cpu_to_be32(table_size); 2504 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2505 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2506 dte_tables->WindowSize = dte_data->window_size; 2507 dte_tables->temp_select = dte_data->temp_select; 2508 dte_tables->DTE_mode = dte_data->dte_mode; 2509 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2510 2511 if (tdep_count > 0) 2512 table_size--; 2513 2514 for (i = 0; i < table_size; i++) { 2515 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2516 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2517 } 2518 2519 dte_tables->Tdep_count = tdep_count; 2520 2521 for (i = 0; i < (u32)tdep_count; i++) { 2522 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2523 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2524 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2525 } 2526 2527 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2528 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2529 kfree(dte_tables); 2530 2531 return ret; 2532 } 2533 2534 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2535 u16 *max, u16 *min) 2536 { 2537 struct si_power_info *si_pi = si_get_pi(rdev); 2538 struct radeon_cac_leakage_table *table = 2539 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2540 u32 i; 2541 u32 v0_loadline; 2542 2543 2544 if (table == NULL) 2545 return -EINVAL; 2546 2547 *max = 0; 2548 *min = 0xFFFF; 2549 2550 for (i = 0; i < table->count; i++) { 2551 if (table->entries[i].vddc > *max) 2552 *max = table->entries[i].vddc; 2553 if (table->entries[i].vddc < *min) 2554 *min = table->entries[i].vddc; 2555 } 2556 2557 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2558 return -EINVAL; 2559 2560 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2561 2562 if (v0_loadline > 0xFFFFUL) 2563 return -EINVAL; 2564 2565 *min = (u16)v0_loadline; 2566 2567 if ((*min > *max) || (*max == 0) || (*min == 0)) 2568 return -EINVAL; 2569 2570 return 0; 2571 } 2572 2573 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2574 { 2575 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2576 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2577 } 2578 2579 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2580 PP_SIslands_CacConfig *cac_tables, 2581 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2582 u16 t0, u16 t_step) 2583 { 2584 struct si_power_info *si_pi = si_get_pi(rdev); 2585 u32 leakage; 2586 unsigned int i, j; 2587 s32 t; 2588 u32 smc_leakage; 2589 u32 scaling_factor; 2590 u16 voltage; 2591 2592 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2593 2594 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2595 t = (1000 * (i * t_step + t0)); 2596 2597 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2598 voltage = vddc_max - (vddc_step * j); 2599 2600 si_calculate_leakage_for_v_and_t(rdev, 2601 &si_pi->powertune_data->leakage_coefficients, 2602 voltage, 2603 t, 2604 si_pi->dyn_powertune_data.cac_leakage, 2605 &leakage); 2606 2607 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2608 2609 if (smc_leakage > 0xFFFF) 2610 smc_leakage = 0xFFFF; 2611 2612 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2613 cpu_to_be16((u16)smc_leakage); 2614 } 2615 } 2616 return 0; 2617 } 2618 2619 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2620 PP_SIslands_CacConfig *cac_tables, 2621 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2622 { 2623 struct si_power_info *si_pi = si_get_pi(rdev); 2624 u32 leakage; 2625 unsigned int i, j; 2626 u32 smc_leakage; 2627 u32 scaling_factor; 2628 u16 voltage; 2629 2630 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2631 2632 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2633 voltage = vddc_max - (vddc_step * j); 2634 2635 si_calculate_leakage_for_v(rdev, 2636 &si_pi->powertune_data->leakage_coefficients, 2637 si_pi->powertune_data->fixed_kt, 2638 voltage, 2639 si_pi->dyn_powertune_data.cac_leakage, 2640 &leakage); 2641 2642 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2643 2644 if (smc_leakage > 0xFFFF) 2645 smc_leakage = 0xFFFF; 2646 2647 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2648 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2649 cpu_to_be16((u16)smc_leakage); 2650 } 2651 return 0; 2652 } 2653 2654 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2655 { 2656 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2657 struct si_power_info *si_pi = si_get_pi(rdev); 2658 PP_SIslands_CacConfig *cac_tables = NULL; 2659 u16 vddc_max, vddc_min, vddc_step; 2660 u16 t0, t_step; 2661 u32 load_line_slope, reg; 2662 int ret = 0; 2663 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2664 2665 if (ni_pi->enable_cac == false) 2666 return 0; 2667 2668 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2669 if (!cac_tables) 2670 return -ENOMEM; 2671 2672 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2673 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2674 WREG32(CG_CAC_CTRL, reg); 2675 2676 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2677 si_pi->dyn_powertune_data.dc_pwr_value = 2678 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2679 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2680 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2681 2682 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2683 2684 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2685 if (ret) 2686 goto done_free; 2687 2688 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2689 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2690 t_step = 4; 2691 t0 = 60; 2692 2693 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2694 ret = si_init_dte_leakage_table(rdev, cac_tables, 2695 vddc_max, vddc_min, vddc_step, 2696 t0, t_step); 2697 else 2698 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2699 vddc_max, vddc_min, vddc_step); 2700 if (ret) 2701 goto done_free; 2702 2703 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2704 2705 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2706 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2707 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2708 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2709 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2710 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2711 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2712 cac_tables->calculation_repeats = cpu_to_be32(2); 2713 cac_tables->dc_cac = cpu_to_be32(0); 2714 cac_tables->log2_PG_LKG_SCALE = 12; 2715 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2716 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2717 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2718 2719 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2720 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2721 2722 if (ret) 2723 goto done_free; 2724 2725 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2726 2727 done_free: 2728 if (ret) { 2729 ni_pi->enable_cac = false; 2730 ni_pi->enable_power_containment = false; 2731 } 2732 2733 kfree(cac_tables); 2734 2735 return 0; 2736 } 2737 2738 static int si_program_cac_config_registers(struct radeon_device *rdev, 2739 const struct si_cac_config_reg *cac_config_regs) 2740 { 2741 const struct si_cac_config_reg *config_regs = cac_config_regs; 2742 u32 data = 0, offset; 2743 2744 if (!config_regs) 2745 return -EINVAL; 2746 2747 while (config_regs->offset != 0xFFFFFFFF) { 2748 switch (config_regs->type) { 2749 case SISLANDS_CACCONFIG_CGIND: 2750 offset = SMC_CG_IND_START + config_regs->offset; 2751 if (offset < SMC_CG_IND_END) 2752 data = RREG32_SMC(offset); 2753 break; 2754 default: 2755 data = RREG32(config_regs->offset << 2); 2756 break; 2757 } 2758 2759 data &= ~config_regs->mask; 2760 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2761 2762 switch (config_regs->type) { 2763 case SISLANDS_CACCONFIG_CGIND: 2764 offset = SMC_CG_IND_START + config_regs->offset; 2765 if (offset < SMC_CG_IND_END) 2766 WREG32_SMC(offset, data); 2767 break; 2768 default: 2769 WREG32(config_regs->offset << 2, data); 2770 break; 2771 } 2772 config_regs++; 2773 } 2774 return 0; 2775 } 2776 2777 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2778 { 2779 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2780 struct si_power_info *si_pi = si_get_pi(rdev); 2781 int ret; 2782 2783 if ((ni_pi->enable_cac == false) || 2784 (ni_pi->cac_configuration_required == false)) 2785 return 0; 2786 2787 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2788 if (ret) 2789 return ret; 2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2791 if (ret) 2792 return ret; 2793 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2794 if (ret) 2795 return ret; 2796 2797 return 0; 2798 } 2799 2800 static int si_enable_smc_cac(struct radeon_device *rdev, 2801 struct radeon_ps *radeon_new_state, 2802 bool enable) 2803 { 2804 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2805 struct si_power_info *si_pi = si_get_pi(rdev); 2806 PPSMC_Result smc_result; 2807 int ret = 0; 2808 2809 if (ni_pi->enable_cac) { 2810 if (enable) { 2811 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2812 if (ni_pi->support_cac_long_term_average) { 2813 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2814 if (smc_result != PPSMC_Result_OK) 2815 ni_pi->support_cac_long_term_average = false; 2816 } 2817 2818 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2819 if (smc_result != PPSMC_Result_OK) { 2820 ret = -EINVAL; 2821 ni_pi->cac_enabled = false; 2822 } else { 2823 ni_pi->cac_enabled = true; 2824 } 2825 2826 if (si_pi->enable_dte) { 2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2828 if (smc_result != PPSMC_Result_OK) 2829 ret = -EINVAL; 2830 } 2831 } 2832 } else if (ni_pi->cac_enabled) { 2833 if (si_pi->enable_dte) 2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2835 2836 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2837 2838 ni_pi->cac_enabled = false; 2839 2840 if (ni_pi->support_cac_long_term_average) 2841 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2842 } 2843 } 2844 return ret; 2845 } 2846 2847 static int si_init_smc_spll_table(struct radeon_device *rdev) 2848 { 2849 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2850 struct si_power_info *si_pi = si_get_pi(rdev); 2851 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2852 SISLANDS_SMC_SCLK_VALUE sclk_params; 2853 u32 fb_div, p_div; 2854 u32 clk_s, clk_v; 2855 u32 sclk = 0; 2856 int ret = 0; 2857 u32 tmp; 2858 int i; 2859 2860 if (si_pi->spll_table_start == 0) 2861 return -EINVAL; 2862 2863 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2864 if (spll_table == NULL) 2865 return -ENOMEM; 2866 2867 for (i = 0; i < 256; i++) { 2868 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2869 if (ret) 2870 break; 2871 2872 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2873 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2874 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2875 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2876 2877 fb_div &= ~0x00001FFF; 2878 fb_div >>= 1; 2879 clk_v >>= 6; 2880 2881 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2882 ret = -EINVAL; 2883 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2884 ret = -EINVAL; 2885 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2886 ret = -EINVAL; 2887 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2888 ret = -EINVAL; 2889 2890 if (ret) 2891 break; 2892 2893 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2894 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2895 spll_table->freq[i] = cpu_to_be32(tmp); 2896 2897 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2898 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2899 spll_table->ss[i] = cpu_to_be32(tmp); 2900 2901 sclk += 512; 2902 } 2903 2904 2905 if (!ret) 2906 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2907 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2908 si_pi->sram_end); 2909 2910 if (ret) 2911 ni_pi->enable_power_containment = false; 2912 2913 kfree(spll_table); 2914 2915 return ret; 2916 } 2917 2918 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2919 u16 vce_voltage) 2920 { 2921 u16 highest_leakage = 0; 2922 struct si_power_info *si_pi = si_get_pi(rdev); 2923 int i; 2924 2925 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2926 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2927 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2928 } 2929 2930 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2931 return highest_leakage; 2932 2933 return vce_voltage; 2934 } 2935 2936 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2937 u32 evclk, u32 ecclk, u16 *voltage) 2938 { 2939 u32 i; 2940 int ret = -EINVAL; 2941 struct radeon_vce_clock_voltage_dependency_table *table = 2942 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2943 2944 if (((evclk == 0) && (ecclk == 0)) || 2945 (table && (table->count == 0))) { 2946 *voltage = 0; 2947 return 0; 2948 } 2949 2950 for (i = 0; i < table->count; i++) { 2951 if ((evclk <= table->entries[i].evclk) && 2952 (ecclk <= table->entries[i].ecclk)) { 2953 *voltage = table->entries[i].v; 2954 ret = 0; 2955 break; 2956 } 2957 } 2958 2959 /* if no match return the highest voltage */ 2960 if (ret) 2961 *voltage = table->entries[table->count - 1].v; 2962 2963 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2964 2965 return ret; 2966 } 2967 2968 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2969 struct radeon_ps *rps) 2970 { 2971 struct ni_ps *ps = ni_get_ps(rps); 2972 struct radeon_clock_and_voltage_limits *max_limits; 2973 bool disable_mclk_switching = false; 2974 bool disable_sclk_switching = false; 2975 u32 mclk, sclk; 2976 u16 vddc, vddci, min_vce_voltage = 0; 2977 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2978 u32 max_sclk = 0, max_mclk = 0; 2979 int i; 2980 2981 if (rdev->family == CHIP_HAINAN) { 2982 if ((rdev->pdev->revision == 0x81) || 2983 (rdev->pdev->revision == 0x83) || 2984 (rdev->pdev->revision == 0xC3) || 2985 (rdev->pdev->device == 0x6664) || 2986 (rdev->pdev->device == 0x6665) || 2987 (rdev->pdev->device == 0x6667)) { 2988 max_sclk = 75000; 2989 } 2990 if ((rdev->pdev->revision == 0xC3) || 2991 (rdev->pdev->device == 0x6665)) { 2992 max_sclk = 60000; 2993 max_mclk = 80000; 2994 } 2995 } else if (rdev->family == CHIP_OLAND) { 2996 if ((rdev->pdev->revision == 0xC7) || 2997 (rdev->pdev->revision == 0x80) || 2998 (rdev->pdev->revision == 0x81) || 2999 (rdev->pdev->revision == 0x83) || 3000 (rdev->pdev->revision == 0x87) || 3001 (rdev->pdev->device == 0x6604) || 3002 (rdev->pdev->device == 0x6605)) { 3003 max_sclk = 75000; 3004 } 3005 } 3006 3007 if (rps->vce_active) { 3008 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3009 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3010 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3011 &min_vce_voltage); 3012 } else { 3013 rps->evclk = 0; 3014 rps->ecclk = 0; 3015 } 3016 3017 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3018 ni_dpm_vblank_too_short(rdev)) 3019 disable_mclk_switching = true; 3020 3021 if (rps->vclk || rps->dclk) { 3022 disable_mclk_switching = true; 3023 disable_sclk_switching = true; 3024 } 3025 3026 if (rdev->pm.dpm.ac_power) 3027 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3028 else 3029 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3030 3031 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3032 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3033 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3034 } 3035 if (rdev->pm.dpm.ac_power == false) { 3036 for (i = 0; i < ps->performance_level_count; i++) { 3037 if (ps->performance_levels[i].mclk > max_limits->mclk) 3038 ps->performance_levels[i].mclk = max_limits->mclk; 3039 if (ps->performance_levels[i].sclk > max_limits->sclk) 3040 ps->performance_levels[i].sclk = max_limits->sclk; 3041 if (ps->performance_levels[i].vddc > max_limits->vddc) 3042 ps->performance_levels[i].vddc = max_limits->vddc; 3043 if (ps->performance_levels[i].vddci > max_limits->vddci) 3044 ps->performance_levels[i].vddci = max_limits->vddci; 3045 } 3046 } 3047 3048 /* limit clocks to max supported clocks based on voltage dependency tables */ 3049 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3050 &max_sclk_vddc); 3051 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3052 &max_mclk_vddci); 3053 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3054 &max_mclk_vddc); 3055 3056 for (i = 0; i < ps->performance_level_count; i++) { 3057 if (max_sclk_vddc) { 3058 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3059 ps->performance_levels[i].sclk = max_sclk_vddc; 3060 } 3061 if (max_mclk_vddci) { 3062 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3063 ps->performance_levels[i].mclk = max_mclk_vddci; 3064 } 3065 if (max_mclk_vddc) { 3066 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3067 ps->performance_levels[i].mclk = max_mclk_vddc; 3068 } 3069 if (max_mclk) { 3070 if (ps->performance_levels[i].mclk > max_mclk) 3071 ps->performance_levels[i].mclk = max_mclk; 3072 } 3073 if (max_sclk) { 3074 if (ps->performance_levels[i].sclk > max_sclk) 3075 ps->performance_levels[i].sclk = max_sclk; 3076 } 3077 } 3078 3079 /* XXX validate the min clocks required for display */ 3080 3081 if (disable_mclk_switching) { 3082 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3083 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3084 } else { 3085 mclk = ps->performance_levels[0].mclk; 3086 vddci = ps->performance_levels[0].vddci; 3087 } 3088 3089 if (disable_sclk_switching) { 3090 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3091 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3092 } else { 3093 sclk = ps->performance_levels[0].sclk; 3094 vddc = ps->performance_levels[0].vddc; 3095 } 3096 3097 if (rps->vce_active) { 3098 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3099 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3100 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3101 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3102 } 3103 3104 /* adjusted low state */ 3105 ps->performance_levels[0].sclk = sclk; 3106 ps->performance_levels[0].mclk = mclk; 3107 ps->performance_levels[0].vddc = vddc; 3108 ps->performance_levels[0].vddci = vddci; 3109 3110 if (disable_sclk_switching) { 3111 sclk = ps->performance_levels[0].sclk; 3112 for (i = 1; i < ps->performance_level_count; i++) { 3113 if (sclk < ps->performance_levels[i].sclk) 3114 sclk = ps->performance_levels[i].sclk; 3115 } 3116 for (i = 0; i < ps->performance_level_count; i++) { 3117 ps->performance_levels[i].sclk = sclk; 3118 ps->performance_levels[i].vddc = vddc; 3119 } 3120 } else { 3121 for (i = 1; i < ps->performance_level_count; i++) { 3122 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3123 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3124 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3125 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3126 } 3127 } 3128 3129 if (disable_mclk_switching) { 3130 mclk = ps->performance_levels[0].mclk; 3131 for (i = 1; i < ps->performance_level_count; i++) { 3132 if (mclk < ps->performance_levels[i].mclk) 3133 mclk = ps->performance_levels[i].mclk; 3134 } 3135 for (i = 0; i < ps->performance_level_count; i++) { 3136 ps->performance_levels[i].mclk = mclk; 3137 ps->performance_levels[i].vddci = vddci; 3138 } 3139 } else { 3140 for (i = 1; i < ps->performance_level_count; i++) { 3141 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3142 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3143 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3144 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3145 } 3146 } 3147 3148 for (i = 0; i < ps->performance_level_count; i++) 3149 btc_adjust_clock_combinations(rdev, max_limits, 3150 &ps->performance_levels[i]); 3151 3152 for (i = 0; i < ps->performance_level_count; i++) { 3153 if (ps->performance_levels[i].vddc < min_vce_voltage) 3154 ps->performance_levels[i].vddc = min_vce_voltage; 3155 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3156 ps->performance_levels[i].sclk, 3157 max_limits->vddc, &ps->performance_levels[i].vddc); 3158 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3159 ps->performance_levels[i].mclk, 3160 max_limits->vddci, &ps->performance_levels[i].vddci); 3161 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3162 ps->performance_levels[i].mclk, 3163 max_limits->vddc, &ps->performance_levels[i].vddc); 3164 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3165 rdev->clock.current_dispclk, 3166 max_limits->vddc, &ps->performance_levels[i].vddc); 3167 } 3168 3169 for (i = 0; i < ps->performance_level_count; i++) { 3170 btc_apply_voltage_delta_rules(rdev, 3171 max_limits->vddc, max_limits->vddci, 3172 &ps->performance_levels[i].vddc, 3173 &ps->performance_levels[i].vddci); 3174 } 3175 3176 ps->dc_compatible = true; 3177 for (i = 0; i < ps->performance_level_count; i++) { 3178 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3179 ps->dc_compatible = false; 3180 } 3181 } 3182 3183 #if 0 3184 static int si_read_smc_soft_register(struct radeon_device *rdev, 3185 u16 reg_offset, u32 *value) 3186 { 3187 struct si_power_info *si_pi = si_get_pi(rdev); 3188 3189 return si_read_smc_sram_dword(rdev, 3190 si_pi->soft_regs_start + reg_offset, value, 3191 si_pi->sram_end); 3192 } 3193 #endif 3194 3195 static int si_write_smc_soft_register(struct radeon_device *rdev, 3196 u16 reg_offset, u32 value) 3197 { 3198 struct si_power_info *si_pi = si_get_pi(rdev); 3199 3200 return si_write_smc_sram_dword(rdev, 3201 si_pi->soft_regs_start + reg_offset, 3202 value, si_pi->sram_end); 3203 } 3204 3205 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3206 { 3207 bool ret = false; 3208 u32 tmp, width, row, column, bank, density; 3209 bool is_memory_gddr5, is_special; 3210 3211 tmp = RREG32(MC_SEQ_MISC0); 3212 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3213 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3214 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3215 3216 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3217 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3218 3219 tmp = RREG32(MC_ARB_RAMCFG); 3220 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3221 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3222 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3223 3224 density = (1 << (row + column - 20 + bank)) * width; 3225 3226 if ((rdev->pdev->device == 0x6819) && 3227 is_memory_gddr5 && is_special && (density == 0x400)) 3228 ret = true; 3229 3230 return ret; 3231 } 3232 3233 static void si_get_leakage_vddc(struct radeon_device *rdev) 3234 { 3235 struct si_power_info *si_pi = si_get_pi(rdev); 3236 u16 vddc, count = 0; 3237 int i, ret; 3238 3239 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3240 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3241 3242 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3243 si_pi->leakage_voltage.entries[count].voltage = vddc; 3244 si_pi->leakage_voltage.entries[count].leakage_index = 3245 SISLANDS_LEAKAGE_INDEX0 + i; 3246 count++; 3247 } 3248 } 3249 si_pi->leakage_voltage.count = count; 3250 } 3251 3252 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3253 u32 index, u16 *leakage_voltage) 3254 { 3255 struct si_power_info *si_pi = si_get_pi(rdev); 3256 int i; 3257 3258 if (leakage_voltage == NULL) 3259 return -EINVAL; 3260 3261 if ((index & 0xff00) != 0xff00) 3262 return -EINVAL; 3263 3264 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3265 return -EINVAL; 3266 3267 if (index < SISLANDS_LEAKAGE_INDEX0) 3268 return -EINVAL; 3269 3270 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3271 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3272 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3273 return 0; 3274 } 3275 } 3276 return -EAGAIN; 3277 } 3278 3279 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3280 { 3281 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3282 bool want_thermal_protection; 3283 enum radeon_dpm_event_src dpm_event_src; 3284 3285 switch (sources) { 3286 case 0: 3287 default: 3288 want_thermal_protection = false; 3289 break; 3290 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3291 want_thermal_protection = true; 3292 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3293 break; 3294 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3295 want_thermal_protection = true; 3296 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3297 break; 3298 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3299 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3300 want_thermal_protection = true; 3301 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3302 break; 3303 } 3304 3305 if (want_thermal_protection) { 3306 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3307 if (pi->thermal_protection) 3308 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3309 } else { 3310 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3311 } 3312 } 3313 3314 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3315 enum radeon_dpm_auto_throttle_src source, 3316 bool enable) 3317 { 3318 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3319 3320 if (enable) { 3321 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3322 pi->active_auto_throttle_sources |= 1 << source; 3323 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3324 } 3325 } else { 3326 if (pi->active_auto_throttle_sources & (1 << source)) { 3327 pi->active_auto_throttle_sources &= ~(1 << source); 3328 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3329 } 3330 } 3331 } 3332 3333 static void si_start_dpm(struct radeon_device *rdev) 3334 { 3335 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3336 } 3337 3338 static void si_stop_dpm(struct radeon_device *rdev) 3339 { 3340 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3341 } 3342 3343 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3344 { 3345 if (enable) 3346 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3347 else 3348 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3349 3350 } 3351 3352 #if 0 3353 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3354 u32 thermal_level) 3355 { 3356 PPSMC_Result ret; 3357 3358 if (thermal_level == 0) { 3359 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3360 if (ret == PPSMC_Result_OK) 3361 return 0; 3362 else 3363 return -EINVAL; 3364 } 3365 return 0; 3366 } 3367 3368 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3369 { 3370 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3371 } 3372 #endif 3373 3374 #if 0 3375 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3376 { 3377 if (ac_power) 3378 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3379 0 : -EINVAL; 3380 3381 return 0; 3382 } 3383 #endif 3384 3385 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3386 PPSMC_Msg msg, u32 parameter) 3387 { 3388 WREG32(SMC_SCRATCH0, parameter); 3389 return si_send_msg_to_smc(rdev, msg); 3390 } 3391 3392 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3393 { 3394 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3395 return -EINVAL; 3396 3397 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3398 0 : -EINVAL; 3399 } 3400 3401 int si_dpm_force_performance_level(struct radeon_device *rdev, 3402 enum radeon_dpm_forced_level level) 3403 { 3404 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3405 struct ni_ps *ps = ni_get_ps(rps); 3406 u32 levels = ps->performance_level_count; 3407 3408 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3409 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3410 return -EINVAL; 3411 3412 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3413 return -EINVAL; 3414 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3415 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3416 return -EINVAL; 3417 3418 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3419 return -EINVAL; 3420 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3421 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3422 return -EINVAL; 3423 3424 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3425 return -EINVAL; 3426 } 3427 3428 rdev->pm.dpm.forced_level = level; 3429 3430 return 0; 3431 } 3432 3433 #if 0 3434 static int si_set_boot_state(struct radeon_device *rdev) 3435 { 3436 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3437 0 : -EINVAL; 3438 } 3439 #endif 3440 3441 static int si_set_sw_state(struct radeon_device *rdev) 3442 { 3443 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3444 0 : -EINVAL; 3445 } 3446 3447 static int si_halt_smc(struct radeon_device *rdev) 3448 { 3449 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3450 return -EINVAL; 3451 3452 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3453 0 : -EINVAL; 3454 } 3455 3456 static int si_resume_smc(struct radeon_device *rdev) 3457 { 3458 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3459 return -EINVAL; 3460 3461 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3462 0 : -EINVAL; 3463 } 3464 3465 static void si_dpm_start_smc(struct radeon_device *rdev) 3466 { 3467 si_program_jump_on_start(rdev); 3468 si_start_smc(rdev); 3469 si_start_smc_clock(rdev); 3470 } 3471 3472 static void si_dpm_stop_smc(struct radeon_device *rdev) 3473 { 3474 si_reset_smc(rdev); 3475 si_stop_smc_clock(rdev); 3476 } 3477 3478 static int si_process_firmware_header(struct radeon_device *rdev) 3479 { 3480 struct si_power_info *si_pi = si_get_pi(rdev); 3481 u32 tmp; 3482 int ret; 3483 3484 ret = si_read_smc_sram_dword(rdev, 3485 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3486 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3487 &tmp, si_pi->sram_end); 3488 if (ret) 3489 return ret; 3490 3491 si_pi->state_table_start = tmp; 3492 3493 ret = si_read_smc_sram_dword(rdev, 3494 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3495 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3496 &tmp, si_pi->sram_end); 3497 if (ret) 3498 return ret; 3499 3500 si_pi->soft_regs_start = tmp; 3501 3502 ret = si_read_smc_sram_dword(rdev, 3503 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3504 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3505 &tmp, si_pi->sram_end); 3506 if (ret) 3507 return ret; 3508 3509 si_pi->mc_reg_table_start = tmp; 3510 3511 ret = si_read_smc_sram_dword(rdev, 3512 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3513 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3514 &tmp, si_pi->sram_end); 3515 if (ret) 3516 return ret; 3517 3518 si_pi->fan_table_start = tmp; 3519 3520 ret = si_read_smc_sram_dword(rdev, 3521 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3522 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3523 &tmp, si_pi->sram_end); 3524 if (ret) 3525 return ret; 3526 3527 si_pi->arb_table_start = tmp; 3528 3529 ret = si_read_smc_sram_dword(rdev, 3530 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3531 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3532 &tmp, si_pi->sram_end); 3533 if (ret) 3534 return ret; 3535 3536 si_pi->cac_table_start = tmp; 3537 3538 ret = si_read_smc_sram_dword(rdev, 3539 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3540 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3541 &tmp, si_pi->sram_end); 3542 if (ret) 3543 return ret; 3544 3545 si_pi->dte_table_start = tmp; 3546 3547 ret = si_read_smc_sram_dword(rdev, 3548 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3549 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3550 &tmp, si_pi->sram_end); 3551 if (ret) 3552 return ret; 3553 3554 si_pi->spll_table_start = tmp; 3555 3556 ret = si_read_smc_sram_dword(rdev, 3557 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3558 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3559 &tmp, si_pi->sram_end); 3560 if (ret) 3561 return ret; 3562 3563 si_pi->papm_cfg_table_start = tmp; 3564 3565 return ret; 3566 } 3567 3568 static void si_read_clock_registers(struct radeon_device *rdev) 3569 { 3570 struct si_power_info *si_pi = si_get_pi(rdev); 3571 3572 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3573 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3574 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3575 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3576 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3577 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3578 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3579 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3580 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3581 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3582 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3583 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3584 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3585 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3586 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3587 } 3588 3589 static void si_enable_thermal_protection(struct radeon_device *rdev, 3590 bool enable) 3591 { 3592 if (enable) 3593 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3594 else 3595 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3596 } 3597 3598 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3599 { 3600 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3601 } 3602 3603 #if 0 3604 static int si_enter_ulp_state(struct radeon_device *rdev) 3605 { 3606 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3607 3608 udelay(25000); 3609 3610 return 0; 3611 } 3612 3613 static int si_exit_ulp_state(struct radeon_device *rdev) 3614 { 3615 int i; 3616 3617 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3618 3619 udelay(7000); 3620 3621 for (i = 0; i < rdev->usec_timeout; i++) { 3622 if (RREG32(SMC_RESP_0) == 1) 3623 break; 3624 udelay(1000); 3625 } 3626 3627 return 0; 3628 } 3629 #endif 3630 3631 static int si_notify_smc_display_change(struct radeon_device *rdev, 3632 bool has_display) 3633 { 3634 PPSMC_Msg msg = has_display ? 3635 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3636 3637 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3638 0 : -EINVAL; 3639 } 3640 3641 static void si_program_response_times(struct radeon_device *rdev) 3642 { 3643 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3644 u32 vddc_dly, acpi_dly, vbi_dly; 3645 u32 reference_clock; 3646 3647 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3648 3649 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3650 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3651 3652 if (voltage_response_time == 0) 3653 voltage_response_time = 1000; 3654 3655 acpi_delay_time = 15000; 3656 vbi_time_out = 100000; 3657 3658 reference_clock = radeon_get_xclk(rdev); 3659 3660 vddc_dly = (voltage_response_time * reference_clock) / 100; 3661 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3662 vbi_dly = (vbi_time_out * reference_clock) / 100; 3663 3664 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3665 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3666 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3667 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3668 } 3669 3670 static void si_program_ds_registers(struct radeon_device *rdev) 3671 { 3672 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3673 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3674 3675 if (eg_pi->sclk_deep_sleep) { 3676 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3677 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3678 ~AUTOSCALE_ON_SS_CLEAR); 3679 } 3680 } 3681 3682 static void si_program_display_gap(struct radeon_device *rdev) 3683 { 3684 u32 tmp, pipe; 3685 int i; 3686 3687 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3688 if (rdev->pm.dpm.new_active_crtc_count > 0) 3689 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3690 else 3691 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3692 3693 if (rdev->pm.dpm.new_active_crtc_count > 1) 3694 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3695 else 3696 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3697 3698 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3699 3700 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3701 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3702 3703 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3704 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3705 /* find the first active crtc */ 3706 for (i = 0; i < rdev->num_crtc; i++) { 3707 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3708 break; 3709 } 3710 if (i == rdev->num_crtc) 3711 pipe = 0; 3712 else 3713 pipe = i; 3714 3715 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3716 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3717 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3718 } 3719 3720 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3721 * This can be a problem on PowerXpress systems or if you want to use the card 3722 * for offscreen rendering or compute if there are no crtcs enabled. 3723 */ 3724 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3725 } 3726 3727 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3728 { 3729 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3730 3731 if (enable) { 3732 if (pi->sclk_ss) 3733 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3734 } else { 3735 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3736 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3737 } 3738 } 3739 3740 static void si_setup_bsp(struct radeon_device *rdev) 3741 { 3742 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3743 u32 xclk = radeon_get_xclk(rdev); 3744 3745 r600_calculate_u_and_p(pi->asi, 3746 xclk, 3747 16, 3748 &pi->bsp, 3749 &pi->bsu); 3750 3751 r600_calculate_u_and_p(pi->pasi, 3752 xclk, 3753 16, 3754 &pi->pbsp, 3755 &pi->pbsu); 3756 3757 3758 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3759 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3760 3761 WREG32(CG_BSP, pi->dsp); 3762 } 3763 3764 static void si_program_git(struct radeon_device *rdev) 3765 { 3766 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3767 } 3768 3769 static void si_program_tp(struct radeon_device *rdev) 3770 { 3771 int i; 3772 enum r600_td td = R600_TD_DFLT; 3773 3774 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3775 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3776 3777 if (td == R600_TD_AUTO) 3778 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3779 else 3780 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3781 3782 if (td == R600_TD_UP) 3783 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3784 3785 if (td == R600_TD_DOWN) 3786 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3787 } 3788 3789 static void si_program_tpp(struct radeon_device *rdev) 3790 { 3791 WREG32(CG_TPC, R600_TPC_DFLT); 3792 } 3793 3794 static void si_program_sstp(struct radeon_device *rdev) 3795 { 3796 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3797 } 3798 3799 static void si_enable_display_gap(struct radeon_device *rdev) 3800 { 3801 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3802 3803 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3804 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3805 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3806 3807 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3808 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3809 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3810 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3811 } 3812 3813 static void si_program_vc(struct radeon_device *rdev) 3814 { 3815 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3816 3817 WREG32(CG_FTV, pi->vrc); 3818 } 3819 3820 static void si_clear_vc(struct radeon_device *rdev) 3821 { 3822 WREG32(CG_FTV, 0); 3823 } 3824 3825 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3826 { 3827 u8 mc_para_index; 3828 3829 if (memory_clock < 10000) 3830 mc_para_index = 0; 3831 else if (memory_clock >= 80000) 3832 mc_para_index = 0x0f; 3833 else 3834 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3835 return mc_para_index; 3836 } 3837 3838 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3839 { 3840 u8 mc_para_index; 3841 3842 if (strobe_mode) { 3843 if (memory_clock < 12500) 3844 mc_para_index = 0x00; 3845 else if (memory_clock > 47500) 3846 mc_para_index = 0x0f; 3847 else 3848 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3849 } else { 3850 if (memory_clock < 65000) 3851 mc_para_index = 0x00; 3852 else if (memory_clock > 135000) 3853 mc_para_index = 0x0f; 3854 else 3855 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3856 } 3857 return mc_para_index; 3858 } 3859 3860 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3861 { 3862 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3863 bool strobe_mode = false; 3864 u8 result = 0; 3865 3866 if (mclk <= pi->mclk_strobe_mode_threshold) 3867 strobe_mode = true; 3868 3869 if (pi->mem_gddr5) 3870 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3871 else 3872 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3873 3874 if (strobe_mode) 3875 result |= SISLANDS_SMC_STROBE_ENABLE; 3876 3877 return result; 3878 } 3879 3880 static int si_upload_firmware(struct radeon_device *rdev) 3881 { 3882 struct si_power_info *si_pi = si_get_pi(rdev); 3883 int ret; 3884 3885 si_reset_smc(rdev); 3886 si_stop_smc_clock(rdev); 3887 3888 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3889 3890 return ret; 3891 } 3892 3893 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3894 const struct atom_voltage_table *table, 3895 const struct radeon_phase_shedding_limits_table *limits) 3896 { 3897 u32 data, num_bits, num_levels; 3898 3899 if ((table == NULL) || (limits == NULL)) 3900 return false; 3901 3902 data = table->mask_low; 3903 3904 num_bits = hweight32(data); 3905 3906 if (num_bits == 0) 3907 return false; 3908 3909 num_levels = (1 << num_bits); 3910 3911 if (table->count != num_levels) 3912 return false; 3913 3914 if (limits->count != (num_levels - 1)) 3915 return false; 3916 3917 return true; 3918 } 3919 3920 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3921 u32 max_voltage_steps, 3922 struct atom_voltage_table *voltage_table) 3923 { 3924 unsigned int i, diff; 3925 3926 if (voltage_table->count <= max_voltage_steps) 3927 return; 3928 3929 diff = voltage_table->count - max_voltage_steps; 3930 3931 for (i= 0; i < max_voltage_steps; i++) 3932 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3933 3934 voltage_table->count = max_voltage_steps; 3935 } 3936 3937 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3938 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3939 struct atom_voltage_table *voltage_table) 3940 { 3941 u32 i; 3942 3943 if (voltage_dependency_table == NULL) 3944 return -EINVAL; 3945 3946 voltage_table->mask_low = 0; 3947 voltage_table->phase_delay = 0; 3948 3949 voltage_table->count = voltage_dependency_table->count; 3950 for (i = 0; i < voltage_table->count; i++) { 3951 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3952 voltage_table->entries[i].smio_low = 0; 3953 } 3954 3955 return 0; 3956 } 3957 3958 static int si_construct_voltage_tables(struct radeon_device *rdev) 3959 { 3960 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3961 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3962 struct si_power_info *si_pi = si_get_pi(rdev); 3963 int ret; 3964 3965 if (pi->voltage_control) { 3966 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3967 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3968 if (ret) 3969 return ret; 3970 3971 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3972 si_trim_voltage_table_to_fit_state_table(rdev, 3973 SISLANDS_MAX_NO_VREG_STEPS, 3974 &eg_pi->vddc_voltage_table); 3975 } else if (si_pi->voltage_control_svi2) { 3976 ret = si_get_svi2_voltage_table(rdev, 3977 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3978 &eg_pi->vddc_voltage_table); 3979 if (ret) 3980 return ret; 3981 } else { 3982 return -EINVAL; 3983 } 3984 3985 if (eg_pi->vddci_control) { 3986 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3987 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3988 if (ret) 3989 return ret; 3990 3991 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3992 si_trim_voltage_table_to_fit_state_table(rdev, 3993 SISLANDS_MAX_NO_VREG_STEPS, 3994 &eg_pi->vddci_voltage_table); 3995 } 3996 if (si_pi->vddci_control_svi2) { 3997 ret = si_get_svi2_voltage_table(rdev, 3998 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3999 &eg_pi->vddci_voltage_table); 4000 if (ret) 4001 return ret; 4002 } 4003 4004 if (pi->mvdd_control) { 4005 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4006 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4007 4008 if (ret) { 4009 pi->mvdd_control = false; 4010 return ret; 4011 } 4012 4013 if (si_pi->mvdd_voltage_table.count == 0) { 4014 pi->mvdd_control = false; 4015 return -EINVAL; 4016 } 4017 4018 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4019 si_trim_voltage_table_to_fit_state_table(rdev, 4020 SISLANDS_MAX_NO_VREG_STEPS, 4021 &si_pi->mvdd_voltage_table); 4022 } 4023 4024 if (si_pi->vddc_phase_shed_control) { 4025 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4026 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4027 if (ret) 4028 si_pi->vddc_phase_shed_control = false; 4029 4030 if ((si_pi->vddc_phase_shed_table.count == 0) || 4031 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4032 si_pi->vddc_phase_shed_control = false; 4033 } 4034 4035 return 0; 4036 } 4037 4038 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4039 const struct atom_voltage_table *voltage_table, 4040 SISLANDS_SMC_STATETABLE *table) 4041 { 4042 unsigned int i; 4043 4044 for (i = 0; i < voltage_table->count; i++) 4045 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4046 } 4047 4048 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4049 SISLANDS_SMC_STATETABLE *table) 4050 { 4051 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4052 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4053 struct si_power_info *si_pi = si_get_pi(rdev); 4054 u8 i; 4055 4056 if (si_pi->voltage_control_svi2) { 4057 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4058 si_pi->svc_gpio_id); 4059 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4060 si_pi->svd_gpio_id); 4061 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4062 2); 4063 } else { 4064 if (eg_pi->vddc_voltage_table.count) { 4065 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4066 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4067 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4068 4069 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4070 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4071 table->maxVDDCIndexInPPTable = i; 4072 break; 4073 } 4074 } 4075 } 4076 4077 if (eg_pi->vddci_voltage_table.count) { 4078 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4079 4080 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4081 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4082 } 4083 4084 4085 if (si_pi->mvdd_voltage_table.count) { 4086 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4087 4088 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4089 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4090 } 4091 4092 if (si_pi->vddc_phase_shed_control) { 4093 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4094 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4095 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4096 4097 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4098 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4099 4100 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4101 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4102 } else { 4103 si_pi->vddc_phase_shed_control = false; 4104 } 4105 } 4106 } 4107 4108 return 0; 4109 } 4110 4111 static int si_populate_voltage_value(struct radeon_device *rdev, 4112 const struct atom_voltage_table *table, 4113 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4114 { 4115 unsigned int i; 4116 4117 for (i = 0; i < table->count; i++) { 4118 if (value <= table->entries[i].value) { 4119 voltage->index = (u8)i; 4120 voltage->value = cpu_to_be16(table->entries[i].value); 4121 break; 4122 } 4123 } 4124 4125 if (i >= table->count) 4126 return -EINVAL; 4127 4128 return 0; 4129 } 4130 4131 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4132 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4133 { 4134 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4135 struct si_power_info *si_pi = si_get_pi(rdev); 4136 4137 if (pi->mvdd_control) { 4138 if (mclk <= pi->mvdd_split_frequency) 4139 voltage->index = 0; 4140 else 4141 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4142 4143 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4144 } 4145 return 0; 4146 } 4147 4148 static int si_get_std_voltage_value(struct radeon_device *rdev, 4149 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4150 u16 *std_voltage) 4151 { 4152 u16 v_index; 4153 bool voltage_found = false; 4154 *std_voltage = be16_to_cpu(voltage->value); 4155 4156 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4157 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4158 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4159 return -EINVAL; 4160 4161 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4162 if (be16_to_cpu(voltage->value) == 4163 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4164 voltage_found = true; 4165 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4166 *std_voltage = 4167 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4168 else 4169 *std_voltage = 4170 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4171 break; 4172 } 4173 } 4174 4175 if (!voltage_found) { 4176 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4177 if (be16_to_cpu(voltage->value) <= 4178 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4179 voltage_found = true; 4180 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4181 *std_voltage = 4182 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4183 else 4184 *std_voltage = 4185 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4186 break; 4187 } 4188 } 4189 } 4190 } else { 4191 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4192 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4193 } 4194 } 4195 4196 return 0; 4197 } 4198 4199 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4200 u16 value, u8 index, 4201 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4202 { 4203 voltage->index = index; 4204 voltage->value = cpu_to_be16(value); 4205 4206 return 0; 4207 } 4208 4209 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4210 const struct radeon_phase_shedding_limits_table *limits, 4211 u16 voltage, u32 sclk, u32 mclk, 4212 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4213 { 4214 unsigned int i; 4215 4216 for (i = 0; i < limits->count; i++) { 4217 if ((voltage <= limits->entries[i].voltage) && 4218 (sclk <= limits->entries[i].sclk) && 4219 (mclk <= limits->entries[i].mclk)) 4220 break; 4221 } 4222 4223 smc_voltage->phase_settings = (u8)i; 4224 4225 return 0; 4226 } 4227 4228 static int si_init_arb_table_index(struct radeon_device *rdev) 4229 { 4230 struct si_power_info *si_pi = si_get_pi(rdev); 4231 u32 tmp; 4232 int ret; 4233 4234 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4235 if (ret) 4236 return ret; 4237 4238 tmp &= 0x00FFFFFF; 4239 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4240 4241 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4242 } 4243 4244 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4245 { 4246 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4247 } 4248 4249 static int si_reset_to_default(struct radeon_device *rdev) 4250 { 4251 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4252 0 : -EINVAL; 4253 } 4254 4255 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4256 { 4257 struct si_power_info *si_pi = si_get_pi(rdev); 4258 u32 tmp; 4259 int ret; 4260 4261 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4262 &tmp, si_pi->sram_end); 4263 if (ret) 4264 return ret; 4265 4266 tmp = (tmp >> 24) & 0xff; 4267 4268 if (tmp == MC_CG_ARB_FREQ_F0) 4269 return 0; 4270 4271 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4272 } 4273 4274 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4275 u32 engine_clock) 4276 { 4277 u32 dram_rows; 4278 u32 dram_refresh_rate; 4279 u32 mc_arb_rfsh_rate; 4280 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4281 4282 if (tmp >= 4) 4283 dram_rows = 16384; 4284 else 4285 dram_rows = 1 << (tmp + 10); 4286 4287 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4288 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4289 4290 return mc_arb_rfsh_rate; 4291 } 4292 4293 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4294 struct rv7xx_pl *pl, 4295 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4296 { 4297 u32 dram_timing; 4298 u32 dram_timing2; 4299 u32 burst_time; 4300 4301 arb_regs->mc_arb_rfsh_rate = 4302 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4303 4304 radeon_atom_set_engine_dram_timings(rdev, 4305 pl->sclk, 4306 pl->mclk); 4307 4308 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4309 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4310 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4311 4312 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4313 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4314 arb_regs->mc_arb_burst_time = (u8)burst_time; 4315 4316 return 0; 4317 } 4318 4319 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4320 struct radeon_ps *radeon_state, 4321 unsigned int first_arb_set) 4322 { 4323 struct si_power_info *si_pi = si_get_pi(rdev); 4324 struct ni_ps *state = ni_get_ps(radeon_state); 4325 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4326 int i, ret = 0; 4327 4328 for (i = 0; i < state->performance_level_count; i++) { 4329 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4330 if (ret) 4331 break; 4332 ret = si_copy_bytes_to_smc(rdev, 4333 si_pi->arb_table_start + 4334 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4335 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4336 (u8 *)&arb_regs, 4337 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4338 si_pi->sram_end); 4339 if (ret) 4340 break; 4341 } 4342 4343 return ret; 4344 } 4345 4346 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4347 struct radeon_ps *radeon_new_state) 4348 { 4349 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4350 SISLANDS_DRIVER_STATE_ARB_INDEX); 4351 } 4352 4353 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4354 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4355 { 4356 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4357 struct si_power_info *si_pi = si_get_pi(rdev); 4358 4359 if (pi->mvdd_control) 4360 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4361 si_pi->mvdd_bootup_value, voltage); 4362 4363 return 0; 4364 } 4365 4366 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4367 struct radeon_ps *radeon_initial_state, 4368 SISLANDS_SMC_STATETABLE *table) 4369 { 4370 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4371 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4372 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4373 struct si_power_info *si_pi = si_get_pi(rdev); 4374 u32 reg; 4375 int ret; 4376 4377 table->initialState.levels[0].mclk.vDLL_CNTL = 4378 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4379 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4380 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4381 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4382 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4383 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4384 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4385 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4386 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4387 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4388 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4389 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4390 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4391 table->initialState.levels[0].mclk.vMPLL_SS = 4392 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4393 table->initialState.levels[0].mclk.vMPLL_SS2 = 4394 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4395 4396 table->initialState.levels[0].mclk.mclk_value = 4397 cpu_to_be32(initial_state->performance_levels[0].mclk); 4398 4399 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4400 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4401 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4402 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4403 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4404 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4405 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4406 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4407 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4408 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4409 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4410 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4411 4412 table->initialState.levels[0].sclk.sclk_value = 4413 cpu_to_be32(initial_state->performance_levels[0].sclk); 4414 4415 table->initialState.levels[0].arbRefreshState = 4416 SISLANDS_INITIAL_STATE_ARB_INDEX; 4417 4418 table->initialState.levels[0].ACIndex = 0; 4419 4420 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4421 initial_state->performance_levels[0].vddc, 4422 &table->initialState.levels[0].vddc); 4423 4424 if (!ret) { 4425 u16 std_vddc; 4426 4427 ret = si_get_std_voltage_value(rdev, 4428 &table->initialState.levels[0].vddc, 4429 &std_vddc); 4430 if (!ret) 4431 si_populate_std_voltage_value(rdev, std_vddc, 4432 table->initialState.levels[0].vddc.index, 4433 &table->initialState.levels[0].std_vddc); 4434 } 4435 4436 if (eg_pi->vddci_control) 4437 si_populate_voltage_value(rdev, 4438 &eg_pi->vddci_voltage_table, 4439 initial_state->performance_levels[0].vddci, 4440 &table->initialState.levels[0].vddci); 4441 4442 if (si_pi->vddc_phase_shed_control) 4443 si_populate_phase_shedding_value(rdev, 4444 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4445 initial_state->performance_levels[0].vddc, 4446 initial_state->performance_levels[0].sclk, 4447 initial_state->performance_levels[0].mclk, 4448 &table->initialState.levels[0].vddc); 4449 4450 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4451 4452 reg = CG_R(0xffff) | CG_L(0); 4453 table->initialState.levels[0].aT = cpu_to_be32(reg); 4454 4455 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4456 4457 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4458 4459 if (pi->mem_gddr5) { 4460 table->initialState.levels[0].strobeMode = 4461 si_get_strobe_mode_settings(rdev, 4462 initial_state->performance_levels[0].mclk); 4463 4464 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4465 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4466 else 4467 table->initialState.levels[0].mcFlags = 0; 4468 } 4469 4470 table->initialState.levelCount = 1; 4471 4472 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4473 4474 table->initialState.levels[0].dpm2.MaxPS = 0; 4475 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4476 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4477 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4478 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4479 4480 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4481 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4482 4483 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4484 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4485 4486 return 0; 4487 } 4488 4489 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4490 SISLANDS_SMC_STATETABLE *table) 4491 { 4492 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4493 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4494 struct si_power_info *si_pi = si_get_pi(rdev); 4495 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4496 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4497 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4498 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4499 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4500 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4501 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4502 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4503 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4504 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4505 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4506 u32 reg; 4507 int ret; 4508 4509 table->ACPIState = table->initialState; 4510 4511 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4512 4513 if (pi->acpi_vddc) { 4514 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4515 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4516 if (!ret) { 4517 u16 std_vddc; 4518 4519 ret = si_get_std_voltage_value(rdev, 4520 &table->ACPIState.levels[0].vddc, &std_vddc); 4521 if (!ret) 4522 si_populate_std_voltage_value(rdev, std_vddc, 4523 table->ACPIState.levels[0].vddc.index, 4524 &table->ACPIState.levels[0].std_vddc); 4525 } 4526 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4527 4528 if (si_pi->vddc_phase_shed_control) { 4529 si_populate_phase_shedding_value(rdev, 4530 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4531 pi->acpi_vddc, 4532 0, 4533 0, 4534 &table->ACPIState.levels[0].vddc); 4535 } 4536 } else { 4537 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4538 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4539 if (!ret) { 4540 u16 std_vddc; 4541 4542 ret = si_get_std_voltage_value(rdev, 4543 &table->ACPIState.levels[0].vddc, &std_vddc); 4544 4545 if (!ret) 4546 si_populate_std_voltage_value(rdev, std_vddc, 4547 table->ACPIState.levels[0].vddc.index, 4548 &table->ACPIState.levels[0].std_vddc); 4549 } 4550 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4551 si_pi->sys_pcie_mask, 4552 si_pi->boot_pcie_gen, 4553 RADEON_PCIE_GEN1); 4554 4555 if (si_pi->vddc_phase_shed_control) 4556 si_populate_phase_shedding_value(rdev, 4557 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4558 pi->min_vddc_in_table, 4559 0, 4560 0, 4561 &table->ACPIState.levels[0].vddc); 4562 } 4563 4564 if (pi->acpi_vddc) { 4565 if (eg_pi->acpi_vddci) 4566 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4567 eg_pi->acpi_vddci, 4568 &table->ACPIState.levels[0].vddci); 4569 } 4570 4571 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4572 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4573 4574 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4575 4576 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4577 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4578 4579 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4580 cpu_to_be32(dll_cntl); 4581 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4582 cpu_to_be32(mclk_pwrmgt_cntl); 4583 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4584 cpu_to_be32(mpll_ad_func_cntl); 4585 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4586 cpu_to_be32(mpll_dq_func_cntl); 4587 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4588 cpu_to_be32(mpll_func_cntl); 4589 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4590 cpu_to_be32(mpll_func_cntl_1); 4591 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4592 cpu_to_be32(mpll_func_cntl_2); 4593 table->ACPIState.levels[0].mclk.vMPLL_SS = 4594 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4595 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4596 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4597 4598 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4599 cpu_to_be32(spll_func_cntl); 4600 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4601 cpu_to_be32(spll_func_cntl_2); 4602 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4603 cpu_to_be32(spll_func_cntl_3); 4604 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4605 cpu_to_be32(spll_func_cntl_4); 4606 4607 table->ACPIState.levels[0].mclk.mclk_value = 0; 4608 table->ACPIState.levels[0].sclk.sclk_value = 0; 4609 4610 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4611 4612 if (eg_pi->dynamic_ac_timing) 4613 table->ACPIState.levels[0].ACIndex = 0; 4614 4615 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4616 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4617 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4618 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4619 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4620 4621 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4622 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4623 4624 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4625 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4626 4627 return 0; 4628 } 4629 4630 static int si_populate_ulv_state(struct radeon_device *rdev, 4631 SISLANDS_SMC_SWSTATE *state) 4632 { 4633 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4634 struct si_power_info *si_pi = si_get_pi(rdev); 4635 struct si_ulv_param *ulv = &si_pi->ulv; 4636 u32 sclk_in_sr = 1350; /* ??? */ 4637 int ret; 4638 4639 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4640 &state->levels[0]); 4641 if (!ret) { 4642 if (eg_pi->sclk_deep_sleep) { 4643 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4644 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4645 else 4646 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4647 } 4648 if (ulv->one_pcie_lane_in_ulv) 4649 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4650 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4651 state->levels[0].ACIndex = 1; 4652 state->levels[0].std_vddc = state->levels[0].vddc; 4653 state->levelCount = 1; 4654 4655 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4656 } 4657 4658 return ret; 4659 } 4660 4661 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4662 { 4663 struct si_power_info *si_pi = si_get_pi(rdev); 4664 struct si_ulv_param *ulv = &si_pi->ulv; 4665 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4666 int ret; 4667 4668 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4669 &arb_regs); 4670 if (ret) 4671 return ret; 4672 4673 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4674 ulv->volt_change_delay); 4675 4676 ret = si_copy_bytes_to_smc(rdev, 4677 si_pi->arb_table_start + 4678 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4679 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4680 (u8 *)&arb_regs, 4681 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4682 si_pi->sram_end); 4683 4684 return ret; 4685 } 4686 4687 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4688 { 4689 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4690 4691 pi->mvdd_split_frequency = 30000; 4692 } 4693 4694 static int si_init_smc_table(struct radeon_device *rdev) 4695 { 4696 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4697 struct si_power_info *si_pi = si_get_pi(rdev); 4698 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4699 const struct si_ulv_param *ulv = &si_pi->ulv; 4700 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4701 int ret; 4702 u32 lane_width; 4703 u32 vr_hot_gpio; 4704 4705 si_populate_smc_voltage_tables(rdev, table); 4706 4707 switch (rdev->pm.int_thermal_type) { 4708 case THERMAL_TYPE_SI: 4709 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4710 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4711 break; 4712 case THERMAL_TYPE_NONE: 4713 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4714 break; 4715 default: 4716 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4717 break; 4718 } 4719 4720 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4721 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4722 4723 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4724 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4725 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4726 } 4727 4728 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4729 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4730 4731 if (pi->mem_gddr5) 4732 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4733 4734 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4735 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4736 4737 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4738 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4739 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4740 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4741 vr_hot_gpio); 4742 } 4743 4744 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4745 if (ret) 4746 return ret; 4747 4748 ret = si_populate_smc_acpi_state(rdev, table); 4749 if (ret) 4750 return ret; 4751 4752 table->driverState = table->initialState; 4753 4754 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4755 SISLANDS_INITIAL_STATE_ARB_INDEX); 4756 if (ret) 4757 return ret; 4758 4759 if (ulv->supported && ulv->pl.vddc) { 4760 ret = si_populate_ulv_state(rdev, &table->ULVState); 4761 if (ret) 4762 return ret; 4763 4764 ret = si_program_ulv_memory_timing_parameters(rdev); 4765 if (ret) 4766 return ret; 4767 4768 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4769 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4770 4771 lane_width = radeon_get_pcie_lanes(rdev); 4772 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4773 } else { 4774 table->ULVState = table->initialState; 4775 } 4776 4777 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4778 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4779 si_pi->sram_end); 4780 } 4781 4782 static int si_calculate_sclk_params(struct radeon_device *rdev, 4783 u32 engine_clock, 4784 SISLANDS_SMC_SCLK_VALUE *sclk) 4785 { 4786 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4787 struct si_power_info *si_pi = si_get_pi(rdev); 4788 struct atom_clock_dividers dividers; 4789 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4790 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4791 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4792 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4793 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4794 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4795 u64 tmp; 4796 u32 reference_clock = rdev->clock.spll.reference_freq; 4797 u32 reference_divider; 4798 u32 fbdiv; 4799 int ret; 4800 4801 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4802 engine_clock, false, ÷rs); 4803 if (ret) 4804 return ret; 4805 4806 reference_divider = 1 + dividers.ref_div; 4807 4808 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4809 do_div(tmp, reference_clock); 4810 fbdiv = (u32) tmp; 4811 4812 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4813 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4814 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4815 4816 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4817 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4818 4819 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4820 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4821 spll_func_cntl_3 |= SPLL_DITHEN; 4822 4823 if (pi->sclk_ss) { 4824 struct radeon_atom_ss ss; 4825 u32 vco_freq = engine_clock * dividers.post_div; 4826 4827 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4828 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4829 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4830 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4831 4832 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4833 cg_spll_spread_spectrum |= CLK_S(clk_s); 4834 cg_spll_spread_spectrum |= SSEN; 4835 4836 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4837 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4838 } 4839 } 4840 4841 sclk->sclk_value = engine_clock; 4842 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4843 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4844 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4845 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4846 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4847 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4848 4849 return 0; 4850 } 4851 4852 static int si_populate_sclk_value(struct radeon_device *rdev, 4853 u32 engine_clock, 4854 SISLANDS_SMC_SCLK_VALUE *sclk) 4855 { 4856 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4857 int ret; 4858 4859 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4860 if (!ret) { 4861 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4862 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4863 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4864 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4865 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4866 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4867 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4868 } 4869 4870 return ret; 4871 } 4872 4873 static int si_populate_mclk_value(struct radeon_device *rdev, 4874 u32 engine_clock, 4875 u32 memory_clock, 4876 SISLANDS_SMC_MCLK_VALUE *mclk, 4877 bool strobe_mode, 4878 bool dll_state_on) 4879 { 4880 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4881 struct si_power_info *si_pi = si_get_pi(rdev); 4882 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4883 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4884 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4885 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4886 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4887 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4888 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4889 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4890 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4891 struct atom_mpll_param mpll_param; 4892 int ret; 4893 4894 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4895 if (ret) 4896 return ret; 4897 4898 mpll_func_cntl &= ~BWCTRL_MASK; 4899 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4900 4901 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4902 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4903 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4904 4905 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4906 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4907 4908 if (pi->mem_gddr5) { 4909 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4910 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4911 YCLK_POST_DIV(mpll_param.post_div); 4912 } 4913 4914 if (pi->mclk_ss) { 4915 struct radeon_atom_ss ss; 4916 u32 freq_nom; 4917 u32 tmp; 4918 u32 reference_clock = rdev->clock.mpll.reference_freq; 4919 4920 if (pi->mem_gddr5) 4921 freq_nom = memory_clock * 4; 4922 else 4923 freq_nom = memory_clock * 2; 4924 4925 tmp = freq_nom / reference_clock; 4926 tmp = tmp * tmp; 4927 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4928 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4929 u32 clks = reference_clock * 5 / ss.rate; 4930 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4931 4932 mpll_ss1 &= ~CLKV_MASK; 4933 mpll_ss1 |= CLKV(clkv); 4934 4935 mpll_ss2 &= ~CLKS_MASK; 4936 mpll_ss2 |= CLKS(clks); 4937 } 4938 } 4939 4940 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4941 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4942 4943 if (dll_state_on) 4944 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4945 else 4946 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4947 4948 mclk->mclk_value = cpu_to_be32(memory_clock); 4949 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4950 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4951 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4952 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4953 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4954 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4955 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4956 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4957 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4958 4959 return 0; 4960 } 4961 4962 static void si_populate_smc_sp(struct radeon_device *rdev, 4963 struct radeon_ps *radeon_state, 4964 SISLANDS_SMC_SWSTATE *smc_state) 4965 { 4966 struct ni_ps *ps = ni_get_ps(radeon_state); 4967 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4968 int i; 4969 4970 for (i = 0; i < ps->performance_level_count - 1; i++) 4971 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4972 4973 smc_state->levels[ps->performance_level_count - 1].bSP = 4974 cpu_to_be32(pi->psp); 4975 } 4976 4977 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4978 struct rv7xx_pl *pl, 4979 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4980 { 4981 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4982 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4983 struct si_power_info *si_pi = si_get_pi(rdev); 4984 int ret; 4985 bool dll_state_on; 4986 u16 std_vddc; 4987 bool gmc_pg = false; 4988 4989 if (eg_pi->pcie_performance_request && 4990 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4991 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4992 else 4993 level->gen2PCIE = (u8)pl->pcie_gen; 4994 4995 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4996 if (ret) 4997 return ret; 4998 4999 level->mcFlags = 0; 5000 5001 if (pi->mclk_stutter_mode_threshold && 5002 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5003 !eg_pi->uvd_enabled && 5004 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5005 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5006 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5007 5008 if (gmc_pg) 5009 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5010 } 5011 5012 if (pi->mem_gddr5) { 5013 if (pl->mclk > pi->mclk_edc_enable_threshold) 5014 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5015 5016 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5017 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5018 5019 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5020 5021 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5022 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5023 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5024 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5025 else 5026 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5027 } else { 5028 dll_state_on = false; 5029 } 5030 } else { 5031 level->strobeMode = si_get_strobe_mode_settings(rdev, 5032 pl->mclk); 5033 5034 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5035 } 5036 5037 ret = si_populate_mclk_value(rdev, 5038 pl->sclk, 5039 pl->mclk, 5040 &level->mclk, 5041 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5042 if (ret) 5043 return ret; 5044 5045 ret = si_populate_voltage_value(rdev, 5046 &eg_pi->vddc_voltage_table, 5047 pl->vddc, &level->vddc); 5048 if (ret) 5049 return ret; 5050 5051 5052 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5053 if (ret) 5054 return ret; 5055 5056 ret = si_populate_std_voltage_value(rdev, std_vddc, 5057 level->vddc.index, &level->std_vddc); 5058 if (ret) 5059 return ret; 5060 5061 if (eg_pi->vddci_control) { 5062 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5063 pl->vddci, &level->vddci); 5064 if (ret) 5065 return ret; 5066 } 5067 5068 if (si_pi->vddc_phase_shed_control) { 5069 ret = si_populate_phase_shedding_value(rdev, 5070 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5071 pl->vddc, 5072 pl->sclk, 5073 pl->mclk, 5074 &level->vddc); 5075 if (ret) 5076 return ret; 5077 } 5078 5079 level->MaxPoweredUpCU = si_pi->max_cu; 5080 5081 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5082 5083 return ret; 5084 } 5085 5086 static int si_populate_smc_t(struct radeon_device *rdev, 5087 struct radeon_ps *radeon_state, 5088 SISLANDS_SMC_SWSTATE *smc_state) 5089 { 5090 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5091 struct ni_ps *state = ni_get_ps(radeon_state); 5092 u32 a_t; 5093 u32 t_l, t_h; 5094 u32 high_bsp; 5095 int i, ret; 5096 5097 if (state->performance_level_count >= 9) 5098 return -EINVAL; 5099 5100 if (state->performance_level_count < 2) { 5101 a_t = CG_R(0xffff) | CG_L(0); 5102 smc_state->levels[0].aT = cpu_to_be32(a_t); 5103 return 0; 5104 } 5105 5106 smc_state->levels[0].aT = cpu_to_be32(0); 5107 5108 for (i = 0; i <= state->performance_level_count - 2; i++) { 5109 ret = r600_calculate_at( 5110 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5111 100 * R600_AH_DFLT, 5112 state->performance_levels[i + 1].sclk, 5113 state->performance_levels[i].sclk, 5114 &t_l, 5115 &t_h); 5116 5117 if (ret) { 5118 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5119 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5120 } 5121 5122 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5123 a_t |= CG_R(t_l * pi->bsp / 20000); 5124 smc_state->levels[i].aT = cpu_to_be32(a_t); 5125 5126 high_bsp = (i == state->performance_level_count - 2) ? 5127 pi->pbsp : pi->bsp; 5128 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5129 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5130 } 5131 5132 return 0; 5133 } 5134 5135 static int si_disable_ulv(struct radeon_device *rdev) 5136 { 5137 struct si_power_info *si_pi = si_get_pi(rdev); 5138 struct si_ulv_param *ulv = &si_pi->ulv; 5139 5140 if (ulv->supported) 5141 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5142 0 : -EINVAL; 5143 5144 return 0; 5145 } 5146 5147 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5148 struct radeon_ps *radeon_state) 5149 { 5150 const struct si_power_info *si_pi = si_get_pi(rdev); 5151 const struct si_ulv_param *ulv = &si_pi->ulv; 5152 const struct ni_ps *state = ni_get_ps(radeon_state); 5153 int i; 5154 5155 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5156 return false; 5157 5158 /* XXX validate against display requirements! */ 5159 5160 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5161 if (rdev->clock.current_dispclk <= 5162 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5163 if (ulv->pl.vddc < 5164 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5165 return false; 5166 } 5167 } 5168 5169 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5170 return false; 5171 5172 return true; 5173 } 5174 5175 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5176 struct radeon_ps *radeon_new_state) 5177 { 5178 const struct si_power_info *si_pi = si_get_pi(rdev); 5179 const struct si_ulv_param *ulv = &si_pi->ulv; 5180 5181 if (ulv->supported) { 5182 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5183 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5184 0 : -EINVAL; 5185 } 5186 return 0; 5187 } 5188 5189 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5190 struct radeon_ps *radeon_state, 5191 SISLANDS_SMC_SWSTATE *smc_state) 5192 { 5193 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5194 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5195 struct si_power_info *si_pi = si_get_pi(rdev); 5196 struct ni_ps *state = ni_get_ps(radeon_state); 5197 int i, ret; 5198 u32 threshold; 5199 u32 sclk_in_sr = 1350; /* ??? */ 5200 5201 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5202 return -EINVAL; 5203 5204 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5205 5206 if (radeon_state->vclk && radeon_state->dclk) { 5207 eg_pi->uvd_enabled = true; 5208 if (eg_pi->smu_uvd_hs) 5209 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5210 } else { 5211 eg_pi->uvd_enabled = false; 5212 } 5213 5214 if (state->dc_compatible) 5215 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5216 5217 smc_state->levelCount = 0; 5218 for (i = 0; i < state->performance_level_count; i++) { 5219 if (eg_pi->sclk_deep_sleep) { 5220 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5221 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5222 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5223 else 5224 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5225 } 5226 } 5227 5228 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5229 &smc_state->levels[i]); 5230 smc_state->levels[i].arbRefreshState = 5231 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5232 5233 if (ret) 5234 return ret; 5235 5236 if (ni_pi->enable_power_containment) 5237 smc_state->levels[i].displayWatermark = 5238 (state->performance_levels[i].sclk < threshold) ? 5239 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5240 else 5241 smc_state->levels[i].displayWatermark = (i < 2) ? 5242 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5243 5244 if (eg_pi->dynamic_ac_timing) 5245 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5246 else 5247 smc_state->levels[i].ACIndex = 0; 5248 5249 smc_state->levelCount++; 5250 } 5251 5252 si_write_smc_soft_register(rdev, 5253 SI_SMC_SOFT_REGISTER_watermark_threshold, 5254 threshold / 512); 5255 5256 si_populate_smc_sp(rdev, radeon_state, smc_state); 5257 5258 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5259 if (ret) 5260 ni_pi->enable_power_containment = false; 5261 5262 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5263 if (ret) 5264 ni_pi->enable_sq_ramping = false; 5265 5266 return si_populate_smc_t(rdev, radeon_state, smc_state); 5267 } 5268 5269 static int si_upload_sw_state(struct radeon_device *rdev, 5270 struct radeon_ps *radeon_new_state) 5271 { 5272 struct si_power_info *si_pi = si_get_pi(rdev); 5273 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5274 int ret; 5275 u32 address = si_pi->state_table_start + 5276 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5277 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5278 ((new_state->performance_level_count - 1) * 5279 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5280 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5281 5282 memset(smc_state, 0, state_size); 5283 5284 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5285 if (ret) 5286 return ret; 5287 5288 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5289 state_size, si_pi->sram_end); 5290 5291 return ret; 5292 } 5293 5294 static int si_upload_ulv_state(struct radeon_device *rdev) 5295 { 5296 struct si_power_info *si_pi = si_get_pi(rdev); 5297 struct si_ulv_param *ulv = &si_pi->ulv; 5298 int ret = 0; 5299 5300 if (ulv->supported && ulv->pl.vddc) { 5301 u32 address = si_pi->state_table_start + 5302 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5303 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5304 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5305 5306 memset(smc_state, 0, state_size); 5307 5308 ret = si_populate_ulv_state(rdev, smc_state); 5309 if (!ret) 5310 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5311 state_size, si_pi->sram_end); 5312 } 5313 5314 return ret; 5315 } 5316 5317 static int si_upload_smc_data(struct radeon_device *rdev) 5318 { 5319 struct radeon_crtc *radeon_crtc = NULL; 5320 int i; 5321 5322 if (rdev->pm.dpm.new_active_crtc_count == 0) 5323 return 0; 5324 5325 for (i = 0; i < rdev->num_crtc; i++) { 5326 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5327 radeon_crtc = rdev->mode_info.crtcs[i]; 5328 break; 5329 } 5330 } 5331 5332 if (radeon_crtc == NULL) 5333 return 0; 5334 5335 if (radeon_crtc->line_time <= 0) 5336 return 0; 5337 5338 if (si_write_smc_soft_register(rdev, 5339 SI_SMC_SOFT_REGISTER_crtc_index, 5340 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5341 return 0; 5342 5343 if (si_write_smc_soft_register(rdev, 5344 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5345 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5346 return 0; 5347 5348 if (si_write_smc_soft_register(rdev, 5349 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5350 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5351 return 0; 5352 5353 return 0; 5354 } 5355 5356 static int si_set_mc_special_registers(struct radeon_device *rdev, 5357 struct si_mc_reg_table *table) 5358 { 5359 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5360 u8 i, j, k; 5361 u32 temp_reg; 5362 5363 for (i = 0, j = table->last; i < table->last; i++) { 5364 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5365 return -EINVAL; 5366 switch (table->mc_reg_address[i].s1 << 2) { 5367 case MC_SEQ_MISC1: 5368 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5369 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5370 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5371 for (k = 0; k < table->num_entries; k++) 5372 table->mc_reg_table_entry[k].mc_data[j] = 5373 ((temp_reg & 0xffff0000)) | 5374 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5375 j++; 5376 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5377 return -EINVAL; 5378 5379 temp_reg = RREG32(MC_PMG_CMD_MRS); 5380 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5381 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5382 for (k = 0; k < table->num_entries; k++) { 5383 table->mc_reg_table_entry[k].mc_data[j] = 5384 (temp_reg & 0xffff0000) | 5385 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5386 if (!pi->mem_gddr5) 5387 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5388 } 5389 j++; 5390 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5391 return -EINVAL; 5392 5393 if (!pi->mem_gddr5) { 5394 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5395 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5396 for (k = 0; k < table->num_entries; k++) 5397 table->mc_reg_table_entry[k].mc_data[j] = 5398 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5399 j++; 5400 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5401 return -EINVAL; 5402 } 5403 break; 5404 case MC_SEQ_RESERVE_M: 5405 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5406 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5407 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5408 for(k = 0; k < table->num_entries; k++) 5409 table->mc_reg_table_entry[k].mc_data[j] = 5410 (temp_reg & 0xffff0000) | 5411 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5412 j++; 5413 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5414 return -EINVAL; 5415 break; 5416 default: 5417 break; 5418 } 5419 } 5420 5421 table->last = j; 5422 5423 return 0; 5424 } 5425 5426 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5427 { 5428 bool result = true; 5429 5430 switch (in_reg) { 5431 case MC_SEQ_RAS_TIMING >> 2: 5432 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5433 break; 5434 case MC_SEQ_CAS_TIMING >> 2: 5435 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5436 break; 5437 case MC_SEQ_MISC_TIMING >> 2: 5438 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5439 break; 5440 case MC_SEQ_MISC_TIMING2 >> 2: 5441 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5442 break; 5443 case MC_SEQ_RD_CTL_D0 >> 2: 5444 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5445 break; 5446 case MC_SEQ_RD_CTL_D1 >> 2: 5447 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5448 break; 5449 case MC_SEQ_WR_CTL_D0 >> 2: 5450 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5451 break; 5452 case MC_SEQ_WR_CTL_D1 >> 2: 5453 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5454 break; 5455 case MC_PMG_CMD_EMRS >> 2: 5456 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5457 break; 5458 case MC_PMG_CMD_MRS >> 2: 5459 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5460 break; 5461 case MC_PMG_CMD_MRS1 >> 2: 5462 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5463 break; 5464 case MC_SEQ_PMG_TIMING >> 2: 5465 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5466 break; 5467 case MC_PMG_CMD_MRS2 >> 2: 5468 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5469 break; 5470 case MC_SEQ_WR_CTL_2 >> 2: 5471 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5472 break; 5473 default: 5474 result = false; 5475 break; 5476 } 5477 5478 return result; 5479 } 5480 5481 static void si_set_valid_flag(struct si_mc_reg_table *table) 5482 { 5483 u8 i, j; 5484 5485 for (i = 0; i < table->last; i++) { 5486 for (j = 1; j < table->num_entries; j++) { 5487 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5488 table->valid_flag |= 1 << i; 5489 break; 5490 } 5491 } 5492 } 5493 } 5494 5495 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5496 { 5497 u32 i; 5498 u16 address; 5499 5500 for (i = 0; i < table->last; i++) 5501 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5502 address : table->mc_reg_address[i].s1; 5503 5504 } 5505 5506 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5507 struct si_mc_reg_table *si_table) 5508 { 5509 u8 i, j; 5510 5511 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5512 return -EINVAL; 5513 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5514 return -EINVAL; 5515 5516 for (i = 0; i < table->last; i++) 5517 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5518 si_table->last = table->last; 5519 5520 for (i = 0; i < table->num_entries; i++) { 5521 si_table->mc_reg_table_entry[i].mclk_max = 5522 table->mc_reg_table_entry[i].mclk_max; 5523 for (j = 0; j < table->last; j++) { 5524 si_table->mc_reg_table_entry[i].mc_data[j] = 5525 table->mc_reg_table_entry[i].mc_data[j]; 5526 } 5527 } 5528 si_table->num_entries = table->num_entries; 5529 5530 return 0; 5531 } 5532 5533 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5534 { 5535 struct si_power_info *si_pi = si_get_pi(rdev); 5536 struct atom_mc_reg_table *table; 5537 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5538 u8 module_index = rv770_get_memory_module_index(rdev); 5539 int ret; 5540 5541 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5542 if (!table) 5543 return -ENOMEM; 5544 5545 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5546 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5547 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5548 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5549 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5550 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5551 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5552 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5553 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5554 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5555 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5556 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5557 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5558 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5559 5560 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5561 if (ret) 5562 goto init_mc_done; 5563 5564 ret = si_copy_vbios_mc_reg_table(table, si_table); 5565 if (ret) 5566 goto init_mc_done; 5567 5568 si_set_s0_mc_reg_index(si_table); 5569 5570 ret = si_set_mc_special_registers(rdev, si_table); 5571 if (ret) 5572 goto init_mc_done; 5573 5574 si_set_valid_flag(si_table); 5575 5576 init_mc_done: 5577 kfree(table); 5578 5579 return ret; 5580 5581 } 5582 5583 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5584 SMC_SIslands_MCRegisters *mc_reg_table) 5585 { 5586 struct si_power_info *si_pi = si_get_pi(rdev); 5587 u32 i, j; 5588 5589 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5590 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5591 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5592 break; 5593 mc_reg_table->address[i].s0 = 5594 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5595 mc_reg_table->address[i].s1 = 5596 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5597 i++; 5598 } 5599 } 5600 mc_reg_table->last = (u8)i; 5601 } 5602 5603 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5604 SMC_SIslands_MCRegisterSet *data, 5605 u32 num_entries, u32 valid_flag) 5606 { 5607 u32 i, j; 5608 5609 for(i = 0, j = 0; j < num_entries; j++) { 5610 if (valid_flag & (1 << j)) { 5611 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5612 i++; 5613 } 5614 } 5615 } 5616 5617 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5618 struct rv7xx_pl *pl, 5619 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5620 { 5621 struct si_power_info *si_pi = si_get_pi(rdev); 5622 u32 i = 0; 5623 5624 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5625 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5626 break; 5627 } 5628 5629 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5630 --i; 5631 5632 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5633 mc_reg_table_data, si_pi->mc_reg_table.last, 5634 si_pi->mc_reg_table.valid_flag); 5635 } 5636 5637 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5638 struct radeon_ps *radeon_state, 5639 SMC_SIslands_MCRegisters *mc_reg_table) 5640 { 5641 struct ni_ps *state = ni_get_ps(radeon_state); 5642 int i; 5643 5644 for (i = 0; i < state->performance_level_count; i++) { 5645 si_convert_mc_reg_table_entry_to_smc(rdev, 5646 &state->performance_levels[i], 5647 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5648 } 5649 } 5650 5651 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5652 struct radeon_ps *radeon_boot_state) 5653 { 5654 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5655 struct si_power_info *si_pi = si_get_pi(rdev); 5656 struct si_ulv_param *ulv = &si_pi->ulv; 5657 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5658 5659 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5660 5661 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5662 5663 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5664 5665 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5666 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5667 5668 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5669 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5670 si_pi->mc_reg_table.last, 5671 si_pi->mc_reg_table.valid_flag); 5672 5673 if (ulv->supported && ulv->pl.vddc != 0) 5674 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5675 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5676 else 5677 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5678 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5679 si_pi->mc_reg_table.last, 5680 si_pi->mc_reg_table.valid_flag); 5681 5682 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5683 5684 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5685 (u8 *)smc_mc_reg_table, 5686 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5687 } 5688 5689 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5690 struct radeon_ps *radeon_new_state) 5691 { 5692 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5693 struct si_power_info *si_pi = si_get_pi(rdev); 5694 u32 address = si_pi->mc_reg_table_start + 5695 offsetof(SMC_SIslands_MCRegisters, 5696 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5697 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5698 5699 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5700 5701 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5702 5703 5704 return si_copy_bytes_to_smc(rdev, address, 5705 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5706 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5707 si_pi->sram_end); 5708 5709 } 5710 5711 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5712 { 5713 if (enable) 5714 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5715 else 5716 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5717 } 5718 5719 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5720 struct radeon_ps *radeon_state) 5721 { 5722 struct ni_ps *state = ni_get_ps(radeon_state); 5723 int i; 5724 u16 pcie_speed, max_speed = 0; 5725 5726 for (i = 0; i < state->performance_level_count; i++) { 5727 pcie_speed = state->performance_levels[i].pcie_gen; 5728 if (max_speed < pcie_speed) 5729 max_speed = pcie_speed; 5730 } 5731 return max_speed; 5732 } 5733 5734 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5735 { 5736 u32 speed_cntl; 5737 5738 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5739 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5740 5741 return (u16)speed_cntl; 5742 } 5743 5744 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5745 struct radeon_ps *radeon_new_state, 5746 struct radeon_ps *radeon_current_state) 5747 { 5748 struct si_power_info *si_pi = si_get_pi(rdev); 5749 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5750 enum radeon_pcie_gen current_link_speed; 5751 5752 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5753 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5754 else 5755 current_link_speed = si_pi->force_pcie_gen; 5756 5757 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5758 si_pi->pspp_notify_required = false; 5759 if (target_link_speed > current_link_speed) { 5760 switch (target_link_speed) { 5761 #if defined(CONFIG_ACPI) 5762 case RADEON_PCIE_GEN3: 5763 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5764 break; 5765 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5766 if (current_link_speed == RADEON_PCIE_GEN2) 5767 break; 5768 /* fall through */ 5769 case RADEON_PCIE_GEN2: 5770 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5771 break; 5772 #endif 5773 /* fall through */ 5774 default: 5775 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5776 break; 5777 } 5778 } else { 5779 if (target_link_speed < current_link_speed) 5780 si_pi->pspp_notify_required = true; 5781 } 5782 } 5783 5784 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5785 struct radeon_ps *radeon_new_state, 5786 struct radeon_ps *radeon_current_state) 5787 { 5788 struct si_power_info *si_pi = si_get_pi(rdev); 5789 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5790 u8 request; 5791 5792 if (si_pi->pspp_notify_required) { 5793 if (target_link_speed == RADEON_PCIE_GEN3) 5794 request = PCIE_PERF_REQ_PECI_GEN3; 5795 else if (target_link_speed == RADEON_PCIE_GEN2) 5796 request = PCIE_PERF_REQ_PECI_GEN2; 5797 else 5798 request = PCIE_PERF_REQ_PECI_GEN1; 5799 5800 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5801 (si_get_current_pcie_speed(rdev) > 0)) 5802 return; 5803 5804 #if defined(CONFIG_ACPI) 5805 radeon_acpi_pcie_performance_request(rdev, request, false); 5806 #endif 5807 } 5808 } 5809 5810 #if 0 5811 static int si_ds_request(struct radeon_device *rdev, 5812 bool ds_status_on, u32 count_write) 5813 { 5814 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5815 5816 if (eg_pi->sclk_deep_sleep) { 5817 if (ds_status_on) 5818 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5819 PPSMC_Result_OK) ? 5820 0 : -EINVAL; 5821 else 5822 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5823 PPSMC_Result_OK) ? 0 : -EINVAL; 5824 } 5825 return 0; 5826 } 5827 #endif 5828 5829 static void si_set_max_cu_value(struct radeon_device *rdev) 5830 { 5831 struct si_power_info *si_pi = si_get_pi(rdev); 5832 5833 if (rdev->family == CHIP_VERDE) { 5834 switch (rdev->pdev->device) { 5835 case 0x6820: 5836 case 0x6825: 5837 case 0x6821: 5838 case 0x6823: 5839 case 0x6827: 5840 si_pi->max_cu = 10; 5841 break; 5842 case 0x682D: 5843 case 0x6824: 5844 case 0x682F: 5845 case 0x6826: 5846 si_pi->max_cu = 8; 5847 break; 5848 case 0x6828: 5849 case 0x6830: 5850 case 0x6831: 5851 case 0x6838: 5852 case 0x6839: 5853 case 0x683D: 5854 si_pi->max_cu = 10; 5855 break; 5856 case 0x683B: 5857 case 0x683F: 5858 case 0x6829: 5859 si_pi->max_cu = 8; 5860 break; 5861 default: 5862 si_pi->max_cu = 0; 5863 break; 5864 } 5865 } else { 5866 si_pi->max_cu = 0; 5867 } 5868 } 5869 5870 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5871 struct radeon_clock_voltage_dependency_table *table) 5872 { 5873 u32 i; 5874 int j; 5875 u16 leakage_voltage; 5876 5877 if (table) { 5878 for (i = 0; i < table->count; i++) { 5879 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5880 table->entries[i].v, 5881 &leakage_voltage)) { 5882 case 0: 5883 table->entries[i].v = leakage_voltage; 5884 break; 5885 case -EAGAIN: 5886 return -EINVAL; 5887 case -EINVAL: 5888 default: 5889 break; 5890 } 5891 } 5892 5893 for (j = (table->count - 2); j >= 0; j--) { 5894 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5895 table->entries[j].v : table->entries[j + 1].v; 5896 } 5897 } 5898 return 0; 5899 } 5900 5901 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5902 { 5903 int ret = 0; 5904 5905 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5906 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5907 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5908 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5909 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5910 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5911 return ret; 5912 } 5913 5914 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5915 struct radeon_ps *radeon_new_state, 5916 struct radeon_ps *radeon_current_state) 5917 { 5918 u32 lane_width; 5919 u32 new_lane_width = 5920 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5921 u32 current_lane_width = 5922 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5923 5924 if (new_lane_width != current_lane_width) { 5925 radeon_set_pcie_lanes(rdev, new_lane_width); 5926 lane_width = radeon_get_pcie_lanes(rdev); 5927 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5928 } 5929 } 5930 5931 static void si_set_vce_clock(struct radeon_device *rdev, 5932 struct radeon_ps *new_rps, 5933 struct radeon_ps *old_rps) 5934 { 5935 if ((old_rps->evclk != new_rps->evclk) || 5936 (old_rps->ecclk != new_rps->ecclk)) { 5937 /* turn the clocks on when encoding, off otherwise */ 5938 if (new_rps->evclk || new_rps->ecclk) 5939 vce_v1_0_enable_mgcg(rdev, false); 5940 else 5941 vce_v1_0_enable_mgcg(rdev, true); 5942 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5943 } 5944 } 5945 5946 void si_dpm_setup_asic(struct radeon_device *rdev) 5947 { 5948 int r; 5949 5950 r = si_mc_load_microcode(rdev); 5951 if (r) 5952 DRM_ERROR("Failed to load MC firmware!\n"); 5953 rv770_get_memory_type(rdev); 5954 si_read_clock_registers(rdev); 5955 si_enable_acpi_power_management(rdev); 5956 } 5957 5958 static int si_thermal_enable_alert(struct radeon_device *rdev, 5959 bool enable) 5960 { 5961 u32 thermal_int = RREG32(CG_THERMAL_INT); 5962 5963 if (enable) { 5964 PPSMC_Result result; 5965 5966 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5967 WREG32(CG_THERMAL_INT, thermal_int); 5968 rdev->irq.dpm_thermal = false; 5969 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5970 if (result != PPSMC_Result_OK) { 5971 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5972 return -EINVAL; 5973 } 5974 } else { 5975 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5976 WREG32(CG_THERMAL_INT, thermal_int); 5977 rdev->irq.dpm_thermal = true; 5978 } 5979 5980 return 0; 5981 } 5982 5983 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5984 int min_temp, int max_temp) 5985 { 5986 int low_temp = 0 * 1000; 5987 int high_temp = 255 * 1000; 5988 5989 if (low_temp < min_temp) 5990 low_temp = min_temp; 5991 if (high_temp > max_temp) 5992 high_temp = max_temp; 5993 if (high_temp < low_temp) { 5994 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5995 return -EINVAL; 5996 } 5997 5998 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5999 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6000 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6001 6002 rdev->pm.dpm.thermal.min_temp = low_temp; 6003 rdev->pm.dpm.thermal.max_temp = high_temp; 6004 6005 return 0; 6006 } 6007 6008 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6009 { 6010 struct si_power_info *si_pi = si_get_pi(rdev); 6011 u32 tmp; 6012 6013 if (si_pi->fan_ctrl_is_in_default_mode) { 6014 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6015 si_pi->fan_ctrl_default_mode = tmp; 6016 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6017 si_pi->t_min = tmp; 6018 si_pi->fan_ctrl_is_in_default_mode = false; 6019 } 6020 6021 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6022 tmp |= TMIN(0); 6023 WREG32(CG_FDO_CTRL2, tmp); 6024 6025 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6026 tmp |= FDO_PWM_MODE(mode); 6027 WREG32(CG_FDO_CTRL2, tmp); 6028 } 6029 6030 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6031 { 6032 struct si_power_info *si_pi = si_get_pi(rdev); 6033 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6034 u32 duty100; 6035 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6036 u16 fdo_min, slope1, slope2; 6037 u32 reference_clock, tmp; 6038 int ret; 6039 u64 tmp64; 6040 6041 if (!si_pi->fan_table_start) { 6042 rdev->pm.dpm.fan.ucode_fan_control = false; 6043 return 0; 6044 } 6045 6046 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6047 6048 if (duty100 == 0) { 6049 rdev->pm.dpm.fan.ucode_fan_control = false; 6050 return 0; 6051 } 6052 6053 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6054 do_div(tmp64, 10000); 6055 fdo_min = (u16)tmp64; 6056 6057 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6058 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6059 6060 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6061 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6062 6063 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6064 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6065 6066 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6067 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6068 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6069 6070 fan_table.slope1 = cpu_to_be16(slope1); 6071 fan_table.slope2 = cpu_to_be16(slope2); 6072 6073 fan_table.fdo_min = cpu_to_be16(fdo_min); 6074 6075 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6076 6077 fan_table.hys_up = cpu_to_be16(1); 6078 6079 fan_table.hys_slope = cpu_to_be16(1); 6080 6081 fan_table.temp_resp_lim = cpu_to_be16(5); 6082 6083 reference_clock = radeon_get_xclk(rdev); 6084 6085 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6086 reference_clock) / 1600); 6087 6088 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6089 6090 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6091 fan_table.temp_src = (uint8_t)tmp; 6092 6093 ret = si_copy_bytes_to_smc(rdev, 6094 si_pi->fan_table_start, 6095 (u8 *)(&fan_table), 6096 sizeof(fan_table), 6097 si_pi->sram_end); 6098 6099 if (ret) { 6100 DRM_ERROR("Failed to load fan table to the SMC."); 6101 rdev->pm.dpm.fan.ucode_fan_control = false; 6102 } 6103 6104 return 0; 6105 } 6106 6107 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6108 { 6109 struct si_power_info *si_pi = si_get_pi(rdev); 6110 PPSMC_Result ret; 6111 6112 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6113 if (ret == PPSMC_Result_OK) { 6114 si_pi->fan_is_controlled_by_smc = true; 6115 return 0; 6116 } else { 6117 return -EINVAL; 6118 } 6119 } 6120 6121 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6122 { 6123 struct si_power_info *si_pi = si_get_pi(rdev); 6124 PPSMC_Result ret; 6125 6126 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6127 6128 if (ret == PPSMC_Result_OK) { 6129 si_pi->fan_is_controlled_by_smc = false; 6130 return 0; 6131 } else { 6132 return -EINVAL; 6133 } 6134 } 6135 6136 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6137 u32 *speed) 6138 { 6139 u32 duty, duty100; 6140 u64 tmp64; 6141 6142 if (rdev->pm.no_fan) 6143 return -ENOENT; 6144 6145 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6146 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6147 6148 if (duty100 == 0) 6149 return -EINVAL; 6150 6151 tmp64 = (u64)duty * 100; 6152 do_div(tmp64, duty100); 6153 *speed = (u32)tmp64; 6154 6155 if (*speed > 100) 6156 *speed = 100; 6157 6158 return 0; 6159 } 6160 6161 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6162 u32 speed) 6163 { 6164 struct si_power_info *si_pi = si_get_pi(rdev); 6165 u32 tmp; 6166 u32 duty, duty100; 6167 u64 tmp64; 6168 6169 if (rdev->pm.no_fan) 6170 return -ENOENT; 6171 6172 if (si_pi->fan_is_controlled_by_smc) 6173 return -EINVAL; 6174 6175 if (speed > 100) 6176 return -EINVAL; 6177 6178 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6179 6180 if (duty100 == 0) 6181 return -EINVAL; 6182 6183 tmp64 = (u64)speed * duty100; 6184 do_div(tmp64, 100); 6185 duty = (u32)tmp64; 6186 6187 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6188 tmp |= FDO_STATIC_DUTY(duty); 6189 WREG32(CG_FDO_CTRL0, tmp); 6190 6191 return 0; 6192 } 6193 6194 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6195 { 6196 if (mode) { 6197 /* stop auto-manage */ 6198 if (rdev->pm.dpm.fan.ucode_fan_control) 6199 si_fan_ctrl_stop_smc_fan_control(rdev); 6200 si_fan_ctrl_set_static_mode(rdev, mode); 6201 } else { 6202 /* restart auto-manage */ 6203 if (rdev->pm.dpm.fan.ucode_fan_control) 6204 si_thermal_start_smc_fan_control(rdev); 6205 else 6206 si_fan_ctrl_set_default_mode(rdev); 6207 } 6208 } 6209 6210 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6211 { 6212 struct si_power_info *si_pi = si_get_pi(rdev); 6213 u32 tmp; 6214 6215 if (si_pi->fan_is_controlled_by_smc) 6216 return 0; 6217 6218 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6219 return (tmp >> FDO_PWM_MODE_SHIFT); 6220 } 6221 6222 #if 0 6223 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6224 u32 *speed) 6225 { 6226 u32 tach_period; 6227 u32 xclk = radeon_get_xclk(rdev); 6228 6229 if (rdev->pm.no_fan) 6230 return -ENOENT; 6231 6232 if (rdev->pm.fan_pulses_per_revolution == 0) 6233 return -ENOENT; 6234 6235 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6236 if (tach_period == 0) 6237 return -ENOENT; 6238 6239 *speed = 60 * xclk * 10000 / tach_period; 6240 6241 return 0; 6242 } 6243 6244 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6245 u32 speed) 6246 { 6247 u32 tach_period, tmp; 6248 u32 xclk = radeon_get_xclk(rdev); 6249 6250 if (rdev->pm.no_fan) 6251 return -ENOENT; 6252 6253 if (rdev->pm.fan_pulses_per_revolution == 0) 6254 return -ENOENT; 6255 6256 if ((speed < rdev->pm.fan_min_rpm) || 6257 (speed > rdev->pm.fan_max_rpm)) 6258 return -EINVAL; 6259 6260 if (rdev->pm.dpm.fan.ucode_fan_control) 6261 si_fan_ctrl_stop_smc_fan_control(rdev); 6262 6263 tach_period = 60 * xclk * 10000 / (8 * speed); 6264 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6265 tmp |= TARGET_PERIOD(tach_period); 6266 WREG32(CG_TACH_CTRL, tmp); 6267 6268 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6269 6270 return 0; 6271 } 6272 #endif 6273 6274 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6275 { 6276 struct si_power_info *si_pi = si_get_pi(rdev); 6277 u32 tmp; 6278 6279 if (!si_pi->fan_ctrl_is_in_default_mode) { 6280 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6281 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6282 WREG32(CG_FDO_CTRL2, tmp); 6283 6284 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6285 tmp |= TMIN(si_pi->t_min); 6286 WREG32(CG_FDO_CTRL2, tmp); 6287 si_pi->fan_ctrl_is_in_default_mode = true; 6288 } 6289 } 6290 6291 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6292 { 6293 if (rdev->pm.dpm.fan.ucode_fan_control) { 6294 si_fan_ctrl_start_smc_fan_control(rdev); 6295 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6296 } 6297 } 6298 6299 static void si_thermal_initialize(struct radeon_device *rdev) 6300 { 6301 u32 tmp; 6302 6303 if (rdev->pm.fan_pulses_per_revolution) { 6304 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6305 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6306 WREG32(CG_TACH_CTRL, tmp); 6307 } 6308 6309 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6310 tmp |= TACH_PWM_RESP_RATE(0x28); 6311 WREG32(CG_FDO_CTRL2, tmp); 6312 } 6313 6314 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6315 { 6316 int ret; 6317 6318 si_thermal_initialize(rdev); 6319 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6320 if (ret) 6321 return ret; 6322 ret = si_thermal_enable_alert(rdev, true); 6323 if (ret) 6324 return ret; 6325 if (rdev->pm.dpm.fan.ucode_fan_control) { 6326 ret = si_halt_smc(rdev); 6327 if (ret) 6328 return ret; 6329 ret = si_thermal_setup_fan_table(rdev); 6330 if (ret) 6331 return ret; 6332 ret = si_resume_smc(rdev); 6333 if (ret) 6334 return ret; 6335 si_thermal_start_smc_fan_control(rdev); 6336 } 6337 6338 return 0; 6339 } 6340 6341 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6342 { 6343 if (!rdev->pm.no_fan) { 6344 si_fan_ctrl_set_default_mode(rdev); 6345 si_fan_ctrl_stop_smc_fan_control(rdev); 6346 } 6347 } 6348 6349 int si_dpm_enable(struct radeon_device *rdev) 6350 { 6351 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6352 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6353 struct si_power_info *si_pi = si_get_pi(rdev); 6354 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6355 int ret; 6356 6357 if (si_is_smc_running(rdev)) 6358 return -EINVAL; 6359 if (pi->voltage_control || si_pi->voltage_control_svi2) 6360 si_enable_voltage_control(rdev, true); 6361 if (pi->mvdd_control) 6362 si_get_mvdd_configuration(rdev); 6363 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6364 ret = si_construct_voltage_tables(rdev); 6365 if (ret) { 6366 DRM_ERROR("si_construct_voltage_tables failed\n"); 6367 return ret; 6368 } 6369 } 6370 if (eg_pi->dynamic_ac_timing) { 6371 ret = si_initialize_mc_reg_table(rdev); 6372 if (ret) 6373 eg_pi->dynamic_ac_timing = false; 6374 } 6375 if (pi->dynamic_ss) 6376 si_enable_spread_spectrum(rdev, true); 6377 if (pi->thermal_protection) 6378 si_enable_thermal_protection(rdev, true); 6379 si_setup_bsp(rdev); 6380 si_program_git(rdev); 6381 si_program_tp(rdev); 6382 si_program_tpp(rdev); 6383 si_program_sstp(rdev); 6384 si_enable_display_gap(rdev); 6385 si_program_vc(rdev); 6386 ret = si_upload_firmware(rdev); 6387 if (ret) { 6388 DRM_ERROR("si_upload_firmware failed\n"); 6389 return ret; 6390 } 6391 ret = si_process_firmware_header(rdev); 6392 if (ret) { 6393 DRM_ERROR("si_process_firmware_header failed\n"); 6394 return ret; 6395 } 6396 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6397 if (ret) { 6398 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6399 return ret; 6400 } 6401 ret = si_init_smc_table(rdev); 6402 if (ret) { 6403 DRM_ERROR("si_init_smc_table failed\n"); 6404 return ret; 6405 } 6406 ret = si_init_smc_spll_table(rdev); 6407 if (ret) { 6408 DRM_ERROR("si_init_smc_spll_table failed\n"); 6409 return ret; 6410 } 6411 ret = si_init_arb_table_index(rdev); 6412 if (ret) { 6413 DRM_ERROR("si_init_arb_table_index failed\n"); 6414 return ret; 6415 } 6416 if (eg_pi->dynamic_ac_timing) { 6417 ret = si_populate_mc_reg_table(rdev, boot_ps); 6418 if (ret) { 6419 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6420 return ret; 6421 } 6422 } 6423 ret = si_initialize_smc_cac_tables(rdev); 6424 if (ret) { 6425 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6426 return ret; 6427 } 6428 ret = si_initialize_hardware_cac_manager(rdev); 6429 if (ret) { 6430 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6431 return ret; 6432 } 6433 ret = si_initialize_smc_dte_tables(rdev); 6434 if (ret) { 6435 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6436 return ret; 6437 } 6438 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6439 if (ret) { 6440 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6441 return ret; 6442 } 6443 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6444 if (ret) { 6445 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6446 return ret; 6447 } 6448 si_program_response_times(rdev); 6449 si_program_ds_registers(rdev); 6450 si_dpm_start_smc(rdev); 6451 ret = si_notify_smc_display_change(rdev, false); 6452 if (ret) { 6453 DRM_ERROR("si_notify_smc_display_change failed\n"); 6454 return ret; 6455 } 6456 si_enable_sclk_control(rdev, true); 6457 si_start_dpm(rdev); 6458 6459 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6460 6461 si_thermal_start_thermal_controller(rdev); 6462 6463 ni_update_current_ps(rdev, boot_ps); 6464 6465 return 0; 6466 } 6467 6468 static int si_set_temperature_range(struct radeon_device *rdev) 6469 { 6470 int ret; 6471 6472 ret = si_thermal_enable_alert(rdev, false); 6473 if (ret) 6474 return ret; 6475 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6476 if (ret) 6477 return ret; 6478 ret = si_thermal_enable_alert(rdev, true); 6479 if (ret) 6480 return ret; 6481 6482 return ret; 6483 } 6484 6485 int si_dpm_late_enable(struct radeon_device *rdev) 6486 { 6487 int ret; 6488 6489 ret = si_set_temperature_range(rdev); 6490 if (ret) 6491 return ret; 6492 6493 return ret; 6494 } 6495 6496 void si_dpm_disable(struct radeon_device *rdev) 6497 { 6498 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6499 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6500 6501 if (!si_is_smc_running(rdev)) 6502 return; 6503 si_thermal_stop_thermal_controller(rdev); 6504 si_disable_ulv(rdev); 6505 si_clear_vc(rdev); 6506 if (pi->thermal_protection) 6507 si_enable_thermal_protection(rdev, false); 6508 si_enable_power_containment(rdev, boot_ps, false); 6509 si_enable_smc_cac(rdev, boot_ps, false); 6510 si_enable_spread_spectrum(rdev, false); 6511 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6512 si_stop_dpm(rdev); 6513 si_reset_to_default(rdev); 6514 si_dpm_stop_smc(rdev); 6515 si_force_switch_to_arb_f0(rdev); 6516 6517 ni_update_current_ps(rdev, boot_ps); 6518 } 6519 6520 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6521 { 6522 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6523 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6524 struct radeon_ps *new_ps = &requested_ps; 6525 6526 ni_update_requested_ps(rdev, new_ps); 6527 6528 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6529 6530 return 0; 6531 } 6532 6533 static int si_power_control_set_level(struct radeon_device *rdev) 6534 { 6535 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6536 int ret; 6537 6538 ret = si_restrict_performance_levels_before_switch(rdev); 6539 if (ret) 6540 return ret; 6541 ret = si_halt_smc(rdev); 6542 if (ret) 6543 return ret; 6544 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6545 if (ret) 6546 return ret; 6547 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6548 if (ret) 6549 return ret; 6550 ret = si_resume_smc(rdev); 6551 if (ret) 6552 return ret; 6553 ret = si_set_sw_state(rdev); 6554 if (ret) 6555 return ret; 6556 return 0; 6557 } 6558 6559 int si_dpm_set_power_state(struct radeon_device *rdev) 6560 { 6561 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6562 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6563 struct radeon_ps *old_ps = &eg_pi->current_rps; 6564 int ret; 6565 6566 ret = si_disable_ulv(rdev); 6567 if (ret) { 6568 DRM_ERROR("si_disable_ulv failed\n"); 6569 return ret; 6570 } 6571 ret = si_restrict_performance_levels_before_switch(rdev); 6572 if (ret) { 6573 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6574 return ret; 6575 } 6576 if (eg_pi->pcie_performance_request) 6577 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6578 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6579 ret = si_enable_power_containment(rdev, new_ps, false); 6580 if (ret) { 6581 DRM_ERROR("si_enable_power_containment failed\n"); 6582 return ret; 6583 } 6584 ret = si_enable_smc_cac(rdev, new_ps, false); 6585 if (ret) { 6586 DRM_ERROR("si_enable_smc_cac failed\n"); 6587 return ret; 6588 } 6589 ret = si_halt_smc(rdev); 6590 if (ret) { 6591 DRM_ERROR("si_halt_smc failed\n"); 6592 return ret; 6593 } 6594 ret = si_upload_sw_state(rdev, new_ps); 6595 if (ret) { 6596 DRM_ERROR("si_upload_sw_state failed\n"); 6597 return ret; 6598 } 6599 ret = si_upload_smc_data(rdev); 6600 if (ret) { 6601 DRM_ERROR("si_upload_smc_data failed\n"); 6602 return ret; 6603 } 6604 ret = si_upload_ulv_state(rdev); 6605 if (ret) { 6606 DRM_ERROR("si_upload_ulv_state failed\n"); 6607 return ret; 6608 } 6609 if (eg_pi->dynamic_ac_timing) { 6610 ret = si_upload_mc_reg_table(rdev, new_ps); 6611 if (ret) { 6612 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6613 return ret; 6614 } 6615 } 6616 ret = si_program_memory_timing_parameters(rdev, new_ps); 6617 if (ret) { 6618 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6619 return ret; 6620 } 6621 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6622 6623 ret = si_resume_smc(rdev); 6624 if (ret) { 6625 DRM_ERROR("si_resume_smc failed\n"); 6626 return ret; 6627 } 6628 ret = si_set_sw_state(rdev); 6629 if (ret) { 6630 DRM_ERROR("si_set_sw_state failed\n"); 6631 return ret; 6632 } 6633 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6634 si_set_vce_clock(rdev, new_ps, old_ps); 6635 if (eg_pi->pcie_performance_request) 6636 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6637 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6638 if (ret) { 6639 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6640 return ret; 6641 } 6642 ret = si_enable_smc_cac(rdev, new_ps, true); 6643 if (ret) { 6644 DRM_ERROR("si_enable_smc_cac failed\n"); 6645 return ret; 6646 } 6647 ret = si_enable_power_containment(rdev, new_ps, true); 6648 if (ret) { 6649 DRM_ERROR("si_enable_power_containment failed\n"); 6650 return ret; 6651 } 6652 6653 ret = si_power_control_set_level(rdev); 6654 if (ret) { 6655 DRM_ERROR("si_power_control_set_level failed\n"); 6656 return ret; 6657 } 6658 6659 return 0; 6660 } 6661 6662 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6663 { 6664 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6665 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6666 6667 ni_update_current_ps(rdev, new_ps); 6668 } 6669 6670 #if 0 6671 void si_dpm_reset_asic(struct radeon_device *rdev) 6672 { 6673 si_restrict_performance_levels_before_switch(rdev); 6674 si_disable_ulv(rdev); 6675 si_set_boot_state(rdev); 6676 } 6677 #endif 6678 6679 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6680 { 6681 si_program_display_gap(rdev); 6682 } 6683 6684 union power_info { 6685 struct _ATOM_POWERPLAY_INFO info; 6686 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6687 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6688 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6689 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6690 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6691 }; 6692 6693 union pplib_clock_info { 6694 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6695 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6696 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6697 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6698 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6699 }; 6700 6701 union pplib_power_state { 6702 struct _ATOM_PPLIB_STATE v1; 6703 struct _ATOM_PPLIB_STATE_V2 v2; 6704 }; 6705 6706 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6707 struct radeon_ps *rps, 6708 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6709 u8 table_rev) 6710 { 6711 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6712 rps->class = le16_to_cpu(non_clock_info->usClassification); 6713 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6714 6715 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6716 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6717 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6718 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6719 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6720 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6721 } else { 6722 rps->vclk = 0; 6723 rps->dclk = 0; 6724 } 6725 6726 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6727 rdev->pm.dpm.boot_ps = rps; 6728 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6729 rdev->pm.dpm.uvd_ps = rps; 6730 } 6731 6732 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6733 struct radeon_ps *rps, int index, 6734 union pplib_clock_info *clock_info) 6735 { 6736 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6737 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6738 struct si_power_info *si_pi = si_get_pi(rdev); 6739 struct ni_ps *ps = ni_get_ps(rps); 6740 u16 leakage_voltage; 6741 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6742 int ret; 6743 6744 ps->performance_level_count = index + 1; 6745 6746 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6747 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6748 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6749 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6750 6751 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6752 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6753 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6754 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6755 si_pi->sys_pcie_mask, 6756 si_pi->boot_pcie_gen, 6757 clock_info->si.ucPCIEGen); 6758 6759 /* patch up vddc if necessary */ 6760 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6761 &leakage_voltage); 6762 if (ret == 0) 6763 pl->vddc = leakage_voltage; 6764 6765 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6766 pi->acpi_vddc = pl->vddc; 6767 eg_pi->acpi_vddci = pl->vddci; 6768 si_pi->acpi_pcie_gen = pl->pcie_gen; 6769 } 6770 6771 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6772 index == 0) { 6773 /* XXX disable for A0 tahiti */ 6774 si_pi->ulv.supported = false; 6775 si_pi->ulv.pl = *pl; 6776 si_pi->ulv.one_pcie_lane_in_ulv = false; 6777 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6778 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6779 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6780 } 6781 6782 if (pi->min_vddc_in_table > pl->vddc) 6783 pi->min_vddc_in_table = pl->vddc; 6784 6785 if (pi->max_vddc_in_table < pl->vddc) 6786 pi->max_vddc_in_table = pl->vddc; 6787 6788 /* patch up boot state */ 6789 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6790 u16 vddc, vddci, mvdd; 6791 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6792 pl->mclk = rdev->clock.default_mclk; 6793 pl->sclk = rdev->clock.default_sclk; 6794 pl->vddc = vddc; 6795 pl->vddci = vddci; 6796 si_pi->mvdd_bootup_value = mvdd; 6797 } 6798 6799 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6800 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6801 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6802 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6803 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6804 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6805 } 6806 } 6807 6808 static int si_parse_power_table(struct radeon_device *rdev) 6809 { 6810 struct radeon_mode_info *mode_info = &rdev->mode_info; 6811 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6812 union pplib_power_state *power_state; 6813 int i, j, k, non_clock_array_index, clock_array_index; 6814 union pplib_clock_info *clock_info; 6815 struct _StateArray *state_array; 6816 struct _ClockInfoArray *clock_info_array; 6817 struct _NonClockInfoArray *non_clock_info_array; 6818 union power_info *power_info; 6819 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6820 u16 data_offset; 6821 u8 frev, crev; 6822 u8 *power_state_offset; 6823 struct ni_ps *ps; 6824 6825 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6826 &frev, &crev, &data_offset)) 6827 return -EINVAL; 6828 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6829 6830 state_array = (struct _StateArray *) 6831 (mode_info->atom_context->bios + data_offset + 6832 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6833 clock_info_array = (struct _ClockInfoArray *) 6834 (mode_info->atom_context->bios + data_offset + 6835 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6836 non_clock_info_array = (struct _NonClockInfoArray *) 6837 (mode_info->atom_context->bios + data_offset + 6838 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6839 6840 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 6841 sizeof(struct radeon_ps), 6842 GFP_KERNEL); 6843 if (!rdev->pm.dpm.ps) 6844 return -ENOMEM; 6845 power_state_offset = (u8 *)state_array->states; 6846 for (i = 0; i < state_array->ucNumEntries; i++) { 6847 u8 *idx; 6848 power_state = (union pplib_power_state *)power_state_offset; 6849 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6850 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6851 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6852 if (!rdev->pm.power_state[i].clock_info) 6853 return -EINVAL; 6854 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6855 if (ps == NULL) { 6856 kfree(rdev->pm.dpm.ps); 6857 return -ENOMEM; 6858 } 6859 rdev->pm.dpm.ps[i].ps_priv = ps; 6860 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6861 non_clock_info, 6862 non_clock_info_array->ucEntrySize); 6863 k = 0; 6864 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6865 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6866 clock_array_index = idx[j]; 6867 if (clock_array_index >= clock_info_array->ucNumEntries) 6868 continue; 6869 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6870 break; 6871 clock_info = (union pplib_clock_info *) 6872 ((u8 *)&clock_info_array->clockInfo[0] + 6873 (clock_array_index * clock_info_array->ucEntrySize)); 6874 si_parse_pplib_clock_info(rdev, 6875 &rdev->pm.dpm.ps[i], k, 6876 clock_info); 6877 k++; 6878 } 6879 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6880 } 6881 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6882 6883 /* fill in the vce power states */ 6884 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6885 u32 sclk, mclk; 6886 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6887 clock_info = (union pplib_clock_info *) 6888 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6889 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6890 sclk |= clock_info->si.ucEngineClockHigh << 16; 6891 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6892 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6893 rdev->pm.dpm.vce_states[i].sclk = sclk; 6894 rdev->pm.dpm.vce_states[i].mclk = mclk; 6895 } 6896 6897 return 0; 6898 } 6899 6900 int si_dpm_init(struct radeon_device *rdev) 6901 { 6902 struct rv7xx_power_info *pi; 6903 struct evergreen_power_info *eg_pi; 6904 struct ni_power_info *ni_pi; 6905 struct si_power_info *si_pi; 6906 struct atom_clock_dividers dividers; 6907 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 6908 struct pci_dev *root = rdev->pdev->bus->self; 6909 int ret; 6910 6911 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6912 if (si_pi == NULL) 6913 return -ENOMEM; 6914 rdev->pm.dpm.priv = si_pi; 6915 ni_pi = &si_pi->ni; 6916 eg_pi = &ni_pi->eg; 6917 pi = &eg_pi->rv7xx; 6918 6919 if (!pci_is_root_bus(rdev->pdev->bus)) 6920 speed_cap = pcie_get_speed_cap(root); 6921 if (speed_cap == PCI_SPEED_UNKNOWN) { 6922 si_pi->sys_pcie_mask = 0; 6923 } else { 6924 if (speed_cap == PCIE_SPEED_8_0GT) 6925 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6926 RADEON_PCIE_SPEED_50 | 6927 RADEON_PCIE_SPEED_80; 6928 else if (speed_cap == PCIE_SPEED_5_0GT) 6929 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6930 RADEON_PCIE_SPEED_50; 6931 else 6932 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 6933 } 6934 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6935 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6936 6937 si_set_max_cu_value(rdev); 6938 6939 rv770_get_max_vddc(rdev); 6940 si_get_leakage_vddc(rdev); 6941 si_patch_dependency_tables_based_on_leakage(rdev); 6942 6943 pi->acpi_vddc = 0; 6944 eg_pi->acpi_vddci = 0; 6945 pi->min_vddc_in_table = 0; 6946 pi->max_vddc_in_table = 0; 6947 6948 ret = r600_get_platform_caps(rdev); 6949 if (ret) 6950 return ret; 6951 6952 ret = r600_parse_extended_power_table(rdev); 6953 if (ret) 6954 return ret; 6955 6956 ret = si_parse_power_table(rdev); 6957 if (ret) 6958 return ret; 6959 6960 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6961 kcalloc(4, 6962 sizeof(struct radeon_clock_voltage_dependency_entry), 6963 GFP_KERNEL); 6964 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6965 r600_free_extended_power_table(rdev); 6966 return -ENOMEM; 6967 } 6968 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6973 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6974 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6975 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6976 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6977 6978 if (rdev->pm.dpm.voltage_response_time == 0) 6979 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6980 if (rdev->pm.dpm.backbias_response_time == 0) 6981 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6982 6983 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6984 0, false, ÷rs); 6985 if (ret) 6986 pi->ref_div = dividers.ref_div + 1; 6987 else 6988 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6989 6990 eg_pi->smu_uvd_hs = false; 6991 6992 pi->mclk_strobe_mode_threshold = 40000; 6993 if (si_is_special_1gb_platform(rdev)) 6994 pi->mclk_stutter_mode_threshold = 0; 6995 else 6996 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6997 pi->mclk_edc_enable_threshold = 40000; 6998 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6999 7000 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7001 7002 pi->voltage_control = 7003 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7004 VOLTAGE_OBJ_GPIO_LUT); 7005 if (!pi->voltage_control) { 7006 si_pi->voltage_control_svi2 = 7007 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7008 VOLTAGE_OBJ_SVID2); 7009 if (si_pi->voltage_control_svi2) 7010 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7011 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7012 } 7013 7014 pi->mvdd_control = 7015 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7016 VOLTAGE_OBJ_GPIO_LUT); 7017 7018 eg_pi->vddci_control = 7019 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7020 VOLTAGE_OBJ_GPIO_LUT); 7021 if (!eg_pi->vddci_control) 7022 si_pi->vddci_control_svi2 = 7023 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7024 VOLTAGE_OBJ_SVID2); 7025 7026 si_pi->vddc_phase_shed_control = 7027 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7028 VOLTAGE_OBJ_PHASE_LUT); 7029 7030 rv770_get_engine_memory_ss(rdev); 7031 7032 pi->asi = RV770_ASI_DFLT; 7033 pi->pasi = CYPRESS_HASI_DFLT; 7034 pi->vrc = SISLANDS_VRC_DFLT; 7035 7036 pi->gfx_clock_gating = true; 7037 7038 eg_pi->sclk_deep_sleep = true; 7039 si_pi->sclk_deep_sleep_above_low = false; 7040 7041 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7042 pi->thermal_protection = true; 7043 else 7044 pi->thermal_protection = false; 7045 7046 eg_pi->dynamic_ac_timing = true; 7047 7048 eg_pi->light_sleep = true; 7049 #if defined(CONFIG_ACPI) 7050 eg_pi->pcie_performance_request = 7051 radeon_acpi_is_pcie_performance_request_supported(rdev); 7052 #else 7053 eg_pi->pcie_performance_request = false; 7054 #endif 7055 7056 si_pi->sram_end = SMC_RAM_END; 7057 7058 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7059 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7060 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7061 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7062 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7063 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7064 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7065 7066 si_initialize_powertune_defaults(rdev); 7067 7068 /* make sure dc limits are valid */ 7069 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7070 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7071 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7072 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7073 7074 si_pi->fan_ctrl_is_in_default_mode = true; 7075 7076 return 0; 7077 } 7078 7079 void si_dpm_fini(struct radeon_device *rdev) 7080 { 7081 int i; 7082 7083 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7084 kfree(rdev->pm.dpm.ps[i].ps_priv); 7085 } 7086 kfree(rdev->pm.dpm.ps); 7087 kfree(rdev->pm.dpm.priv); 7088 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7089 r600_free_extended_power_table(rdev); 7090 } 7091 7092 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7093 struct seq_file *m) 7094 { 7095 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7096 struct radeon_ps *rps = &eg_pi->current_rps; 7097 struct ni_ps *ps = ni_get_ps(rps); 7098 struct rv7xx_pl *pl; 7099 u32 current_index = 7100 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7101 CURRENT_STATE_INDEX_SHIFT; 7102 7103 if (current_index >= ps->performance_level_count) { 7104 seq_printf(m, "invalid dpm profile %d\n", current_index); 7105 } else { 7106 pl = &ps->performance_levels[current_index]; 7107 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7108 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7109 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7110 } 7111 } 7112 7113 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7114 { 7115 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7116 struct radeon_ps *rps = &eg_pi->current_rps; 7117 struct ni_ps *ps = ni_get_ps(rps); 7118 struct rv7xx_pl *pl; 7119 u32 current_index = 7120 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7121 CURRENT_STATE_INDEX_SHIFT; 7122 7123 if (current_index >= ps->performance_level_count) { 7124 return 0; 7125 } else { 7126 pl = &ps->performance_levels[current_index]; 7127 return pl->sclk; 7128 } 7129 } 7130 7131 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7132 { 7133 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7134 struct radeon_ps *rps = &eg_pi->current_rps; 7135 struct ni_ps *ps = ni_get_ps(rps); 7136 struct rv7xx_pl *pl; 7137 u32 current_index = 7138 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7139 CURRENT_STATE_INDEX_SHIFT; 7140 7141 if (current_index >= ps->performance_level_count) { 7142 return 0; 7143 } else { 7144 pl = &ps->performance_levels[current_index]; 7145 return pl->mclk; 7146 } 7147 } 7148