1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "drmP.h" 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 static const struct si_dte_data dte_data_tahiti_le = 255 { 256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 258 0x5, 259 0xAFC8, 260 0x64, 261 0x32, 262 1, 263 0, 264 0x10, 265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 268 85, 269 true 270 }; 271 272 static const struct si_dte_data dte_data_tahiti_pro = 273 { 274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 275 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 276 5, 277 45000, 278 100, 279 0xA, 280 1, 281 0, 282 0x10, 283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 286 90, 287 true 288 }; 289 290 static const struct si_dte_data dte_data_new_zealand = 291 { 292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 294 0x5, 295 0xAFC8, 296 0x69, 297 0x32, 298 1, 299 0, 300 0x10, 301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 304 85, 305 true 306 }; 307 308 static const struct si_dte_data dte_data_aruba_pro = 309 { 310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 311 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 312 5, 313 45000, 314 100, 315 0xA, 316 1, 317 0, 318 0x10, 319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 322 90, 323 true 324 }; 325 326 static const struct si_dte_data dte_data_malta = 327 { 328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 329 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 330 5, 331 45000, 332 100, 333 0xA, 334 1, 335 0, 336 0x10, 337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 340 90, 341 true 342 }; 343 344 struct si_cac_config_reg cac_weights_pitcairn[] = 345 { 346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 406 { 0xFFFFFFFF } 407 }; 408 409 static const struct si_cac_config_reg lcac_pitcairn[] = 410 { 411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0xFFFFFFFF } 498 }; 499 500 static const struct si_cac_config_reg cac_override_pitcairn[] = 501 { 502 { 0xFFFFFFFF } 503 }; 504 505 static const struct si_powertune_data powertune_data_pitcairn = 506 { 507 ((1 << 16) | 27027), 508 5, 509 0, 510 6, 511 100, 512 { 513 51600000UL, 514 1800000UL, 515 7194395UL, 516 309631529UL, 517 -1270850L, 518 4513710L, 519 100 520 }, 521 117830498UL, 522 12, 523 { 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0 532 }, 533 true 534 }; 535 536 static const struct si_dte_data dte_data_pitcairn = 537 { 538 { 0, 0, 0, 0, 0 }, 539 { 0, 0, 0, 0, 0 }, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 0, 551 false 552 }; 553 554 static const struct si_dte_data dte_data_curacao_xt = 555 { 556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 557 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 558 5, 559 45000, 560 100, 561 0xA, 562 1, 563 0, 564 0x10, 565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 568 90, 569 true 570 }; 571 572 static const struct si_dte_data dte_data_curacao_pro = 573 { 574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 575 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 576 5, 577 45000, 578 100, 579 0xA, 580 1, 581 0, 582 0x10, 583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 586 90, 587 true 588 }; 589 590 static const struct si_dte_data dte_data_neptune_xt = 591 { 592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 593 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 594 5, 595 45000, 596 100, 597 0xA, 598 1, 599 0, 600 0x10, 601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 604 90, 605 true 606 }; 607 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 609 { 610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 670 { 0xFFFFFFFF } 671 }; 672 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 674 { 675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 735 { 0xFFFFFFFF } 736 }; 737 738 static const struct si_cac_config_reg cac_weights_heathrow[] = 739 { 740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 800 { 0xFFFFFFFF } 801 }; 802 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 804 { 805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 865 { 0xFFFFFFFF } 866 }; 867 868 static const struct si_cac_config_reg cac_weights_cape_verde[] = 869 { 870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 930 { 0xFFFFFFFF } 931 }; 932 933 static const struct si_cac_config_reg lcac_cape_verde[] = 934 { 935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0xFFFFFFFF } 990 }; 991 992 static const struct si_cac_config_reg cac_override_cape_verde[] = 993 { 994 { 0xFFFFFFFF } 995 }; 996 997 static const struct si_powertune_data powertune_data_cape_verde = 998 { 999 ((1 << 16) | 0x6993), 1000 5, 1001 0, 1002 7, 1003 105, 1004 { 1005 0UL, 1006 0UL, 1007 7194395UL, 1008 309631529UL, 1009 -1270850L, 1010 4513710L, 1011 100 1012 }, 1013 117830498UL, 1014 12, 1015 { 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0 1024 }, 1025 true 1026 }; 1027 1028 static const struct si_dte_data dte_data_cape_verde = 1029 { 1030 { 0, 0, 0, 0, 0 }, 1031 { 0, 0, 0, 0, 0 }, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 0, 1043 false 1044 }; 1045 1046 static const struct si_dte_data dte_data_venus_xtx = 1047 { 1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1050 5, 1051 55000, 1052 0x69, 1053 0xA, 1054 1, 1055 0, 1056 0x3, 1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 90, 1061 true 1062 }; 1063 1064 static const struct si_dte_data dte_data_venus_xt = 1065 { 1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1068 5, 1069 55000, 1070 0x69, 1071 0xA, 1072 1, 1073 0, 1074 0x3, 1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 90, 1079 true 1080 }; 1081 1082 static const struct si_dte_data dte_data_venus_pro = 1083 { 1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1086 5, 1087 55000, 1088 0x69, 1089 0xA, 1090 1, 1091 0, 1092 0x3, 1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 90, 1097 true 1098 }; 1099 1100 struct si_cac_config_reg cac_weights_oland[] = 1101 { 1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1162 { 0xFFFFFFFF } 1163 }; 1164 1165 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1166 { 1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1227 { 0xFFFFFFFF } 1228 }; 1229 1230 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1231 { 1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1292 { 0xFFFFFFFF } 1293 }; 1294 1295 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1296 { 1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1357 { 0xFFFFFFFF } 1358 }; 1359 1360 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1361 { 1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1422 { 0xFFFFFFFF } 1423 }; 1424 1425 static const struct si_cac_config_reg lcac_oland[] = 1426 { 1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0xFFFFFFFF } 1470 }; 1471 1472 static const struct si_cac_config_reg lcac_mars_pro[] = 1473 { 1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0xFFFFFFFF } 1517 }; 1518 1519 static const struct si_cac_config_reg cac_override_oland[] = 1520 { 1521 { 0xFFFFFFFF } 1522 }; 1523 1524 static const struct si_powertune_data powertune_data_oland = 1525 { 1526 ((1 << 16) | 0x6993), 1527 5, 1528 0, 1529 7, 1530 105, 1531 { 1532 0UL, 1533 0UL, 1534 7194395UL, 1535 309631529UL, 1536 -1270850L, 1537 4513710L, 1538 100 1539 }, 1540 117830498UL, 1541 12, 1542 { 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0 1551 }, 1552 true 1553 }; 1554 1555 static const struct si_powertune_data powertune_data_mars_pro = 1556 { 1557 ((1 << 16) | 0x6993), 1558 5, 1559 0, 1560 7, 1561 105, 1562 { 1563 0UL, 1564 0UL, 1565 7194395UL, 1566 309631529UL, 1567 -1270850L, 1568 4513710L, 1569 100 1570 }, 1571 117830498UL, 1572 12, 1573 { 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0 1582 }, 1583 true 1584 }; 1585 1586 static const struct si_dte_data dte_data_oland = 1587 { 1588 { 0, 0, 0, 0, 0 }, 1589 { 0, 0, 0, 0, 0 }, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 0, 1601 false 1602 }; 1603 1604 static const struct si_dte_data dte_data_mars_pro = 1605 { 1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1607 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1608 5, 1609 55000, 1610 105, 1611 0xA, 1612 1, 1613 0, 1614 0x10, 1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1618 90, 1619 true 1620 }; 1621 1622 static const struct si_dte_data dte_data_sun_xt = 1623 { 1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1625 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1626 5, 1627 55000, 1628 105, 1629 0xA, 1630 1, 1631 0, 1632 0x10, 1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1636 90, 1637 true 1638 }; 1639 1640 1641 static const struct si_cac_config_reg cac_weights_hainan[] = 1642 { 1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1703 { 0xFFFFFFFF } 1704 }; 1705 1706 static const struct si_powertune_data powertune_data_hainan = 1707 { 1708 ((1 << 16) | 0x6993), 1709 5, 1710 0, 1711 9, 1712 105, 1713 { 1714 0UL, 1715 0UL, 1716 7194395UL, 1717 309631529UL, 1718 -1270850L, 1719 4513710L, 1720 100 1721 }, 1722 117830498UL, 1723 12, 1724 { 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0 1733 }, 1734 true 1735 }; 1736 1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1741 1742 extern int si_mc_load_microcode(struct radeon_device *rdev); 1743 1744 static int si_populate_voltage_value(struct radeon_device *rdev, 1745 const struct atom_voltage_table *table, 1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1747 static int si_get_std_voltage_value(struct radeon_device *rdev, 1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1749 u16 *std_voltage); 1750 static int si_write_smc_soft_register(struct radeon_device *rdev, 1751 u16 reg_offset, u32 value); 1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1753 struct rv7xx_pl *pl, 1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1755 static int si_calculate_sclk_params(struct radeon_device *rdev, 1756 u32 engine_clock, 1757 SISLANDS_SMC_SCLK_VALUE *sclk); 1758 1759 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1760 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1761 1762 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1763 { 1764 struct si_power_info *pi = rdev->pm.dpm.priv; 1765 1766 return pi; 1767 } 1768 1769 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1770 u16 v, s32 t, u32 ileakage, u32 *leakage) 1771 { 1772 s64 kt, kv, leakage_w, i_leakage, vddc; 1773 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1774 s64 tmp; 1775 1776 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1777 vddc = div64_s64(drm_int2fixp(v), 1000); 1778 temperature = div64_s64(drm_int2fixp(t), 1000); 1779 1780 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1781 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1782 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1783 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1784 t_ref = drm_int2fixp(coeff->t_ref); 1785 1786 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1787 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1788 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1789 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1790 1791 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1792 1793 *leakage = drm_fixp2int(leakage_w * 1000); 1794 } 1795 1796 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1797 const struct ni_leakage_coeffients *coeff, 1798 u16 v, 1799 s32 t, 1800 u32 i_leakage, 1801 u32 *leakage) 1802 { 1803 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1804 } 1805 1806 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1807 const u32 fixed_kt, u16 v, 1808 u32 ileakage, u32 *leakage) 1809 { 1810 s64 kt, kv, leakage_w, i_leakage, vddc; 1811 1812 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1813 vddc = div64_s64(drm_int2fixp(v), 1000); 1814 1815 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1816 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1817 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1818 1819 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1820 1821 *leakage = drm_fixp2int(leakage_w * 1000); 1822 } 1823 1824 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1825 const struct ni_leakage_coeffients *coeff, 1826 const u32 fixed_kt, 1827 u16 v, 1828 u32 i_leakage, 1829 u32 *leakage) 1830 { 1831 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1832 } 1833 1834 1835 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1836 struct si_dte_data *dte_data) 1837 { 1838 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1839 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1840 u32 k = dte_data->k; 1841 u32 t_max = dte_data->max_t; 1842 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1843 u32 t_0 = dte_data->t0; 1844 u32 i; 1845 1846 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1847 dte_data->tdep_count = 3; 1848 1849 for (i = 0; i < k; i++) { 1850 dte_data->r[i] = 1851 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1852 (p_limit2 * (u32)100); 1853 } 1854 1855 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1856 1857 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1858 dte_data->tdep_r[i] = dte_data->r[4]; 1859 } 1860 } else { 1861 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1862 } 1863 } 1864 1865 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1866 { 1867 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1868 struct si_power_info *si_pi = si_get_pi(rdev); 1869 bool update_dte_from_pl2 = false; 1870 1871 if (rdev->family == CHIP_TAHITI) { 1872 si_pi->cac_weights = cac_weights_tahiti; 1873 si_pi->lcac_config = lcac_tahiti; 1874 si_pi->cac_override = cac_override_tahiti; 1875 si_pi->powertune_data = &powertune_data_tahiti; 1876 si_pi->dte_data = dte_data_tahiti; 1877 1878 switch (rdev->pdev->device) { 1879 case 0x6798: 1880 si_pi->dte_data.enable_dte_by_default = true; 1881 break; 1882 case 0x6799: 1883 si_pi->dte_data = dte_data_new_zealand; 1884 break; 1885 case 0x6790: 1886 case 0x6791: 1887 case 0x6792: 1888 case 0x679E: 1889 si_pi->dte_data = dte_data_aruba_pro; 1890 update_dte_from_pl2 = true; 1891 break; 1892 case 0x679B: 1893 si_pi->dte_data = dte_data_malta; 1894 update_dte_from_pl2 = true; 1895 break; 1896 case 0x679A: 1897 si_pi->dte_data = dte_data_tahiti_pro; 1898 update_dte_from_pl2 = true; 1899 break; 1900 default: 1901 if (si_pi->dte_data.enable_dte_by_default == true) 1902 DRM_ERROR("DTE is not enabled!\n"); 1903 break; 1904 } 1905 } else if (rdev->family == CHIP_PITCAIRN) { 1906 switch (rdev->pdev->device) { 1907 case 0x6810: 1908 case 0x6818: 1909 si_pi->cac_weights = cac_weights_pitcairn; 1910 si_pi->lcac_config = lcac_pitcairn; 1911 si_pi->cac_override = cac_override_pitcairn; 1912 si_pi->powertune_data = &powertune_data_pitcairn; 1913 si_pi->dte_data = dte_data_curacao_xt; 1914 update_dte_from_pl2 = true; 1915 break; 1916 case 0x6819: 1917 case 0x6811: 1918 si_pi->cac_weights = cac_weights_pitcairn; 1919 si_pi->lcac_config = lcac_pitcairn; 1920 si_pi->cac_override = cac_override_pitcairn; 1921 si_pi->powertune_data = &powertune_data_pitcairn; 1922 si_pi->dte_data = dte_data_curacao_pro; 1923 update_dte_from_pl2 = true; 1924 break; 1925 case 0x6800: 1926 case 0x6806: 1927 si_pi->cac_weights = cac_weights_pitcairn; 1928 si_pi->lcac_config = lcac_pitcairn; 1929 si_pi->cac_override = cac_override_pitcairn; 1930 si_pi->powertune_data = &powertune_data_pitcairn; 1931 si_pi->dte_data = dte_data_neptune_xt; 1932 update_dte_from_pl2 = true; 1933 break; 1934 default: 1935 si_pi->cac_weights = cac_weights_pitcairn; 1936 si_pi->lcac_config = lcac_pitcairn; 1937 si_pi->cac_override = cac_override_pitcairn; 1938 si_pi->powertune_data = &powertune_data_pitcairn; 1939 si_pi->dte_data = dte_data_pitcairn; 1940 break; 1941 } 1942 } else if (rdev->family == CHIP_VERDE) { 1943 si_pi->lcac_config = lcac_cape_verde; 1944 si_pi->cac_override = cac_override_cape_verde; 1945 si_pi->powertune_data = &powertune_data_cape_verde; 1946 1947 switch (rdev->pdev->device) { 1948 case 0x683B: 1949 case 0x683F: 1950 case 0x6829: 1951 case 0x6835: 1952 si_pi->cac_weights = cac_weights_cape_verde_pro; 1953 si_pi->dte_data = dte_data_cape_verde; 1954 break; 1955 case 0x682C: 1956 si_pi->cac_weights = cac_weights_cape_verde_pro; 1957 si_pi->dte_data = dte_data_sun_xt; 1958 break; 1959 case 0x6825: 1960 case 0x6827: 1961 si_pi->cac_weights = cac_weights_heathrow; 1962 si_pi->dte_data = dte_data_cape_verde; 1963 break; 1964 case 0x6824: 1965 case 0x682D: 1966 si_pi->cac_weights = cac_weights_chelsea_xt; 1967 si_pi->dte_data = dte_data_cape_verde; 1968 break; 1969 case 0x682F: 1970 si_pi->cac_weights = cac_weights_chelsea_pro; 1971 si_pi->dte_data = dte_data_cape_verde; 1972 break; 1973 case 0x6820: 1974 si_pi->cac_weights = cac_weights_heathrow; 1975 si_pi->dte_data = dte_data_venus_xtx; 1976 break; 1977 case 0x6821: 1978 si_pi->cac_weights = cac_weights_heathrow; 1979 si_pi->dte_data = dte_data_venus_xt; 1980 break; 1981 case 0x6823: 1982 case 0x682B: 1983 case 0x6822: 1984 case 0x682A: 1985 si_pi->cac_weights = cac_weights_chelsea_pro; 1986 si_pi->dte_data = dte_data_venus_pro; 1987 break; 1988 default: 1989 si_pi->cac_weights = cac_weights_cape_verde; 1990 si_pi->dte_data = dte_data_cape_verde; 1991 break; 1992 } 1993 } else if (rdev->family == CHIP_OLAND) { 1994 switch (rdev->pdev->device) { 1995 case 0x6601: 1996 case 0x6621: 1997 case 0x6603: 1998 case 0x6605: 1999 si_pi->cac_weights = cac_weights_mars_pro; 2000 si_pi->lcac_config = lcac_mars_pro; 2001 si_pi->cac_override = cac_override_oland; 2002 si_pi->powertune_data = &powertune_data_mars_pro; 2003 si_pi->dte_data = dte_data_mars_pro; 2004 update_dte_from_pl2 = true; 2005 break; 2006 case 0x6600: 2007 case 0x6606: 2008 case 0x6620: 2009 case 0x6604: 2010 si_pi->cac_weights = cac_weights_mars_xt; 2011 si_pi->lcac_config = lcac_mars_pro; 2012 si_pi->cac_override = cac_override_oland; 2013 si_pi->powertune_data = &powertune_data_mars_pro; 2014 si_pi->dte_data = dte_data_mars_pro; 2015 update_dte_from_pl2 = true; 2016 break; 2017 case 0x6611: 2018 case 0x6613: 2019 case 0x6608: 2020 si_pi->cac_weights = cac_weights_oland_pro; 2021 si_pi->lcac_config = lcac_mars_pro; 2022 si_pi->cac_override = cac_override_oland; 2023 si_pi->powertune_data = &powertune_data_mars_pro; 2024 si_pi->dte_data = dte_data_mars_pro; 2025 update_dte_from_pl2 = true; 2026 break; 2027 case 0x6610: 2028 si_pi->cac_weights = cac_weights_oland_xt; 2029 si_pi->lcac_config = lcac_mars_pro; 2030 si_pi->cac_override = cac_override_oland; 2031 si_pi->powertune_data = &powertune_data_mars_pro; 2032 si_pi->dte_data = dte_data_mars_pro; 2033 update_dte_from_pl2 = true; 2034 break; 2035 default: 2036 si_pi->cac_weights = cac_weights_oland; 2037 si_pi->lcac_config = lcac_oland; 2038 si_pi->cac_override = cac_override_oland; 2039 si_pi->powertune_data = &powertune_data_oland; 2040 si_pi->dte_data = dte_data_oland; 2041 break; 2042 } 2043 } else if (rdev->family == CHIP_HAINAN) { 2044 si_pi->cac_weights = cac_weights_hainan; 2045 si_pi->lcac_config = lcac_oland; 2046 si_pi->cac_override = cac_override_oland; 2047 si_pi->powertune_data = &powertune_data_hainan; 2048 si_pi->dte_data = dte_data_sun_xt; 2049 update_dte_from_pl2 = true; 2050 } else { 2051 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2052 return; 2053 } 2054 2055 ni_pi->enable_power_containment = false; 2056 ni_pi->enable_cac = false; 2057 ni_pi->enable_sq_ramping = false; 2058 si_pi->enable_dte = false; 2059 2060 if (si_pi->powertune_data->enable_powertune_by_default) { 2061 ni_pi->enable_power_containment= true; 2062 ni_pi->enable_cac = true; 2063 if (si_pi->dte_data.enable_dte_by_default) { 2064 si_pi->enable_dte = true; 2065 if (update_dte_from_pl2) 2066 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2067 2068 } 2069 ni_pi->enable_sq_ramping = true; 2070 } 2071 2072 ni_pi->driver_calculate_cac_leakage = true; 2073 ni_pi->cac_configuration_required = true; 2074 2075 if (ni_pi->cac_configuration_required) { 2076 ni_pi->support_cac_long_term_average = true; 2077 si_pi->dyn_powertune_data.l2_lta_window_size = 2078 si_pi->powertune_data->l2_lta_window_size_default; 2079 si_pi->dyn_powertune_data.lts_truncate = 2080 si_pi->powertune_data->lts_truncate_default; 2081 } else { 2082 ni_pi->support_cac_long_term_average = false; 2083 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2084 si_pi->dyn_powertune_data.lts_truncate = 0; 2085 } 2086 2087 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2088 } 2089 2090 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2091 { 2092 return 1; 2093 } 2094 2095 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2096 { 2097 u32 xclk; 2098 u32 wintime; 2099 u32 cac_window; 2100 u32 cac_window_size; 2101 2102 xclk = radeon_get_xclk(rdev); 2103 2104 if (xclk == 0) 2105 return 0; 2106 2107 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2108 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2109 2110 wintime = (cac_window_size * 100) / xclk; 2111 2112 return wintime; 2113 } 2114 2115 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2116 { 2117 return power_in_watts; 2118 } 2119 2120 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2121 bool adjust_polarity, 2122 u32 tdp_adjustment, 2123 u32 *tdp_limit, 2124 u32 *near_tdp_limit) 2125 { 2126 u32 adjustment_delta, max_tdp_limit; 2127 2128 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2129 return -EINVAL; 2130 2131 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2132 2133 if (adjust_polarity) { 2134 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2135 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2136 } else { 2137 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2138 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2139 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2140 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2141 else 2142 *near_tdp_limit = 0; 2143 } 2144 2145 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2146 return -EINVAL; 2147 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2148 return -EINVAL; 2149 2150 return 0; 2151 } 2152 2153 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2154 struct radeon_ps *radeon_state) 2155 { 2156 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2157 struct si_power_info *si_pi = si_get_pi(rdev); 2158 2159 if (ni_pi->enable_power_containment) { 2160 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2161 PP_SIslands_PAPMParameters *papm_parm; 2162 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2163 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2164 u32 tdp_limit; 2165 u32 near_tdp_limit; 2166 int ret; 2167 2168 if (scaling_factor == 0) 2169 return -EINVAL; 2170 2171 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2172 2173 ret = si_calculate_adjusted_tdp_limits(rdev, 2174 false, /* ??? */ 2175 rdev->pm.dpm.tdp_adjustment, 2176 &tdp_limit, 2177 &near_tdp_limit); 2178 if (ret) 2179 return ret; 2180 2181 smc_table->dpm2Params.TDPLimit = 2182 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2183 smc_table->dpm2Params.NearTDPLimit = 2184 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2185 smc_table->dpm2Params.SafePowerLimit = 2186 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2187 2188 ret = si_copy_bytes_to_smc(rdev, 2189 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2190 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2191 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2192 sizeof(u32) * 3, 2193 si_pi->sram_end); 2194 if (ret) 2195 return ret; 2196 2197 if (si_pi->enable_ppm) { 2198 papm_parm = &si_pi->papm_parm; 2199 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2200 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2201 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2202 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2203 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2204 papm_parm->PlatformPowerLimit = 0xffffffff; 2205 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2206 2207 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2208 (u8 *)papm_parm, 2209 sizeof(PP_SIslands_PAPMParameters), 2210 si_pi->sram_end); 2211 if (ret) 2212 return ret; 2213 } 2214 } 2215 return 0; 2216 } 2217 2218 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2219 struct radeon_ps *radeon_state) 2220 { 2221 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2222 struct si_power_info *si_pi = si_get_pi(rdev); 2223 2224 if (ni_pi->enable_power_containment) { 2225 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2226 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2227 int ret; 2228 2229 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2230 2231 smc_table->dpm2Params.NearTDPLimit = 2232 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2233 smc_table->dpm2Params.SafePowerLimit = 2234 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2235 2236 ret = si_copy_bytes_to_smc(rdev, 2237 (si_pi->state_table_start + 2238 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2239 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2240 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2241 sizeof(u32) * 2, 2242 si_pi->sram_end); 2243 if (ret) 2244 return ret; 2245 } 2246 2247 return 0; 2248 } 2249 2250 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2251 const u16 prev_std_vddc, 2252 const u16 curr_std_vddc) 2253 { 2254 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2255 u64 prev_vddc = (u64)prev_std_vddc; 2256 u64 curr_vddc = (u64)curr_std_vddc; 2257 u64 pwr_efficiency_ratio, n, d; 2258 2259 if ((prev_vddc == 0) || (curr_vddc == 0)) 2260 return 0; 2261 2262 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2263 d = prev_vddc * prev_vddc; 2264 pwr_efficiency_ratio = div64_u64(n, d); 2265 2266 if (pwr_efficiency_ratio > (u64)0xFFFF) 2267 return 0; 2268 2269 return (u16)pwr_efficiency_ratio; 2270 } 2271 2272 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2273 struct radeon_ps *radeon_state) 2274 { 2275 struct si_power_info *si_pi = si_get_pi(rdev); 2276 2277 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2278 radeon_state->vclk && radeon_state->dclk) 2279 return true; 2280 2281 return false; 2282 } 2283 2284 static int si_populate_power_containment_values(struct radeon_device *rdev, 2285 struct radeon_ps *radeon_state, 2286 SISLANDS_SMC_SWSTATE *smc_state) 2287 { 2288 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2289 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2290 struct ni_ps *state = ni_get_ps(radeon_state); 2291 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2292 u32 prev_sclk; 2293 u32 max_sclk; 2294 u32 min_sclk; 2295 u16 prev_std_vddc; 2296 u16 curr_std_vddc; 2297 int i; 2298 u16 pwr_efficiency_ratio; 2299 u8 max_ps_percent; 2300 bool disable_uvd_power_tune; 2301 int ret; 2302 2303 if (ni_pi->enable_power_containment == false) 2304 return 0; 2305 2306 if (state->performance_level_count == 0) 2307 return -EINVAL; 2308 2309 if (smc_state->levelCount != state->performance_level_count) 2310 return -EINVAL; 2311 2312 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2313 2314 smc_state->levels[0].dpm2.MaxPS = 0; 2315 smc_state->levels[0].dpm2.NearTDPDec = 0; 2316 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2317 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2318 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2319 2320 for (i = 1; i < state->performance_level_count; i++) { 2321 prev_sclk = state->performance_levels[i-1].sclk; 2322 max_sclk = state->performance_levels[i].sclk; 2323 if (i == 1) 2324 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2325 else 2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2327 2328 if (prev_sclk > max_sclk) 2329 return -EINVAL; 2330 2331 if ((max_ps_percent == 0) || 2332 (prev_sclk == max_sclk) || 2333 disable_uvd_power_tune) { 2334 min_sclk = max_sclk; 2335 } else if (i == 1) { 2336 min_sclk = prev_sclk; 2337 } else { 2338 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2339 } 2340 2341 if (min_sclk < state->performance_levels[0].sclk) 2342 min_sclk = state->performance_levels[0].sclk; 2343 2344 if (min_sclk == 0) 2345 return -EINVAL; 2346 2347 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2348 state->performance_levels[i-1].vddc, &vddc); 2349 if (ret) 2350 return ret; 2351 2352 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2353 if (ret) 2354 return ret; 2355 2356 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2357 state->performance_levels[i].vddc, &vddc); 2358 if (ret) 2359 return ret; 2360 2361 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2362 if (ret) 2363 return ret; 2364 2365 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2366 prev_std_vddc, curr_std_vddc); 2367 2368 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2369 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2370 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2371 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2372 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2373 } 2374 2375 return 0; 2376 } 2377 2378 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2379 struct radeon_ps *radeon_state, 2380 SISLANDS_SMC_SWSTATE *smc_state) 2381 { 2382 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2383 struct ni_ps *state = ni_get_ps(radeon_state); 2384 u32 sq_power_throttle, sq_power_throttle2; 2385 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2386 int i; 2387 2388 if (state->performance_level_count == 0) 2389 return -EINVAL; 2390 2391 if (smc_state->levelCount != state->performance_level_count) 2392 return -EINVAL; 2393 2394 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2395 return -EINVAL; 2396 2397 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2398 enable_sq_ramping = false; 2399 2400 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2401 enable_sq_ramping = false; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2410 enable_sq_ramping = false; 2411 2412 for (i = 0; i < state->performance_level_count; i++) { 2413 sq_power_throttle = 0; 2414 sq_power_throttle2 = 0; 2415 2416 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2417 enable_sq_ramping) { 2418 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2419 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2420 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2421 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2422 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2423 } else { 2424 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2425 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2426 } 2427 2428 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2429 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2430 } 2431 2432 return 0; 2433 } 2434 2435 static int si_enable_power_containment(struct radeon_device *rdev, 2436 struct radeon_ps *radeon_new_state, 2437 bool enable) 2438 { 2439 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2440 PPSMC_Result smc_result; 2441 int ret = 0; 2442 2443 if (ni_pi->enable_power_containment) { 2444 if (enable) { 2445 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2446 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2447 if (smc_result != PPSMC_Result_OK) { 2448 ret = -EINVAL; 2449 ni_pi->pc_enabled = false; 2450 } else { 2451 ni_pi->pc_enabled = true; 2452 } 2453 } 2454 } else { 2455 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2456 if (smc_result != PPSMC_Result_OK) 2457 ret = -EINVAL; 2458 ni_pi->pc_enabled = false; 2459 } 2460 } 2461 2462 return ret; 2463 } 2464 2465 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2466 { 2467 struct si_power_info *si_pi = si_get_pi(rdev); 2468 int ret = 0; 2469 struct si_dte_data *dte_data = &si_pi->dte_data; 2470 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2471 u32 table_size; 2472 u8 tdep_count; 2473 u32 i; 2474 2475 if (dte_data == NULL) 2476 si_pi->enable_dte = false; 2477 2478 if (si_pi->enable_dte == false) 2479 return 0; 2480 2481 if (dte_data->k <= 0) 2482 return -EINVAL; 2483 2484 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2485 if (dte_tables == NULL) { 2486 si_pi->enable_dte = false; 2487 return -ENOMEM; 2488 } 2489 2490 table_size = dte_data->k; 2491 2492 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2493 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2494 2495 tdep_count = dte_data->tdep_count; 2496 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2497 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2498 2499 dte_tables->K = cpu_to_be32(table_size); 2500 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2501 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2502 dte_tables->WindowSize = dte_data->window_size; 2503 dte_tables->temp_select = dte_data->temp_select; 2504 dte_tables->DTE_mode = dte_data->dte_mode; 2505 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2506 2507 if (tdep_count > 0) 2508 table_size--; 2509 2510 for (i = 0; i < table_size; i++) { 2511 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2512 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2513 } 2514 2515 dte_tables->Tdep_count = tdep_count; 2516 2517 for (i = 0; i < (u32)tdep_count; i++) { 2518 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2519 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2520 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2521 } 2522 2523 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2524 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2525 kfree(dte_tables); 2526 2527 return ret; 2528 } 2529 2530 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2531 u16 *max, u16 *min) 2532 { 2533 struct si_power_info *si_pi = si_get_pi(rdev); 2534 struct radeon_cac_leakage_table *table = 2535 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2536 u32 i; 2537 u32 v0_loadline; 2538 2539 2540 if (table == NULL) 2541 return -EINVAL; 2542 2543 *max = 0; 2544 *min = 0xFFFF; 2545 2546 for (i = 0; i < table->count; i++) { 2547 if (table->entries[i].vddc > *max) 2548 *max = table->entries[i].vddc; 2549 if (table->entries[i].vddc < *min) 2550 *min = table->entries[i].vddc; 2551 } 2552 2553 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2554 return -EINVAL; 2555 2556 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2557 2558 if (v0_loadline > 0xFFFFUL) 2559 return -EINVAL; 2560 2561 *min = (u16)v0_loadline; 2562 2563 if ((*min > *max) || (*max == 0) || (*min == 0)) 2564 return -EINVAL; 2565 2566 return 0; 2567 } 2568 2569 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2570 { 2571 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2572 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2573 } 2574 2575 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2576 PP_SIslands_CacConfig *cac_tables, 2577 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2578 u16 t0, u16 t_step) 2579 { 2580 struct si_power_info *si_pi = si_get_pi(rdev); 2581 u32 leakage; 2582 unsigned int i, j; 2583 s32 t; 2584 u32 smc_leakage; 2585 u32 scaling_factor; 2586 u16 voltage; 2587 2588 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2589 2590 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2591 t = (1000 * (i * t_step + t0)); 2592 2593 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2594 voltage = vddc_max - (vddc_step * j); 2595 2596 si_calculate_leakage_for_v_and_t(rdev, 2597 &si_pi->powertune_data->leakage_coefficients, 2598 voltage, 2599 t, 2600 si_pi->dyn_powertune_data.cac_leakage, 2601 &leakage); 2602 2603 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2604 2605 if (smc_leakage > 0xFFFF) 2606 smc_leakage = 0xFFFF; 2607 2608 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2609 cpu_to_be16((u16)smc_leakage); 2610 } 2611 } 2612 return 0; 2613 } 2614 2615 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2616 PP_SIslands_CacConfig *cac_tables, 2617 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2618 { 2619 struct si_power_info *si_pi = si_get_pi(rdev); 2620 u32 leakage; 2621 unsigned int i, j; 2622 u32 smc_leakage; 2623 u32 scaling_factor; 2624 u16 voltage; 2625 2626 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2627 2628 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2629 voltage = vddc_max - (vddc_step * j); 2630 2631 si_calculate_leakage_for_v(rdev, 2632 &si_pi->powertune_data->leakage_coefficients, 2633 si_pi->powertune_data->fixed_kt, 2634 voltage, 2635 si_pi->dyn_powertune_data.cac_leakage, 2636 &leakage); 2637 2638 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2639 2640 if (smc_leakage > 0xFFFF) 2641 smc_leakage = 0xFFFF; 2642 2643 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2644 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2645 cpu_to_be16((u16)smc_leakage); 2646 } 2647 return 0; 2648 } 2649 2650 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2651 { 2652 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2653 struct si_power_info *si_pi = si_get_pi(rdev); 2654 PP_SIslands_CacConfig *cac_tables = NULL; 2655 u16 vddc_max, vddc_min, vddc_step; 2656 u16 t0, t_step; 2657 u32 load_line_slope, reg; 2658 int ret = 0; 2659 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2660 2661 if (ni_pi->enable_cac == false) 2662 return 0; 2663 2664 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2665 if (!cac_tables) 2666 return -ENOMEM; 2667 2668 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2669 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2670 WREG32(CG_CAC_CTRL, reg); 2671 2672 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2673 si_pi->dyn_powertune_data.dc_pwr_value = 2674 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2675 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2676 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2677 2678 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2679 2680 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2681 if (ret) 2682 goto done_free; 2683 2684 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2685 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2686 t_step = 4; 2687 t0 = 60; 2688 2689 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2690 ret = si_init_dte_leakage_table(rdev, cac_tables, 2691 vddc_max, vddc_min, vddc_step, 2692 t0, t_step); 2693 else 2694 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2695 vddc_max, vddc_min, vddc_step); 2696 if (ret) 2697 goto done_free; 2698 2699 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2700 2701 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2702 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2703 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2704 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2705 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2706 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2707 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2708 cac_tables->calculation_repeats = cpu_to_be32(2); 2709 cac_tables->dc_cac = cpu_to_be32(0); 2710 cac_tables->log2_PG_LKG_SCALE = 12; 2711 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2712 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2713 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2714 2715 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2716 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2717 2718 if (ret) 2719 goto done_free; 2720 2721 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2722 2723 done_free: 2724 if (ret) { 2725 ni_pi->enable_cac = false; 2726 ni_pi->enable_power_containment = false; 2727 } 2728 2729 kfree(cac_tables); 2730 2731 return 0; 2732 } 2733 2734 static int si_program_cac_config_registers(struct radeon_device *rdev, 2735 const struct si_cac_config_reg *cac_config_regs) 2736 { 2737 const struct si_cac_config_reg *config_regs = cac_config_regs; 2738 u32 data = 0, offset; 2739 2740 if (!config_regs) 2741 return -EINVAL; 2742 2743 while (config_regs->offset != 0xFFFFFFFF) { 2744 switch (config_regs->type) { 2745 case SISLANDS_CACCONFIG_CGIND: 2746 offset = SMC_CG_IND_START + config_regs->offset; 2747 if (offset < SMC_CG_IND_END) 2748 data = RREG32_SMC(offset); 2749 break; 2750 default: 2751 data = RREG32(config_regs->offset << 2); 2752 break; 2753 } 2754 2755 data &= ~config_regs->mask; 2756 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2757 2758 switch (config_regs->type) { 2759 case SISLANDS_CACCONFIG_CGIND: 2760 offset = SMC_CG_IND_START + config_regs->offset; 2761 if (offset < SMC_CG_IND_END) 2762 WREG32_SMC(offset, data); 2763 break; 2764 default: 2765 WREG32(config_regs->offset << 2, data); 2766 break; 2767 } 2768 config_regs++; 2769 } 2770 return 0; 2771 } 2772 2773 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2774 { 2775 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2776 struct si_power_info *si_pi = si_get_pi(rdev); 2777 int ret; 2778 2779 if ((ni_pi->enable_cac == false) || 2780 (ni_pi->cac_configuration_required == false)) 2781 return 0; 2782 2783 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2784 if (ret) 2785 return ret; 2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2787 if (ret) 2788 return ret; 2789 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2790 if (ret) 2791 return ret; 2792 2793 return 0; 2794 } 2795 2796 static int si_enable_smc_cac(struct radeon_device *rdev, 2797 struct radeon_ps *radeon_new_state, 2798 bool enable) 2799 { 2800 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2801 struct si_power_info *si_pi = si_get_pi(rdev); 2802 PPSMC_Result smc_result; 2803 int ret = 0; 2804 2805 if (ni_pi->enable_cac) { 2806 if (enable) { 2807 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2808 if (ni_pi->support_cac_long_term_average) { 2809 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2810 if (smc_result != PPSMC_Result_OK) 2811 ni_pi->support_cac_long_term_average = false; 2812 } 2813 2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2815 if (smc_result != PPSMC_Result_OK) { 2816 ret = -EINVAL; 2817 ni_pi->cac_enabled = false; 2818 } else { 2819 ni_pi->cac_enabled = true; 2820 } 2821 2822 if (si_pi->enable_dte) { 2823 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2824 if (smc_result != PPSMC_Result_OK) 2825 ret = -EINVAL; 2826 } 2827 } 2828 } else if (ni_pi->cac_enabled) { 2829 if (si_pi->enable_dte) 2830 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2831 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2833 2834 ni_pi->cac_enabled = false; 2835 2836 if (ni_pi->support_cac_long_term_average) 2837 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2838 } 2839 } 2840 return ret; 2841 } 2842 2843 static int si_init_smc_spll_table(struct radeon_device *rdev) 2844 { 2845 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2846 struct si_power_info *si_pi = si_get_pi(rdev); 2847 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2848 SISLANDS_SMC_SCLK_VALUE sclk_params; 2849 u32 fb_div, p_div; 2850 u32 clk_s, clk_v; 2851 u32 sclk = 0; 2852 int ret = 0; 2853 u32 tmp; 2854 int i; 2855 2856 if (si_pi->spll_table_start == 0) 2857 return -EINVAL; 2858 2859 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2860 if (spll_table == NULL) 2861 return -ENOMEM; 2862 2863 for (i = 0; i < 256; i++) { 2864 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2865 if (ret) 2866 break; 2867 2868 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2869 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2870 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2871 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2872 2873 fb_div &= ~0x00001FFF; 2874 fb_div >>= 1; 2875 clk_v >>= 6; 2876 2877 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2878 ret = -EINVAL; 2879 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2880 ret = -EINVAL; 2881 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2882 ret = -EINVAL; 2883 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2884 ret = -EINVAL; 2885 2886 if (ret) 2887 break; 2888 2889 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2890 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2891 spll_table->freq[i] = cpu_to_be32(tmp); 2892 2893 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2894 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2895 spll_table->ss[i] = cpu_to_be32(tmp); 2896 2897 sclk += 512; 2898 } 2899 2900 2901 if (!ret) 2902 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2903 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2904 si_pi->sram_end); 2905 2906 if (ret) 2907 ni_pi->enable_power_containment = false; 2908 2909 kfree(spll_table); 2910 2911 return ret; 2912 } 2913 2914 struct si_dpm_quirk { 2915 u32 chip_vendor; 2916 u32 chip_device; 2917 u32 subsys_vendor; 2918 u32 subsys_device; 2919 u32 max_sclk; 2920 u32 max_mclk; 2921 }; 2922 2923 /* cards with dpm stability problems */ 2924 static struct si_dpm_quirk si_dpm_quirk_list[] = { 2925 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 2926 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2927 { 0, 0, 0, 0 }, 2928 }; 2929 2930 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2931 struct radeon_ps *rps) 2932 { 2933 struct ni_ps *ps = ni_get_ps(rps); 2934 struct radeon_clock_and_voltage_limits *max_limits; 2935 bool disable_mclk_switching = false; 2936 bool disable_sclk_switching = false; 2937 u32 mclk, sclk; 2938 u16 vddc, vddci; 2939 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2940 u32 max_sclk = 0, max_mclk = 0; 2941 int i; 2942 struct si_dpm_quirk *p = si_dpm_quirk_list; 2943 2944 /* Apply dpm quirks */ 2945 while (p && p->chip_device != 0) { 2946 if (rdev->pdev->vendor == p->chip_vendor && 2947 rdev->pdev->device == p->chip_device && 2948 rdev->pdev->subsystem_vendor == p->subsys_vendor && 2949 rdev->pdev->subsystem_device == p->subsys_device) { 2950 max_sclk = p->max_sclk; 2951 max_mclk = p->max_mclk; 2952 break; 2953 } 2954 ++p; 2955 } 2956 2957 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2958 ni_dpm_vblank_too_short(rdev)) 2959 disable_mclk_switching = true; 2960 2961 if (rps->vclk || rps->dclk) { 2962 disable_mclk_switching = true; 2963 disable_sclk_switching = true; 2964 } 2965 2966 if (rdev->pm.dpm.ac_power) 2967 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2968 else 2969 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2970 2971 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2972 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2973 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2974 } 2975 if (rdev->pm.dpm.ac_power == false) { 2976 for (i = 0; i < ps->performance_level_count; i++) { 2977 if (ps->performance_levels[i].mclk > max_limits->mclk) 2978 ps->performance_levels[i].mclk = max_limits->mclk; 2979 if (ps->performance_levels[i].sclk > max_limits->sclk) 2980 ps->performance_levels[i].sclk = max_limits->sclk; 2981 if (ps->performance_levels[i].vddc > max_limits->vddc) 2982 ps->performance_levels[i].vddc = max_limits->vddc; 2983 if (ps->performance_levels[i].vddci > max_limits->vddci) 2984 ps->performance_levels[i].vddci = max_limits->vddci; 2985 } 2986 } 2987 2988 /* limit clocks to max supported clocks based on voltage dependency tables */ 2989 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2990 &max_sclk_vddc); 2991 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2992 &max_mclk_vddci); 2993 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2994 &max_mclk_vddc); 2995 2996 for (i = 0; i < ps->performance_level_count; i++) { 2997 if (max_sclk_vddc) { 2998 if (ps->performance_levels[i].sclk > max_sclk_vddc) 2999 ps->performance_levels[i].sclk = max_sclk_vddc; 3000 } 3001 if (max_mclk_vddci) { 3002 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3003 ps->performance_levels[i].mclk = max_mclk_vddci; 3004 } 3005 if (max_mclk_vddc) { 3006 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3007 ps->performance_levels[i].mclk = max_mclk_vddc; 3008 } 3009 if (max_mclk) { 3010 if (ps->performance_levels[i].mclk > max_mclk) 3011 ps->performance_levels[i].mclk = max_mclk; 3012 } 3013 if (max_sclk) { 3014 if (ps->performance_levels[i].sclk > max_sclk) 3015 ps->performance_levels[i].sclk = max_sclk; 3016 } 3017 } 3018 3019 /* XXX validate the min clocks required for display */ 3020 3021 if (disable_mclk_switching) { 3022 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3023 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3024 } else { 3025 mclk = ps->performance_levels[0].mclk; 3026 vddci = ps->performance_levels[0].vddci; 3027 } 3028 3029 if (disable_sclk_switching) { 3030 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3031 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3032 } else { 3033 sclk = ps->performance_levels[0].sclk; 3034 vddc = ps->performance_levels[0].vddc; 3035 } 3036 3037 /* adjusted low state */ 3038 ps->performance_levels[0].sclk = sclk; 3039 ps->performance_levels[0].mclk = mclk; 3040 ps->performance_levels[0].vddc = vddc; 3041 ps->performance_levels[0].vddci = vddci; 3042 3043 if (disable_sclk_switching) { 3044 sclk = ps->performance_levels[0].sclk; 3045 for (i = 1; i < ps->performance_level_count; i++) { 3046 if (sclk < ps->performance_levels[i].sclk) 3047 sclk = ps->performance_levels[i].sclk; 3048 } 3049 for (i = 0; i < ps->performance_level_count; i++) { 3050 ps->performance_levels[i].sclk = sclk; 3051 ps->performance_levels[i].vddc = vddc; 3052 } 3053 } else { 3054 for (i = 1; i < ps->performance_level_count; i++) { 3055 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3056 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3057 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3058 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3059 } 3060 } 3061 3062 if (disable_mclk_switching) { 3063 mclk = ps->performance_levels[0].mclk; 3064 for (i = 1; i < ps->performance_level_count; i++) { 3065 if (mclk < ps->performance_levels[i].mclk) 3066 mclk = ps->performance_levels[i].mclk; 3067 } 3068 for (i = 0; i < ps->performance_level_count; i++) { 3069 ps->performance_levels[i].mclk = mclk; 3070 ps->performance_levels[i].vddci = vddci; 3071 } 3072 } else { 3073 for (i = 1; i < ps->performance_level_count; i++) { 3074 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3075 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3076 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3077 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3078 } 3079 } 3080 3081 for (i = 0; i < ps->performance_level_count; i++) 3082 btc_adjust_clock_combinations(rdev, max_limits, 3083 &ps->performance_levels[i]); 3084 3085 for (i = 0; i < ps->performance_level_count; i++) { 3086 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3087 ps->performance_levels[i].sclk, 3088 max_limits->vddc, &ps->performance_levels[i].vddc); 3089 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3090 ps->performance_levels[i].mclk, 3091 max_limits->vddci, &ps->performance_levels[i].vddci); 3092 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3093 ps->performance_levels[i].mclk, 3094 max_limits->vddc, &ps->performance_levels[i].vddc); 3095 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3096 rdev->clock.current_dispclk, 3097 max_limits->vddc, &ps->performance_levels[i].vddc); 3098 } 3099 3100 for (i = 0; i < ps->performance_level_count; i++) { 3101 btc_apply_voltage_delta_rules(rdev, 3102 max_limits->vddc, max_limits->vddci, 3103 &ps->performance_levels[i].vddc, 3104 &ps->performance_levels[i].vddci); 3105 } 3106 3107 ps->dc_compatible = true; 3108 for (i = 0; i < ps->performance_level_count; i++) { 3109 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3110 ps->dc_compatible = false; 3111 } 3112 3113 } 3114 3115 #if 0 3116 static int si_read_smc_soft_register(struct radeon_device *rdev, 3117 u16 reg_offset, u32 *value) 3118 { 3119 struct si_power_info *si_pi = si_get_pi(rdev); 3120 3121 return si_read_smc_sram_dword(rdev, 3122 si_pi->soft_regs_start + reg_offset, value, 3123 si_pi->sram_end); 3124 } 3125 #endif 3126 3127 static int si_write_smc_soft_register(struct radeon_device *rdev, 3128 u16 reg_offset, u32 value) 3129 { 3130 struct si_power_info *si_pi = si_get_pi(rdev); 3131 3132 return si_write_smc_sram_dword(rdev, 3133 si_pi->soft_regs_start + reg_offset, 3134 value, si_pi->sram_end); 3135 } 3136 3137 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3138 { 3139 bool ret = false; 3140 u32 tmp, width, row, column, bank, density; 3141 bool is_memory_gddr5, is_special; 3142 3143 tmp = RREG32(MC_SEQ_MISC0); 3144 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3145 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3146 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3147 3148 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3149 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3150 3151 tmp = RREG32(MC_ARB_RAMCFG); 3152 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3153 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3154 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3155 3156 density = (1 << (row + column - 20 + bank)) * width; 3157 3158 if ((rdev->pdev->device == 0x6819) && 3159 is_memory_gddr5 && is_special && (density == 0x400)) 3160 ret = true; 3161 3162 return ret; 3163 } 3164 3165 static void si_get_leakage_vddc(struct radeon_device *rdev) 3166 { 3167 struct si_power_info *si_pi = si_get_pi(rdev); 3168 u16 vddc, count = 0; 3169 int i, ret; 3170 3171 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3172 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3173 3174 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3175 si_pi->leakage_voltage.entries[count].voltage = vddc; 3176 si_pi->leakage_voltage.entries[count].leakage_index = 3177 SISLANDS_LEAKAGE_INDEX0 + i; 3178 count++; 3179 } 3180 } 3181 si_pi->leakage_voltage.count = count; 3182 } 3183 3184 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3185 u32 index, u16 *leakage_voltage) 3186 { 3187 struct si_power_info *si_pi = si_get_pi(rdev); 3188 int i; 3189 3190 if (leakage_voltage == NULL) 3191 return -EINVAL; 3192 3193 if ((index & 0xff00) != 0xff00) 3194 return -EINVAL; 3195 3196 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3197 return -EINVAL; 3198 3199 if (index < SISLANDS_LEAKAGE_INDEX0) 3200 return -EINVAL; 3201 3202 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3203 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3204 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3205 return 0; 3206 } 3207 } 3208 return -EAGAIN; 3209 } 3210 3211 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3212 { 3213 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3214 bool want_thermal_protection; 3215 enum radeon_dpm_event_src dpm_event_src; 3216 3217 switch (sources) { 3218 case 0: 3219 default: 3220 want_thermal_protection = false; 3221 break; 3222 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3223 want_thermal_protection = true; 3224 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3225 break; 3226 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3227 want_thermal_protection = true; 3228 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3229 break; 3230 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3231 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3232 want_thermal_protection = true; 3233 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3234 break; 3235 } 3236 3237 if (want_thermal_protection) { 3238 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3239 if (pi->thermal_protection) 3240 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3241 } else { 3242 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3243 } 3244 } 3245 3246 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3247 enum radeon_dpm_auto_throttle_src source, 3248 bool enable) 3249 { 3250 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3251 3252 if (enable) { 3253 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3254 pi->active_auto_throttle_sources |= 1 << source; 3255 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3256 } 3257 } else { 3258 if (pi->active_auto_throttle_sources & (1 << source)) { 3259 pi->active_auto_throttle_sources &= ~(1 << source); 3260 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3261 } 3262 } 3263 } 3264 3265 static void si_start_dpm(struct radeon_device *rdev) 3266 { 3267 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3268 } 3269 3270 static void si_stop_dpm(struct radeon_device *rdev) 3271 { 3272 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3273 } 3274 3275 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3276 { 3277 if (enable) 3278 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3279 else 3280 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3281 3282 } 3283 3284 #if 0 3285 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3286 u32 thermal_level) 3287 { 3288 PPSMC_Result ret; 3289 3290 if (thermal_level == 0) { 3291 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3292 if (ret == PPSMC_Result_OK) 3293 return 0; 3294 else 3295 return -EINVAL; 3296 } 3297 return 0; 3298 } 3299 3300 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3301 { 3302 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3303 } 3304 #endif 3305 3306 #if 0 3307 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3308 { 3309 if (ac_power) 3310 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3311 0 : -EINVAL; 3312 3313 return 0; 3314 } 3315 #endif 3316 3317 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3318 PPSMC_Msg msg, u32 parameter) 3319 { 3320 WREG32(SMC_SCRATCH0, parameter); 3321 return si_send_msg_to_smc(rdev, msg); 3322 } 3323 3324 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3325 { 3326 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3327 return -EINVAL; 3328 3329 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3330 0 : -EINVAL; 3331 } 3332 3333 int si_dpm_force_performance_level(struct radeon_device *rdev, 3334 enum radeon_dpm_forced_level level) 3335 { 3336 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3337 struct ni_ps *ps = ni_get_ps(rps); 3338 u32 levels = ps->performance_level_count; 3339 3340 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3341 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3342 return -EINVAL; 3343 3344 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3345 return -EINVAL; 3346 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3347 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3348 return -EINVAL; 3349 3350 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3351 return -EINVAL; 3352 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3353 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3354 return -EINVAL; 3355 3356 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3357 return -EINVAL; 3358 } 3359 3360 rdev->pm.dpm.forced_level = level; 3361 3362 return 0; 3363 } 3364 3365 #if 0 3366 static int si_set_boot_state(struct radeon_device *rdev) 3367 { 3368 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3369 0 : -EINVAL; 3370 } 3371 #endif 3372 3373 static int si_set_sw_state(struct radeon_device *rdev) 3374 { 3375 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3376 0 : -EINVAL; 3377 } 3378 3379 static int si_halt_smc(struct radeon_device *rdev) 3380 { 3381 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3382 return -EINVAL; 3383 3384 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3385 0 : -EINVAL; 3386 } 3387 3388 static int si_resume_smc(struct radeon_device *rdev) 3389 { 3390 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3391 return -EINVAL; 3392 3393 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3394 0 : -EINVAL; 3395 } 3396 3397 static void si_dpm_start_smc(struct radeon_device *rdev) 3398 { 3399 si_program_jump_on_start(rdev); 3400 si_start_smc(rdev); 3401 si_start_smc_clock(rdev); 3402 } 3403 3404 static void si_dpm_stop_smc(struct radeon_device *rdev) 3405 { 3406 si_reset_smc(rdev); 3407 si_stop_smc_clock(rdev); 3408 } 3409 3410 static int si_process_firmware_header(struct radeon_device *rdev) 3411 { 3412 struct si_power_info *si_pi = si_get_pi(rdev); 3413 u32 tmp; 3414 int ret; 3415 3416 ret = si_read_smc_sram_dword(rdev, 3417 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3418 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3419 &tmp, si_pi->sram_end); 3420 if (ret) 3421 return ret; 3422 3423 si_pi->state_table_start = tmp; 3424 3425 ret = si_read_smc_sram_dword(rdev, 3426 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3427 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3428 &tmp, si_pi->sram_end); 3429 if (ret) 3430 return ret; 3431 3432 si_pi->soft_regs_start = tmp; 3433 3434 ret = si_read_smc_sram_dword(rdev, 3435 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3436 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3437 &tmp, si_pi->sram_end); 3438 if (ret) 3439 return ret; 3440 3441 si_pi->mc_reg_table_start = tmp; 3442 3443 ret = si_read_smc_sram_dword(rdev, 3444 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3445 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3446 &tmp, si_pi->sram_end); 3447 if (ret) 3448 return ret; 3449 3450 si_pi->fan_table_start = tmp; 3451 3452 ret = si_read_smc_sram_dword(rdev, 3453 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3454 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3455 &tmp, si_pi->sram_end); 3456 if (ret) 3457 return ret; 3458 3459 si_pi->arb_table_start = tmp; 3460 3461 ret = si_read_smc_sram_dword(rdev, 3462 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3463 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3464 &tmp, si_pi->sram_end); 3465 if (ret) 3466 return ret; 3467 3468 si_pi->cac_table_start = tmp; 3469 3470 ret = si_read_smc_sram_dword(rdev, 3471 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3472 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3473 &tmp, si_pi->sram_end); 3474 if (ret) 3475 return ret; 3476 3477 si_pi->dte_table_start = tmp; 3478 3479 ret = si_read_smc_sram_dword(rdev, 3480 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3481 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3482 &tmp, si_pi->sram_end); 3483 if (ret) 3484 return ret; 3485 3486 si_pi->spll_table_start = tmp; 3487 3488 ret = si_read_smc_sram_dword(rdev, 3489 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3490 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3491 &tmp, si_pi->sram_end); 3492 if (ret) 3493 return ret; 3494 3495 si_pi->papm_cfg_table_start = tmp; 3496 3497 return ret; 3498 } 3499 3500 static void si_read_clock_registers(struct radeon_device *rdev) 3501 { 3502 struct si_power_info *si_pi = si_get_pi(rdev); 3503 3504 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3505 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3506 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3507 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3508 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3509 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3510 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3511 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3512 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3513 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3514 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3515 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3516 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3517 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3518 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3519 } 3520 3521 static void si_enable_thermal_protection(struct radeon_device *rdev, 3522 bool enable) 3523 { 3524 if (enable) 3525 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3526 else 3527 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3528 } 3529 3530 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3531 { 3532 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3533 } 3534 3535 #if 0 3536 static int si_enter_ulp_state(struct radeon_device *rdev) 3537 { 3538 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3539 3540 udelay(25000); 3541 3542 return 0; 3543 } 3544 3545 static int si_exit_ulp_state(struct radeon_device *rdev) 3546 { 3547 int i; 3548 3549 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3550 3551 udelay(7000); 3552 3553 for (i = 0; i < rdev->usec_timeout; i++) { 3554 if (RREG32(SMC_RESP_0) == 1) 3555 break; 3556 udelay(1000); 3557 } 3558 3559 return 0; 3560 } 3561 #endif 3562 3563 static int si_notify_smc_display_change(struct radeon_device *rdev, 3564 bool has_display) 3565 { 3566 PPSMC_Msg msg = has_display ? 3567 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3568 3569 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3570 0 : -EINVAL; 3571 } 3572 3573 static void si_program_response_times(struct radeon_device *rdev) 3574 { 3575 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3576 u32 vddc_dly, acpi_dly, vbi_dly; 3577 u32 reference_clock; 3578 3579 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3580 3581 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3582 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3583 3584 if (voltage_response_time == 0) 3585 voltage_response_time = 1000; 3586 3587 acpi_delay_time = 15000; 3588 vbi_time_out = 100000; 3589 3590 reference_clock = radeon_get_xclk(rdev); 3591 3592 vddc_dly = (voltage_response_time * reference_clock) / 100; 3593 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3594 vbi_dly = (vbi_time_out * reference_clock) / 100; 3595 3596 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3597 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3598 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3599 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3600 } 3601 3602 static void si_program_ds_registers(struct radeon_device *rdev) 3603 { 3604 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3605 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3606 3607 if (eg_pi->sclk_deep_sleep) { 3608 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3609 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3610 ~AUTOSCALE_ON_SS_CLEAR); 3611 } 3612 } 3613 3614 static void si_program_display_gap(struct radeon_device *rdev) 3615 { 3616 u32 tmp, pipe; 3617 int i; 3618 3619 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3620 if (rdev->pm.dpm.new_active_crtc_count > 0) 3621 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3622 else 3623 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3624 3625 if (rdev->pm.dpm.new_active_crtc_count > 1) 3626 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3627 else 3628 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3629 3630 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3631 3632 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3633 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3634 3635 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3636 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3637 /* find the first active crtc */ 3638 for (i = 0; i < rdev->num_crtc; i++) { 3639 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3640 break; 3641 } 3642 if (i == rdev->num_crtc) 3643 pipe = 0; 3644 else 3645 pipe = i; 3646 3647 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3648 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3649 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3650 } 3651 3652 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3653 * This can be a problem on PowerXpress systems or if you want to use the card 3654 * for offscreen rendering or compute if there are no crtcs enabled. 3655 */ 3656 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3657 } 3658 3659 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3660 { 3661 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3662 3663 if (enable) { 3664 if (pi->sclk_ss) 3665 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3666 } else { 3667 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3668 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3669 } 3670 } 3671 3672 static void si_setup_bsp(struct radeon_device *rdev) 3673 { 3674 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3675 u32 xclk = radeon_get_xclk(rdev); 3676 3677 r600_calculate_u_and_p(pi->asi, 3678 xclk, 3679 16, 3680 &pi->bsp, 3681 &pi->bsu); 3682 3683 r600_calculate_u_and_p(pi->pasi, 3684 xclk, 3685 16, 3686 &pi->pbsp, 3687 &pi->pbsu); 3688 3689 3690 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3691 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3692 3693 WREG32(CG_BSP, pi->dsp); 3694 } 3695 3696 static void si_program_git(struct radeon_device *rdev) 3697 { 3698 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3699 } 3700 3701 static void si_program_tp(struct radeon_device *rdev) 3702 { 3703 int i; 3704 enum r600_td td = R600_TD_DFLT; 3705 3706 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3707 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3708 3709 if (td == R600_TD_AUTO) 3710 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3711 else 3712 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3713 3714 if (td == R600_TD_UP) 3715 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3716 3717 if (td == R600_TD_DOWN) 3718 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3719 } 3720 3721 static void si_program_tpp(struct radeon_device *rdev) 3722 { 3723 WREG32(CG_TPC, R600_TPC_DFLT); 3724 } 3725 3726 static void si_program_sstp(struct radeon_device *rdev) 3727 { 3728 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3729 } 3730 3731 static void si_enable_display_gap(struct radeon_device *rdev) 3732 { 3733 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3734 3735 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3736 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3737 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3738 3739 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3740 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3741 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3742 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3743 } 3744 3745 static void si_program_vc(struct radeon_device *rdev) 3746 { 3747 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3748 3749 WREG32(CG_FTV, pi->vrc); 3750 } 3751 3752 static void si_clear_vc(struct radeon_device *rdev) 3753 { 3754 WREG32(CG_FTV, 0); 3755 } 3756 3757 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3758 { 3759 u8 mc_para_index; 3760 3761 if (memory_clock < 10000) 3762 mc_para_index = 0; 3763 else if (memory_clock >= 80000) 3764 mc_para_index = 0x0f; 3765 else 3766 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3767 return mc_para_index; 3768 } 3769 3770 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3771 { 3772 u8 mc_para_index; 3773 3774 if (strobe_mode) { 3775 if (memory_clock < 12500) 3776 mc_para_index = 0x00; 3777 else if (memory_clock > 47500) 3778 mc_para_index = 0x0f; 3779 else 3780 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3781 } else { 3782 if (memory_clock < 65000) 3783 mc_para_index = 0x00; 3784 else if (memory_clock > 135000) 3785 mc_para_index = 0x0f; 3786 else 3787 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3788 } 3789 return mc_para_index; 3790 } 3791 3792 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3793 { 3794 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3795 bool strobe_mode = false; 3796 u8 result = 0; 3797 3798 if (mclk <= pi->mclk_strobe_mode_threshold) 3799 strobe_mode = true; 3800 3801 if (pi->mem_gddr5) 3802 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3803 else 3804 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3805 3806 if (strobe_mode) 3807 result |= SISLANDS_SMC_STROBE_ENABLE; 3808 3809 return result; 3810 } 3811 3812 static int si_upload_firmware(struct radeon_device *rdev) 3813 { 3814 struct si_power_info *si_pi = si_get_pi(rdev); 3815 int ret; 3816 3817 si_reset_smc(rdev); 3818 si_stop_smc_clock(rdev); 3819 3820 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3821 3822 return ret; 3823 } 3824 3825 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3826 const struct atom_voltage_table *table, 3827 const struct radeon_phase_shedding_limits_table *limits) 3828 { 3829 u32 data, num_bits, num_levels; 3830 3831 if ((table == NULL) || (limits == NULL)) 3832 return false; 3833 3834 data = table->mask_low; 3835 3836 num_bits = hweight32(data); 3837 3838 if (num_bits == 0) 3839 return false; 3840 3841 num_levels = (1 << num_bits); 3842 3843 if (table->count != num_levels) 3844 return false; 3845 3846 if (limits->count != (num_levels - 1)) 3847 return false; 3848 3849 return true; 3850 } 3851 3852 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3853 u32 max_voltage_steps, 3854 struct atom_voltage_table *voltage_table) 3855 { 3856 unsigned int i, diff; 3857 3858 if (voltage_table->count <= max_voltage_steps) 3859 return; 3860 3861 diff = voltage_table->count - max_voltage_steps; 3862 3863 for (i= 0; i < max_voltage_steps; i++) 3864 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3865 3866 voltage_table->count = max_voltage_steps; 3867 } 3868 3869 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3870 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3871 struct atom_voltage_table *voltage_table) 3872 { 3873 u32 i; 3874 3875 if (voltage_dependency_table == NULL) 3876 return -EINVAL; 3877 3878 voltage_table->mask_low = 0; 3879 voltage_table->phase_delay = 0; 3880 3881 voltage_table->count = voltage_dependency_table->count; 3882 for (i = 0; i < voltage_table->count; i++) { 3883 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3884 voltage_table->entries[i].smio_low = 0; 3885 } 3886 3887 return 0; 3888 } 3889 3890 static int si_construct_voltage_tables(struct radeon_device *rdev) 3891 { 3892 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3893 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3894 struct si_power_info *si_pi = si_get_pi(rdev); 3895 int ret; 3896 3897 if (pi->voltage_control) { 3898 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3899 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3900 if (ret) 3901 return ret; 3902 3903 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3904 si_trim_voltage_table_to_fit_state_table(rdev, 3905 SISLANDS_MAX_NO_VREG_STEPS, 3906 &eg_pi->vddc_voltage_table); 3907 } else if (si_pi->voltage_control_svi2) { 3908 ret = si_get_svi2_voltage_table(rdev, 3909 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3910 &eg_pi->vddc_voltage_table); 3911 if (ret) 3912 return ret; 3913 } else { 3914 return -EINVAL; 3915 } 3916 3917 if (eg_pi->vddci_control) { 3918 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3919 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3920 if (ret) 3921 return ret; 3922 3923 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3924 si_trim_voltage_table_to_fit_state_table(rdev, 3925 SISLANDS_MAX_NO_VREG_STEPS, 3926 &eg_pi->vddci_voltage_table); 3927 } 3928 if (si_pi->vddci_control_svi2) { 3929 ret = si_get_svi2_voltage_table(rdev, 3930 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3931 &eg_pi->vddci_voltage_table); 3932 if (ret) 3933 return ret; 3934 } 3935 3936 if (pi->mvdd_control) { 3937 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3938 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3939 3940 if (ret) { 3941 pi->mvdd_control = false; 3942 return ret; 3943 } 3944 3945 if (si_pi->mvdd_voltage_table.count == 0) { 3946 pi->mvdd_control = false; 3947 return -EINVAL; 3948 } 3949 3950 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3951 si_trim_voltage_table_to_fit_state_table(rdev, 3952 SISLANDS_MAX_NO_VREG_STEPS, 3953 &si_pi->mvdd_voltage_table); 3954 } 3955 3956 if (si_pi->vddc_phase_shed_control) { 3957 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3958 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3959 if (ret) 3960 si_pi->vddc_phase_shed_control = false; 3961 3962 if ((si_pi->vddc_phase_shed_table.count == 0) || 3963 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3964 si_pi->vddc_phase_shed_control = false; 3965 } 3966 3967 return 0; 3968 } 3969 3970 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3971 const struct atom_voltage_table *voltage_table, 3972 SISLANDS_SMC_STATETABLE *table) 3973 { 3974 unsigned int i; 3975 3976 for (i = 0; i < voltage_table->count; i++) 3977 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3978 } 3979 3980 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3981 SISLANDS_SMC_STATETABLE *table) 3982 { 3983 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3984 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3985 struct si_power_info *si_pi = si_get_pi(rdev); 3986 u8 i; 3987 3988 if (si_pi->voltage_control_svi2) { 3989 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 3990 si_pi->svc_gpio_id); 3991 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 3992 si_pi->svd_gpio_id); 3993 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 3994 2); 3995 } else { 3996 if (eg_pi->vddc_voltage_table.count) { 3997 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3998 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3999 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4000 4001 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4002 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4003 table->maxVDDCIndexInPPTable = i; 4004 break; 4005 } 4006 } 4007 } 4008 4009 if (eg_pi->vddci_voltage_table.count) { 4010 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4011 4012 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4013 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4014 } 4015 4016 4017 if (si_pi->mvdd_voltage_table.count) { 4018 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4019 4020 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4021 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4022 } 4023 4024 if (si_pi->vddc_phase_shed_control) { 4025 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4026 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4027 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4028 4029 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4030 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4031 4032 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4033 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4034 } else { 4035 si_pi->vddc_phase_shed_control = false; 4036 } 4037 } 4038 } 4039 4040 return 0; 4041 } 4042 4043 static int si_populate_voltage_value(struct radeon_device *rdev, 4044 const struct atom_voltage_table *table, 4045 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4046 { 4047 unsigned int i; 4048 4049 for (i = 0; i < table->count; i++) { 4050 if (value <= table->entries[i].value) { 4051 voltage->index = (u8)i; 4052 voltage->value = cpu_to_be16(table->entries[i].value); 4053 break; 4054 } 4055 } 4056 4057 if (i >= table->count) 4058 return -EINVAL; 4059 4060 return 0; 4061 } 4062 4063 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4064 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4065 { 4066 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4067 struct si_power_info *si_pi = si_get_pi(rdev); 4068 4069 if (pi->mvdd_control) { 4070 if (mclk <= pi->mvdd_split_frequency) 4071 voltage->index = 0; 4072 else 4073 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4074 4075 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4076 } 4077 return 0; 4078 } 4079 4080 static int si_get_std_voltage_value(struct radeon_device *rdev, 4081 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4082 u16 *std_voltage) 4083 { 4084 u16 v_index; 4085 bool voltage_found = false; 4086 *std_voltage = be16_to_cpu(voltage->value); 4087 4088 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4089 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4090 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4091 return -EINVAL; 4092 4093 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4094 if (be16_to_cpu(voltage->value) == 4095 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4096 voltage_found = true; 4097 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4098 *std_voltage = 4099 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4100 else 4101 *std_voltage = 4102 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4103 break; 4104 } 4105 } 4106 4107 if (!voltage_found) { 4108 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4109 if (be16_to_cpu(voltage->value) <= 4110 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4111 voltage_found = true; 4112 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4113 *std_voltage = 4114 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4115 else 4116 *std_voltage = 4117 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4118 break; 4119 } 4120 } 4121 } 4122 } else { 4123 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4124 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4125 } 4126 } 4127 4128 return 0; 4129 } 4130 4131 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4132 u16 value, u8 index, 4133 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4134 { 4135 voltage->index = index; 4136 voltage->value = cpu_to_be16(value); 4137 4138 return 0; 4139 } 4140 4141 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4142 const struct radeon_phase_shedding_limits_table *limits, 4143 u16 voltage, u32 sclk, u32 mclk, 4144 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4145 { 4146 unsigned int i; 4147 4148 for (i = 0; i < limits->count; i++) { 4149 if ((voltage <= limits->entries[i].voltage) && 4150 (sclk <= limits->entries[i].sclk) && 4151 (mclk <= limits->entries[i].mclk)) 4152 break; 4153 } 4154 4155 smc_voltage->phase_settings = (u8)i; 4156 4157 return 0; 4158 } 4159 4160 static int si_init_arb_table_index(struct radeon_device *rdev) 4161 { 4162 struct si_power_info *si_pi = si_get_pi(rdev); 4163 u32 tmp; 4164 int ret; 4165 4166 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4167 if (ret) 4168 return ret; 4169 4170 tmp &= 0x00FFFFFF; 4171 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4172 4173 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4174 } 4175 4176 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4177 { 4178 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4179 } 4180 4181 static int si_reset_to_default(struct radeon_device *rdev) 4182 { 4183 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4184 0 : -EINVAL; 4185 } 4186 4187 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4188 { 4189 struct si_power_info *si_pi = si_get_pi(rdev); 4190 u32 tmp; 4191 int ret; 4192 4193 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4194 &tmp, si_pi->sram_end); 4195 if (ret) 4196 return ret; 4197 4198 tmp = (tmp >> 24) & 0xff; 4199 4200 if (tmp == MC_CG_ARB_FREQ_F0) 4201 return 0; 4202 4203 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4204 } 4205 4206 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4207 u32 engine_clock) 4208 { 4209 u32 dram_rows; 4210 u32 dram_refresh_rate; 4211 u32 mc_arb_rfsh_rate; 4212 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4213 4214 if (tmp >= 4) 4215 dram_rows = 16384; 4216 else 4217 dram_rows = 1 << (tmp + 10); 4218 4219 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4220 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4221 4222 return mc_arb_rfsh_rate; 4223 } 4224 4225 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4226 struct rv7xx_pl *pl, 4227 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4228 { 4229 u32 dram_timing; 4230 u32 dram_timing2; 4231 u32 burst_time; 4232 4233 arb_regs->mc_arb_rfsh_rate = 4234 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4235 4236 radeon_atom_set_engine_dram_timings(rdev, 4237 pl->sclk, 4238 pl->mclk); 4239 4240 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4241 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4242 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4243 4244 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4245 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4246 arb_regs->mc_arb_burst_time = (u8)burst_time; 4247 4248 return 0; 4249 } 4250 4251 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4252 struct radeon_ps *radeon_state, 4253 unsigned int first_arb_set) 4254 { 4255 struct si_power_info *si_pi = si_get_pi(rdev); 4256 struct ni_ps *state = ni_get_ps(radeon_state); 4257 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4258 int i, ret = 0; 4259 4260 for (i = 0; i < state->performance_level_count; i++) { 4261 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4262 if (ret) 4263 break; 4264 ret = si_copy_bytes_to_smc(rdev, 4265 si_pi->arb_table_start + 4266 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4267 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4268 (u8 *)&arb_regs, 4269 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4270 si_pi->sram_end); 4271 if (ret) 4272 break; 4273 } 4274 4275 return ret; 4276 } 4277 4278 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4279 struct radeon_ps *radeon_new_state) 4280 { 4281 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4282 SISLANDS_DRIVER_STATE_ARB_INDEX); 4283 } 4284 4285 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4286 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4287 { 4288 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4289 struct si_power_info *si_pi = si_get_pi(rdev); 4290 4291 if (pi->mvdd_control) 4292 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4293 si_pi->mvdd_bootup_value, voltage); 4294 4295 return 0; 4296 } 4297 4298 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4299 struct radeon_ps *radeon_initial_state, 4300 SISLANDS_SMC_STATETABLE *table) 4301 { 4302 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4303 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4304 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4305 struct si_power_info *si_pi = si_get_pi(rdev); 4306 u32 reg; 4307 int ret; 4308 4309 table->initialState.levels[0].mclk.vDLL_CNTL = 4310 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4311 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4312 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4313 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4314 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4315 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4316 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4317 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4318 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4319 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4320 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4321 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4322 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4323 table->initialState.levels[0].mclk.vMPLL_SS = 4324 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4325 table->initialState.levels[0].mclk.vMPLL_SS2 = 4326 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4327 4328 table->initialState.levels[0].mclk.mclk_value = 4329 cpu_to_be32(initial_state->performance_levels[0].mclk); 4330 4331 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4332 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4333 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4334 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4335 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4336 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4337 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4338 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4339 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4340 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4341 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4342 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4343 4344 table->initialState.levels[0].sclk.sclk_value = 4345 cpu_to_be32(initial_state->performance_levels[0].sclk); 4346 4347 table->initialState.levels[0].arbRefreshState = 4348 SISLANDS_INITIAL_STATE_ARB_INDEX; 4349 4350 table->initialState.levels[0].ACIndex = 0; 4351 4352 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4353 initial_state->performance_levels[0].vddc, 4354 &table->initialState.levels[0].vddc); 4355 4356 if (!ret) { 4357 u16 std_vddc; 4358 4359 ret = si_get_std_voltage_value(rdev, 4360 &table->initialState.levels[0].vddc, 4361 &std_vddc); 4362 if (!ret) 4363 si_populate_std_voltage_value(rdev, std_vddc, 4364 table->initialState.levels[0].vddc.index, 4365 &table->initialState.levels[0].std_vddc); 4366 } 4367 4368 if (eg_pi->vddci_control) 4369 si_populate_voltage_value(rdev, 4370 &eg_pi->vddci_voltage_table, 4371 initial_state->performance_levels[0].vddci, 4372 &table->initialState.levels[0].vddci); 4373 4374 if (si_pi->vddc_phase_shed_control) 4375 si_populate_phase_shedding_value(rdev, 4376 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4377 initial_state->performance_levels[0].vddc, 4378 initial_state->performance_levels[0].sclk, 4379 initial_state->performance_levels[0].mclk, 4380 &table->initialState.levels[0].vddc); 4381 4382 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4383 4384 reg = CG_R(0xffff) | CG_L(0); 4385 table->initialState.levels[0].aT = cpu_to_be32(reg); 4386 4387 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4388 4389 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4390 4391 if (pi->mem_gddr5) { 4392 table->initialState.levels[0].strobeMode = 4393 si_get_strobe_mode_settings(rdev, 4394 initial_state->performance_levels[0].mclk); 4395 4396 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4397 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4398 else 4399 table->initialState.levels[0].mcFlags = 0; 4400 } 4401 4402 table->initialState.levelCount = 1; 4403 4404 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4405 4406 table->initialState.levels[0].dpm2.MaxPS = 0; 4407 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4408 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4409 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4410 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4411 4412 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4413 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4414 4415 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4416 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4417 4418 return 0; 4419 } 4420 4421 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4422 SISLANDS_SMC_STATETABLE *table) 4423 { 4424 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4425 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4426 struct si_power_info *si_pi = si_get_pi(rdev); 4427 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4428 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4429 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4430 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4431 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4432 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4433 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4434 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4435 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4436 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4437 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4438 u32 reg; 4439 int ret; 4440 4441 table->ACPIState = table->initialState; 4442 4443 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4444 4445 if (pi->acpi_vddc) { 4446 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4447 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4448 if (!ret) { 4449 u16 std_vddc; 4450 4451 ret = si_get_std_voltage_value(rdev, 4452 &table->ACPIState.levels[0].vddc, &std_vddc); 4453 if (!ret) 4454 si_populate_std_voltage_value(rdev, std_vddc, 4455 table->ACPIState.levels[0].vddc.index, 4456 &table->ACPIState.levels[0].std_vddc); 4457 } 4458 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4459 4460 if (si_pi->vddc_phase_shed_control) { 4461 si_populate_phase_shedding_value(rdev, 4462 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4463 pi->acpi_vddc, 4464 0, 4465 0, 4466 &table->ACPIState.levels[0].vddc); 4467 } 4468 } else { 4469 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4470 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4471 if (!ret) { 4472 u16 std_vddc; 4473 4474 ret = si_get_std_voltage_value(rdev, 4475 &table->ACPIState.levels[0].vddc, &std_vddc); 4476 4477 if (!ret) 4478 si_populate_std_voltage_value(rdev, std_vddc, 4479 table->ACPIState.levels[0].vddc.index, 4480 &table->ACPIState.levels[0].std_vddc); 4481 } 4482 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4483 si_pi->sys_pcie_mask, 4484 si_pi->boot_pcie_gen, 4485 RADEON_PCIE_GEN1); 4486 4487 if (si_pi->vddc_phase_shed_control) 4488 si_populate_phase_shedding_value(rdev, 4489 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4490 pi->min_vddc_in_table, 4491 0, 4492 0, 4493 &table->ACPIState.levels[0].vddc); 4494 } 4495 4496 if (pi->acpi_vddc) { 4497 if (eg_pi->acpi_vddci) 4498 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4499 eg_pi->acpi_vddci, 4500 &table->ACPIState.levels[0].vddci); 4501 } 4502 4503 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4504 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4505 4506 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4507 4508 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4509 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4510 4511 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4512 cpu_to_be32(dll_cntl); 4513 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4514 cpu_to_be32(mclk_pwrmgt_cntl); 4515 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4516 cpu_to_be32(mpll_ad_func_cntl); 4517 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4518 cpu_to_be32(mpll_dq_func_cntl); 4519 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4520 cpu_to_be32(mpll_func_cntl); 4521 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4522 cpu_to_be32(mpll_func_cntl_1); 4523 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4524 cpu_to_be32(mpll_func_cntl_2); 4525 table->ACPIState.levels[0].mclk.vMPLL_SS = 4526 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4527 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4528 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4529 4530 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4531 cpu_to_be32(spll_func_cntl); 4532 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4533 cpu_to_be32(spll_func_cntl_2); 4534 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4535 cpu_to_be32(spll_func_cntl_3); 4536 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4537 cpu_to_be32(spll_func_cntl_4); 4538 4539 table->ACPIState.levels[0].mclk.mclk_value = 0; 4540 table->ACPIState.levels[0].sclk.sclk_value = 0; 4541 4542 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4543 4544 if (eg_pi->dynamic_ac_timing) 4545 table->ACPIState.levels[0].ACIndex = 0; 4546 4547 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4548 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4549 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4550 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4551 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4552 4553 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4554 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4555 4556 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4557 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4558 4559 return 0; 4560 } 4561 4562 static int si_populate_ulv_state(struct radeon_device *rdev, 4563 SISLANDS_SMC_SWSTATE *state) 4564 { 4565 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4566 struct si_power_info *si_pi = si_get_pi(rdev); 4567 struct si_ulv_param *ulv = &si_pi->ulv; 4568 u32 sclk_in_sr = 1350; /* ??? */ 4569 int ret; 4570 4571 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4572 &state->levels[0]); 4573 if (!ret) { 4574 if (eg_pi->sclk_deep_sleep) { 4575 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4576 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4577 else 4578 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4579 } 4580 if (ulv->one_pcie_lane_in_ulv) 4581 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4582 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4583 state->levels[0].ACIndex = 1; 4584 state->levels[0].std_vddc = state->levels[0].vddc; 4585 state->levelCount = 1; 4586 4587 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4588 } 4589 4590 return ret; 4591 } 4592 4593 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4594 { 4595 struct si_power_info *si_pi = si_get_pi(rdev); 4596 struct si_ulv_param *ulv = &si_pi->ulv; 4597 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4598 int ret; 4599 4600 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4601 &arb_regs); 4602 if (ret) 4603 return ret; 4604 4605 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4606 ulv->volt_change_delay); 4607 4608 ret = si_copy_bytes_to_smc(rdev, 4609 si_pi->arb_table_start + 4610 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4611 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4612 (u8 *)&arb_regs, 4613 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4614 si_pi->sram_end); 4615 4616 return ret; 4617 } 4618 4619 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4620 { 4621 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4622 4623 pi->mvdd_split_frequency = 30000; 4624 } 4625 4626 static int si_init_smc_table(struct radeon_device *rdev) 4627 { 4628 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4629 struct si_power_info *si_pi = si_get_pi(rdev); 4630 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4631 const struct si_ulv_param *ulv = &si_pi->ulv; 4632 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4633 int ret; 4634 u32 lane_width; 4635 u32 vr_hot_gpio; 4636 4637 si_populate_smc_voltage_tables(rdev, table); 4638 4639 switch (rdev->pm.int_thermal_type) { 4640 case THERMAL_TYPE_SI: 4641 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4642 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4643 break; 4644 case THERMAL_TYPE_NONE: 4645 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4646 break; 4647 default: 4648 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4649 break; 4650 } 4651 4652 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4653 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4654 4655 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4656 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4657 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4658 } 4659 4660 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4661 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4662 4663 if (pi->mem_gddr5) 4664 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4665 4666 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4667 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4668 4669 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4670 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4671 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4672 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4673 vr_hot_gpio); 4674 } 4675 4676 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4677 if (ret) 4678 return ret; 4679 4680 ret = si_populate_smc_acpi_state(rdev, table); 4681 if (ret) 4682 return ret; 4683 4684 table->driverState = table->initialState; 4685 4686 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4687 SISLANDS_INITIAL_STATE_ARB_INDEX); 4688 if (ret) 4689 return ret; 4690 4691 if (ulv->supported && ulv->pl.vddc) { 4692 ret = si_populate_ulv_state(rdev, &table->ULVState); 4693 if (ret) 4694 return ret; 4695 4696 ret = si_program_ulv_memory_timing_parameters(rdev); 4697 if (ret) 4698 return ret; 4699 4700 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4701 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4702 4703 lane_width = radeon_get_pcie_lanes(rdev); 4704 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4705 } else { 4706 table->ULVState = table->initialState; 4707 } 4708 4709 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4710 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4711 si_pi->sram_end); 4712 } 4713 4714 static int si_calculate_sclk_params(struct radeon_device *rdev, 4715 u32 engine_clock, 4716 SISLANDS_SMC_SCLK_VALUE *sclk) 4717 { 4718 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4719 struct si_power_info *si_pi = si_get_pi(rdev); 4720 struct atom_clock_dividers dividers; 4721 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4722 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4723 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4724 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4725 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4726 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4727 u64 tmp; 4728 u32 reference_clock = rdev->clock.spll.reference_freq; 4729 u32 reference_divider; 4730 u32 fbdiv; 4731 int ret; 4732 4733 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4734 engine_clock, false, ÷rs); 4735 if (ret) 4736 return ret; 4737 4738 reference_divider = 1 + dividers.ref_div; 4739 4740 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4741 do_div(tmp, reference_clock); 4742 fbdiv = (u32) tmp; 4743 4744 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4745 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4746 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4747 4748 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4749 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4750 4751 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4752 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4753 spll_func_cntl_3 |= SPLL_DITHEN; 4754 4755 if (pi->sclk_ss) { 4756 struct radeon_atom_ss ss; 4757 u32 vco_freq = engine_clock * dividers.post_div; 4758 4759 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4760 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4761 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4762 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4763 4764 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4765 cg_spll_spread_spectrum |= CLK_S(clk_s); 4766 cg_spll_spread_spectrum |= SSEN; 4767 4768 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4769 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4770 } 4771 } 4772 4773 sclk->sclk_value = engine_clock; 4774 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4775 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4776 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4777 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4778 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4779 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4780 4781 return 0; 4782 } 4783 4784 static int si_populate_sclk_value(struct radeon_device *rdev, 4785 u32 engine_clock, 4786 SISLANDS_SMC_SCLK_VALUE *sclk) 4787 { 4788 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4789 int ret; 4790 4791 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4792 if (!ret) { 4793 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4794 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4795 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4796 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4797 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4798 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4799 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4800 } 4801 4802 return ret; 4803 } 4804 4805 static int si_populate_mclk_value(struct radeon_device *rdev, 4806 u32 engine_clock, 4807 u32 memory_clock, 4808 SISLANDS_SMC_MCLK_VALUE *mclk, 4809 bool strobe_mode, 4810 bool dll_state_on) 4811 { 4812 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4813 struct si_power_info *si_pi = si_get_pi(rdev); 4814 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4815 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4816 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4817 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4818 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4819 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4820 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4821 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4822 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4823 struct atom_mpll_param mpll_param; 4824 int ret; 4825 4826 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4827 if (ret) 4828 return ret; 4829 4830 mpll_func_cntl &= ~BWCTRL_MASK; 4831 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4832 4833 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4834 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4835 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4836 4837 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4838 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4839 4840 if (pi->mem_gddr5) { 4841 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4842 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4843 YCLK_POST_DIV(mpll_param.post_div); 4844 } 4845 4846 if (pi->mclk_ss) { 4847 struct radeon_atom_ss ss; 4848 u32 freq_nom; 4849 u32 tmp; 4850 u32 reference_clock = rdev->clock.mpll.reference_freq; 4851 4852 if (pi->mem_gddr5) 4853 freq_nom = memory_clock * 4; 4854 else 4855 freq_nom = memory_clock * 2; 4856 4857 tmp = freq_nom / reference_clock; 4858 tmp = tmp * tmp; 4859 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4860 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4861 u32 clks = reference_clock * 5 / ss.rate; 4862 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4863 4864 mpll_ss1 &= ~CLKV_MASK; 4865 mpll_ss1 |= CLKV(clkv); 4866 4867 mpll_ss2 &= ~CLKS_MASK; 4868 mpll_ss2 |= CLKS(clks); 4869 } 4870 } 4871 4872 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4873 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4874 4875 if (dll_state_on) 4876 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4877 else 4878 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4879 4880 mclk->mclk_value = cpu_to_be32(memory_clock); 4881 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4882 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4883 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4884 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4885 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4886 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4887 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4888 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4889 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4890 4891 return 0; 4892 } 4893 4894 static void si_populate_smc_sp(struct radeon_device *rdev, 4895 struct radeon_ps *radeon_state, 4896 SISLANDS_SMC_SWSTATE *smc_state) 4897 { 4898 struct ni_ps *ps = ni_get_ps(radeon_state); 4899 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4900 int i; 4901 4902 for (i = 0; i < ps->performance_level_count - 1; i++) 4903 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4904 4905 smc_state->levels[ps->performance_level_count - 1].bSP = 4906 cpu_to_be32(pi->psp); 4907 } 4908 4909 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4910 struct rv7xx_pl *pl, 4911 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4912 { 4913 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4914 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4915 struct si_power_info *si_pi = si_get_pi(rdev); 4916 int ret; 4917 bool dll_state_on; 4918 u16 std_vddc; 4919 bool gmc_pg = false; 4920 4921 if (eg_pi->pcie_performance_request && 4922 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4923 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4924 else 4925 level->gen2PCIE = (u8)pl->pcie_gen; 4926 4927 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4928 if (ret) 4929 return ret; 4930 4931 level->mcFlags = 0; 4932 4933 if (pi->mclk_stutter_mode_threshold && 4934 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4935 !eg_pi->uvd_enabled && 4936 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4937 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4938 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4939 4940 if (gmc_pg) 4941 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4942 } 4943 4944 if (pi->mem_gddr5) { 4945 if (pl->mclk > pi->mclk_edc_enable_threshold) 4946 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4947 4948 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4949 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4950 4951 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4952 4953 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4954 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4955 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4956 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4957 else 4958 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4959 } else { 4960 dll_state_on = false; 4961 } 4962 } else { 4963 level->strobeMode = si_get_strobe_mode_settings(rdev, 4964 pl->mclk); 4965 4966 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4967 } 4968 4969 ret = si_populate_mclk_value(rdev, 4970 pl->sclk, 4971 pl->mclk, 4972 &level->mclk, 4973 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4974 if (ret) 4975 return ret; 4976 4977 ret = si_populate_voltage_value(rdev, 4978 &eg_pi->vddc_voltage_table, 4979 pl->vddc, &level->vddc); 4980 if (ret) 4981 return ret; 4982 4983 4984 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4985 if (ret) 4986 return ret; 4987 4988 ret = si_populate_std_voltage_value(rdev, std_vddc, 4989 level->vddc.index, &level->std_vddc); 4990 if (ret) 4991 return ret; 4992 4993 if (eg_pi->vddci_control) { 4994 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4995 pl->vddci, &level->vddci); 4996 if (ret) 4997 return ret; 4998 } 4999 5000 if (si_pi->vddc_phase_shed_control) { 5001 ret = si_populate_phase_shedding_value(rdev, 5002 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5003 pl->vddc, 5004 pl->sclk, 5005 pl->mclk, 5006 &level->vddc); 5007 if (ret) 5008 return ret; 5009 } 5010 5011 level->MaxPoweredUpCU = si_pi->max_cu; 5012 5013 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5014 5015 return ret; 5016 } 5017 5018 static int si_populate_smc_t(struct radeon_device *rdev, 5019 struct radeon_ps *radeon_state, 5020 SISLANDS_SMC_SWSTATE *smc_state) 5021 { 5022 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5023 struct ni_ps *state = ni_get_ps(radeon_state); 5024 u32 a_t; 5025 u32 t_l, t_h; 5026 u32 high_bsp; 5027 int i, ret; 5028 5029 if (state->performance_level_count >= 9) 5030 return -EINVAL; 5031 5032 if (state->performance_level_count < 2) { 5033 a_t = CG_R(0xffff) | CG_L(0); 5034 smc_state->levels[0].aT = cpu_to_be32(a_t); 5035 return 0; 5036 } 5037 5038 smc_state->levels[0].aT = cpu_to_be32(0); 5039 5040 for (i = 0; i <= state->performance_level_count - 2; i++) { 5041 ret = r600_calculate_at( 5042 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5043 100 * R600_AH_DFLT, 5044 state->performance_levels[i + 1].sclk, 5045 state->performance_levels[i].sclk, 5046 &t_l, 5047 &t_h); 5048 5049 if (ret) { 5050 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5051 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5052 } 5053 5054 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5055 a_t |= CG_R(t_l * pi->bsp / 20000); 5056 smc_state->levels[i].aT = cpu_to_be32(a_t); 5057 5058 high_bsp = (i == state->performance_level_count - 2) ? 5059 pi->pbsp : pi->bsp; 5060 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5061 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5062 } 5063 5064 return 0; 5065 } 5066 5067 static int si_disable_ulv(struct radeon_device *rdev) 5068 { 5069 struct si_power_info *si_pi = si_get_pi(rdev); 5070 struct si_ulv_param *ulv = &si_pi->ulv; 5071 5072 if (ulv->supported) 5073 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5074 0 : -EINVAL; 5075 5076 return 0; 5077 } 5078 5079 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5080 struct radeon_ps *radeon_state) 5081 { 5082 const struct si_power_info *si_pi = si_get_pi(rdev); 5083 const struct si_ulv_param *ulv = &si_pi->ulv; 5084 const struct ni_ps *state = ni_get_ps(radeon_state); 5085 int i; 5086 5087 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5088 return false; 5089 5090 /* XXX validate against display requirements! */ 5091 5092 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5093 if (rdev->clock.current_dispclk <= 5094 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5095 if (ulv->pl.vddc < 5096 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5097 return false; 5098 } 5099 } 5100 5101 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5102 return false; 5103 5104 return true; 5105 } 5106 5107 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5108 struct radeon_ps *radeon_new_state) 5109 { 5110 const struct si_power_info *si_pi = si_get_pi(rdev); 5111 const struct si_ulv_param *ulv = &si_pi->ulv; 5112 5113 if (ulv->supported) { 5114 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5115 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5116 0 : -EINVAL; 5117 } 5118 return 0; 5119 } 5120 5121 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5122 struct radeon_ps *radeon_state, 5123 SISLANDS_SMC_SWSTATE *smc_state) 5124 { 5125 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5126 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5127 struct si_power_info *si_pi = si_get_pi(rdev); 5128 struct ni_ps *state = ni_get_ps(radeon_state); 5129 int i, ret; 5130 u32 threshold; 5131 u32 sclk_in_sr = 1350; /* ??? */ 5132 5133 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5134 return -EINVAL; 5135 5136 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5137 5138 if (radeon_state->vclk && radeon_state->dclk) { 5139 eg_pi->uvd_enabled = true; 5140 if (eg_pi->smu_uvd_hs) 5141 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5142 } else { 5143 eg_pi->uvd_enabled = false; 5144 } 5145 5146 if (state->dc_compatible) 5147 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5148 5149 smc_state->levelCount = 0; 5150 for (i = 0; i < state->performance_level_count; i++) { 5151 if (eg_pi->sclk_deep_sleep) { 5152 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5153 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5154 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5155 else 5156 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5157 } 5158 } 5159 5160 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5161 &smc_state->levels[i]); 5162 smc_state->levels[i].arbRefreshState = 5163 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5164 5165 if (ret) 5166 return ret; 5167 5168 if (ni_pi->enable_power_containment) 5169 smc_state->levels[i].displayWatermark = 5170 (state->performance_levels[i].sclk < threshold) ? 5171 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5172 else 5173 smc_state->levels[i].displayWatermark = (i < 2) ? 5174 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5175 5176 if (eg_pi->dynamic_ac_timing) 5177 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5178 else 5179 smc_state->levels[i].ACIndex = 0; 5180 5181 smc_state->levelCount++; 5182 } 5183 5184 si_write_smc_soft_register(rdev, 5185 SI_SMC_SOFT_REGISTER_watermark_threshold, 5186 threshold / 512); 5187 5188 si_populate_smc_sp(rdev, radeon_state, smc_state); 5189 5190 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5191 if (ret) 5192 ni_pi->enable_power_containment = false; 5193 5194 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5195 if (ret) 5196 ni_pi->enable_sq_ramping = false; 5197 5198 return si_populate_smc_t(rdev, radeon_state, smc_state); 5199 } 5200 5201 static int si_upload_sw_state(struct radeon_device *rdev, 5202 struct radeon_ps *radeon_new_state) 5203 { 5204 struct si_power_info *si_pi = si_get_pi(rdev); 5205 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5206 int ret; 5207 u32 address = si_pi->state_table_start + 5208 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5209 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5210 ((new_state->performance_level_count - 1) * 5211 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5212 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5213 5214 memset(smc_state, 0, state_size); 5215 5216 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5217 if (ret) 5218 return ret; 5219 5220 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5221 state_size, si_pi->sram_end); 5222 5223 return ret; 5224 } 5225 5226 static int si_upload_ulv_state(struct radeon_device *rdev) 5227 { 5228 struct si_power_info *si_pi = si_get_pi(rdev); 5229 struct si_ulv_param *ulv = &si_pi->ulv; 5230 int ret = 0; 5231 5232 if (ulv->supported && ulv->pl.vddc) { 5233 u32 address = si_pi->state_table_start + 5234 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5235 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5236 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5237 5238 memset(smc_state, 0, state_size); 5239 5240 ret = si_populate_ulv_state(rdev, smc_state); 5241 if (!ret) 5242 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5243 state_size, si_pi->sram_end); 5244 } 5245 5246 return ret; 5247 } 5248 5249 static int si_upload_smc_data(struct radeon_device *rdev) 5250 { 5251 struct radeon_crtc *radeon_crtc = NULL; 5252 int i; 5253 5254 if (rdev->pm.dpm.new_active_crtc_count == 0) 5255 return 0; 5256 5257 for (i = 0; i < rdev->num_crtc; i++) { 5258 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5259 radeon_crtc = rdev->mode_info.crtcs[i]; 5260 break; 5261 } 5262 } 5263 5264 if (radeon_crtc == NULL) 5265 return 0; 5266 5267 if (radeon_crtc->line_time <= 0) 5268 return 0; 5269 5270 if (si_write_smc_soft_register(rdev, 5271 SI_SMC_SOFT_REGISTER_crtc_index, 5272 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5273 return 0; 5274 5275 if (si_write_smc_soft_register(rdev, 5276 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5277 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5278 return 0; 5279 5280 if (si_write_smc_soft_register(rdev, 5281 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5282 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5283 return 0; 5284 5285 return 0; 5286 } 5287 5288 static int si_set_mc_special_registers(struct radeon_device *rdev, 5289 struct si_mc_reg_table *table) 5290 { 5291 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5292 u8 i, j, k; 5293 u32 temp_reg; 5294 5295 for (i = 0, j = table->last; i < table->last; i++) { 5296 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5297 return -EINVAL; 5298 switch (table->mc_reg_address[i].s1 << 2) { 5299 case MC_SEQ_MISC1: 5300 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5301 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5302 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5303 for (k = 0; k < table->num_entries; k++) 5304 table->mc_reg_table_entry[k].mc_data[j] = 5305 ((temp_reg & 0xffff0000)) | 5306 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5307 j++; 5308 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5309 return -EINVAL; 5310 5311 temp_reg = RREG32(MC_PMG_CMD_MRS); 5312 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5313 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5314 for (k = 0; k < table->num_entries; k++) { 5315 table->mc_reg_table_entry[k].mc_data[j] = 5316 (temp_reg & 0xffff0000) | 5317 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5318 if (!pi->mem_gddr5) 5319 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5320 } 5321 j++; 5322 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5323 return -EINVAL; 5324 5325 if (!pi->mem_gddr5) { 5326 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5327 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5328 for (k = 0; k < table->num_entries; k++) 5329 table->mc_reg_table_entry[k].mc_data[j] = 5330 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5331 j++; 5332 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5333 return -EINVAL; 5334 } 5335 break; 5336 case MC_SEQ_RESERVE_M: 5337 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5338 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5339 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5340 for(k = 0; k < table->num_entries; k++) 5341 table->mc_reg_table_entry[k].mc_data[j] = 5342 (temp_reg & 0xffff0000) | 5343 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5344 j++; 5345 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5346 return -EINVAL; 5347 break; 5348 default: 5349 break; 5350 } 5351 } 5352 5353 table->last = j; 5354 5355 return 0; 5356 } 5357 5358 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5359 { 5360 bool result = true; 5361 5362 switch (in_reg) { 5363 case MC_SEQ_RAS_TIMING >> 2: 5364 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5365 break; 5366 case MC_SEQ_CAS_TIMING >> 2: 5367 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5368 break; 5369 case MC_SEQ_MISC_TIMING >> 2: 5370 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5371 break; 5372 case MC_SEQ_MISC_TIMING2 >> 2: 5373 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5374 break; 5375 case MC_SEQ_RD_CTL_D0 >> 2: 5376 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5377 break; 5378 case MC_SEQ_RD_CTL_D1 >> 2: 5379 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5380 break; 5381 case MC_SEQ_WR_CTL_D0 >> 2: 5382 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5383 break; 5384 case MC_SEQ_WR_CTL_D1 >> 2: 5385 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5386 break; 5387 case MC_PMG_CMD_EMRS >> 2: 5388 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5389 break; 5390 case MC_PMG_CMD_MRS >> 2: 5391 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5392 break; 5393 case MC_PMG_CMD_MRS1 >> 2: 5394 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5395 break; 5396 case MC_SEQ_PMG_TIMING >> 2: 5397 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5398 break; 5399 case MC_PMG_CMD_MRS2 >> 2: 5400 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5401 break; 5402 case MC_SEQ_WR_CTL_2 >> 2: 5403 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5404 break; 5405 default: 5406 result = false; 5407 break; 5408 } 5409 5410 return result; 5411 } 5412 5413 static void si_set_valid_flag(struct si_mc_reg_table *table) 5414 { 5415 u8 i, j; 5416 5417 for (i = 0; i < table->last; i++) { 5418 for (j = 1; j < table->num_entries; j++) { 5419 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5420 table->valid_flag |= 1 << i; 5421 break; 5422 } 5423 } 5424 } 5425 } 5426 5427 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5428 { 5429 u32 i; 5430 u16 address; 5431 5432 for (i = 0; i < table->last; i++) 5433 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5434 address : table->mc_reg_address[i].s1; 5435 5436 } 5437 5438 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5439 struct si_mc_reg_table *si_table) 5440 { 5441 u8 i, j; 5442 5443 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5444 return -EINVAL; 5445 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5446 return -EINVAL; 5447 5448 for (i = 0; i < table->last; i++) 5449 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5450 si_table->last = table->last; 5451 5452 for (i = 0; i < table->num_entries; i++) { 5453 si_table->mc_reg_table_entry[i].mclk_max = 5454 table->mc_reg_table_entry[i].mclk_max; 5455 for (j = 0; j < table->last; j++) { 5456 si_table->mc_reg_table_entry[i].mc_data[j] = 5457 table->mc_reg_table_entry[i].mc_data[j]; 5458 } 5459 } 5460 si_table->num_entries = table->num_entries; 5461 5462 return 0; 5463 } 5464 5465 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5466 { 5467 struct si_power_info *si_pi = si_get_pi(rdev); 5468 struct atom_mc_reg_table *table; 5469 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5470 u8 module_index = rv770_get_memory_module_index(rdev); 5471 int ret; 5472 5473 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5474 if (!table) 5475 return -ENOMEM; 5476 5477 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5478 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5479 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5480 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5481 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5482 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5483 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5484 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5485 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5486 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5487 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5488 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5489 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5490 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5491 5492 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5493 if (ret) 5494 goto init_mc_done; 5495 5496 ret = si_copy_vbios_mc_reg_table(table, si_table); 5497 if (ret) 5498 goto init_mc_done; 5499 5500 si_set_s0_mc_reg_index(si_table); 5501 5502 ret = si_set_mc_special_registers(rdev, si_table); 5503 if (ret) 5504 goto init_mc_done; 5505 5506 si_set_valid_flag(si_table); 5507 5508 init_mc_done: 5509 kfree(table); 5510 5511 return ret; 5512 5513 } 5514 5515 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5516 SMC_SIslands_MCRegisters *mc_reg_table) 5517 { 5518 struct si_power_info *si_pi = si_get_pi(rdev); 5519 u32 i, j; 5520 5521 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5522 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5523 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5524 break; 5525 mc_reg_table->address[i].s0 = 5526 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5527 mc_reg_table->address[i].s1 = 5528 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5529 i++; 5530 } 5531 } 5532 mc_reg_table->last = (u8)i; 5533 } 5534 5535 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5536 SMC_SIslands_MCRegisterSet *data, 5537 u32 num_entries, u32 valid_flag) 5538 { 5539 u32 i, j; 5540 5541 for(i = 0, j = 0; j < num_entries; j++) { 5542 if (valid_flag & (1 << j)) { 5543 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5544 i++; 5545 } 5546 } 5547 } 5548 5549 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5550 struct rv7xx_pl *pl, 5551 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5552 { 5553 struct si_power_info *si_pi = si_get_pi(rdev); 5554 u32 i = 0; 5555 5556 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5557 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5558 break; 5559 } 5560 5561 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5562 --i; 5563 5564 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5565 mc_reg_table_data, si_pi->mc_reg_table.last, 5566 si_pi->mc_reg_table.valid_flag); 5567 } 5568 5569 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5570 struct radeon_ps *radeon_state, 5571 SMC_SIslands_MCRegisters *mc_reg_table) 5572 { 5573 struct ni_ps *state = ni_get_ps(radeon_state); 5574 int i; 5575 5576 for (i = 0; i < state->performance_level_count; i++) { 5577 si_convert_mc_reg_table_entry_to_smc(rdev, 5578 &state->performance_levels[i], 5579 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5580 } 5581 } 5582 5583 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5584 struct radeon_ps *radeon_boot_state) 5585 { 5586 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5587 struct si_power_info *si_pi = si_get_pi(rdev); 5588 struct si_ulv_param *ulv = &si_pi->ulv; 5589 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5590 5591 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5592 5593 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5594 5595 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5596 5597 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5598 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5599 5600 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5601 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5602 si_pi->mc_reg_table.last, 5603 si_pi->mc_reg_table.valid_flag); 5604 5605 if (ulv->supported && ulv->pl.vddc != 0) 5606 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5607 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5608 else 5609 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5610 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5611 si_pi->mc_reg_table.last, 5612 si_pi->mc_reg_table.valid_flag); 5613 5614 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5615 5616 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5617 (u8 *)smc_mc_reg_table, 5618 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5619 } 5620 5621 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5622 struct radeon_ps *radeon_new_state) 5623 { 5624 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5625 struct si_power_info *si_pi = si_get_pi(rdev); 5626 u32 address = si_pi->mc_reg_table_start + 5627 offsetof(SMC_SIslands_MCRegisters, 5628 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5629 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5630 5631 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5632 5633 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5634 5635 5636 return si_copy_bytes_to_smc(rdev, address, 5637 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5638 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5639 si_pi->sram_end); 5640 5641 } 5642 5643 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5644 { 5645 if (enable) 5646 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5647 else 5648 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5649 } 5650 5651 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5652 struct radeon_ps *radeon_state) 5653 { 5654 struct ni_ps *state = ni_get_ps(radeon_state); 5655 int i; 5656 u16 pcie_speed, max_speed = 0; 5657 5658 for (i = 0; i < state->performance_level_count; i++) { 5659 pcie_speed = state->performance_levels[i].pcie_gen; 5660 if (max_speed < pcie_speed) 5661 max_speed = pcie_speed; 5662 } 5663 return max_speed; 5664 } 5665 5666 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5667 { 5668 u32 speed_cntl; 5669 5670 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5671 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5672 5673 return (u16)speed_cntl; 5674 } 5675 5676 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5677 struct radeon_ps *radeon_new_state, 5678 struct radeon_ps *radeon_current_state) 5679 { 5680 struct si_power_info *si_pi = si_get_pi(rdev); 5681 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5682 enum radeon_pcie_gen current_link_speed; 5683 5684 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5685 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5686 else 5687 current_link_speed = si_pi->force_pcie_gen; 5688 5689 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5690 si_pi->pspp_notify_required = false; 5691 if (target_link_speed > current_link_speed) { 5692 switch (target_link_speed) { 5693 #if defined(CONFIG_ACPI) 5694 case RADEON_PCIE_GEN3: 5695 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5696 break; 5697 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5698 if (current_link_speed == RADEON_PCIE_GEN2) 5699 break; 5700 case RADEON_PCIE_GEN2: 5701 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5702 break; 5703 #endif 5704 default: 5705 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5706 break; 5707 } 5708 } else { 5709 if (target_link_speed < current_link_speed) 5710 si_pi->pspp_notify_required = true; 5711 } 5712 } 5713 5714 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5715 struct radeon_ps *radeon_new_state, 5716 struct radeon_ps *radeon_current_state) 5717 { 5718 struct si_power_info *si_pi = si_get_pi(rdev); 5719 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5720 u8 request; 5721 5722 if (si_pi->pspp_notify_required) { 5723 if (target_link_speed == RADEON_PCIE_GEN3) 5724 request = PCIE_PERF_REQ_PECI_GEN3; 5725 else if (target_link_speed == RADEON_PCIE_GEN2) 5726 request = PCIE_PERF_REQ_PECI_GEN2; 5727 else 5728 request = PCIE_PERF_REQ_PECI_GEN1; 5729 5730 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5731 (si_get_current_pcie_speed(rdev) > 0)) 5732 return; 5733 5734 #if defined(CONFIG_ACPI) 5735 radeon_acpi_pcie_performance_request(rdev, request, false); 5736 #endif 5737 } 5738 } 5739 5740 #if 0 5741 static int si_ds_request(struct radeon_device *rdev, 5742 bool ds_status_on, u32 count_write) 5743 { 5744 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5745 5746 if (eg_pi->sclk_deep_sleep) { 5747 if (ds_status_on) 5748 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5749 PPSMC_Result_OK) ? 5750 0 : -EINVAL; 5751 else 5752 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5753 PPSMC_Result_OK) ? 0 : -EINVAL; 5754 } 5755 return 0; 5756 } 5757 #endif 5758 5759 static void si_set_max_cu_value(struct radeon_device *rdev) 5760 { 5761 struct si_power_info *si_pi = si_get_pi(rdev); 5762 5763 if (rdev->family == CHIP_VERDE) { 5764 switch (rdev->pdev->device) { 5765 case 0x6820: 5766 case 0x6825: 5767 case 0x6821: 5768 case 0x6823: 5769 case 0x6827: 5770 si_pi->max_cu = 10; 5771 break; 5772 case 0x682D: 5773 case 0x6824: 5774 case 0x682F: 5775 case 0x6826: 5776 si_pi->max_cu = 8; 5777 break; 5778 case 0x6828: 5779 case 0x6830: 5780 case 0x6831: 5781 case 0x6838: 5782 case 0x6839: 5783 case 0x683D: 5784 si_pi->max_cu = 10; 5785 break; 5786 case 0x683B: 5787 case 0x683F: 5788 case 0x6829: 5789 si_pi->max_cu = 8; 5790 break; 5791 default: 5792 si_pi->max_cu = 0; 5793 break; 5794 } 5795 } else { 5796 si_pi->max_cu = 0; 5797 } 5798 } 5799 5800 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5801 struct radeon_clock_voltage_dependency_table *table) 5802 { 5803 u32 i; 5804 int j; 5805 u16 leakage_voltage; 5806 5807 if (table) { 5808 for (i = 0; i < table->count; i++) { 5809 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5810 table->entries[i].v, 5811 &leakage_voltage)) { 5812 case 0: 5813 table->entries[i].v = leakage_voltage; 5814 break; 5815 case -EAGAIN: 5816 return -EINVAL; 5817 case -EINVAL: 5818 default: 5819 break; 5820 } 5821 } 5822 5823 for (j = (table->count - 2); j >= 0; j--) { 5824 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5825 table->entries[j].v : table->entries[j + 1].v; 5826 } 5827 } 5828 return 0; 5829 } 5830 5831 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5832 { 5833 int ret = 0; 5834 5835 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5836 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5837 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5838 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5839 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5840 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5841 return ret; 5842 } 5843 5844 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5845 struct radeon_ps *radeon_new_state, 5846 struct radeon_ps *radeon_current_state) 5847 { 5848 u32 lane_width; 5849 u32 new_lane_width = 5850 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5851 u32 current_lane_width = 5852 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5853 5854 if (new_lane_width != current_lane_width) { 5855 radeon_set_pcie_lanes(rdev, new_lane_width); 5856 lane_width = radeon_get_pcie_lanes(rdev); 5857 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5858 } 5859 } 5860 5861 void si_dpm_setup_asic(struct radeon_device *rdev) 5862 { 5863 int r; 5864 5865 r = si_mc_load_microcode(rdev); 5866 if (r) 5867 DRM_ERROR("Failed to load MC firmware!\n"); 5868 rv770_get_memory_type(rdev); 5869 si_read_clock_registers(rdev); 5870 si_enable_acpi_power_management(rdev); 5871 } 5872 5873 static int si_thermal_enable_alert(struct radeon_device *rdev, 5874 bool enable) 5875 { 5876 u32 thermal_int = RREG32(CG_THERMAL_INT); 5877 5878 if (enable) { 5879 PPSMC_Result result; 5880 5881 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5882 WREG32(CG_THERMAL_INT, thermal_int); 5883 rdev->irq.dpm_thermal = false; 5884 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5885 if (result != PPSMC_Result_OK) { 5886 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5887 return -EINVAL; 5888 } 5889 } else { 5890 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5891 WREG32(CG_THERMAL_INT, thermal_int); 5892 rdev->irq.dpm_thermal = true; 5893 } 5894 5895 return 0; 5896 } 5897 5898 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5899 int min_temp, int max_temp) 5900 { 5901 int low_temp = 0 * 1000; 5902 int high_temp = 255 * 1000; 5903 5904 if (low_temp < min_temp) 5905 low_temp = min_temp; 5906 if (high_temp > max_temp) 5907 high_temp = max_temp; 5908 if (high_temp < low_temp) { 5909 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5910 return -EINVAL; 5911 } 5912 5913 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5914 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5915 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5916 5917 rdev->pm.dpm.thermal.min_temp = low_temp; 5918 rdev->pm.dpm.thermal.max_temp = high_temp; 5919 5920 return 0; 5921 } 5922 5923 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 5924 { 5925 struct si_power_info *si_pi = si_get_pi(rdev); 5926 u32 tmp; 5927 5928 if (si_pi->fan_ctrl_is_in_default_mode) { 5929 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 5930 si_pi->fan_ctrl_default_mode = tmp; 5931 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 5932 si_pi->t_min = tmp; 5933 si_pi->fan_ctrl_is_in_default_mode = false; 5934 } 5935 5936 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 5937 tmp |= TMIN(0); 5938 WREG32(CG_FDO_CTRL2, tmp); 5939 5940 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 5941 tmp |= FDO_PWM_MODE(mode); 5942 WREG32(CG_FDO_CTRL2, tmp); 5943 } 5944 5945 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 5946 { 5947 struct si_power_info *si_pi = si_get_pi(rdev); 5948 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 5949 u32 duty100; 5950 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 5951 u16 fdo_min, slope1, slope2; 5952 u32 reference_clock, tmp; 5953 int ret; 5954 u64 tmp64; 5955 5956 if (!si_pi->fan_table_start) { 5957 rdev->pm.dpm.fan.ucode_fan_control = false; 5958 return 0; 5959 } 5960 5961 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 5962 5963 if (duty100 == 0) { 5964 rdev->pm.dpm.fan.ucode_fan_control = false; 5965 return 0; 5966 } 5967 5968 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 5969 do_div(tmp64, 10000); 5970 fdo_min = (u16)tmp64; 5971 5972 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 5973 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 5974 5975 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 5976 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 5977 5978 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 5979 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 5980 5981 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 5982 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 5983 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 5984 5985 fan_table.slope1 = cpu_to_be16(slope1); 5986 fan_table.slope2 = cpu_to_be16(slope2); 5987 5988 fan_table.fdo_min = cpu_to_be16(fdo_min); 5989 5990 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 5991 5992 fan_table.hys_up = cpu_to_be16(1); 5993 5994 fan_table.hys_slope = cpu_to_be16(1); 5995 5996 fan_table.temp_resp_lim = cpu_to_be16(5); 5997 5998 reference_clock = radeon_get_xclk(rdev); 5999 6000 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6001 reference_clock) / 1600); 6002 6003 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6004 6005 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6006 fan_table.temp_src = (uint8_t)tmp; 6007 6008 ret = si_copy_bytes_to_smc(rdev, 6009 si_pi->fan_table_start, 6010 (u8 *)(&fan_table), 6011 sizeof(fan_table), 6012 si_pi->sram_end); 6013 6014 if (ret) { 6015 DRM_ERROR("Failed to load fan table to the SMC."); 6016 rdev->pm.dpm.fan.ucode_fan_control = false; 6017 } 6018 6019 return 0; 6020 } 6021 6022 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6023 { 6024 struct si_power_info *si_pi = si_get_pi(rdev); 6025 PPSMC_Result ret; 6026 6027 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6028 if (ret == PPSMC_Result_OK) { 6029 si_pi->fan_is_controlled_by_smc = true; 6030 return 0; 6031 } else { 6032 return -EINVAL; 6033 } 6034 } 6035 6036 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6037 { 6038 struct si_power_info *si_pi = si_get_pi(rdev); 6039 PPSMC_Result ret; 6040 6041 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6042 6043 if (ret == PPSMC_Result_OK) { 6044 si_pi->fan_is_controlled_by_smc = false; 6045 return 0; 6046 } else { 6047 return -EINVAL; 6048 } 6049 } 6050 6051 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6052 u32 *speed) 6053 { 6054 u32 duty, duty100; 6055 u64 tmp64; 6056 6057 if (rdev->pm.no_fan) 6058 return -ENOENT; 6059 6060 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6061 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6062 6063 if (duty100 == 0) 6064 return -EINVAL; 6065 6066 tmp64 = (u64)duty * 100; 6067 do_div(tmp64, duty100); 6068 *speed = (u32)tmp64; 6069 6070 if (*speed > 100) 6071 *speed = 100; 6072 6073 return 0; 6074 } 6075 6076 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6077 u32 speed) 6078 { 6079 struct si_power_info *si_pi = si_get_pi(rdev); 6080 u32 tmp; 6081 u32 duty, duty100; 6082 u64 tmp64; 6083 6084 if (rdev->pm.no_fan) 6085 return -ENOENT; 6086 6087 if (si_pi->fan_is_controlled_by_smc) 6088 return -EINVAL; 6089 6090 if (speed > 100) 6091 return -EINVAL; 6092 6093 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6094 6095 if (duty100 == 0) 6096 return -EINVAL; 6097 6098 tmp64 = (u64)speed * duty100; 6099 do_div(tmp64, 100); 6100 duty = (u32)tmp64; 6101 6102 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6103 tmp |= FDO_STATIC_DUTY(duty); 6104 WREG32(CG_FDO_CTRL0, tmp); 6105 6106 return 0; 6107 } 6108 6109 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6110 { 6111 if (mode) { 6112 /* stop auto-manage */ 6113 if (rdev->pm.dpm.fan.ucode_fan_control) 6114 si_fan_ctrl_stop_smc_fan_control(rdev); 6115 si_fan_ctrl_set_static_mode(rdev, mode); 6116 } else { 6117 /* restart auto-manage */ 6118 if (rdev->pm.dpm.fan.ucode_fan_control) 6119 si_thermal_start_smc_fan_control(rdev); 6120 else 6121 si_fan_ctrl_set_default_mode(rdev); 6122 } 6123 } 6124 6125 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6126 { 6127 struct si_power_info *si_pi = si_get_pi(rdev); 6128 u32 tmp; 6129 6130 if (si_pi->fan_is_controlled_by_smc) 6131 return 0; 6132 6133 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6134 return (tmp >> FDO_PWM_MODE_SHIFT); 6135 } 6136 6137 #if 0 6138 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6139 u32 *speed) 6140 { 6141 u32 tach_period; 6142 u32 xclk = radeon_get_xclk(rdev); 6143 6144 if (rdev->pm.no_fan) 6145 return -ENOENT; 6146 6147 if (rdev->pm.fan_pulses_per_revolution == 0) 6148 return -ENOENT; 6149 6150 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6151 if (tach_period == 0) 6152 return -ENOENT; 6153 6154 *speed = 60 * xclk * 10000 / tach_period; 6155 6156 return 0; 6157 } 6158 6159 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6160 u32 speed) 6161 { 6162 u32 tach_period, tmp; 6163 u32 xclk = radeon_get_xclk(rdev); 6164 6165 if (rdev->pm.no_fan) 6166 return -ENOENT; 6167 6168 if (rdev->pm.fan_pulses_per_revolution == 0) 6169 return -ENOENT; 6170 6171 if ((speed < rdev->pm.fan_min_rpm) || 6172 (speed > rdev->pm.fan_max_rpm)) 6173 return -EINVAL; 6174 6175 if (rdev->pm.dpm.fan.ucode_fan_control) 6176 si_fan_ctrl_stop_smc_fan_control(rdev); 6177 6178 tach_period = 60 * xclk * 10000 / (8 * speed); 6179 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6180 tmp |= TARGET_PERIOD(tach_period); 6181 WREG32(CG_TACH_CTRL, tmp); 6182 6183 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6184 6185 return 0; 6186 } 6187 #endif 6188 6189 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6190 { 6191 struct si_power_info *si_pi = si_get_pi(rdev); 6192 u32 tmp; 6193 6194 if (!si_pi->fan_ctrl_is_in_default_mode) { 6195 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6196 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6197 WREG32(CG_FDO_CTRL2, tmp); 6198 6199 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6200 tmp |= TMIN(si_pi->t_min); 6201 WREG32(CG_FDO_CTRL2, tmp); 6202 si_pi->fan_ctrl_is_in_default_mode = true; 6203 } 6204 } 6205 6206 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6207 { 6208 if (rdev->pm.dpm.fan.ucode_fan_control) { 6209 si_fan_ctrl_start_smc_fan_control(rdev); 6210 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6211 } 6212 } 6213 6214 static void si_thermal_initialize(struct radeon_device *rdev) 6215 { 6216 u32 tmp; 6217 6218 if (rdev->pm.fan_pulses_per_revolution) { 6219 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6220 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6221 WREG32(CG_TACH_CTRL, tmp); 6222 } 6223 6224 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6225 tmp |= TACH_PWM_RESP_RATE(0x28); 6226 WREG32(CG_FDO_CTRL2, tmp); 6227 } 6228 6229 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6230 { 6231 int ret; 6232 6233 si_thermal_initialize(rdev); 6234 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6235 if (ret) 6236 return ret; 6237 ret = si_thermal_enable_alert(rdev, true); 6238 if (ret) 6239 return ret; 6240 if (rdev->pm.dpm.fan.ucode_fan_control) { 6241 ret = si_halt_smc(rdev); 6242 if (ret) 6243 return ret; 6244 ret = si_thermal_setup_fan_table(rdev); 6245 if (ret) 6246 return ret; 6247 ret = si_resume_smc(rdev); 6248 if (ret) 6249 return ret; 6250 si_thermal_start_smc_fan_control(rdev); 6251 } 6252 6253 return 0; 6254 } 6255 6256 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6257 { 6258 if (!rdev->pm.no_fan) { 6259 si_fan_ctrl_set_default_mode(rdev); 6260 si_fan_ctrl_stop_smc_fan_control(rdev); 6261 } 6262 } 6263 6264 int si_dpm_enable(struct radeon_device *rdev) 6265 { 6266 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6267 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6268 struct si_power_info *si_pi = si_get_pi(rdev); 6269 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6270 int ret; 6271 6272 if (si_is_smc_running(rdev)) 6273 return -EINVAL; 6274 if (pi->voltage_control || si_pi->voltage_control_svi2) 6275 si_enable_voltage_control(rdev, true); 6276 if (pi->mvdd_control) 6277 si_get_mvdd_configuration(rdev); 6278 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6279 ret = si_construct_voltage_tables(rdev); 6280 if (ret) { 6281 DRM_ERROR("si_construct_voltage_tables failed\n"); 6282 return ret; 6283 } 6284 } 6285 if (eg_pi->dynamic_ac_timing) { 6286 ret = si_initialize_mc_reg_table(rdev); 6287 if (ret) 6288 eg_pi->dynamic_ac_timing = false; 6289 } 6290 if (pi->dynamic_ss) 6291 si_enable_spread_spectrum(rdev, true); 6292 if (pi->thermal_protection) 6293 si_enable_thermal_protection(rdev, true); 6294 si_setup_bsp(rdev); 6295 si_program_git(rdev); 6296 si_program_tp(rdev); 6297 si_program_tpp(rdev); 6298 si_program_sstp(rdev); 6299 si_enable_display_gap(rdev); 6300 si_program_vc(rdev); 6301 ret = si_upload_firmware(rdev); 6302 if (ret) { 6303 DRM_ERROR("si_upload_firmware failed\n"); 6304 return ret; 6305 } 6306 ret = si_process_firmware_header(rdev); 6307 if (ret) { 6308 DRM_ERROR("si_process_firmware_header failed\n"); 6309 return ret; 6310 } 6311 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6312 if (ret) { 6313 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6314 return ret; 6315 } 6316 ret = si_init_smc_table(rdev); 6317 if (ret) { 6318 DRM_ERROR("si_init_smc_table failed\n"); 6319 return ret; 6320 } 6321 ret = si_init_smc_spll_table(rdev); 6322 if (ret) { 6323 DRM_ERROR("si_init_smc_spll_table failed\n"); 6324 return ret; 6325 } 6326 ret = si_init_arb_table_index(rdev); 6327 if (ret) { 6328 DRM_ERROR("si_init_arb_table_index failed\n"); 6329 return ret; 6330 } 6331 if (eg_pi->dynamic_ac_timing) { 6332 ret = si_populate_mc_reg_table(rdev, boot_ps); 6333 if (ret) { 6334 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6335 return ret; 6336 } 6337 } 6338 ret = si_initialize_smc_cac_tables(rdev); 6339 if (ret) { 6340 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6341 return ret; 6342 } 6343 ret = si_initialize_hardware_cac_manager(rdev); 6344 if (ret) { 6345 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6346 return ret; 6347 } 6348 ret = si_initialize_smc_dte_tables(rdev); 6349 if (ret) { 6350 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6351 return ret; 6352 } 6353 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6354 if (ret) { 6355 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6356 return ret; 6357 } 6358 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6359 if (ret) { 6360 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6361 return ret; 6362 } 6363 si_program_response_times(rdev); 6364 si_program_ds_registers(rdev); 6365 si_dpm_start_smc(rdev); 6366 ret = si_notify_smc_display_change(rdev, false); 6367 if (ret) { 6368 DRM_ERROR("si_notify_smc_display_change failed\n"); 6369 return ret; 6370 } 6371 si_enable_sclk_control(rdev, true); 6372 si_start_dpm(rdev); 6373 6374 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6375 6376 si_thermal_start_thermal_controller(rdev); 6377 6378 ni_update_current_ps(rdev, boot_ps); 6379 6380 return 0; 6381 } 6382 6383 static int si_set_temperature_range(struct radeon_device *rdev) 6384 { 6385 int ret; 6386 6387 ret = si_thermal_enable_alert(rdev, false); 6388 if (ret) 6389 return ret; 6390 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6391 if (ret) 6392 return ret; 6393 ret = si_thermal_enable_alert(rdev, true); 6394 if (ret) 6395 return ret; 6396 6397 return ret; 6398 } 6399 6400 int si_dpm_late_enable(struct radeon_device *rdev) 6401 { 6402 int ret; 6403 6404 ret = si_set_temperature_range(rdev); 6405 if (ret) 6406 return ret; 6407 6408 return ret; 6409 } 6410 6411 void si_dpm_disable(struct radeon_device *rdev) 6412 { 6413 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6414 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6415 6416 if (!si_is_smc_running(rdev)) 6417 return; 6418 si_thermal_stop_thermal_controller(rdev); 6419 si_disable_ulv(rdev); 6420 si_clear_vc(rdev); 6421 if (pi->thermal_protection) 6422 si_enable_thermal_protection(rdev, false); 6423 si_enable_power_containment(rdev, boot_ps, false); 6424 si_enable_smc_cac(rdev, boot_ps, false); 6425 si_enable_spread_spectrum(rdev, false); 6426 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6427 si_stop_dpm(rdev); 6428 si_reset_to_default(rdev); 6429 si_dpm_stop_smc(rdev); 6430 si_force_switch_to_arb_f0(rdev); 6431 6432 ni_update_current_ps(rdev, boot_ps); 6433 } 6434 6435 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6436 { 6437 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6438 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6439 struct radeon_ps *new_ps = &requested_ps; 6440 6441 ni_update_requested_ps(rdev, new_ps); 6442 6443 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6444 6445 return 0; 6446 } 6447 6448 static int si_power_control_set_level(struct radeon_device *rdev) 6449 { 6450 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6451 int ret; 6452 6453 ret = si_restrict_performance_levels_before_switch(rdev); 6454 if (ret) 6455 return ret; 6456 ret = si_halt_smc(rdev); 6457 if (ret) 6458 return ret; 6459 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6460 if (ret) 6461 return ret; 6462 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6463 if (ret) 6464 return ret; 6465 ret = si_resume_smc(rdev); 6466 if (ret) 6467 return ret; 6468 ret = si_set_sw_state(rdev); 6469 if (ret) 6470 return ret; 6471 return 0; 6472 } 6473 6474 int si_dpm_set_power_state(struct radeon_device *rdev) 6475 { 6476 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6477 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6478 struct radeon_ps *old_ps = &eg_pi->current_rps; 6479 int ret; 6480 6481 ret = si_disable_ulv(rdev); 6482 if (ret) { 6483 DRM_ERROR("si_disable_ulv failed\n"); 6484 return ret; 6485 } 6486 ret = si_restrict_performance_levels_before_switch(rdev); 6487 if (ret) { 6488 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6489 return ret; 6490 } 6491 if (eg_pi->pcie_performance_request) 6492 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6493 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6494 ret = si_enable_power_containment(rdev, new_ps, false); 6495 if (ret) { 6496 DRM_ERROR("si_enable_power_containment failed\n"); 6497 return ret; 6498 } 6499 ret = si_enable_smc_cac(rdev, new_ps, false); 6500 if (ret) { 6501 DRM_ERROR("si_enable_smc_cac failed\n"); 6502 return ret; 6503 } 6504 ret = si_halt_smc(rdev); 6505 if (ret) { 6506 DRM_ERROR("si_halt_smc failed\n"); 6507 return ret; 6508 } 6509 ret = si_upload_sw_state(rdev, new_ps); 6510 if (ret) { 6511 DRM_ERROR("si_upload_sw_state failed\n"); 6512 return ret; 6513 } 6514 ret = si_upload_smc_data(rdev); 6515 if (ret) { 6516 DRM_ERROR("si_upload_smc_data failed\n"); 6517 return ret; 6518 } 6519 ret = si_upload_ulv_state(rdev); 6520 if (ret) { 6521 DRM_ERROR("si_upload_ulv_state failed\n"); 6522 return ret; 6523 } 6524 if (eg_pi->dynamic_ac_timing) { 6525 ret = si_upload_mc_reg_table(rdev, new_ps); 6526 if (ret) { 6527 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6528 return ret; 6529 } 6530 } 6531 ret = si_program_memory_timing_parameters(rdev, new_ps); 6532 if (ret) { 6533 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6534 return ret; 6535 } 6536 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6537 6538 ret = si_resume_smc(rdev); 6539 if (ret) { 6540 DRM_ERROR("si_resume_smc failed\n"); 6541 return ret; 6542 } 6543 ret = si_set_sw_state(rdev); 6544 if (ret) { 6545 DRM_ERROR("si_set_sw_state failed\n"); 6546 return ret; 6547 } 6548 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6549 if (eg_pi->pcie_performance_request) 6550 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6551 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6552 if (ret) { 6553 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6554 return ret; 6555 } 6556 ret = si_enable_smc_cac(rdev, new_ps, true); 6557 if (ret) { 6558 DRM_ERROR("si_enable_smc_cac failed\n"); 6559 return ret; 6560 } 6561 ret = si_enable_power_containment(rdev, new_ps, true); 6562 if (ret) { 6563 DRM_ERROR("si_enable_power_containment failed\n"); 6564 return ret; 6565 } 6566 6567 ret = si_power_control_set_level(rdev); 6568 if (ret) { 6569 DRM_ERROR("si_power_control_set_level failed\n"); 6570 return ret; 6571 } 6572 6573 return 0; 6574 } 6575 6576 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6577 { 6578 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6579 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6580 6581 ni_update_current_ps(rdev, new_ps); 6582 } 6583 6584 #if 0 6585 void si_dpm_reset_asic(struct radeon_device *rdev) 6586 { 6587 si_restrict_performance_levels_before_switch(rdev); 6588 si_disable_ulv(rdev); 6589 si_set_boot_state(rdev); 6590 } 6591 #endif 6592 6593 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6594 { 6595 si_program_display_gap(rdev); 6596 } 6597 6598 union power_info { 6599 struct _ATOM_POWERPLAY_INFO info; 6600 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6601 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6602 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6603 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6604 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6605 }; 6606 6607 union pplib_clock_info { 6608 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6609 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6610 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6611 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6612 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6613 }; 6614 6615 union pplib_power_state { 6616 struct _ATOM_PPLIB_STATE v1; 6617 struct _ATOM_PPLIB_STATE_V2 v2; 6618 }; 6619 6620 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6621 struct radeon_ps *rps, 6622 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6623 u8 table_rev) 6624 { 6625 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6626 rps->class = le16_to_cpu(non_clock_info->usClassification); 6627 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6628 6629 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6630 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6631 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6632 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6633 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6634 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6635 } else { 6636 rps->vclk = 0; 6637 rps->dclk = 0; 6638 } 6639 6640 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6641 rdev->pm.dpm.boot_ps = rps; 6642 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6643 rdev->pm.dpm.uvd_ps = rps; 6644 } 6645 6646 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6647 struct radeon_ps *rps, int index, 6648 union pplib_clock_info *clock_info) 6649 { 6650 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6651 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6652 struct si_power_info *si_pi = si_get_pi(rdev); 6653 struct ni_ps *ps = ni_get_ps(rps); 6654 u16 leakage_voltage; 6655 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6656 int ret; 6657 6658 ps->performance_level_count = index + 1; 6659 6660 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6661 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6662 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6663 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6664 6665 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6666 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6667 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6668 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6669 si_pi->sys_pcie_mask, 6670 si_pi->boot_pcie_gen, 6671 clock_info->si.ucPCIEGen); 6672 6673 /* patch up vddc if necessary */ 6674 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6675 &leakage_voltage); 6676 if (ret == 0) 6677 pl->vddc = leakage_voltage; 6678 6679 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6680 pi->acpi_vddc = pl->vddc; 6681 eg_pi->acpi_vddci = pl->vddci; 6682 si_pi->acpi_pcie_gen = pl->pcie_gen; 6683 } 6684 6685 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6686 index == 0) { 6687 /* XXX disable for A0 tahiti */ 6688 si_pi->ulv.supported = false; 6689 si_pi->ulv.pl = *pl; 6690 si_pi->ulv.one_pcie_lane_in_ulv = false; 6691 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6692 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6693 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6694 } 6695 6696 if (pi->min_vddc_in_table > pl->vddc) 6697 pi->min_vddc_in_table = pl->vddc; 6698 6699 if (pi->max_vddc_in_table < pl->vddc) 6700 pi->max_vddc_in_table = pl->vddc; 6701 6702 /* patch up boot state */ 6703 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6704 u16 vddc, vddci, mvdd; 6705 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6706 pl->mclk = rdev->clock.default_mclk; 6707 pl->sclk = rdev->clock.default_sclk; 6708 pl->vddc = vddc; 6709 pl->vddci = vddci; 6710 si_pi->mvdd_bootup_value = mvdd; 6711 } 6712 6713 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6714 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6715 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6716 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6717 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6718 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6719 } 6720 } 6721 6722 static int si_parse_power_table(struct radeon_device *rdev) 6723 { 6724 struct radeon_mode_info *mode_info = &rdev->mode_info; 6725 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6726 union pplib_power_state *power_state; 6727 int i, j, k, non_clock_array_index, clock_array_index; 6728 union pplib_clock_info *clock_info; 6729 struct _StateArray *state_array; 6730 struct _ClockInfoArray *clock_info_array; 6731 struct _NonClockInfoArray *non_clock_info_array; 6732 union power_info *power_info; 6733 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6734 u16 data_offset; 6735 u8 frev, crev; 6736 u8 *power_state_offset; 6737 struct ni_ps *ps; 6738 6739 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6740 &frev, &crev, &data_offset)) 6741 return -EINVAL; 6742 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6743 6744 state_array = (struct _StateArray *) 6745 (mode_info->atom_context->bios + data_offset + 6746 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6747 clock_info_array = (struct _ClockInfoArray *) 6748 (mode_info->atom_context->bios + data_offset + 6749 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6750 non_clock_info_array = (struct _NonClockInfoArray *) 6751 (mode_info->atom_context->bios + data_offset + 6752 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6753 6754 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6755 state_array->ucNumEntries, GFP_KERNEL); 6756 if (!rdev->pm.dpm.ps) 6757 return -ENOMEM; 6758 power_state_offset = (u8 *)state_array->states; 6759 for (i = 0; i < state_array->ucNumEntries; i++) { 6760 u8 *idx; 6761 power_state = (union pplib_power_state *)power_state_offset; 6762 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6763 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6764 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6765 if (!rdev->pm.power_state[i].clock_info) 6766 return -EINVAL; 6767 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6768 if (ps == NULL) { 6769 kfree(rdev->pm.dpm.ps); 6770 return -ENOMEM; 6771 } 6772 rdev->pm.dpm.ps[i].ps_priv = ps; 6773 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6774 non_clock_info, 6775 non_clock_info_array->ucEntrySize); 6776 k = 0; 6777 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6778 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6779 clock_array_index = idx[j]; 6780 if (clock_array_index >= clock_info_array->ucNumEntries) 6781 continue; 6782 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6783 break; 6784 clock_info = (union pplib_clock_info *) 6785 ((u8 *)&clock_info_array->clockInfo[0] + 6786 (clock_array_index * clock_info_array->ucEntrySize)); 6787 si_parse_pplib_clock_info(rdev, 6788 &rdev->pm.dpm.ps[i], k, 6789 clock_info); 6790 k++; 6791 } 6792 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6793 } 6794 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6795 return 0; 6796 } 6797 6798 int si_dpm_init(struct radeon_device *rdev) 6799 { 6800 struct rv7xx_power_info *pi; 6801 struct evergreen_power_info *eg_pi; 6802 struct ni_power_info *ni_pi; 6803 struct si_power_info *si_pi; 6804 struct atom_clock_dividers dividers; 6805 int ret; 6806 u32 mask; 6807 6808 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6809 if (si_pi == NULL) 6810 return -ENOMEM; 6811 rdev->pm.dpm.priv = si_pi; 6812 ni_pi = &si_pi->ni; 6813 eg_pi = &ni_pi->eg; 6814 pi = &eg_pi->rv7xx; 6815 6816 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6817 if (ret) 6818 si_pi->sys_pcie_mask = 0; 6819 else 6820 si_pi->sys_pcie_mask = mask; 6821 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6822 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6823 6824 si_set_max_cu_value(rdev); 6825 6826 rv770_get_max_vddc(rdev); 6827 si_get_leakage_vddc(rdev); 6828 si_patch_dependency_tables_based_on_leakage(rdev); 6829 6830 pi->acpi_vddc = 0; 6831 eg_pi->acpi_vddci = 0; 6832 pi->min_vddc_in_table = 0; 6833 pi->max_vddc_in_table = 0; 6834 6835 ret = r600_get_platform_caps(rdev); 6836 if (ret) 6837 return ret; 6838 6839 ret = si_parse_power_table(rdev); 6840 if (ret) 6841 return ret; 6842 ret = r600_parse_extended_power_table(rdev); 6843 if (ret) 6844 return ret; 6845 6846 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6847 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6848 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6849 r600_free_extended_power_table(rdev); 6850 return -ENOMEM; 6851 } 6852 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6853 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6854 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6855 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6856 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6857 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6858 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6859 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6860 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6861 6862 if (rdev->pm.dpm.voltage_response_time == 0) 6863 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6864 if (rdev->pm.dpm.backbias_response_time == 0) 6865 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6866 6867 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6868 0, false, ÷rs); 6869 if (ret) 6870 pi->ref_div = dividers.ref_div + 1; 6871 else 6872 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6873 6874 eg_pi->smu_uvd_hs = false; 6875 6876 pi->mclk_strobe_mode_threshold = 40000; 6877 if (si_is_special_1gb_platform(rdev)) 6878 pi->mclk_stutter_mode_threshold = 0; 6879 else 6880 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6881 pi->mclk_edc_enable_threshold = 40000; 6882 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6883 6884 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6885 6886 pi->voltage_control = 6887 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6888 VOLTAGE_OBJ_GPIO_LUT); 6889 if (!pi->voltage_control) { 6890 si_pi->voltage_control_svi2 = 6891 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6892 VOLTAGE_OBJ_SVID2); 6893 if (si_pi->voltage_control_svi2) 6894 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6895 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6896 } 6897 6898 pi->mvdd_control = 6899 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6900 VOLTAGE_OBJ_GPIO_LUT); 6901 6902 eg_pi->vddci_control = 6903 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6904 VOLTAGE_OBJ_GPIO_LUT); 6905 if (!eg_pi->vddci_control) 6906 si_pi->vddci_control_svi2 = 6907 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6908 VOLTAGE_OBJ_SVID2); 6909 6910 si_pi->vddc_phase_shed_control = 6911 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6912 VOLTAGE_OBJ_PHASE_LUT); 6913 6914 rv770_get_engine_memory_ss(rdev); 6915 6916 pi->asi = RV770_ASI_DFLT; 6917 pi->pasi = CYPRESS_HASI_DFLT; 6918 pi->vrc = SISLANDS_VRC_DFLT; 6919 6920 pi->gfx_clock_gating = true; 6921 6922 eg_pi->sclk_deep_sleep = true; 6923 si_pi->sclk_deep_sleep_above_low = false; 6924 6925 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6926 pi->thermal_protection = true; 6927 else 6928 pi->thermal_protection = false; 6929 6930 eg_pi->dynamic_ac_timing = true; 6931 6932 eg_pi->light_sleep = true; 6933 #if defined(CONFIG_ACPI) 6934 eg_pi->pcie_performance_request = 6935 radeon_acpi_is_pcie_performance_request_supported(rdev); 6936 #else 6937 eg_pi->pcie_performance_request = false; 6938 #endif 6939 6940 si_pi->sram_end = SMC_RAM_END; 6941 6942 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6943 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6944 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6945 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6946 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6947 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6948 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6949 6950 si_initialize_powertune_defaults(rdev); 6951 6952 /* make sure dc limits are valid */ 6953 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6954 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6955 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6956 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6957 6958 si_pi->fan_ctrl_is_in_default_mode = true; 6959 6960 return 0; 6961 } 6962 6963 void si_dpm_fini(struct radeon_device *rdev) 6964 { 6965 int i; 6966 6967 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6968 kfree(rdev->pm.dpm.ps[i].ps_priv); 6969 } 6970 kfree(rdev->pm.dpm.ps); 6971 kfree(rdev->pm.dpm.priv); 6972 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6973 r600_free_extended_power_table(rdev); 6974 } 6975 6976 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6977 struct seq_file *m) 6978 { 6979 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6980 struct radeon_ps *rps = &eg_pi->current_rps; 6981 struct ni_ps *ps = ni_get_ps(rps); 6982 struct rv7xx_pl *pl; 6983 u32 current_index = 6984 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6985 CURRENT_STATE_INDEX_SHIFT; 6986 6987 if (current_index >= ps->performance_level_count) { 6988 seq_printf(m, "invalid dpm profile %d\n", current_index); 6989 } else { 6990 pl = &ps->performance_levels[current_index]; 6991 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6992 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6993 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6994 } 6995 } 6996