1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "drmP.h" 25 #include "radeon.h" 26 #include "sid.h" 27 #include "r600_dpm.h" 28 #include "si_dpm.h" 29 #include "atom.h" 30 #include <linux/math64.h> 31 #include <linux/seq_file.h> 32 33 #define MC_CG_ARB_FREQ_F0 0x0a 34 #define MC_CG_ARB_FREQ_F1 0x0b 35 #define MC_CG_ARB_FREQ_F2 0x0c 36 #define MC_CG_ARB_FREQ_F3 0x0d 37 38 #define SMC_RAM_END 0x20000 39 40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 41 42 static const struct si_cac_config_reg cac_weights_tahiti[] = 43 { 44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 104 { 0xFFFFFFFF } 105 }; 106 107 static const struct si_cac_config_reg lcac_tahiti[] = 108 { 109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0xFFFFFFFF } 196 197 }; 198 199 static const struct si_cac_config_reg cac_override_tahiti[] = 200 { 201 { 0xFFFFFFFF } 202 }; 203 204 static const struct si_powertune_data powertune_data_tahiti = 205 { 206 ((1 << 16) | 27027), 207 6, 208 0, 209 4, 210 95, 211 { 212 0UL, 213 0UL, 214 4521550UL, 215 309631529UL, 216 -1270850L, 217 4513710L, 218 40 219 }, 220 595000000UL, 221 12, 222 { 223 0, 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0 231 }, 232 true 233 }; 234 235 static const struct si_dte_data dte_data_tahiti = 236 { 237 { 1159409, 0, 0, 0, 0 }, 238 { 777, 0, 0, 0, 0 }, 239 2, 240 54000, 241 127000, 242 25, 243 2, 244 10, 245 13, 246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 249 85, 250 false 251 }; 252 253 static const struct si_dte_data dte_data_tahiti_le = 254 { 255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 257 0x5, 258 0xAFC8, 259 0x64, 260 0x32, 261 1, 262 0, 263 0x10, 264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 267 85, 268 true 269 }; 270 271 static const struct si_dte_data dte_data_tahiti_pro = 272 { 273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 274 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 275 5, 276 45000, 277 100, 278 0xA, 279 1, 280 0, 281 0x10, 282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 285 90, 286 true 287 }; 288 289 static const struct si_dte_data dte_data_new_zealand = 290 { 291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 293 0x5, 294 0xAFC8, 295 0x69, 296 0x32, 297 1, 298 0, 299 0x10, 300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 303 85, 304 true 305 }; 306 307 static const struct si_dte_data dte_data_aruba_pro = 308 { 309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 310 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 311 5, 312 45000, 313 100, 314 0xA, 315 1, 316 0, 317 0x10, 318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 321 90, 322 true 323 }; 324 325 static const struct si_dte_data dte_data_malta = 326 { 327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 328 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 329 5, 330 45000, 331 100, 332 0xA, 333 1, 334 0, 335 0x10, 336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 339 90, 340 true 341 }; 342 343 struct si_cac_config_reg cac_weights_pitcairn[] = 344 { 345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 405 { 0xFFFFFFFF } 406 }; 407 408 static const struct si_cac_config_reg lcac_pitcairn[] = 409 { 410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0xFFFFFFFF } 497 }; 498 499 static const struct si_cac_config_reg cac_override_pitcairn[] = 500 { 501 { 0xFFFFFFFF } 502 }; 503 504 static const struct si_powertune_data powertune_data_pitcairn = 505 { 506 ((1 << 16) | 27027), 507 5, 508 0, 509 6, 510 100, 511 { 512 51600000UL, 513 1800000UL, 514 7194395UL, 515 309631529UL, 516 -1270850L, 517 4513710L, 518 100 519 }, 520 117830498UL, 521 12, 522 { 523 0, 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0 531 }, 532 true 533 }; 534 535 static const struct si_dte_data dte_data_pitcairn = 536 { 537 { 0, 0, 0, 0, 0 }, 538 { 0, 0, 0, 0, 0 }, 539 0, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 0, 550 false 551 }; 552 553 static const struct si_dte_data dte_data_curacao_xt = 554 { 555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 556 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 557 5, 558 45000, 559 100, 560 0xA, 561 1, 562 0, 563 0x10, 564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 567 90, 568 true 569 }; 570 571 static const struct si_dte_data dte_data_curacao_pro = 572 { 573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 574 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 575 5, 576 45000, 577 100, 578 0xA, 579 1, 580 0, 581 0x10, 582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 585 90, 586 true 587 }; 588 589 static const struct si_dte_data dte_data_neptune_xt = 590 { 591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 592 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 593 5, 594 45000, 595 100, 596 0xA, 597 1, 598 0, 599 0x10, 600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 603 90, 604 true 605 }; 606 607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 608 { 609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 669 { 0xFFFFFFFF } 670 }; 671 672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 673 { 674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 734 { 0xFFFFFFFF } 735 }; 736 737 static const struct si_cac_config_reg cac_weights_heathrow[] = 738 { 739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 799 { 0xFFFFFFFF } 800 }; 801 802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 803 { 804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 864 { 0xFFFFFFFF } 865 }; 866 867 static const struct si_cac_config_reg cac_weights_cape_verde[] = 868 { 869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 929 { 0xFFFFFFFF } 930 }; 931 932 static const struct si_cac_config_reg lcac_cape_verde[] = 933 { 934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0xFFFFFFFF } 989 }; 990 991 static const struct si_cac_config_reg cac_override_cape_verde[] = 992 { 993 { 0xFFFFFFFF } 994 }; 995 996 static const struct si_powertune_data powertune_data_cape_verde = 997 { 998 ((1 << 16) | 0x6993), 999 5, 1000 0, 1001 7, 1002 105, 1003 { 1004 0UL, 1005 0UL, 1006 7194395UL, 1007 309631529UL, 1008 -1270850L, 1009 4513710L, 1010 100 1011 }, 1012 117830498UL, 1013 12, 1014 { 1015 0, 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0 1023 }, 1024 true 1025 }; 1026 1027 static const struct si_dte_data dte_data_cape_verde = 1028 { 1029 { 0, 0, 0, 0, 0 }, 1030 { 0, 0, 0, 0, 0 }, 1031 0, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 0, 1042 false 1043 }; 1044 1045 static const struct si_dte_data dte_data_venus_xtx = 1046 { 1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1049 5, 1050 55000, 1051 0x69, 1052 0xA, 1053 1, 1054 0, 1055 0x3, 1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 90, 1060 true 1061 }; 1062 1063 static const struct si_dte_data dte_data_venus_xt = 1064 { 1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1067 5, 1068 55000, 1069 0x69, 1070 0xA, 1071 1, 1072 0, 1073 0x3, 1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 90, 1078 true 1079 }; 1080 1081 static const struct si_dte_data dte_data_venus_pro = 1082 { 1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1085 5, 1086 55000, 1087 0x69, 1088 0xA, 1089 1, 1090 0, 1091 0x3, 1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 90, 1096 true 1097 }; 1098 1099 struct si_cac_config_reg cac_weights_oland[] = 1100 { 1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1161 { 0xFFFFFFFF } 1162 }; 1163 1164 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1165 { 1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1226 { 0xFFFFFFFF } 1227 }; 1228 1229 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1230 { 1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1291 { 0xFFFFFFFF } 1292 }; 1293 1294 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1295 { 1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1356 { 0xFFFFFFFF } 1357 }; 1358 1359 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1360 { 1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1421 { 0xFFFFFFFF } 1422 }; 1423 1424 static const struct si_cac_config_reg lcac_oland[] = 1425 { 1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0xFFFFFFFF } 1469 }; 1470 1471 static const struct si_cac_config_reg lcac_mars_pro[] = 1472 { 1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0xFFFFFFFF } 1516 }; 1517 1518 static const struct si_cac_config_reg cac_override_oland[] = 1519 { 1520 { 0xFFFFFFFF } 1521 }; 1522 1523 static const struct si_powertune_data powertune_data_oland = 1524 { 1525 ((1 << 16) | 0x6993), 1526 5, 1527 0, 1528 7, 1529 105, 1530 { 1531 0UL, 1532 0UL, 1533 7194395UL, 1534 309631529UL, 1535 -1270850L, 1536 4513710L, 1537 100 1538 }, 1539 117830498UL, 1540 12, 1541 { 1542 0, 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0 1550 }, 1551 true 1552 }; 1553 1554 static const struct si_powertune_data powertune_data_mars_pro = 1555 { 1556 ((1 << 16) | 0x6993), 1557 5, 1558 0, 1559 7, 1560 105, 1561 { 1562 0UL, 1563 0UL, 1564 7194395UL, 1565 309631529UL, 1566 -1270850L, 1567 4513710L, 1568 100 1569 }, 1570 117830498UL, 1571 12, 1572 { 1573 0, 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0 1581 }, 1582 true 1583 }; 1584 1585 static const struct si_dte_data dte_data_oland = 1586 { 1587 { 0, 0, 0, 0, 0 }, 1588 { 0, 0, 0, 0, 0 }, 1589 0, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 0, 1600 false 1601 }; 1602 1603 static const struct si_dte_data dte_data_mars_pro = 1604 { 1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1606 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1607 5, 1608 55000, 1609 105, 1610 0xA, 1611 1, 1612 0, 1613 0x10, 1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1617 90, 1618 true 1619 }; 1620 1621 static const struct si_dte_data dte_data_sun_xt = 1622 { 1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1624 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1625 5, 1626 55000, 1627 105, 1628 0xA, 1629 1, 1630 0, 1631 0x10, 1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1635 90, 1636 true 1637 }; 1638 1639 1640 static const struct si_cac_config_reg cac_weights_hainan[] = 1641 { 1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1702 { 0xFFFFFFFF } 1703 }; 1704 1705 static const struct si_powertune_data powertune_data_hainan = 1706 { 1707 ((1 << 16) | 0x6993), 1708 5, 1709 0, 1710 9, 1711 105, 1712 { 1713 0UL, 1714 0UL, 1715 7194395UL, 1716 309631529UL, 1717 -1270850L, 1718 4513710L, 1719 100 1720 }, 1721 117830498UL, 1722 12, 1723 { 1724 0, 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0 1732 }, 1733 true 1734 }; 1735 1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1740 1741 extern int si_mc_load_microcode(struct radeon_device *rdev); 1742 1743 static int si_populate_voltage_value(struct radeon_device *rdev, 1744 const struct atom_voltage_table *table, 1745 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1746 static int si_get_std_voltage_value(struct radeon_device *rdev, 1747 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1748 u16 *std_voltage); 1749 static int si_write_smc_soft_register(struct radeon_device *rdev, 1750 u16 reg_offset, u32 value); 1751 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1752 struct rv7xx_pl *pl, 1753 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1754 static int si_calculate_sclk_params(struct radeon_device *rdev, 1755 u32 engine_clock, 1756 SISLANDS_SMC_SCLK_VALUE *sclk); 1757 1758 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1759 { 1760 struct si_power_info *pi = rdev->pm.dpm.priv; 1761 1762 return pi; 1763 } 1764 1765 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1766 u16 v, s32 t, u32 ileakage, u32 *leakage) 1767 { 1768 s64 kt, kv, leakage_w, i_leakage, vddc; 1769 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1770 s64 tmp; 1771 1772 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1773 vddc = div64_s64(drm_int2fixp(v), 1000); 1774 temperature = div64_s64(drm_int2fixp(t), 1000); 1775 1776 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1777 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1778 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1779 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1780 t_ref = drm_int2fixp(coeff->t_ref); 1781 1782 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1783 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1784 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1785 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1786 1787 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1788 1789 *leakage = drm_fixp2int(leakage_w * 1000); 1790 } 1791 1792 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1793 const struct ni_leakage_coeffients *coeff, 1794 u16 v, 1795 s32 t, 1796 u32 i_leakage, 1797 u32 *leakage) 1798 { 1799 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1800 } 1801 1802 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1803 const u32 fixed_kt, u16 v, 1804 u32 ileakage, u32 *leakage) 1805 { 1806 s64 kt, kv, leakage_w, i_leakage, vddc; 1807 1808 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1809 vddc = div64_s64(drm_int2fixp(v), 1000); 1810 1811 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1812 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1813 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1814 1815 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1816 1817 *leakage = drm_fixp2int(leakage_w * 1000); 1818 } 1819 1820 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1821 const struct ni_leakage_coeffients *coeff, 1822 const u32 fixed_kt, 1823 u16 v, 1824 u32 i_leakage, 1825 u32 *leakage) 1826 { 1827 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1828 } 1829 1830 1831 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1832 struct si_dte_data *dte_data) 1833 { 1834 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1835 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1836 u32 k = dte_data->k; 1837 u32 t_max = dte_data->max_t; 1838 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1839 u32 t_0 = dte_data->t0; 1840 u32 i; 1841 1842 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1843 dte_data->tdep_count = 3; 1844 1845 for (i = 0; i < k; i++) { 1846 dte_data->r[i] = 1847 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1848 (p_limit2 * (u32)100); 1849 } 1850 1851 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1852 1853 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1854 dte_data->tdep_r[i] = dte_data->r[4]; 1855 } 1856 } else { 1857 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1858 } 1859 } 1860 1861 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1862 { 1863 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1864 struct si_power_info *si_pi = si_get_pi(rdev); 1865 bool update_dte_from_pl2 = false; 1866 1867 if (rdev->family == CHIP_TAHITI) { 1868 si_pi->cac_weights = cac_weights_tahiti; 1869 si_pi->lcac_config = lcac_tahiti; 1870 si_pi->cac_override = cac_override_tahiti; 1871 si_pi->powertune_data = &powertune_data_tahiti; 1872 si_pi->dte_data = dte_data_tahiti; 1873 1874 switch (rdev->pdev->device) { 1875 case 0x6798: 1876 si_pi->dte_data.enable_dte_by_default = true; 1877 break; 1878 case 0x6799: 1879 si_pi->dte_data = dte_data_new_zealand; 1880 break; 1881 case 0x6790: 1882 case 0x6791: 1883 case 0x6792: 1884 case 0x679E: 1885 si_pi->dte_data = dte_data_aruba_pro; 1886 update_dte_from_pl2 = true; 1887 break; 1888 case 0x679B: 1889 si_pi->dte_data = dte_data_malta; 1890 update_dte_from_pl2 = true; 1891 break; 1892 case 0x679A: 1893 si_pi->dte_data = dte_data_tahiti_pro; 1894 update_dte_from_pl2 = true; 1895 break; 1896 default: 1897 if (si_pi->dte_data.enable_dte_by_default == true) 1898 DRM_ERROR("DTE is not enabled!\n"); 1899 break; 1900 } 1901 } else if (rdev->family == CHIP_PITCAIRN) { 1902 switch (rdev->pdev->device) { 1903 case 0x6810: 1904 case 0x6818: 1905 si_pi->cac_weights = cac_weights_pitcairn; 1906 si_pi->lcac_config = lcac_pitcairn; 1907 si_pi->cac_override = cac_override_pitcairn; 1908 si_pi->powertune_data = &powertune_data_pitcairn; 1909 si_pi->dte_data = dte_data_curacao_xt; 1910 update_dte_from_pl2 = true; 1911 break; 1912 case 0x6819: 1913 case 0x6811: 1914 si_pi->cac_weights = cac_weights_pitcairn; 1915 si_pi->lcac_config = lcac_pitcairn; 1916 si_pi->cac_override = cac_override_pitcairn; 1917 si_pi->powertune_data = &powertune_data_pitcairn; 1918 si_pi->dte_data = dte_data_curacao_pro; 1919 update_dte_from_pl2 = true; 1920 break; 1921 case 0x6800: 1922 case 0x6806: 1923 si_pi->cac_weights = cac_weights_pitcairn; 1924 si_pi->lcac_config = lcac_pitcairn; 1925 si_pi->cac_override = cac_override_pitcairn; 1926 si_pi->powertune_data = &powertune_data_pitcairn; 1927 si_pi->dte_data = dte_data_neptune_xt; 1928 update_dte_from_pl2 = true; 1929 break; 1930 default: 1931 si_pi->cac_weights = cac_weights_pitcairn; 1932 si_pi->lcac_config = lcac_pitcairn; 1933 si_pi->cac_override = cac_override_pitcairn; 1934 si_pi->powertune_data = &powertune_data_pitcairn; 1935 si_pi->dte_data = dte_data_pitcairn; 1936 break; 1937 } 1938 } else if (rdev->family == CHIP_VERDE) { 1939 si_pi->lcac_config = lcac_cape_verde; 1940 si_pi->cac_override = cac_override_cape_verde; 1941 si_pi->powertune_data = &powertune_data_cape_verde; 1942 1943 switch (rdev->pdev->device) { 1944 case 0x683B: 1945 case 0x683F: 1946 case 0x6829: 1947 case 0x6835: 1948 si_pi->cac_weights = cac_weights_cape_verde_pro; 1949 si_pi->dte_data = dte_data_cape_verde; 1950 break; 1951 case 0x682C: 1952 si_pi->cac_weights = cac_weights_cape_verde_pro; 1953 si_pi->dte_data = dte_data_sun_xt; 1954 break; 1955 case 0x6825: 1956 case 0x6827: 1957 si_pi->cac_weights = cac_weights_heathrow; 1958 si_pi->dte_data = dte_data_cape_verde; 1959 break; 1960 case 0x6824: 1961 case 0x682D: 1962 si_pi->cac_weights = cac_weights_chelsea_xt; 1963 si_pi->dte_data = dte_data_cape_verde; 1964 break; 1965 case 0x682F: 1966 si_pi->cac_weights = cac_weights_chelsea_pro; 1967 si_pi->dte_data = dte_data_cape_verde; 1968 break; 1969 case 0x6820: 1970 si_pi->cac_weights = cac_weights_heathrow; 1971 si_pi->dte_data = dte_data_venus_xtx; 1972 break; 1973 case 0x6821: 1974 si_pi->cac_weights = cac_weights_heathrow; 1975 si_pi->dte_data = dte_data_venus_xt; 1976 break; 1977 case 0x6823: 1978 case 0x682B: 1979 case 0x6822: 1980 case 0x682A: 1981 si_pi->cac_weights = cac_weights_chelsea_pro; 1982 si_pi->dte_data = dte_data_venus_pro; 1983 break; 1984 default: 1985 si_pi->cac_weights = cac_weights_cape_verde; 1986 si_pi->dte_data = dte_data_cape_verde; 1987 break; 1988 } 1989 } else if (rdev->family == CHIP_OLAND) { 1990 switch (rdev->pdev->device) { 1991 case 0x6601: 1992 case 0x6621: 1993 case 0x6603: 1994 case 0x6605: 1995 si_pi->cac_weights = cac_weights_mars_pro; 1996 si_pi->lcac_config = lcac_mars_pro; 1997 si_pi->cac_override = cac_override_oland; 1998 si_pi->powertune_data = &powertune_data_mars_pro; 1999 si_pi->dte_data = dte_data_mars_pro; 2000 update_dte_from_pl2 = true; 2001 break; 2002 case 0x6600: 2003 case 0x6606: 2004 case 0x6620: 2005 case 0x6604: 2006 si_pi->cac_weights = cac_weights_mars_xt; 2007 si_pi->lcac_config = lcac_mars_pro; 2008 si_pi->cac_override = cac_override_oland; 2009 si_pi->powertune_data = &powertune_data_mars_pro; 2010 si_pi->dte_data = dte_data_mars_pro; 2011 update_dte_from_pl2 = true; 2012 break; 2013 case 0x6611: 2014 case 0x6613: 2015 case 0x6608: 2016 si_pi->cac_weights = cac_weights_oland_pro; 2017 si_pi->lcac_config = lcac_mars_pro; 2018 si_pi->cac_override = cac_override_oland; 2019 si_pi->powertune_data = &powertune_data_mars_pro; 2020 si_pi->dte_data = dte_data_mars_pro; 2021 update_dte_from_pl2 = true; 2022 break; 2023 case 0x6610: 2024 si_pi->cac_weights = cac_weights_oland_xt; 2025 si_pi->lcac_config = lcac_mars_pro; 2026 si_pi->cac_override = cac_override_oland; 2027 si_pi->powertune_data = &powertune_data_mars_pro; 2028 si_pi->dte_data = dte_data_mars_pro; 2029 update_dte_from_pl2 = true; 2030 break; 2031 default: 2032 si_pi->cac_weights = cac_weights_oland; 2033 si_pi->lcac_config = lcac_oland; 2034 si_pi->cac_override = cac_override_oland; 2035 si_pi->powertune_data = &powertune_data_oland; 2036 si_pi->dte_data = dte_data_oland; 2037 break; 2038 } 2039 } else if (rdev->family == CHIP_HAINAN) { 2040 si_pi->cac_weights = cac_weights_hainan; 2041 si_pi->lcac_config = lcac_oland; 2042 si_pi->cac_override = cac_override_oland; 2043 si_pi->powertune_data = &powertune_data_hainan; 2044 si_pi->dte_data = dte_data_sun_xt; 2045 update_dte_from_pl2 = true; 2046 } else { 2047 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2048 return; 2049 } 2050 2051 ni_pi->enable_power_containment = false; 2052 ni_pi->enable_cac = false; 2053 ni_pi->enable_sq_ramping = false; 2054 si_pi->enable_dte = false; 2055 2056 if (si_pi->powertune_data->enable_powertune_by_default) { 2057 ni_pi->enable_power_containment= true; 2058 ni_pi->enable_cac = true; 2059 if (si_pi->dte_data.enable_dte_by_default) { 2060 si_pi->enable_dte = true; 2061 if (update_dte_from_pl2) 2062 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2063 2064 } 2065 ni_pi->enable_sq_ramping = true; 2066 } 2067 2068 ni_pi->driver_calculate_cac_leakage = true; 2069 ni_pi->cac_configuration_required = true; 2070 2071 if (ni_pi->cac_configuration_required) { 2072 ni_pi->support_cac_long_term_average = true; 2073 si_pi->dyn_powertune_data.l2_lta_window_size = 2074 si_pi->powertune_data->l2_lta_window_size_default; 2075 si_pi->dyn_powertune_data.lts_truncate = 2076 si_pi->powertune_data->lts_truncate_default; 2077 } else { 2078 ni_pi->support_cac_long_term_average = false; 2079 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2080 si_pi->dyn_powertune_data.lts_truncate = 0; 2081 } 2082 2083 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2084 } 2085 2086 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2087 { 2088 return 1; 2089 } 2090 2091 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2092 { 2093 u32 xclk; 2094 u32 wintime; 2095 u32 cac_window; 2096 u32 cac_window_size; 2097 2098 xclk = radeon_get_xclk(rdev); 2099 2100 if (xclk == 0) 2101 return 0; 2102 2103 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2104 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2105 2106 wintime = (cac_window_size * 100) / xclk; 2107 2108 return wintime; 2109 } 2110 2111 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2112 { 2113 return power_in_watts; 2114 } 2115 2116 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2117 bool adjust_polarity, 2118 u32 tdp_adjustment, 2119 u32 *tdp_limit, 2120 u32 *near_tdp_limit) 2121 { 2122 u32 adjustment_delta, max_tdp_limit; 2123 2124 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2125 return -EINVAL; 2126 2127 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2128 2129 if (adjust_polarity) { 2130 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2131 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2132 } else { 2133 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2134 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2135 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2137 else 2138 *near_tdp_limit = 0; 2139 } 2140 2141 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2142 return -EINVAL; 2143 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2144 return -EINVAL; 2145 2146 return 0; 2147 } 2148 2149 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2150 struct radeon_ps *radeon_state) 2151 { 2152 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2153 struct si_power_info *si_pi = si_get_pi(rdev); 2154 2155 if (ni_pi->enable_power_containment) { 2156 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2157 PP_SIslands_PAPMParameters *papm_parm; 2158 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2159 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2160 u32 tdp_limit; 2161 u32 near_tdp_limit; 2162 int ret; 2163 2164 if (scaling_factor == 0) 2165 return -EINVAL; 2166 2167 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2168 2169 ret = si_calculate_adjusted_tdp_limits(rdev, 2170 false, /* ??? */ 2171 rdev->pm.dpm.tdp_adjustment, 2172 &tdp_limit, 2173 &near_tdp_limit); 2174 if (ret) 2175 return ret; 2176 2177 smc_table->dpm2Params.TDPLimit = 2178 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2179 smc_table->dpm2Params.NearTDPLimit = 2180 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2181 smc_table->dpm2Params.SafePowerLimit = 2182 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2183 2184 ret = si_copy_bytes_to_smc(rdev, 2185 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2186 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2187 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2188 sizeof(u32) * 3, 2189 si_pi->sram_end); 2190 if (ret) 2191 return ret; 2192 2193 if (si_pi->enable_ppm) { 2194 papm_parm = &si_pi->papm_parm; 2195 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2196 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2197 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2198 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2199 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2200 papm_parm->PlatformPowerLimit = 0xffffffff; 2201 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2202 2203 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2204 (u8 *)papm_parm, 2205 sizeof(PP_SIslands_PAPMParameters), 2206 si_pi->sram_end); 2207 if (ret) 2208 return ret; 2209 } 2210 } 2211 return 0; 2212 } 2213 2214 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2215 struct radeon_ps *radeon_state) 2216 { 2217 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2218 struct si_power_info *si_pi = si_get_pi(rdev); 2219 2220 if (ni_pi->enable_power_containment) { 2221 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2222 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2223 int ret; 2224 2225 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2226 2227 smc_table->dpm2Params.NearTDPLimit = 2228 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2229 smc_table->dpm2Params.SafePowerLimit = 2230 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2231 2232 ret = si_copy_bytes_to_smc(rdev, 2233 (si_pi->state_table_start + 2234 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2235 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2236 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2237 sizeof(u32) * 2, 2238 si_pi->sram_end); 2239 if (ret) 2240 return ret; 2241 } 2242 2243 return 0; 2244 } 2245 2246 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2247 const u16 prev_std_vddc, 2248 const u16 curr_std_vddc) 2249 { 2250 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2251 u64 prev_vddc = (u64)prev_std_vddc; 2252 u64 curr_vddc = (u64)curr_std_vddc; 2253 u64 pwr_efficiency_ratio, n, d; 2254 2255 if ((prev_vddc == 0) || (curr_vddc == 0)) 2256 return 0; 2257 2258 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2259 d = prev_vddc * prev_vddc; 2260 pwr_efficiency_ratio = div64_u64(n, d); 2261 2262 if (pwr_efficiency_ratio > (u64)0xFFFF) 2263 return 0; 2264 2265 return (u16)pwr_efficiency_ratio; 2266 } 2267 2268 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2269 struct radeon_ps *radeon_state) 2270 { 2271 struct si_power_info *si_pi = si_get_pi(rdev); 2272 2273 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2274 radeon_state->vclk && radeon_state->dclk) 2275 return true; 2276 2277 return false; 2278 } 2279 2280 static int si_populate_power_containment_values(struct radeon_device *rdev, 2281 struct radeon_ps *radeon_state, 2282 SISLANDS_SMC_SWSTATE *smc_state) 2283 { 2284 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2285 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2286 struct ni_ps *state = ni_get_ps(radeon_state); 2287 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2288 u32 prev_sclk; 2289 u32 max_sclk; 2290 u32 min_sclk; 2291 u16 prev_std_vddc; 2292 u16 curr_std_vddc; 2293 int i; 2294 u16 pwr_efficiency_ratio; 2295 u8 max_ps_percent; 2296 bool disable_uvd_power_tune; 2297 int ret; 2298 2299 if (ni_pi->enable_power_containment == false) 2300 return 0; 2301 2302 if (state->performance_level_count == 0) 2303 return -EINVAL; 2304 2305 if (smc_state->levelCount != state->performance_level_count) 2306 return -EINVAL; 2307 2308 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2309 2310 smc_state->levels[0].dpm2.MaxPS = 0; 2311 smc_state->levels[0].dpm2.NearTDPDec = 0; 2312 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2313 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2314 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2315 2316 for (i = 1; i < state->performance_level_count; i++) { 2317 prev_sclk = state->performance_levels[i-1].sclk; 2318 max_sclk = state->performance_levels[i].sclk; 2319 if (i == 1) 2320 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2321 else 2322 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2323 2324 if (prev_sclk > max_sclk) 2325 return -EINVAL; 2326 2327 if ((max_ps_percent == 0) || 2328 (prev_sclk == max_sclk) || 2329 disable_uvd_power_tune) { 2330 min_sclk = max_sclk; 2331 } else if (i == 1) { 2332 min_sclk = prev_sclk; 2333 } else { 2334 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2335 } 2336 2337 if (min_sclk < state->performance_levels[0].sclk) 2338 min_sclk = state->performance_levels[0].sclk; 2339 2340 if (min_sclk == 0) 2341 return -EINVAL; 2342 2343 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2344 state->performance_levels[i-1].vddc, &vddc); 2345 if (ret) 2346 return ret; 2347 2348 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2349 if (ret) 2350 return ret; 2351 2352 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2353 state->performance_levels[i].vddc, &vddc); 2354 if (ret) 2355 return ret; 2356 2357 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2358 if (ret) 2359 return ret; 2360 2361 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2362 prev_std_vddc, curr_std_vddc); 2363 2364 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2365 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2366 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2367 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2368 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2369 } 2370 2371 return 0; 2372 } 2373 2374 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2375 struct radeon_ps *radeon_state, 2376 SISLANDS_SMC_SWSTATE *smc_state) 2377 { 2378 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2379 struct ni_ps *state = ni_get_ps(radeon_state); 2380 u32 sq_power_throttle, sq_power_throttle2; 2381 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2382 int i; 2383 2384 if (state->performance_level_count == 0) 2385 return -EINVAL; 2386 2387 if (smc_state->levelCount != state->performance_level_count) 2388 return -EINVAL; 2389 2390 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2391 return -EINVAL; 2392 2393 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2394 enable_sq_ramping = false; 2395 2396 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2397 enable_sq_ramping = false; 2398 2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2403 enable_sq_ramping = false; 2404 2405 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2406 enable_sq_ramping = false; 2407 2408 for (i = 0; i < state->performance_level_count; i++) { 2409 sq_power_throttle = 0; 2410 sq_power_throttle2 = 0; 2411 2412 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2413 enable_sq_ramping) { 2414 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2415 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2416 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2417 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2418 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2419 } else { 2420 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2421 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2422 } 2423 2424 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2425 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2426 } 2427 2428 return 0; 2429 } 2430 2431 static int si_enable_power_containment(struct radeon_device *rdev, 2432 struct radeon_ps *radeon_new_state, 2433 bool enable) 2434 { 2435 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2436 PPSMC_Result smc_result; 2437 int ret = 0; 2438 2439 if (ni_pi->enable_power_containment) { 2440 if (enable) { 2441 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2442 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2443 if (smc_result != PPSMC_Result_OK) { 2444 ret = -EINVAL; 2445 ni_pi->pc_enabled = false; 2446 } else { 2447 ni_pi->pc_enabled = true; 2448 } 2449 } 2450 } else { 2451 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2452 if (smc_result != PPSMC_Result_OK) 2453 ret = -EINVAL; 2454 ni_pi->pc_enabled = false; 2455 } 2456 } 2457 2458 return ret; 2459 } 2460 2461 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2462 { 2463 struct si_power_info *si_pi = si_get_pi(rdev); 2464 int ret = 0; 2465 struct si_dte_data *dte_data = &si_pi->dte_data; 2466 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2467 u32 table_size; 2468 u8 tdep_count; 2469 u32 i; 2470 2471 if (dte_data == NULL) 2472 si_pi->enable_dte = false; 2473 2474 if (si_pi->enable_dte == false) 2475 return 0; 2476 2477 if (dte_data->k <= 0) 2478 return -EINVAL; 2479 2480 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2481 if (dte_tables == NULL) { 2482 si_pi->enable_dte = false; 2483 return -ENOMEM; 2484 } 2485 2486 table_size = dte_data->k; 2487 2488 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2489 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2490 2491 tdep_count = dte_data->tdep_count; 2492 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2493 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2494 2495 dte_tables->K = cpu_to_be32(table_size); 2496 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2497 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2498 dte_tables->WindowSize = dte_data->window_size; 2499 dte_tables->temp_select = dte_data->temp_select; 2500 dte_tables->DTE_mode = dte_data->dte_mode; 2501 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2502 2503 if (tdep_count > 0) 2504 table_size--; 2505 2506 for (i = 0; i < table_size; i++) { 2507 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2508 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2509 } 2510 2511 dte_tables->Tdep_count = tdep_count; 2512 2513 for (i = 0; i < (u32)tdep_count; i++) { 2514 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2515 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2516 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2517 } 2518 2519 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2520 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2521 kfree(dte_tables); 2522 2523 return ret; 2524 } 2525 2526 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2527 u16 *max, u16 *min) 2528 { 2529 struct si_power_info *si_pi = si_get_pi(rdev); 2530 struct radeon_cac_leakage_table *table = 2531 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2532 u32 i; 2533 u32 v0_loadline; 2534 2535 2536 if (table == NULL) 2537 return -EINVAL; 2538 2539 *max = 0; 2540 *min = 0xFFFF; 2541 2542 for (i = 0; i < table->count; i++) { 2543 if (table->entries[i].vddc > *max) 2544 *max = table->entries[i].vddc; 2545 if (table->entries[i].vddc < *min) 2546 *min = table->entries[i].vddc; 2547 } 2548 2549 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2550 return -EINVAL; 2551 2552 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2553 2554 if (v0_loadline > 0xFFFFUL) 2555 return -EINVAL; 2556 2557 *min = (u16)v0_loadline; 2558 2559 if ((*min > *max) || (*max == 0) || (*min == 0)) 2560 return -EINVAL; 2561 2562 return 0; 2563 } 2564 2565 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2566 { 2567 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2568 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2569 } 2570 2571 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2572 PP_SIslands_CacConfig *cac_tables, 2573 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2574 u16 t0, u16 t_step) 2575 { 2576 struct si_power_info *si_pi = si_get_pi(rdev); 2577 u32 leakage; 2578 unsigned int i, j; 2579 s32 t; 2580 u32 smc_leakage; 2581 u32 scaling_factor; 2582 u16 voltage; 2583 2584 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2585 2586 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2587 t = (1000 * (i * t_step + t0)); 2588 2589 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2590 voltage = vddc_max - (vddc_step * j); 2591 2592 si_calculate_leakage_for_v_and_t(rdev, 2593 &si_pi->powertune_data->leakage_coefficients, 2594 voltage, 2595 t, 2596 si_pi->dyn_powertune_data.cac_leakage, 2597 &leakage); 2598 2599 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2600 2601 if (smc_leakage > 0xFFFF) 2602 smc_leakage = 0xFFFF; 2603 2604 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2605 cpu_to_be16((u16)smc_leakage); 2606 } 2607 } 2608 return 0; 2609 } 2610 2611 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2612 PP_SIslands_CacConfig *cac_tables, 2613 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2614 { 2615 struct si_power_info *si_pi = si_get_pi(rdev); 2616 u32 leakage; 2617 unsigned int i, j; 2618 u32 smc_leakage; 2619 u32 scaling_factor; 2620 u16 voltage; 2621 2622 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2623 2624 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2625 voltage = vddc_max - (vddc_step * j); 2626 2627 si_calculate_leakage_for_v(rdev, 2628 &si_pi->powertune_data->leakage_coefficients, 2629 si_pi->powertune_data->fixed_kt, 2630 voltage, 2631 si_pi->dyn_powertune_data.cac_leakage, 2632 &leakage); 2633 2634 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2635 2636 if (smc_leakage > 0xFFFF) 2637 smc_leakage = 0xFFFF; 2638 2639 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2640 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2641 cpu_to_be16((u16)smc_leakage); 2642 } 2643 return 0; 2644 } 2645 2646 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2647 { 2648 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2649 struct si_power_info *si_pi = si_get_pi(rdev); 2650 PP_SIslands_CacConfig *cac_tables = NULL; 2651 u16 vddc_max, vddc_min, vddc_step; 2652 u16 t0, t_step; 2653 u32 load_line_slope, reg; 2654 int ret = 0; 2655 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2656 2657 if (ni_pi->enable_cac == false) 2658 return 0; 2659 2660 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2661 if (!cac_tables) 2662 return -ENOMEM; 2663 2664 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2665 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2666 WREG32(CG_CAC_CTRL, reg); 2667 2668 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2669 si_pi->dyn_powertune_data.dc_pwr_value = 2670 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2671 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2672 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2673 2674 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2675 2676 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2677 if (ret) 2678 goto done_free; 2679 2680 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2681 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2682 t_step = 4; 2683 t0 = 60; 2684 2685 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2686 ret = si_init_dte_leakage_table(rdev, cac_tables, 2687 vddc_max, vddc_min, vddc_step, 2688 t0, t_step); 2689 else 2690 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2691 vddc_max, vddc_min, vddc_step); 2692 if (ret) 2693 goto done_free; 2694 2695 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2696 2697 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2698 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2699 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2700 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2701 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2702 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2703 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2704 cac_tables->calculation_repeats = cpu_to_be32(2); 2705 cac_tables->dc_cac = cpu_to_be32(0); 2706 cac_tables->log2_PG_LKG_SCALE = 12; 2707 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2708 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2709 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2710 2711 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2712 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2713 2714 if (ret) 2715 goto done_free; 2716 2717 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2718 2719 done_free: 2720 if (ret) { 2721 ni_pi->enable_cac = false; 2722 ni_pi->enable_power_containment = false; 2723 } 2724 2725 kfree(cac_tables); 2726 2727 return 0; 2728 } 2729 2730 static int si_program_cac_config_registers(struct radeon_device *rdev, 2731 const struct si_cac_config_reg *cac_config_regs) 2732 { 2733 const struct si_cac_config_reg *config_regs = cac_config_regs; 2734 u32 data = 0, offset; 2735 2736 if (!config_regs) 2737 return -EINVAL; 2738 2739 while (config_regs->offset != 0xFFFFFFFF) { 2740 switch (config_regs->type) { 2741 case SISLANDS_CACCONFIG_CGIND: 2742 offset = SMC_CG_IND_START + config_regs->offset; 2743 if (offset < SMC_CG_IND_END) 2744 data = RREG32_SMC(offset); 2745 break; 2746 default: 2747 data = RREG32(config_regs->offset << 2); 2748 break; 2749 } 2750 2751 data &= ~config_regs->mask; 2752 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2753 2754 switch (config_regs->type) { 2755 case SISLANDS_CACCONFIG_CGIND: 2756 offset = SMC_CG_IND_START + config_regs->offset; 2757 if (offset < SMC_CG_IND_END) 2758 WREG32_SMC(offset, data); 2759 break; 2760 default: 2761 WREG32(config_regs->offset << 2, data); 2762 break; 2763 } 2764 config_regs++; 2765 } 2766 return 0; 2767 } 2768 2769 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2770 { 2771 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2772 struct si_power_info *si_pi = si_get_pi(rdev); 2773 int ret; 2774 2775 if ((ni_pi->enable_cac == false) || 2776 (ni_pi->cac_configuration_required == false)) 2777 return 0; 2778 2779 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2780 if (ret) 2781 return ret; 2782 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2783 if (ret) 2784 return ret; 2785 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2786 if (ret) 2787 return ret; 2788 2789 return 0; 2790 } 2791 2792 static int si_enable_smc_cac(struct radeon_device *rdev, 2793 struct radeon_ps *radeon_new_state, 2794 bool enable) 2795 { 2796 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2797 struct si_power_info *si_pi = si_get_pi(rdev); 2798 PPSMC_Result smc_result; 2799 int ret = 0; 2800 2801 if (ni_pi->enable_cac) { 2802 if (enable) { 2803 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2804 if (ni_pi->support_cac_long_term_average) { 2805 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2806 if (smc_result != PPSMC_Result_OK) 2807 ni_pi->support_cac_long_term_average = false; 2808 } 2809 2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2811 if (smc_result != PPSMC_Result_OK) { 2812 ret = -EINVAL; 2813 ni_pi->cac_enabled = false; 2814 } else { 2815 ni_pi->cac_enabled = true; 2816 } 2817 2818 if (si_pi->enable_dte) { 2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2820 if (smc_result != PPSMC_Result_OK) 2821 ret = -EINVAL; 2822 } 2823 } 2824 } else if (ni_pi->cac_enabled) { 2825 if (si_pi->enable_dte) 2826 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2827 2828 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2829 2830 ni_pi->cac_enabled = false; 2831 2832 if (ni_pi->support_cac_long_term_average) 2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2834 } 2835 } 2836 return ret; 2837 } 2838 2839 static int si_init_smc_spll_table(struct radeon_device *rdev) 2840 { 2841 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2842 struct si_power_info *si_pi = si_get_pi(rdev); 2843 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2844 SISLANDS_SMC_SCLK_VALUE sclk_params; 2845 u32 fb_div, p_div; 2846 u32 clk_s, clk_v; 2847 u32 sclk = 0; 2848 int ret = 0; 2849 u32 tmp; 2850 int i; 2851 2852 if (si_pi->spll_table_start == 0) 2853 return -EINVAL; 2854 2855 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2856 if (spll_table == NULL) 2857 return -ENOMEM; 2858 2859 for (i = 0; i < 256; i++) { 2860 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2861 if (ret) 2862 break; 2863 2864 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2865 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2866 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2867 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2868 2869 fb_div &= ~0x00001FFF; 2870 fb_div >>= 1; 2871 clk_v >>= 6; 2872 2873 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2874 ret = -EINVAL; 2875 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2876 ret = -EINVAL; 2877 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2878 ret = -EINVAL; 2879 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2880 ret = -EINVAL; 2881 2882 if (ret) 2883 break; 2884 2885 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2886 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2887 spll_table->freq[i] = cpu_to_be32(tmp); 2888 2889 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2890 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2891 spll_table->ss[i] = cpu_to_be32(tmp); 2892 2893 sclk += 512; 2894 } 2895 2896 2897 if (!ret) 2898 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2899 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2900 si_pi->sram_end); 2901 2902 if (ret) 2903 ni_pi->enable_power_containment = false; 2904 2905 kfree(spll_table); 2906 2907 return ret; 2908 } 2909 2910 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2911 struct radeon_ps *rps) 2912 { 2913 struct ni_ps *ps = ni_get_ps(rps); 2914 struct radeon_clock_and_voltage_limits *max_limits; 2915 bool disable_mclk_switching = false; 2916 bool disable_sclk_switching = false; 2917 u32 mclk, sclk; 2918 u16 vddc, vddci; 2919 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2920 int i; 2921 2922 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2923 ni_dpm_vblank_too_short(rdev)) 2924 disable_mclk_switching = true; 2925 2926 if (rps->vclk || rps->dclk) { 2927 disable_mclk_switching = true; 2928 disable_sclk_switching = true; 2929 } 2930 2931 if (rdev->pm.dpm.ac_power) 2932 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2933 else 2934 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2935 2936 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2937 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2938 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2939 } 2940 if (rdev->pm.dpm.ac_power == false) { 2941 for (i = 0; i < ps->performance_level_count; i++) { 2942 if (ps->performance_levels[i].mclk > max_limits->mclk) 2943 ps->performance_levels[i].mclk = max_limits->mclk; 2944 if (ps->performance_levels[i].sclk > max_limits->sclk) 2945 ps->performance_levels[i].sclk = max_limits->sclk; 2946 if (ps->performance_levels[i].vddc > max_limits->vddc) 2947 ps->performance_levels[i].vddc = max_limits->vddc; 2948 if (ps->performance_levels[i].vddci > max_limits->vddci) 2949 ps->performance_levels[i].vddci = max_limits->vddci; 2950 } 2951 } 2952 2953 /* limit clocks to max supported clocks based on voltage dependency tables */ 2954 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2955 &max_sclk_vddc); 2956 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2957 &max_mclk_vddci); 2958 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2959 &max_mclk_vddc); 2960 2961 for (i = 0; i < ps->performance_level_count; i++) { 2962 if (max_sclk_vddc) { 2963 if (ps->performance_levels[i].sclk > max_sclk_vddc) 2964 ps->performance_levels[i].sclk = max_sclk_vddc; 2965 } 2966 if (max_mclk_vddci) { 2967 if (ps->performance_levels[i].mclk > max_mclk_vddci) 2968 ps->performance_levels[i].mclk = max_mclk_vddci; 2969 } 2970 if (max_mclk_vddc) { 2971 if (ps->performance_levels[i].mclk > max_mclk_vddc) 2972 ps->performance_levels[i].mclk = max_mclk_vddc; 2973 } 2974 } 2975 2976 /* XXX validate the min clocks required for display */ 2977 2978 if (disable_mclk_switching) { 2979 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2980 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2981 } else { 2982 mclk = ps->performance_levels[0].mclk; 2983 vddci = ps->performance_levels[0].vddci; 2984 } 2985 2986 if (disable_sclk_switching) { 2987 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2988 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2989 } else { 2990 sclk = ps->performance_levels[0].sclk; 2991 vddc = ps->performance_levels[0].vddc; 2992 } 2993 2994 /* adjusted low state */ 2995 ps->performance_levels[0].sclk = sclk; 2996 ps->performance_levels[0].mclk = mclk; 2997 ps->performance_levels[0].vddc = vddc; 2998 ps->performance_levels[0].vddci = vddci; 2999 3000 if (disable_sclk_switching) { 3001 sclk = ps->performance_levels[0].sclk; 3002 for (i = 1; i < ps->performance_level_count; i++) { 3003 if (sclk < ps->performance_levels[i].sclk) 3004 sclk = ps->performance_levels[i].sclk; 3005 } 3006 for (i = 0; i < ps->performance_level_count; i++) { 3007 ps->performance_levels[i].sclk = sclk; 3008 ps->performance_levels[i].vddc = vddc; 3009 } 3010 } else { 3011 for (i = 1; i < ps->performance_level_count; i++) { 3012 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3013 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3014 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3015 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3016 } 3017 } 3018 3019 if (disable_mclk_switching) { 3020 mclk = ps->performance_levels[0].mclk; 3021 for (i = 1; i < ps->performance_level_count; i++) { 3022 if (mclk < ps->performance_levels[i].mclk) 3023 mclk = ps->performance_levels[i].mclk; 3024 } 3025 for (i = 0; i < ps->performance_level_count; i++) { 3026 ps->performance_levels[i].mclk = mclk; 3027 ps->performance_levels[i].vddci = vddci; 3028 } 3029 } else { 3030 for (i = 1; i < ps->performance_level_count; i++) { 3031 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3032 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3033 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3034 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3035 } 3036 } 3037 3038 for (i = 0; i < ps->performance_level_count; i++) 3039 btc_adjust_clock_combinations(rdev, max_limits, 3040 &ps->performance_levels[i]); 3041 3042 for (i = 0; i < ps->performance_level_count; i++) { 3043 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3044 ps->performance_levels[i].sclk, 3045 max_limits->vddc, &ps->performance_levels[i].vddc); 3046 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3047 ps->performance_levels[i].mclk, 3048 max_limits->vddci, &ps->performance_levels[i].vddci); 3049 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3050 ps->performance_levels[i].mclk, 3051 max_limits->vddc, &ps->performance_levels[i].vddc); 3052 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3053 rdev->clock.current_dispclk, 3054 max_limits->vddc, &ps->performance_levels[i].vddc); 3055 } 3056 3057 for (i = 0; i < ps->performance_level_count; i++) { 3058 btc_apply_voltage_delta_rules(rdev, 3059 max_limits->vddc, max_limits->vddci, 3060 &ps->performance_levels[i].vddc, 3061 &ps->performance_levels[i].vddci); 3062 } 3063 3064 ps->dc_compatible = true; 3065 for (i = 0; i < ps->performance_level_count; i++) { 3066 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3067 ps->dc_compatible = false; 3068 } 3069 3070 } 3071 3072 #if 0 3073 static int si_read_smc_soft_register(struct radeon_device *rdev, 3074 u16 reg_offset, u32 *value) 3075 { 3076 struct si_power_info *si_pi = si_get_pi(rdev); 3077 3078 return si_read_smc_sram_dword(rdev, 3079 si_pi->soft_regs_start + reg_offset, value, 3080 si_pi->sram_end); 3081 } 3082 #endif 3083 3084 static int si_write_smc_soft_register(struct radeon_device *rdev, 3085 u16 reg_offset, u32 value) 3086 { 3087 struct si_power_info *si_pi = si_get_pi(rdev); 3088 3089 return si_write_smc_sram_dword(rdev, 3090 si_pi->soft_regs_start + reg_offset, 3091 value, si_pi->sram_end); 3092 } 3093 3094 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3095 { 3096 bool ret = false; 3097 u32 tmp, width, row, column, bank, density; 3098 bool is_memory_gddr5, is_special; 3099 3100 tmp = RREG32(MC_SEQ_MISC0); 3101 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3102 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3103 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3104 3105 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3106 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3107 3108 tmp = RREG32(MC_ARB_RAMCFG); 3109 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3110 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3111 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3112 3113 density = (1 << (row + column - 20 + bank)) * width; 3114 3115 if ((rdev->pdev->device == 0x6819) && 3116 is_memory_gddr5 && is_special && (density == 0x400)) 3117 ret = true; 3118 3119 return ret; 3120 } 3121 3122 static void si_get_leakage_vddc(struct radeon_device *rdev) 3123 { 3124 struct si_power_info *si_pi = si_get_pi(rdev); 3125 u16 vddc, count = 0; 3126 int i, ret; 3127 3128 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3129 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3130 3131 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3132 si_pi->leakage_voltage.entries[count].voltage = vddc; 3133 si_pi->leakage_voltage.entries[count].leakage_index = 3134 SISLANDS_LEAKAGE_INDEX0 + i; 3135 count++; 3136 } 3137 } 3138 si_pi->leakage_voltage.count = count; 3139 } 3140 3141 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3142 u32 index, u16 *leakage_voltage) 3143 { 3144 struct si_power_info *si_pi = si_get_pi(rdev); 3145 int i; 3146 3147 if (leakage_voltage == NULL) 3148 return -EINVAL; 3149 3150 if ((index & 0xff00) != 0xff00) 3151 return -EINVAL; 3152 3153 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3154 return -EINVAL; 3155 3156 if (index < SISLANDS_LEAKAGE_INDEX0) 3157 return -EINVAL; 3158 3159 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3160 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3161 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3162 return 0; 3163 } 3164 } 3165 return -EAGAIN; 3166 } 3167 3168 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3169 { 3170 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3171 bool want_thermal_protection; 3172 enum radeon_dpm_event_src dpm_event_src; 3173 3174 switch (sources) { 3175 case 0: 3176 default: 3177 want_thermal_protection = false; 3178 break; 3179 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3180 want_thermal_protection = true; 3181 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3182 break; 3183 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3184 want_thermal_protection = true; 3185 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3186 break; 3187 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3188 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3189 want_thermal_protection = true; 3190 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3191 break; 3192 } 3193 3194 if (want_thermal_protection) { 3195 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3196 if (pi->thermal_protection) 3197 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3198 } else { 3199 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3200 } 3201 } 3202 3203 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3204 enum radeon_dpm_auto_throttle_src source, 3205 bool enable) 3206 { 3207 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3208 3209 if (enable) { 3210 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3211 pi->active_auto_throttle_sources |= 1 << source; 3212 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3213 } 3214 } else { 3215 if (pi->active_auto_throttle_sources & (1 << source)) { 3216 pi->active_auto_throttle_sources &= ~(1 << source); 3217 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3218 } 3219 } 3220 } 3221 3222 static void si_start_dpm(struct radeon_device *rdev) 3223 { 3224 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3225 } 3226 3227 static void si_stop_dpm(struct radeon_device *rdev) 3228 { 3229 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3230 } 3231 3232 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3233 { 3234 if (enable) 3235 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3236 else 3237 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3238 3239 } 3240 3241 #if 0 3242 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3243 u32 thermal_level) 3244 { 3245 PPSMC_Result ret; 3246 3247 if (thermal_level == 0) { 3248 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3249 if (ret == PPSMC_Result_OK) 3250 return 0; 3251 else 3252 return -EINVAL; 3253 } 3254 return 0; 3255 } 3256 3257 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3258 { 3259 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3260 } 3261 #endif 3262 3263 #if 0 3264 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3265 { 3266 if (ac_power) 3267 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3268 0 : -EINVAL; 3269 3270 return 0; 3271 } 3272 #endif 3273 3274 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3275 PPSMC_Msg msg, u32 parameter) 3276 { 3277 WREG32(SMC_SCRATCH0, parameter); 3278 return si_send_msg_to_smc(rdev, msg); 3279 } 3280 3281 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3282 { 3283 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3284 return -EINVAL; 3285 3286 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3287 0 : -EINVAL; 3288 } 3289 3290 int si_dpm_force_performance_level(struct radeon_device *rdev, 3291 enum radeon_dpm_forced_level level) 3292 { 3293 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3294 struct ni_ps *ps = ni_get_ps(rps); 3295 u32 levels = ps->performance_level_count; 3296 3297 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3298 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3299 return -EINVAL; 3300 3301 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3302 return -EINVAL; 3303 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3304 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3305 return -EINVAL; 3306 3307 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3308 return -EINVAL; 3309 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3310 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3311 return -EINVAL; 3312 3313 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3314 return -EINVAL; 3315 } 3316 3317 rdev->pm.dpm.forced_level = level; 3318 3319 return 0; 3320 } 3321 3322 static int si_set_boot_state(struct radeon_device *rdev) 3323 { 3324 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3325 0 : -EINVAL; 3326 } 3327 3328 static int si_set_sw_state(struct radeon_device *rdev) 3329 { 3330 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3331 0 : -EINVAL; 3332 } 3333 3334 static int si_halt_smc(struct radeon_device *rdev) 3335 { 3336 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3337 return -EINVAL; 3338 3339 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3340 0 : -EINVAL; 3341 } 3342 3343 static int si_resume_smc(struct radeon_device *rdev) 3344 { 3345 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3346 return -EINVAL; 3347 3348 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3349 0 : -EINVAL; 3350 } 3351 3352 static void si_dpm_start_smc(struct radeon_device *rdev) 3353 { 3354 si_program_jump_on_start(rdev); 3355 si_start_smc(rdev); 3356 si_start_smc_clock(rdev); 3357 } 3358 3359 static void si_dpm_stop_smc(struct radeon_device *rdev) 3360 { 3361 si_reset_smc(rdev); 3362 si_stop_smc_clock(rdev); 3363 } 3364 3365 static int si_process_firmware_header(struct radeon_device *rdev) 3366 { 3367 struct si_power_info *si_pi = si_get_pi(rdev); 3368 u32 tmp; 3369 int ret; 3370 3371 ret = si_read_smc_sram_dword(rdev, 3372 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3373 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3374 &tmp, si_pi->sram_end); 3375 if (ret) 3376 return ret; 3377 3378 si_pi->state_table_start = tmp; 3379 3380 ret = si_read_smc_sram_dword(rdev, 3381 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3382 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3383 &tmp, si_pi->sram_end); 3384 if (ret) 3385 return ret; 3386 3387 si_pi->soft_regs_start = tmp; 3388 3389 ret = si_read_smc_sram_dword(rdev, 3390 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3391 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3392 &tmp, si_pi->sram_end); 3393 if (ret) 3394 return ret; 3395 3396 si_pi->mc_reg_table_start = tmp; 3397 3398 ret = si_read_smc_sram_dword(rdev, 3399 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3400 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3401 &tmp, si_pi->sram_end); 3402 if (ret) 3403 return ret; 3404 3405 si_pi->arb_table_start = tmp; 3406 3407 ret = si_read_smc_sram_dword(rdev, 3408 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3409 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3410 &tmp, si_pi->sram_end); 3411 if (ret) 3412 return ret; 3413 3414 si_pi->cac_table_start = tmp; 3415 3416 ret = si_read_smc_sram_dword(rdev, 3417 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3418 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3419 &tmp, si_pi->sram_end); 3420 if (ret) 3421 return ret; 3422 3423 si_pi->dte_table_start = tmp; 3424 3425 ret = si_read_smc_sram_dword(rdev, 3426 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3427 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3428 &tmp, si_pi->sram_end); 3429 if (ret) 3430 return ret; 3431 3432 si_pi->spll_table_start = tmp; 3433 3434 ret = si_read_smc_sram_dword(rdev, 3435 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3436 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3437 &tmp, si_pi->sram_end); 3438 if (ret) 3439 return ret; 3440 3441 si_pi->papm_cfg_table_start = tmp; 3442 3443 return ret; 3444 } 3445 3446 static void si_read_clock_registers(struct radeon_device *rdev) 3447 { 3448 struct si_power_info *si_pi = si_get_pi(rdev); 3449 3450 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3451 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3452 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3453 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3454 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3455 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3456 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3457 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3458 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3459 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3460 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3461 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3462 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3463 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3464 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3465 } 3466 3467 static void si_enable_thermal_protection(struct radeon_device *rdev, 3468 bool enable) 3469 { 3470 if (enable) 3471 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3472 else 3473 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3474 } 3475 3476 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3477 { 3478 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3479 } 3480 3481 #if 0 3482 static int si_enter_ulp_state(struct radeon_device *rdev) 3483 { 3484 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3485 3486 udelay(25000); 3487 3488 return 0; 3489 } 3490 3491 static int si_exit_ulp_state(struct radeon_device *rdev) 3492 { 3493 int i; 3494 3495 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3496 3497 udelay(7000); 3498 3499 for (i = 0; i < rdev->usec_timeout; i++) { 3500 if (RREG32(SMC_RESP_0) == 1) 3501 break; 3502 udelay(1000); 3503 } 3504 3505 return 0; 3506 } 3507 #endif 3508 3509 static int si_notify_smc_display_change(struct radeon_device *rdev, 3510 bool has_display) 3511 { 3512 PPSMC_Msg msg = has_display ? 3513 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3514 3515 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3516 0 : -EINVAL; 3517 } 3518 3519 static void si_program_response_times(struct radeon_device *rdev) 3520 { 3521 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3522 u32 vddc_dly, acpi_dly, vbi_dly; 3523 u32 reference_clock; 3524 3525 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3526 3527 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3528 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3529 3530 if (voltage_response_time == 0) 3531 voltage_response_time = 1000; 3532 3533 acpi_delay_time = 15000; 3534 vbi_time_out = 100000; 3535 3536 reference_clock = radeon_get_xclk(rdev); 3537 3538 vddc_dly = (voltage_response_time * reference_clock) / 100; 3539 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3540 vbi_dly = (vbi_time_out * reference_clock) / 100; 3541 3542 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3543 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3544 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3545 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3546 } 3547 3548 static void si_program_ds_registers(struct radeon_device *rdev) 3549 { 3550 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3551 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3552 3553 if (eg_pi->sclk_deep_sleep) { 3554 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3555 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3556 ~AUTOSCALE_ON_SS_CLEAR); 3557 } 3558 } 3559 3560 static void si_program_display_gap(struct radeon_device *rdev) 3561 { 3562 u32 tmp, pipe; 3563 int i; 3564 3565 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3566 if (rdev->pm.dpm.new_active_crtc_count > 0) 3567 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3568 else 3569 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3570 3571 if (rdev->pm.dpm.new_active_crtc_count > 1) 3572 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3573 else 3574 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3575 3576 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3577 3578 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3579 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3580 3581 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3582 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3583 /* find the first active crtc */ 3584 for (i = 0; i < rdev->num_crtc; i++) { 3585 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3586 break; 3587 } 3588 if (i == rdev->num_crtc) 3589 pipe = 0; 3590 else 3591 pipe = i; 3592 3593 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3594 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3595 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3596 } 3597 3598 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3599 * This can be a problem on PowerXpress systems or if you want to use the card 3600 * for offscreen rendering or compute if there are no crtcs enabled. 3601 */ 3602 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3603 } 3604 3605 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3606 { 3607 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3608 3609 if (enable) { 3610 if (pi->sclk_ss) 3611 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3612 } else { 3613 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3614 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3615 } 3616 } 3617 3618 static void si_setup_bsp(struct radeon_device *rdev) 3619 { 3620 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3621 u32 xclk = radeon_get_xclk(rdev); 3622 3623 r600_calculate_u_and_p(pi->asi, 3624 xclk, 3625 16, 3626 &pi->bsp, 3627 &pi->bsu); 3628 3629 r600_calculate_u_and_p(pi->pasi, 3630 xclk, 3631 16, 3632 &pi->pbsp, 3633 &pi->pbsu); 3634 3635 3636 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3637 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3638 3639 WREG32(CG_BSP, pi->dsp); 3640 } 3641 3642 static void si_program_git(struct radeon_device *rdev) 3643 { 3644 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3645 } 3646 3647 static void si_program_tp(struct radeon_device *rdev) 3648 { 3649 int i; 3650 enum r600_td td = R600_TD_DFLT; 3651 3652 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3653 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3654 3655 if (td == R600_TD_AUTO) 3656 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3657 else 3658 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3659 3660 if (td == R600_TD_UP) 3661 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3662 3663 if (td == R600_TD_DOWN) 3664 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3665 } 3666 3667 static void si_program_tpp(struct radeon_device *rdev) 3668 { 3669 WREG32(CG_TPC, R600_TPC_DFLT); 3670 } 3671 3672 static void si_program_sstp(struct radeon_device *rdev) 3673 { 3674 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3675 } 3676 3677 static void si_enable_display_gap(struct radeon_device *rdev) 3678 { 3679 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3680 3681 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3682 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3683 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3684 3685 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3686 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3687 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3688 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3689 } 3690 3691 static void si_program_vc(struct radeon_device *rdev) 3692 { 3693 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3694 3695 WREG32(CG_FTV, pi->vrc); 3696 } 3697 3698 static void si_clear_vc(struct radeon_device *rdev) 3699 { 3700 WREG32(CG_FTV, 0); 3701 } 3702 3703 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3704 { 3705 u8 mc_para_index; 3706 3707 if (memory_clock < 10000) 3708 mc_para_index = 0; 3709 else if (memory_clock >= 80000) 3710 mc_para_index = 0x0f; 3711 else 3712 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3713 return mc_para_index; 3714 } 3715 3716 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3717 { 3718 u8 mc_para_index; 3719 3720 if (strobe_mode) { 3721 if (memory_clock < 12500) 3722 mc_para_index = 0x00; 3723 else if (memory_clock > 47500) 3724 mc_para_index = 0x0f; 3725 else 3726 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3727 } else { 3728 if (memory_clock < 65000) 3729 mc_para_index = 0x00; 3730 else if (memory_clock > 135000) 3731 mc_para_index = 0x0f; 3732 else 3733 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3734 } 3735 return mc_para_index; 3736 } 3737 3738 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3739 { 3740 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3741 bool strobe_mode = false; 3742 u8 result = 0; 3743 3744 if (mclk <= pi->mclk_strobe_mode_threshold) 3745 strobe_mode = true; 3746 3747 if (pi->mem_gddr5) 3748 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3749 else 3750 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3751 3752 if (strobe_mode) 3753 result |= SISLANDS_SMC_STROBE_ENABLE; 3754 3755 return result; 3756 } 3757 3758 static int si_upload_firmware(struct radeon_device *rdev) 3759 { 3760 struct si_power_info *si_pi = si_get_pi(rdev); 3761 int ret; 3762 3763 si_reset_smc(rdev); 3764 si_stop_smc_clock(rdev); 3765 3766 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3767 3768 return ret; 3769 } 3770 3771 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3772 const struct atom_voltage_table *table, 3773 const struct radeon_phase_shedding_limits_table *limits) 3774 { 3775 u32 data, num_bits, num_levels; 3776 3777 if ((table == NULL) || (limits == NULL)) 3778 return false; 3779 3780 data = table->mask_low; 3781 3782 num_bits = hweight32(data); 3783 3784 if (num_bits == 0) 3785 return false; 3786 3787 num_levels = (1 << num_bits); 3788 3789 if (table->count != num_levels) 3790 return false; 3791 3792 if (limits->count != (num_levels - 1)) 3793 return false; 3794 3795 return true; 3796 } 3797 3798 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3799 u32 max_voltage_steps, 3800 struct atom_voltage_table *voltage_table) 3801 { 3802 unsigned int i, diff; 3803 3804 if (voltage_table->count <= max_voltage_steps) 3805 return; 3806 3807 diff = voltage_table->count - max_voltage_steps; 3808 3809 for (i= 0; i < max_voltage_steps; i++) 3810 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3811 3812 voltage_table->count = max_voltage_steps; 3813 } 3814 3815 static int si_construct_voltage_tables(struct radeon_device *rdev) 3816 { 3817 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3818 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3819 struct si_power_info *si_pi = si_get_pi(rdev); 3820 int ret; 3821 3822 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3823 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3824 if (ret) 3825 return ret; 3826 3827 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3828 si_trim_voltage_table_to_fit_state_table(rdev, 3829 SISLANDS_MAX_NO_VREG_STEPS, 3830 &eg_pi->vddc_voltage_table); 3831 3832 if (eg_pi->vddci_control) { 3833 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3834 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3835 if (ret) 3836 return ret; 3837 3838 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3839 si_trim_voltage_table_to_fit_state_table(rdev, 3840 SISLANDS_MAX_NO_VREG_STEPS, 3841 &eg_pi->vddci_voltage_table); 3842 } 3843 3844 if (pi->mvdd_control) { 3845 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3846 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3847 3848 if (ret) { 3849 pi->mvdd_control = false; 3850 return ret; 3851 } 3852 3853 if (si_pi->mvdd_voltage_table.count == 0) { 3854 pi->mvdd_control = false; 3855 return -EINVAL; 3856 } 3857 3858 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3859 si_trim_voltage_table_to_fit_state_table(rdev, 3860 SISLANDS_MAX_NO_VREG_STEPS, 3861 &si_pi->mvdd_voltage_table); 3862 } 3863 3864 if (si_pi->vddc_phase_shed_control) { 3865 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3866 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3867 if (ret) 3868 si_pi->vddc_phase_shed_control = false; 3869 3870 if ((si_pi->vddc_phase_shed_table.count == 0) || 3871 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3872 si_pi->vddc_phase_shed_control = false; 3873 } 3874 3875 return 0; 3876 } 3877 3878 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3879 const struct atom_voltage_table *voltage_table, 3880 SISLANDS_SMC_STATETABLE *table) 3881 { 3882 unsigned int i; 3883 3884 for (i = 0; i < voltage_table->count; i++) 3885 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3886 } 3887 3888 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3889 SISLANDS_SMC_STATETABLE *table) 3890 { 3891 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3892 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3893 struct si_power_info *si_pi = si_get_pi(rdev); 3894 u8 i; 3895 3896 if (eg_pi->vddc_voltage_table.count) { 3897 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3898 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3899 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3900 3901 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3902 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3903 table->maxVDDCIndexInPPTable = i; 3904 break; 3905 } 3906 } 3907 } 3908 3909 if (eg_pi->vddci_voltage_table.count) { 3910 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3911 3912 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3913 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3914 } 3915 3916 3917 if (si_pi->mvdd_voltage_table.count) { 3918 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3919 3920 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3921 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3922 } 3923 3924 if (si_pi->vddc_phase_shed_control) { 3925 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3926 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3927 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3928 3929 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3930 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3931 3932 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3933 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3934 } else { 3935 si_pi->vddc_phase_shed_control = false; 3936 } 3937 } 3938 3939 return 0; 3940 } 3941 3942 static int si_populate_voltage_value(struct radeon_device *rdev, 3943 const struct atom_voltage_table *table, 3944 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3945 { 3946 unsigned int i; 3947 3948 for (i = 0; i < table->count; i++) { 3949 if (value <= table->entries[i].value) { 3950 voltage->index = (u8)i; 3951 voltage->value = cpu_to_be16(table->entries[i].value); 3952 break; 3953 } 3954 } 3955 3956 if (i >= table->count) 3957 return -EINVAL; 3958 3959 return 0; 3960 } 3961 3962 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3963 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3964 { 3965 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3966 struct si_power_info *si_pi = si_get_pi(rdev); 3967 3968 if (pi->mvdd_control) { 3969 if (mclk <= pi->mvdd_split_frequency) 3970 voltage->index = 0; 3971 else 3972 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3973 3974 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3975 } 3976 return 0; 3977 } 3978 3979 static int si_get_std_voltage_value(struct radeon_device *rdev, 3980 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 3981 u16 *std_voltage) 3982 { 3983 u16 v_index; 3984 bool voltage_found = false; 3985 *std_voltage = be16_to_cpu(voltage->value); 3986 3987 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 3988 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 3989 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 3990 return -EINVAL; 3991 3992 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3993 if (be16_to_cpu(voltage->value) == 3994 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3995 voltage_found = true; 3996 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3997 *std_voltage = 3998 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3999 else 4000 *std_voltage = 4001 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4002 break; 4003 } 4004 } 4005 4006 if (!voltage_found) { 4007 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4008 if (be16_to_cpu(voltage->value) <= 4009 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4010 voltage_found = true; 4011 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4012 *std_voltage = 4013 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4014 else 4015 *std_voltage = 4016 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4017 break; 4018 } 4019 } 4020 } 4021 } else { 4022 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4023 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4024 } 4025 } 4026 4027 return 0; 4028 } 4029 4030 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4031 u16 value, u8 index, 4032 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4033 { 4034 voltage->index = index; 4035 voltage->value = cpu_to_be16(value); 4036 4037 return 0; 4038 } 4039 4040 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4041 const struct radeon_phase_shedding_limits_table *limits, 4042 u16 voltage, u32 sclk, u32 mclk, 4043 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4044 { 4045 unsigned int i; 4046 4047 for (i = 0; i < limits->count; i++) { 4048 if ((voltage <= limits->entries[i].voltage) && 4049 (sclk <= limits->entries[i].sclk) && 4050 (mclk <= limits->entries[i].mclk)) 4051 break; 4052 } 4053 4054 smc_voltage->phase_settings = (u8)i; 4055 4056 return 0; 4057 } 4058 4059 static int si_init_arb_table_index(struct radeon_device *rdev) 4060 { 4061 struct si_power_info *si_pi = si_get_pi(rdev); 4062 u32 tmp; 4063 int ret; 4064 4065 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4066 if (ret) 4067 return ret; 4068 4069 tmp &= 0x00FFFFFF; 4070 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4071 4072 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4073 } 4074 4075 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4076 { 4077 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4078 } 4079 4080 static int si_reset_to_default(struct radeon_device *rdev) 4081 { 4082 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4083 0 : -EINVAL; 4084 } 4085 4086 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4087 { 4088 struct si_power_info *si_pi = si_get_pi(rdev); 4089 u32 tmp; 4090 int ret; 4091 4092 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4093 &tmp, si_pi->sram_end); 4094 if (ret) 4095 return ret; 4096 4097 tmp = (tmp >> 24) & 0xff; 4098 4099 if (tmp == MC_CG_ARB_FREQ_F0) 4100 return 0; 4101 4102 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4103 } 4104 4105 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4106 u32 engine_clock) 4107 { 4108 u32 dram_rows; 4109 u32 dram_refresh_rate; 4110 u32 mc_arb_rfsh_rate; 4111 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4112 4113 if (tmp >= 4) 4114 dram_rows = 16384; 4115 else 4116 dram_rows = 1 << (tmp + 10); 4117 4118 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4119 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4120 4121 return mc_arb_rfsh_rate; 4122 } 4123 4124 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4125 struct rv7xx_pl *pl, 4126 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4127 { 4128 u32 dram_timing; 4129 u32 dram_timing2; 4130 u32 burst_time; 4131 4132 arb_regs->mc_arb_rfsh_rate = 4133 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4134 4135 radeon_atom_set_engine_dram_timings(rdev, 4136 pl->sclk, 4137 pl->mclk); 4138 4139 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4140 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4141 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4142 4143 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4144 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4145 arb_regs->mc_arb_burst_time = (u8)burst_time; 4146 4147 return 0; 4148 } 4149 4150 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4151 struct radeon_ps *radeon_state, 4152 unsigned int first_arb_set) 4153 { 4154 struct si_power_info *si_pi = si_get_pi(rdev); 4155 struct ni_ps *state = ni_get_ps(radeon_state); 4156 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4157 int i, ret = 0; 4158 4159 for (i = 0; i < state->performance_level_count; i++) { 4160 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4161 if (ret) 4162 break; 4163 ret = si_copy_bytes_to_smc(rdev, 4164 si_pi->arb_table_start + 4165 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4166 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4167 (u8 *)&arb_regs, 4168 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4169 si_pi->sram_end); 4170 if (ret) 4171 break; 4172 } 4173 4174 return ret; 4175 } 4176 4177 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4178 struct radeon_ps *radeon_new_state) 4179 { 4180 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4181 SISLANDS_DRIVER_STATE_ARB_INDEX); 4182 } 4183 4184 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4185 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4186 { 4187 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4188 struct si_power_info *si_pi = si_get_pi(rdev); 4189 4190 if (pi->mvdd_control) 4191 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4192 si_pi->mvdd_bootup_value, voltage); 4193 4194 return 0; 4195 } 4196 4197 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4198 struct radeon_ps *radeon_initial_state, 4199 SISLANDS_SMC_STATETABLE *table) 4200 { 4201 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4202 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4203 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4204 struct si_power_info *si_pi = si_get_pi(rdev); 4205 u32 reg; 4206 int ret; 4207 4208 table->initialState.levels[0].mclk.vDLL_CNTL = 4209 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4210 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4211 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4212 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4213 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4214 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4215 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4216 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4217 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4218 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4219 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4220 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4221 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4222 table->initialState.levels[0].mclk.vMPLL_SS = 4223 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4224 table->initialState.levels[0].mclk.vMPLL_SS2 = 4225 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4226 4227 table->initialState.levels[0].mclk.mclk_value = 4228 cpu_to_be32(initial_state->performance_levels[0].mclk); 4229 4230 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4231 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4232 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4233 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4234 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4235 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4236 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4237 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4238 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4239 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4240 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4241 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4242 4243 table->initialState.levels[0].sclk.sclk_value = 4244 cpu_to_be32(initial_state->performance_levels[0].sclk); 4245 4246 table->initialState.levels[0].arbRefreshState = 4247 SISLANDS_INITIAL_STATE_ARB_INDEX; 4248 4249 table->initialState.levels[0].ACIndex = 0; 4250 4251 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4252 initial_state->performance_levels[0].vddc, 4253 &table->initialState.levels[0].vddc); 4254 4255 if (!ret) { 4256 u16 std_vddc; 4257 4258 ret = si_get_std_voltage_value(rdev, 4259 &table->initialState.levels[0].vddc, 4260 &std_vddc); 4261 if (!ret) 4262 si_populate_std_voltage_value(rdev, std_vddc, 4263 table->initialState.levels[0].vddc.index, 4264 &table->initialState.levels[0].std_vddc); 4265 } 4266 4267 if (eg_pi->vddci_control) 4268 si_populate_voltage_value(rdev, 4269 &eg_pi->vddci_voltage_table, 4270 initial_state->performance_levels[0].vddci, 4271 &table->initialState.levels[0].vddci); 4272 4273 if (si_pi->vddc_phase_shed_control) 4274 si_populate_phase_shedding_value(rdev, 4275 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4276 initial_state->performance_levels[0].vddc, 4277 initial_state->performance_levels[0].sclk, 4278 initial_state->performance_levels[0].mclk, 4279 &table->initialState.levels[0].vddc); 4280 4281 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4282 4283 reg = CG_R(0xffff) | CG_L(0); 4284 table->initialState.levels[0].aT = cpu_to_be32(reg); 4285 4286 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4287 4288 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4289 4290 if (pi->mem_gddr5) { 4291 table->initialState.levels[0].strobeMode = 4292 si_get_strobe_mode_settings(rdev, 4293 initial_state->performance_levels[0].mclk); 4294 4295 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4296 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4297 else 4298 table->initialState.levels[0].mcFlags = 0; 4299 } 4300 4301 table->initialState.levelCount = 1; 4302 4303 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4304 4305 table->initialState.levels[0].dpm2.MaxPS = 0; 4306 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4307 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4308 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4309 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4310 4311 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4312 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4313 4314 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4315 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4316 4317 return 0; 4318 } 4319 4320 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4321 SISLANDS_SMC_STATETABLE *table) 4322 { 4323 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4324 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4325 struct si_power_info *si_pi = si_get_pi(rdev); 4326 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4327 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4328 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4329 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4330 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4331 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4332 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4333 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4334 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4335 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4336 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4337 u32 reg; 4338 int ret; 4339 4340 table->ACPIState = table->initialState; 4341 4342 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4343 4344 if (pi->acpi_vddc) { 4345 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4346 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4347 if (!ret) { 4348 u16 std_vddc; 4349 4350 ret = si_get_std_voltage_value(rdev, 4351 &table->ACPIState.levels[0].vddc, &std_vddc); 4352 if (!ret) 4353 si_populate_std_voltage_value(rdev, std_vddc, 4354 table->ACPIState.levels[0].vddc.index, 4355 &table->ACPIState.levels[0].std_vddc); 4356 } 4357 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4358 4359 if (si_pi->vddc_phase_shed_control) { 4360 si_populate_phase_shedding_value(rdev, 4361 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4362 pi->acpi_vddc, 4363 0, 4364 0, 4365 &table->ACPIState.levels[0].vddc); 4366 } 4367 } else { 4368 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4369 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4370 if (!ret) { 4371 u16 std_vddc; 4372 4373 ret = si_get_std_voltage_value(rdev, 4374 &table->ACPIState.levels[0].vddc, &std_vddc); 4375 4376 if (!ret) 4377 si_populate_std_voltage_value(rdev, std_vddc, 4378 table->ACPIState.levels[0].vddc.index, 4379 &table->ACPIState.levels[0].std_vddc); 4380 } 4381 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4382 si_pi->sys_pcie_mask, 4383 si_pi->boot_pcie_gen, 4384 RADEON_PCIE_GEN1); 4385 4386 if (si_pi->vddc_phase_shed_control) 4387 si_populate_phase_shedding_value(rdev, 4388 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4389 pi->min_vddc_in_table, 4390 0, 4391 0, 4392 &table->ACPIState.levels[0].vddc); 4393 } 4394 4395 if (pi->acpi_vddc) { 4396 if (eg_pi->acpi_vddci) 4397 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4398 eg_pi->acpi_vddci, 4399 &table->ACPIState.levels[0].vddci); 4400 } 4401 4402 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4403 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4404 4405 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4406 4407 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4408 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4409 4410 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4411 cpu_to_be32(dll_cntl); 4412 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4413 cpu_to_be32(mclk_pwrmgt_cntl); 4414 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4415 cpu_to_be32(mpll_ad_func_cntl); 4416 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4417 cpu_to_be32(mpll_dq_func_cntl); 4418 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4419 cpu_to_be32(mpll_func_cntl); 4420 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4421 cpu_to_be32(mpll_func_cntl_1); 4422 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4423 cpu_to_be32(mpll_func_cntl_2); 4424 table->ACPIState.levels[0].mclk.vMPLL_SS = 4425 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4426 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4427 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4428 4429 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4430 cpu_to_be32(spll_func_cntl); 4431 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4432 cpu_to_be32(spll_func_cntl_2); 4433 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4434 cpu_to_be32(spll_func_cntl_3); 4435 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4436 cpu_to_be32(spll_func_cntl_4); 4437 4438 table->ACPIState.levels[0].mclk.mclk_value = 0; 4439 table->ACPIState.levels[0].sclk.sclk_value = 0; 4440 4441 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4442 4443 if (eg_pi->dynamic_ac_timing) 4444 table->ACPIState.levels[0].ACIndex = 0; 4445 4446 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4447 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4448 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4449 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4450 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4451 4452 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4453 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4454 4455 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4456 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4457 4458 return 0; 4459 } 4460 4461 static int si_populate_ulv_state(struct radeon_device *rdev, 4462 SISLANDS_SMC_SWSTATE *state) 4463 { 4464 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4465 struct si_power_info *si_pi = si_get_pi(rdev); 4466 struct si_ulv_param *ulv = &si_pi->ulv; 4467 u32 sclk_in_sr = 1350; /* ??? */ 4468 int ret; 4469 4470 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4471 &state->levels[0]); 4472 if (!ret) { 4473 if (eg_pi->sclk_deep_sleep) { 4474 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4475 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4476 else 4477 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4478 } 4479 if (ulv->one_pcie_lane_in_ulv) 4480 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4481 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4482 state->levels[0].ACIndex = 1; 4483 state->levels[0].std_vddc = state->levels[0].vddc; 4484 state->levelCount = 1; 4485 4486 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4487 } 4488 4489 return ret; 4490 } 4491 4492 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4493 { 4494 struct si_power_info *si_pi = si_get_pi(rdev); 4495 struct si_ulv_param *ulv = &si_pi->ulv; 4496 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4497 int ret; 4498 4499 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4500 &arb_regs); 4501 if (ret) 4502 return ret; 4503 4504 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4505 ulv->volt_change_delay); 4506 4507 ret = si_copy_bytes_to_smc(rdev, 4508 si_pi->arb_table_start + 4509 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4510 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4511 (u8 *)&arb_regs, 4512 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4513 si_pi->sram_end); 4514 4515 return ret; 4516 } 4517 4518 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4519 { 4520 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4521 4522 pi->mvdd_split_frequency = 30000; 4523 } 4524 4525 static int si_init_smc_table(struct radeon_device *rdev) 4526 { 4527 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4528 struct si_power_info *si_pi = si_get_pi(rdev); 4529 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4530 const struct si_ulv_param *ulv = &si_pi->ulv; 4531 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4532 int ret; 4533 u32 lane_width; 4534 u32 vr_hot_gpio; 4535 4536 si_populate_smc_voltage_tables(rdev, table); 4537 4538 switch (rdev->pm.int_thermal_type) { 4539 case THERMAL_TYPE_SI: 4540 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4541 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4542 break; 4543 case THERMAL_TYPE_NONE: 4544 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4545 break; 4546 default: 4547 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4548 break; 4549 } 4550 4551 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4552 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4553 4554 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4555 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4556 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4557 } 4558 4559 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4560 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4561 4562 if (pi->mem_gddr5) 4563 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4564 4565 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4566 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4567 4568 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4569 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4570 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4571 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4572 vr_hot_gpio); 4573 } 4574 4575 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4576 if (ret) 4577 return ret; 4578 4579 ret = si_populate_smc_acpi_state(rdev, table); 4580 if (ret) 4581 return ret; 4582 4583 table->driverState = table->initialState; 4584 4585 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4586 SISLANDS_INITIAL_STATE_ARB_INDEX); 4587 if (ret) 4588 return ret; 4589 4590 if (ulv->supported && ulv->pl.vddc) { 4591 ret = si_populate_ulv_state(rdev, &table->ULVState); 4592 if (ret) 4593 return ret; 4594 4595 ret = si_program_ulv_memory_timing_parameters(rdev); 4596 if (ret) 4597 return ret; 4598 4599 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4600 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4601 4602 lane_width = radeon_get_pcie_lanes(rdev); 4603 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4604 } else { 4605 table->ULVState = table->initialState; 4606 } 4607 4608 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4609 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4610 si_pi->sram_end); 4611 } 4612 4613 static int si_calculate_sclk_params(struct radeon_device *rdev, 4614 u32 engine_clock, 4615 SISLANDS_SMC_SCLK_VALUE *sclk) 4616 { 4617 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4618 struct si_power_info *si_pi = si_get_pi(rdev); 4619 struct atom_clock_dividers dividers; 4620 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4621 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4622 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4623 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4624 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4625 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4626 u64 tmp; 4627 u32 reference_clock = rdev->clock.spll.reference_freq; 4628 u32 reference_divider; 4629 u32 fbdiv; 4630 int ret; 4631 4632 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4633 engine_clock, false, ÷rs); 4634 if (ret) 4635 return ret; 4636 4637 reference_divider = 1 + dividers.ref_div; 4638 4639 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4640 do_div(tmp, reference_clock); 4641 fbdiv = (u32) tmp; 4642 4643 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4644 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4645 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4646 4647 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4648 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4649 4650 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4651 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4652 spll_func_cntl_3 |= SPLL_DITHEN; 4653 4654 if (pi->sclk_ss) { 4655 struct radeon_atom_ss ss; 4656 u32 vco_freq = engine_clock * dividers.post_div; 4657 4658 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4659 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4660 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4661 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4662 4663 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4664 cg_spll_spread_spectrum |= CLK_S(clk_s); 4665 cg_spll_spread_spectrum |= SSEN; 4666 4667 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4668 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4669 } 4670 } 4671 4672 sclk->sclk_value = engine_clock; 4673 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4674 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4675 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4676 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4677 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4678 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4679 4680 return 0; 4681 } 4682 4683 static int si_populate_sclk_value(struct radeon_device *rdev, 4684 u32 engine_clock, 4685 SISLANDS_SMC_SCLK_VALUE *sclk) 4686 { 4687 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4688 int ret; 4689 4690 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4691 if (!ret) { 4692 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4693 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4694 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4695 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4696 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4697 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4698 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4699 } 4700 4701 return ret; 4702 } 4703 4704 static int si_populate_mclk_value(struct radeon_device *rdev, 4705 u32 engine_clock, 4706 u32 memory_clock, 4707 SISLANDS_SMC_MCLK_VALUE *mclk, 4708 bool strobe_mode, 4709 bool dll_state_on) 4710 { 4711 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4712 struct si_power_info *si_pi = si_get_pi(rdev); 4713 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4714 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4715 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4716 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4717 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4718 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4719 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4720 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4721 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4722 struct atom_mpll_param mpll_param; 4723 int ret; 4724 4725 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4726 if (ret) 4727 return ret; 4728 4729 mpll_func_cntl &= ~BWCTRL_MASK; 4730 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4731 4732 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4733 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4734 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4735 4736 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4737 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4738 4739 if (pi->mem_gddr5) { 4740 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4741 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4742 YCLK_POST_DIV(mpll_param.post_div); 4743 } 4744 4745 if (pi->mclk_ss) { 4746 struct radeon_atom_ss ss; 4747 u32 freq_nom; 4748 u32 tmp; 4749 u32 reference_clock = rdev->clock.mpll.reference_freq; 4750 4751 if (pi->mem_gddr5) 4752 freq_nom = memory_clock * 4; 4753 else 4754 freq_nom = memory_clock * 2; 4755 4756 tmp = freq_nom / reference_clock; 4757 tmp = tmp * tmp; 4758 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4759 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4760 u32 clks = reference_clock * 5 / ss.rate; 4761 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4762 4763 mpll_ss1 &= ~CLKV_MASK; 4764 mpll_ss1 |= CLKV(clkv); 4765 4766 mpll_ss2 &= ~CLKS_MASK; 4767 mpll_ss2 |= CLKS(clks); 4768 } 4769 } 4770 4771 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4772 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4773 4774 if (dll_state_on) 4775 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4776 else 4777 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4778 4779 mclk->mclk_value = cpu_to_be32(memory_clock); 4780 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4781 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4782 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4783 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4784 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4785 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4786 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4787 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4788 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4789 4790 return 0; 4791 } 4792 4793 static void si_populate_smc_sp(struct radeon_device *rdev, 4794 struct radeon_ps *radeon_state, 4795 SISLANDS_SMC_SWSTATE *smc_state) 4796 { 4797 struct ni_ps *ps = ni_get_ps(radeon_state); 4798 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4799 int i; 4800 4801 for (i = 0; i < ps->performance_level_count - 1; i++) 4802 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4803 4804 smc_state->levels[ps->performance_level_count - 1].bSP = 4805 cpu_to_be32(pi->psp); 4806 } 4807 4808 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4809 struct rv7xx_pl *pl, 4810 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4811 { 4812 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4813 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4814 struct si_power_info *si_pi = si_get_pi(rdev); 4815 int ret; 4816 bool dll_state_on; 4817 u16 std_vddc; 4818 bool gmc_pg = false; 4819 4820 if (eg_pi->pcie_performance_request && 4821 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4822 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4823 else 4824 level->gen2PCIE = (u8)pl->pcie_gen; 4825 4826 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4827 if (ret) 4828 return ret; 4829 4830 level->mcFlags = 0; 4831 4832 if (pi->mclk_stutter_mode_threshold && 4833 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4834 !eg_pi->uvd_enabled && 4835 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4836 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4837 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4838 4839 if (gmc_pg) 4840 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4841 } 4842 4843 if (pi->mem_gddr5) { 4844 if (pl->mclk > pi->mclk_edc_enable_threshold) 4845 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4846 4847 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4848 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4849 4850 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4851 4852 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4853 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4854 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4855 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4856 else 4857 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4858 } else { 4859 dll_state_on = false; 4860 } 4861 } else { 4862 level->strobeMode = si_get_strobe_mode_settings(rdev, 4863 pl->mclk); 4864 4865 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4866 } 4867 4868 ret = si_populate_mclk_value(rdev, 4869 pl->sclk, 4870 pl->mclk, 4871 &level->mclk, 4872 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4873 if (ret) 4874 return ret; 4875 4876 ret = si_populate_voltage_value(rdev, 4877 &eg_pi->vddc_voltage_table, 4878 pl->vddc, &level->vddc); 4879 if (ret) 4880 return ret; 4881 4882 4883 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4884 if (ret) 4885 return ret; 4886 4887 ret = si_populate_std_voltage_value(rdev, std_vddc, 4888 level->vddc.index, &level->std_vddc); 4889 if (ret) 4890 return ret; 4891 4892 if (eg_pi->vddci_control) { 4893 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4894 pl->vddci, &level->vddci); 4895 if (ret) 4896 return ret; 4897 } 4898 4899 if (si_pi->vddc_phase_shed_control) { 4900 ret = si_populate_phase_shedding_value(rdev, 4901 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4902 pl->vddc, 4903 pl->sclk, 4904 pl->mclk, 4905 &level->vddc); 4906 if (ret) 4907 return ret; 4908 } 4909 4910 level->MaxPoweredUpCU = si_pi->max_cu; 4911 4912 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4913 4914 return ret; 4915 } 4916 4917 static int si_populate_smc_t(struct radeon_device *rdev, 4918 struct radeon_ps *radeon_state, 4919 SISLANDS_SMC_SWSTATE *smc_state) 4920 { 4921 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4922 struct ni_ps *state = ni_get_ps(radeon_state); 4923 u32 a_t; 4924 u32 t_l, t_h; 4925 u32 high_bsp; 4926 int i, ret; 4927 4928 if (state->performance_level_count >= 9) 4929 return -EINVAL; 4930 4931 if (state->performance_level_count < 2) { 4932 a_t = CG_R(0xffff) | CG_L(0); 4933 smc_state->levels[0].aT = cpu_to_be32(a_t); 4934 return 0; 4935 } 4936 4937 smc_state->levels[0].aT = cpu_to_be32(0); 4938 4939 for (i = 0; i <= state->performance_level_count - 2; i++) { 4940 ret = r600_calculate_at( 4941 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4942 100 * R600_AH_DFLT, 4943 state->performance_levels[i + 1].sclk, 4944 state->performance_levels[i].sclk, 4945 &t_l, 4946 &t_h); 4947 4948 if (ret) { 4949 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4950 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4951 } 4952 4953 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4954 a_t |= CG_R(t_l * pi->bsp / 20000); 4955 smc_state->levels[i].aT = cpu_to_be32(a_t); 4956 4957 high_bsp = (i == state->performance_level_count - 2) ? 4958 pi->pbsp : pi->bsp; 4959 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4960 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4961 } 4962 4963 return 0; 4964 } 4965 4966 static int si_disable_ulv(struct radeon_device *rdev) 4967 { 4968 struct si_power_info *si_pi = si_get_pi(rdev); 4969 struct si_ulv_param *ulv = &si_pi->ulv; 4970 4971 if (ulv->supported) 4972 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4973 0 : -EINVAL; 4974 4975 return 0; 4976 } 4977 4978 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 4979 struct radeon_ps *radeon_state) 4980 { 4981 const struct si_power_info *si_pi = si_get_pi(rdev); 4982 const struct si_ulv_param *ulv = &si_pi->ulv; 4983 const struct ni_ps *state = ni_get_ps(radeon_state); 4984 int i; 4985 4986 if (state->performance_levels[0].mclk != ulv->pl.mclk) 4987 return false; 4988 4989 /* XXX validate against display requirements! */ 4990 4991 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 4992 if (rdev->clock.current_dispclk <= 4993 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 4994 if (ulv->pl.vddc < 4995 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 4996 return false; 4997 } 4998 } 4999 5000 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5001 return false; 5002 5003 return true; 5004 } 5005 5006 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5007 struct radeon_ps *radeon_new_state) 5008 { 5009 const struct si_power_info *si_pi = si_get_pi(rdev); 5010 const struct si_ulv_param *ulv = &si_pi->ulv; 5011 5012 if (ulv->supported) { 5013 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5014 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5015 0 : -EINVAL; 5016 } 5017 return 0; 5018 } 5019 5020 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5021 struct radeon_ps *radeon_state, 5022 SISLANDS_SMC_SWSTATE *smc_state) 5023 { 5024 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5025 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5026 struct si_power_info *si_pi = si_get_pi(rdev); 5027 struct ni_ps *state = ni_get_ps(radeon_state); 5028 int i, ret; 5029 u32 threshold; 5030 u32 sclk_in_sr = 1350; /* ??? */ 5031 5032 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5033 return -EINVAL; 5034 5035 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5036 5037 if (radeon_state->vclk && radeon_state->dclk) { 5038 eg_pi->uvd_enabled = true; 5039 if (eg_pi->smu_uvd_hs) 5040 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5041 } else { 5042 eg_pi->uvd_enabled = false; 5043 } 5044 5045 if (state->dc_compatible) 5046 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5047 5048 smc_state->levelCount = 0; 5049 for (i = 0; i < state->performance_level_count; i++) { 5050 if (eg_pi->sclk_deep_sleep) { 5051 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5052 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5053 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5054 else 5055 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5056 } 5057 } 5058 5059 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5060 &smc_state->levels[i]); 5061 smc_state->levels[i].arbRefreshState = 5062 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5063 5064 if (ret) 5065 return ret; 5066 5067 if (ni_pi->enable_power_containment) 5068 smc_state->levels[i].displayWatermark = 5069 (state->performance_levels[i].sclk < threshold) ? 5070 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5071 else 5072 smc_state->levels[i].displayWatermark = (i < 2) ? 5073 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5074 5075 if (eg_pi->dynamic_ac_timing) 5076 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5077 else 5078 smc_state->levels[i].ACIndex = 0; 5079 5080 smc_state->levelCount++; 5081 } 5082 5083 si_write_smc_soft_register(rdev, 5084 SI_SMC_SOFT_REGISTER_watermark_threshold, 5085 threshold / 512); 5086 5087 si_populate_smc_sp(rdev, radeon_state, smc_state); 5088 5089 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5090 if (ret) 5091 ni_pi->enable_power_containment = false; 5092 5093 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5094 if (ret) 5095 ni_pi->enable_sq_ramping = false; 5096 5097 return si_populate_smc_t(rdev, radeon_state, smc_state); 5098 } 5099 5100 static int si_upload_sw_state(struct radeon_device *rdev, 5101 struct radeon_ps *radeon_new_state) 5102 { 5103 struct si_power_info *si_pi = si_get_pi(rdev); 5104 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5105 int ret; 5106 u32 address = si_pi->state_table_start + 5107 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5108 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5109 ((new_state->performance_level_count - 1) * 5110 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5111 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5112 5113 memset(smc_state, 0, state_size); 5114 5115 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5116 if (ret) 5117 return ret; 5118 5119 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5120 state_size, si_pi->sram_end); 5121 5122 return ret; 5123 } 5124 5125 static int si_upload_ulv_state(struct radeon_device *rdev) 5126 { 5127 struct si_power_info *si_pi = si_get_pi(rdev); 5128 struct si_ulv_param *ulv = &si_pi->ulv; 5129 int ret = 0; 5130 5131 if (ulv->supported && ulv->pl.vddc) { 5132 u32 address = si_pi->state_table_start + 5133 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5134 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5135 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5136 5137 memset(smc_state, 0, state_size); 5138 5139 ret = si_populate_ulv_state(rdev, smc_state); 5140 if (!ret) 5141 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5142 state_size, si_pi->sram_end); 5143 } 5144 5145 return ret; 5146 } 5147 5148 static int si_upload_smc_data(struct radeon_device *rdev) 5149 { 5150 struct radeon_crtc *radeon_crtc = NULL; 5151 int i; 5152 5153 if (rdev->pm.dpm.new_active_crtc_count == 0) 5154 return 0; 5155 5156 for (i = 0; i < rdev->num_crtc; i++) { 5157 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5158 radeon_crtc = rdev->mode_info.crtcs[i]; 5159 break; 5160 } 5161 } 5162 5163 if (radeon_crtc == NULL) 5164 return 0; 5165 5166 if (radeon_crtc->line_time <= 0) 5167 return 0; 5168 5169 if (si_write_smc_soft_register(rdev, 5170 SI_SMC_SOFT_REGISTER_crtc_index, 5171 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5172 return 0; 5173 5174 if (si_write_smc_soft_register(rdev, 5175 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5176 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5177 return 0; 5178 5179 if (si_write_smc_soft_register(rdev, 5180 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5181 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5182 return 0; 5183 5184 return 0; 5185 } 5186 5187 static int si_set_mc_special_registers(struct radeon_device *rdev, 5188 struct si_mc_reg_table *table) 5189 { 5190 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5191 u8 i, j, k; 5192 u32 temp_reg; 5193 5194 for (i = 0, j = table->last; i < table->last; i++) { 5195 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5196 return -EINVAL; 5197 switch (table->mc_reg_address[i].s1 << 2) { 5198 case MC_SEQ_MISC1: 5199 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5200 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5201 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5202 for (k = 0; k < table->num_entries; k++) 5203 table->mc_reg_table_entry[k].mc_data[j] = 5204 ((temp_reg & 0xffff0000)) | 5205 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5206 j++; 5207 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5208 return -EINVAL; 5209 5210 temp_reg = RREG32(MC_PMG_CMD_MRS); 5211 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5212 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5213 for (k = 0; k < table->num_entries; k++) { 5214 table->mc_reg_table_entry[k].mc_data[j] = 5215 (temp_reg & 0xffff0000) | 5216 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5217 if (!pi->mem_gddr5) 5218 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5219 } 5220 j++; 5221 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5222 return -EINVAL; 5223 5224 if (!pi->mem_gddr5) { 5225 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5226 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5227 for (k = 0; k < table->num_entries; k++) 5228 table->mc_reg_table_entry[k].mc_data[j] = 5229 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5230 j++; 5231 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5232 return -EINVAL; 5233 } 5234 break; 5235 case MC_SEQ_RESERVE_M: 5236 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5237 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5238 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5239 for(k = 0; k < table->num_entries; k++) 5240 table->mc_reg_table_entry[k].mc_data[j] = 5241 (temp_reg & 0xffff0000) | 5242 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5243 j++; 5244 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5245 return -EINVAL; 5246 break; 5247 default: 5248 break; 5249 } 5250 } 5251 5252 table->last = j; 5253 5254 return 0; 5255 } 5256 5257 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5258 { 5259 bool result = true; 5260 5261 switch (in_reg) { 5262 case MC_SEQ_RAS_TIMING >> 2: 5263 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5264 break; 5265 case MC_SEQ_CAS_TIMING >> 2: 5266 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5267 break; 5268 case MC_SEQ_MISC_TIMING >> 2: 5269 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5270 break; 5271 case MC_SEQ_MISC_TIMING2 >> 2: 5272 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5273 break; 5274 case MC_SEQ_RD_CTL_D0 >> 2: 5275 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5276 break; 5277 case MC_SEQ_RD_CTL_D1 >> 2: 5278 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5279 break; 5280 case MC_SEQ_WR_CTL_D0 >> 2: 5281 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5282 break; 5283 case MC_SEQ_WR_CTL_D1 >> 2: 5284 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5285 break; 5286 case MC_PMG_CMD_EMRS >> 2: 5287 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5288 break; 5289 case MC_PMG_CMD_MRS >> 2: 5290 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5291 break; 5292 case MC_PMG_CMD_MRS1 >> 2: 5293 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5294 break; 5295 case MC_SEQ_PMG_TIMING >> 2: 5296 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5297 break; 5298 case MC_PMG_CMD_MRS2 >> 2: 5299 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5300 break; 5301 case MC_SEQ_WR_CTL_2 >> 2: 5302 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5303 break; 5304 default: 5305 result = false; 5306 break; 5307 } 5308 5309 return result; 5310 } 5311 5312 static void si_set_valid_flag(struct si_mc_reg_table *table) 5313 { 5314 u8 i, j; 5315 5316 for (i = 0; i < table->last; i++) { 5317 for (j = 1; j < table->num_entries; j++) { 5318 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5319 table->valid_flag |= 1 << i; 5320 break; 5321 } 5322 } 5323 } 5324 } 5325 5326 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5327 { 5328 u32 i; 5329 u16 address; 5330 5331 for (i = 0; i < table->last; i++) 5332 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5333 address : table->mc_reg_address[i].s1; 5334 5335 } 5336 5337 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5338 struct si_mc_reg_table *si_table) 5339 { 5340 u8 i, j; 5341 5342 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5343 return -EINVAL; 5344 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5345 return -EINVAL; 5346 5347 for (i = 0; i < table->last; i++) 5348 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5349 si_table->last = table->last; 5350 5351 for (i = 0; i < table->num_entries; i++) { 5352 si_table->mc_reg_table_entry[i].mclk_max = 5353 table->mc_reg_table_entry[i].mclk_max; 5354 for (j = 0; j < table->last; j++) { 5355 si_table->mc_reg_table_entry[i].mc_data[j] = 5356 table->mc_reg_table_entry[i].mc_data[j]; 5357 } 5358 } 5359 si_table->num_entries = table->num_entries; 5360 5361 return 0; 5362 } 5363 5364 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5365 { 5366 struct si_power_info *si_pi = si_get_pi(rdev); 5367 struct atom_mc_reg_table *table; 5368 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5369 u8 module_index = rv770_get_memory_module_index(rdev); 5370 int ret; 5371 5372 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5373 if (!table) 5374 return -ENOMEM; 5375 5376 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5377 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5378 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5379 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5380 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5381 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5382 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5383 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5384 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5385 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5386 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5387 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5388 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5389 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5390 5391 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5392 if (ret) 5393 goto init_mc_done; 5394 5395 ret = si_copy_vbios_mc_reg_table(table, si_table); 5396 if (ret) 5397 goto init_mc_done; 5398 5399 si_set_s0_mc_reg_index(si_table); 5400 5401 ret = si_set_mc_special_registers(rdev, si_table); 5402 if (ret) 5403 goto init_mc_done; 5404 5405 si_set_valid_flag(si_table); 5406 5407 init_mc_done: 5408 kfree(table); 5409 5410 return ret; 5411 5412 } 5413 5414 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5415 SMC_SIslands_MCRegisters *mc_reg_table) 5416 { 5417 struct si_power_info *si_pi = si_get_pi(rdev); 5418 u32 i, j; 5419 5420 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5421 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5422 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5423 break; 5424 mc_reg_table->address[i].s0 = 5425 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5426 mc_reg_table->address[i].s1 = 5427 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5428 i++; 5429 } 5430 } 5431 mc_reg_table->last = (u8)i; 5432 } 5433 5434 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5435 SMC_SIslands_MCRegisterSet *data, 5436 u32 num_entries, u32 valid_flag) 5437 { 5438 u32 i, j; 5439 5440 for(i = 0, j = 0; j < num_entries; j++) { 5441 if (valid_flag & (1 << j)) { 5442 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5443 i++; 5444 } 5445 } 5446 } 5447 5448 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5449 struct rv7xx_pl *pl, 5450 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5451 { 5452 struct si_power_info *si_pi = si_get_pi(rdev); 5453 u32 i = 0; 5454 5455 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5456 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5457 break; 5458 } 5459 5460 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5461 --i; 5462 5463 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5464 mc_reg_table_data, si_pi->mc_reg_table.last, 5465 si_pi->mc_reg_table.valid_flag); 5466 } 5467 5468 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5469 struct radeon_ps *radeon_state, 5470 SMC_SIslands_MCRegisters *mc_reg_table) 5471 { 5472 struct ni_ps *state = ni_get_ps(radeon_state); 5473 int i; 5474 5475 for (i = 0; i < state->performance_level_count; i++) { 5476 si_convert_mc_reg_table_entry_to_smc(rdev, 5477 &state->performance_levels[i], 5478 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5479 } 5480 } 5481 5482 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5483 struct radeon_ps *radeon_boot_state) 5484 { 5485 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5486 struct si_power_info *si_pi = si_get_pi(rdev); 5487 struct si_ulv_param *ulv = &si_pi->ulv; 5488 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5489 5490 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5491 5492 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5493 5494 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5495 5496 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5497 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5498 5499 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5500 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5501 si_pi->mc_reg_table.last, 5502 si_pi->mc_reg_table.valid_flag); 5503 5504 if (ulv->supported && ulv->pl.vddc != 0) 5505 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5506 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5507 else 5508 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5509 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5510 si_pi->mc_reg_table.last, 5511 si_pi->mc_reg_table.valid_flag); 5512 5513 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5514 5515 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5516 (u8 *)smc_mc_reg_table, 5517 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5518 } 5519 5520 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5521 struct radeon_ps *radeon_new_state) 5522 { 5523 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5524 struct si_power_info *si_pi = si_get_pi(rdev); 5525 u32 address = si_pi->mc_reg_table_start + 5526 offsetof(SMC_SIslands_MCRegisters, 5527 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5528 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5529 5530 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5531 5532 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5533 5534 5535 return si_copy_bytes_to_smc(rdev, address, 5536 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5537 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5538 si_pi->sram_end); 5539 5540 } 5541 5542 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5543 { 5544 if (enable) 5545 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5546 else 5547 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5548 } 5549 5550 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5551 struct radeon_ps *radeon_state) 5552 { 5553 struct ni_ps *state = ni_get_ps(radeon_state); 5554 int i; 5555 u16 pcie_speed, max_speed = 0; 5556 5557 for (i = 0; i < state->performance_level_count; i++) { 5558 pcie_speed = state->performance_levels[i].pcie_gen; 5559 if (max_speed < pcie_speed) 5560 max_speed = pcie_speed; 5561 } 5562 return max_speed; 5563 } 5564 5565 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5566 { 5567 u32 speed_cntl; 5568 5569 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5570 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5571 5572 return (u16)speed_cntl; 5573 } 5574 5575 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5576 struct radeon_ps *radeon_new_state, 5577 struct radeon_ps *radeon_current_state) 5578 { 5579 struct si_power_info *si_pi = si_get_pi(rdev); 5580 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5581 enum radeon_pcie_gen current_link_speed; 5582 5583 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5584 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5585 else 5586 current_link_speed = si_pi->force_pcie_gen; 5587 5588 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5589 si_pi->pspp_notify_required = false; 5590 if (target_link_speed > current_link_speed) { 5591 switch (target_link_speed) { 5592 #if defined(CONFIG_ACPI) 5593 case RADEON_PCIE_GEN3: 5594 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5595 break; 5596 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5597 if (current_link_speed == RADEON_PCIE_GEN2) 5598 break; 5599 case RADEON_PCIE_GEN2: 5600 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5601 break; 5602 #endif 5603 default: 5604 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5605 break; 5606 } 5607 } else { 5608 if (target_link_speed < current_link_speed) 5609 si_pi->pspp_notify_required = true; 5610 } 5611 } 5612 5613 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5614 struct radeon_ps *radeon_new_state, 5615 struct radeon_ps *radeon_current_state) 5616 { 5617 struct si_power_info *si_pi = si_get_pi(rdev); 5618 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5619 u8 request; 5620 5621 if (si_pi->pspp_notify_required) { 5622 if (target_link_speed == RADEON_PCIE_GEN3) 5623 request = PCIE_PERF_REQ_PECI_GEN3; 5624 else if (target_link_speed == RADEON_PCIE_GEN2) 5625 request = PCIE_PERF_REQ_PECI_GEN2; 5626 else 5627 request = PCIE_PERF_REQ_PECI_GEN1; 5628 5629 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5630 (si_get_current_pcie_speed(rdev) > 0)) 5631 return; 5632 5633 #if defined(CONFIG_ACPI) 5634 radeon_acpi_pcie_performance_request(rdev, request, false); 5635 #endif 5636 } 5637 } 5638 5639 #if 0 5640 static int si_ds_request(struct radeon_device *rdev, 5641 bool ds_status_on, u32 count_write) 5642 { 5643 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5644 5645 if (eg_pi->sclk_deep_sleep) { 5646 if (ds_status_on) 5647 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5648 PPSMC_Result_OK) ? 5649 0 : -EINVAL; 5650 else 5651 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5652 PPSMC_Result_OK) ? 0 : -EINVAL; 5653 } 5654 return 0; 5655 } 5656 #endif 5657 5658 static void si_set_max_cu_value(struct radeon_device *rdev) 5659 { 5660 struct si_power_info *si_pi = si_get_pi(rdev); 5661 5662 if (rdev->family == CHIP_VERDE) { 5663 switch (rdev->pdev->device) { 5664 case 0x6820: 5665 case 0x6825: 5666 case 0x6821: 5667 case 0x6823: 5668 case 0x6827: 5669 si_pi->max_cu = 10; 5670 break; 5671 case 0x682D: 5672 case 0x6824: 5673 case 0x682F: 5674 case 0x6826: 5675 si_pi->max_cu = 8; 5676 break; 5677 case 0x6828: 5678 case 0x6830: 5679 case 0x6831: 5680 case 0x6838: 5681 case 0x6839: 5682 case 0x683D: 5683 si_pi->max_cu = 10; 5684 break; 5685 case 0x683B: 5686 case 0x683F: 5687 case 0x6829: 5688 si_pi->max_cu = 8; 5689 break; 5690 default: 5691 si_pi->max_cu = 0; 5692 break; 5693 } 5694 } else { 5695 si_pi->max_cu = 0; 5696 } 5697 } 5698 5699 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5700 struct radeon_clock_voltage_dependency_table *table) 5701 { 5702 u32 i; 5703 int j; 5704 u16 leakage_voltage; 5705 5706 if (table) { 5707 for (i = 0; i < table->count; i++) { 5708 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5709 table->entries[i].v, 5710 &leakage_voltage)) { 5711 case 0: 5712 table->entries[i].v = leakage_voltage; 5713 break; 5714 case -EAGAIN: 5715 return -EINVAL; 5716 case -EINVAL: 5717 default: 5718 break; 5719 } 5720 } 5721 5722 for (j = (table->count - 2); j >= 0; j--) { 5723 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5724 table->entries[j].v : table->entries[j + 1].v; 5725 } 5726 } 5727 return 0; 5728 } 5729 5730 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5731 { 5732 int ret = 0; 5733 5734 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5735 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5736 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5737 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5738 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5739 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5740 return ret; 5741 } 5742 5743 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5744 struct radeon_ps *radeon_new_state, 5745 struct radeon_ps *radeon_current_state) 5746 { 5747 u32 lane_width; 5748 u32 new_lane_width = 5749 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5750 u32 current_lane_width = 5751 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5752 5753 if (new_lane_width != current_lane_width) { 5754 radeon_set_pcie_lanes(rdev, new_lane_width); 5755 lane_width = radeon_get_pcie_lanes(rdev); 5756 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5757 } 5758 } 5759 5760 void si_dpm_setup_asic(struct radeon_device *rdev) 5761 { 5762 int r; 5763 5764 r = si_mc_load_microcode(rdev); 5765 if (r) 5766 DRM_ERROR("Failed to load MC firmware!\n"); 5767 rv770_get_memory_type(rdev); 5768 si_read_clock_registers(rdev); 5769 si_enable_acpi_power_management(rdev); 5770 } 5771 5772 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5773 int min_temp, int max_temp) 5774 { 5775 int low_temp = 0 * 1000; 5776 int high_temp = 255 * 1000; 5777 5778 if (low_temp < min_temp) 5779 low_temp = min_temp; 5780 if (high_temp > max_temp) 5781 high_temp = max_temp; 5782 if (high_temp < low_temp) { 5783 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5784 return -EINVAL; 5785 } 5786 5787 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5788 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5789 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5790 5791 rdev->pm.dpm.thermal.min_temp = low_temp; 5792 rdev->pm.dpm.thermal.max_temp = high_temp; 5793 5794 return 0; 5795 } 5796 5797 int si_dpm_enable(struct radeon_device *rdev) 5798 { 5799 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5800 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5801 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5802 int ret; 5803 5804 if (si_is_smc_running(rdev)) 5805 return -EINVAL; 5806 if (pi->voltage_control) 5807 si_enable_voltage_control(rdev, true); 5808 if (pi->mvdd_control) 5809 si_get_mvdd_configuration(rdev); 5810 if (pi->voltage_control) { 5811 ret = si_construct_voltage_tables(rdev); 5812 if (ret) { 5813 DRM_ERROR("si_construct_voltage_tables failed\n"); 5814 return ret; 5815 } 5816 } 5817 if (eg_pi->dynamic_ac_timing) { 5818 ret = si_initialize_mc_reg_table(rdev); 5819 if (ret) 5820 eg_pi->dynamic_ac_timing = false; 5821 } 5822 if (pi->dynamic_ss) 5823 si_enable_spread_spectrum(rdev, true); 5824 if (pi->thermal_protection) 5825 si_enable_thermal_protection(rdev, true); 5826 si_setup_bsp(rdev); 5827 si_program_git(rdev); 5828 si_program_tp(rdev); 5829 si_program_tpp(rdev); 5830 si_program_sstp(rdev); 5831 si_enable_display_gap(rdev); 5832 si_program_vc(rdev); 5833 ret = si_upload_firmware(rdev); 5834 if (ret) { 5835 DRM_ERROR("si_upload_firmware failed\n"); 5836 return ret; 5837 } 5838 ret = si_process_firmware_header(rdev); 5839 if (ret) { 5840 DRM_ERROR("si_process_firmware_header failed\n"); 5841 return ret; 5842 } 5843 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5844 if (ret) { 5845 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5846 return ret; 5847 } 5848 ret = si_init_smc_table(rdev); 5849 if (ret) { 5850 DRM_ERROR("si_init_smc_table failed\n"); 5851 return ret; 5852 } 5853 ret = si_init_smc_spll_table(rdev); 5854 if (ret) { 5855 DRM_ERROR("si_init_smc_spll_table failed\n"); 5856 return ret; 5857 } 5858 ret = si_init_arb_table_index(rdev); 5859 if (ret) { 5860 DRM_ERROR("si_init_arb_table_index failed\n"); 5861 return ret; 5862 } 5863 if (eg_pi->dynamic_ac_timing) { 5864 ret = si_populate_mc_reg_table(rdev, boot_ps); 5865 if (ret) { 5866 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5867 return ret; 5868 } 5869 } 5870 ret = si_initialize_smc_cac_tables(rdev); 5871 if (ret) { 5872 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5873 return ret; 5874 } 5875 ret = si_initialize_hardware_cac_manager(rdev); 5876 if (ret) { 5877 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5878 return ret; 5879 } 5880 ret = si_initialize_smc_dte_tables(rdev); 5881 if (ret) { 5882 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5883 return ret; 5884 } 5885 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5886 if (ret) { 5887 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5888 return ret; 5889 } 5890 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5891 if (ret) { 5892 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5893 return ret; 5894 } 5895 si_program_response_times(rdev); 5896 si_program_ds_registers(rdev); 5897 si_dpm_start_smc(rdev); 5898 ret = si_notify_smc_display_change(rdev, false); 5899 if (ret) { 5900 DRM_ERROR("si_notify_smc_display_change failed\n"); 5901 return ret; 5902 } 5903 si_enable_sclk_control(rdev, true); 5904 si_start_dpm(rdev); 5905 5906 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5907 5908 ni_update_current_ps(rdev, boot_ps); 5909 5910 return 0; 5911 } 5912 5913 int si_dpm_late_enable(struct radeon_device *rdev) 5914 { 5915 int ret; 5916 5917 if (rdev->irq.installed && 5918 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5919 PPSMC_Result result; 5920 5921 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5922 if (ret) 5923 return ret; 5924 rdev->irq.dpm_thermal = true; 5925 radeon_irq_set(rdev); 5926 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5927 5928 if (result != PPSMC_Result_OK) 5929 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5930 } 5931 5932 return 0; 5933 } 5934 5935 void si_dpm_disable(struct radeon_device *rdev) 5936 { 5937 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5938 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5939 5940 if (!si_is_smc_running(rdev)) 5941 return; 5942 si_disable_ulv(rdev); 5943 si_clear_vc(rdev); 5944 if (pi->thermal_protection) 5945 si_enable_thermal_protection(rdev, false); 5946 si_enable_power_containment(rdev, boot_ps, false); 5947 si_enable_smc_cac(rdev, boot_ps, false); 5948 si_enable_spread_spectrum(rdev, false); 5949 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5950 si_stop_dpm(rdev); 5951 si_reset_to_default(rdev); 5952 si_dpm_stop_smc(rdev); 5953 si_force_switch_to_arb_f0(rdev); 5954 5955 ni_update_current_ps(rdev, boot_ps); 5956 } 5957 5958 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5959 { 5960 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5961 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5962 struct radeon_ps *new_ps = &requested_ps; 5963 5964 ni_update_requested_ps(rdev, new_ps); 5965 5966 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5967 5968 return 0; 5969 } 5970 5971 static int si_power_control_set_level(struct radeon_device *rdev) 5972 { 5973 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5974 int ret; 5975 5976 ret = si_restrict_performance_levels_before_switch(rdev); 5977 if (ret) 5978 return ret; 5979 ret = si_halt_smc(rdev); 5980 if (ret) 5981 return ret; 5982 ret = si_populate_smc_tdp_limits(rdev, new_ps); 5983 if (ret) 5984 return ret; 5985 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 5986 if (ret) 5987 return ret; 5988 ret = si_resume_smc(rdev); 5989 if (ret) 5990 return ret; 5991 ret = si_set_sw_state(rdev); 5992 if (ret) 5993 return ret; 5994 return 0; 5995 } 5996 5997 int si_dpm_set_power_state(struct radeon_device *rdev) 5998 { 5999 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6000 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6001 struct radeon_ps *old_ps = &eg_pi->current_rps; 6002 int ret; 6003 6004 ret = si_disable_ulv(rdev); 6005 if (ret) { 6006 DRM_ERROR("si_disable_ulv failed\n"); 6007 return ret; 6008 } 6009 ret = si_restrict_performance_levels_before_switch(rdev); 6010 if (ret) { 6011 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6012 return ret; 6013 } 6014 if (eg_pi->pcie_performance_request) 6015 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6016 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6017 ret = si_enable_power_containment(rdev, new_ps, false); 6018 if (ret) { 6019 DRM_ERROR("si_enable_power_containment failed\n"); 6020 return ret; 6021 } 6022 ret = si_enable_smc_cac(rdev, new_ps, false); 6023 if (ret) { 6024 DRM_ERROR("si_enable_smc_cac failed\n"); 6025 return ret; 6026 } 6027 ret = si_halt_smc(rdev); 6028 if (ret) { 6029 DRM_ERROR("si_halt_smc failed\n"); 6030 return ret; 6031 } 6032 ret = si_upload_sw_state(rdev, new_ps); 6033 if (ret) { 6034 DRM_ERROR("si_upload_sw_state failed\n"); 6035 return ret; 6036 } 6037 ret = si_upload_smc_data(rdev); 6038 if (ret) { 6039 DRM_ERROR("si_upload_smc_data failed\n"); 6040 return ret; 6041 } 6042 ret = si_upload_ulv_state(rdev); 6043 if (ret) { 6044 DRM_ERROR("si_upload_ulv_state failed\n"); 6045 return ret; 6046 } 6047 if (eg_pi->dynamic_ac_timing) { 6048 ret = si_upload_mc_reg_table(rdev, new_ps); 6049 if (ret) { 6050 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6051 return ret; 6052 } 6053 } 6054 ret = si_program_memory_timing_parameters(rdev, new_ps); 6055 if (ret) { 6056 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6057 return ret; 6058 } 6059 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6060 6061 ret = si_resume_smc(rdev); 6062 if (ret) { 6063 DRM_ERROR("si_resume_smc failed\n"); 6064 return ret; 6065 } 6066 ret = si_set_sw_state(rdev); 6067 if (ret) { 6068 DRM_ERROR("si_set_sw_state failed\n"); 6069 return ret; 6070 } 6071 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6072 if (eg_pi->pcie_performance_request) 6073 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6074 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6075 if (ret) { 6076 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6077 return ret; 6078 } 6079 ret = si_enable_smc_cac(rdev, new_ps, true); 6080 if (ret) { 6081 DRM_ERROR("si_enable_smc_cac failed\n"); 6082 return ret; 6083 } 6084 ret = si_enable_power_containment(rdev, new_ps, true); 6085 if (ret) { 6086 DRM_ERROR("si_enable_power_containment failed\n"); 6087 return ret; 6088 } 6089 6090 ret = si_power_control_set_level(rdev); 6091 if (ret) { 6092 DRM_ERROR("si_power_control_set_level failed\n"); 6093 return ret; 6094 } 6095 6096 return 0; 6097 } 6098 6099 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6100 { 6101 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6102 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6103 6104 ni_update_current_ps(rdev, new_ps); 6105 } 6106 6107 6108 void si_dpm_reset_asic(struct radeon_device *rdev) 6109 { 6110 si_restrict_performance_levels_before_switch(rdev); 6111 si_disable_ulv(rdev); 6112 si_set_boot_state(rdev); 6113 } 6114 6115 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6116 { 6117 si_program_display_gap(rdev); 6118 } 6119 6120 union power_info { 6121 struct _ATOM_POWERPLAY_INFO info; 6122 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6123 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6124 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6125 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6126 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6127 }; 6128 6129 union pplib_clock_info { 6130 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6131 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6132 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6133 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6134 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6135 }; 6136 6137 union pplib_power_state { 6138 struct _ATOM_PPLIB_STATE v1; 6139 struct _ATOM_PPLIB_STATE_V2 v2; 6140 }; 6141 6142 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6143 struct radeon_ps *rps, 6144 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6145 u8 table_rev) 6146 { 6147 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6148 rps->class = le16_to_cpu(non_clock_info->usClassification); 6149 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6150 6151 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6152 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6153 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6154 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6155 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6156 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6157 } else { 6158 rps->vclk = 0; 6159 rps->dclk = 0; 6160 } 6161 6162 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6163 rdev->pm.dpm.boot_ps = rps; 6164 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6165 rdev->pm.dpm.uvd_ps = rps; 6166 } 6167 6168 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6169 struct radeon_ps *rps, int index, 6170 union pplib_clock_info *clock_info) 6171 { 6172 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6173 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6174 struct si_power_info *si_pi = si_get_pi(rdev); 6175 struct ni_ps *ps = ni_get_ps(rps); 6176 u16 leakage_voltage; 6177 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6178 int ret; 6179 6180 ps->performance_level_count = index + 1; 6181 6182 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6183 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6184 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6185 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6186 6187 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6188 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6189 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6190 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6191 si_pi->sys_pcie_mask, 6192 si_pi->boot_pcie_gen, 6193 clock_info->si.ucPCIEGen); 6194 6195 /* patch up vddc if necessary */ 6196 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6197 &leakage_voltage); 6198 if (ret == 0) 6199 pl->vddc = leakage_voltage; 6200 6201 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6202 pi->acpi_vddc = pl->vddc; 6203 eg_pi->acpi_vddci = pl->vddci; 6204 si_pi->acpi_pcie_gen = pl->pcie_gen; 6205 } 6206 6207 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6208 index == 0) { 6209 /* XXX disable for A0 tahiti */ 6210 si_pi->ulv.supported = true; 6211 si_pi->ulv.pl = *pl; 6212 si_pi->ulv.one_pcie_lane_in_ulv = false; 6213 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6214 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6215 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6216 } 6217 6218 if (pi->min_vddc_in_table > pl->vddc) 6219 pi->min_vddc_in_table = pl->vddc; 6220 6221 if (pi->max_vddc_in_table < pl->vddc) 6222 pi->max_vddc_in_table = pl->vddc; 6223 6224 /* patch up boot state */ 6225 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6226 u16 vddc, vddci, mvdd; 6227 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6228 pl->mclk = rdev->clock.default_mclk; 6229 pl->sclk = rdev->clock.default_sclk; 6230 pl->vddc = vddc; 6231 pl->vddci = vddci; 6232 si_pi->mvdd_bootup_value = mvdd; 6233 } 6234 6235 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6236 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6237 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6238 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6239 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6240 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6241 } 6242 } 6243 6244 static int si_parse_power_table(struct radeon_device *rdev) 6245 { 6246 struct radeon_mode_info *mode_info = &rdev->mode_info; 6247 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6248 union pplib_power_state *power_state; 6249 int i, j, k, non_clock_array_index, clock_array_index; 6250 union pplib_clock_info *clock_info; 6251 struct _StateArray *state_array; 6252 struct _ClockInfoArray *clock_info_array; 6253 struct _NonClockInfoArray *non_clock_info_array; 6254 union power_info *power_info; 6255 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6256 u16 data_offset; 6257 u8 frev, crev; 6258 u8 *power_state_offset; 6259 struct ni_ps *ps; 6260 6261 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6262 &frev, &crev, &data_offset)) 6263 return -EINVAL; 6264 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6265 6266 state_array = (struct _StateArray *) 6267 (mode_info->atom_context->bios + data_offset + 6268 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6269 clock_info_array = (struct _ClockInfoArray *) 6270 (mode_info->atom_context->bios + data_offset + 6271 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6272 non_clock_info_array = (struct _NonClockInfoArray *) 6273 (mode_info->atom_context->bios + data_offset + 6274 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6275 6276 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6277 state_array->ucNumEntries, GFP_KERNEL); 6278 if (!rdev->pm.dpm.ps) 6279 return -ENOMEM; 6280 power_state_offset = (u8 *)state_array->states; 6281 for (i = 0; i < state_array->ucNumEntries; i++) { 6282 u8 *idx; 6283 power_state = (union pplib_power_state *)power_state_offset; 6284 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6285 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6286 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6287 if (!rdev->pm.power_state[i].clock_info) 6288 return -EINVAL; 6289 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6290 if (ps == NULL) { 6291 kfree(rdev->pm.dpm.ps); 6292 return -ENOMEM; 6293 } 6294 rdev->pm.dpm.ps[i].ps_priv = ps; 6295 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6296 non_clock_info, 6297 non_clock_info_array->ucEntrySize); 6298 k = 0; 6299 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6300 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6301 clock_array_index = idx[j]; 6302 if (clock_array_index >= clock_info_array->ucNumEntries) 6303 continue; 6304 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6305 break; 6306 clock_info = (union pplib_clock_info *) 6307 ((u8 *)&clock_info_array->clockInfo[0] + 6308 (clock_array_index * clock_info_array->ucEntrySize)); 6309 si_parse_pplib_clock_info(rdev, 6310 &rdev->pm.dpm.ps[i], k, 6311 clock_info); 6312 k++; 6313 } 6314 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6315 } 6316 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6317 return 0; 6318 } 6319 6320 int si_dpm_init(struct radeon_device *rdev) 6321 { 6322 struct rv7xx_power_info *pi; 6323 struct evergreen_power_info *eg_pi; 6324 struct ni_power_info *ni_pi; 6325 struct si_power_info *si_pi; 6326 struct atom_clock_dividers dividers; 6327 int ret; 6328 u32 mask; 6329 6330 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6331 if (si_pi == NULL) 6332 return -ENOMEM; 6333 rdev->pm.dpm.priv = si_pi; 6334 ni_pi = &si_pi->ni; 6335 eg_pi = &ni_pi->eg; 6336 pi = &eg_pi->rv7xx; 6337 6338 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6339 if (ret) 6340 si_pi->sys_pcie_mask = 0; 6341 else 6342 si_pi->sys_pcie_mask = mask; 6343 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6344 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6345 6346 si_set_max_cu_value(rdev); 6347 6348 rv770_get_max_vddc(rdev); 6349 si_get_leakage_vddc(rdev); 6350 si_patch_dependency_tables_based_on_leakage(rdev); 6351 6352 pi->acpi_vddc = 0; 6353 eg_pi->acpi_vddci = 0; 6354 pi->min_vddc_in_table = 0; 6355 pi->max_vddc_in_table = 0; 6356 6357 ret = r600_get_platform_caps(rdev); 6358 if (ret) 6359 return ret; 6360 6361 ret = si_parse_power_table(rdev); 6362 if (ret) 6363 return ret; 6364 ret = r600_parse_extended_power_table(rdev); 6365 if (ret) 6366 return ret; 6367 6368 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6369 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6370 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6371 r600_free_extended_power_table(rdev); 6372 return -ENOMEM; 6373 } 6374 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6375 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6376 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6377 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6378 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6379 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6380 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6381 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6382 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6383 6384 if (rdev->pm.dpm.voltage_response_time == 0) 6385 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6386 if (rdev->pm.dpm.backbias_response_time == 0) 6387 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6388 6389 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6390 0, false, ÷rs); 6391 if (ret) 6392 pi->ref_div = dividers.ref_div + 1; 6393 else 6394 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6395 6396 eg_pi->smu_uvd_hs = false; 6397 6398 pi->mclk_strobe_mode_threshold = 40000; 6399 if (si_is_special_1gb_platform(rdev)) 6400 pi->mclk_stutter_mode_threshold = 0; 6401 else 6402 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6403 pi->mclk_edc_enable_threshold = 40000; 6404 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6405 6406 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6407 6408 pi->voltage_control = 6409 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT); 6410 6411 pi->mvdd_control = 6412 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT); 6413 6414 eg_pi->vddci_control = 6415 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT); 6416 6417 si_pi->vddc_phase_shed_control = 6418 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6419 6420 rv770_get_engine_memory_ss(rdev); 6421 6422 pi->asi = RV770_ASI_DFLT; 6423 pi->pasi = CYPRESS_HASI_DFLT; 6424 pi->vrc = SISLANDS_VRC_DFLT; 6425 6426 pi->gfx_clock_gating = true; 6427 6428 eg_pi->sclk_deep_sleep = true; 6429 si_pi->sclk_deep_sleep_above_low = false; 6430 6431 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6432 pi->thermal_protection = true; 6433 else 6434 pi->thermal_protection = false; 6435 6436 eg_pi->dynamic_ac_timing = true; 6437 6438 eg_pi->light_sleep = true; 6439 #if defined(CONFIG_ACPI) 6440 eg_pi->pcie_performance_request = 6441 radeon_acpi_is_pcie_performance_request_supported(rdev); 6442 #else 6443 eg_pi->pcie_performance_request = false; 6444 #endif 6445 6446 si_pi->sram_end = SMC_RAM_END; 6447 6448 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6449 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6450 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6451 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6452 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6453 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6454 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6455 6456 si_initialize_powertune_defaults(rdev); 6457 6458 /* make sure dc limits are valid */ 6459 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6460 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6461 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6462 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6463 6464 return 0; 6465 } 6466 6467 void si_dpm_fini(struct radeon_device *rdev) 6468 { 6469 int i; 6470 6471 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6472 kfree(rdev->pm.dpm.ps[i].ps_priv); 6473 } 6474 kfree(rdev->pm.dpm.ps); 6475 kfree(rdev->pm.dpm.priv); 6476 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6477 r600_free_extended_power_table(rdev); 6478 } 6479 6480 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6481 struct seq_file *m) 6482 { 6483 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6484 struct radeon_ps *rps = &eg_pi->current_rps; 6485 struct ni_ps *ps = ni_get_ps(rps); 6486 struct rv7xx_pl *pl; 6487 u32 current_index = 6488 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6489 CURRENT_STATE_INDEX_SHIFT; 6490 6491 if (current_index >= ps->performance_level_count) { 6492 seq_printf(m, "invalid dpm profile %d\n", current_index); 6493 } else { 6494 pl = &ps->performance_levels[current_index]; 6495 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6496 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6497 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6498 } 6499 } 6500