1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "drmP.h" 25 #include "radeon.h" 26 #include "radeon_asic.h" 27 #include "sid.h" 28 #include "r600_dpm.h" 29 #include "si_dpm.h" 30 #include "atom.h" 31 #include <linux/math64.h> 32 #include <linux/seq_file.h> 33 34 #define MC_CG_ARB_FREQ_F0 0x0a 35 #define MC_CG_ARB_FREQ_F1 0x0b 36 #define MC_CG_ARB_FREQ_F2 0x0c 37 #define MC_CG_ARB_FREQ_F3 0x0d 38 39 #define SMC_RAM_END 0x20000 40 41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43 static const struct si_cac_config_reg cac_weights_tahiti[] = 44 { 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106 }; 107 108 static const struct si_cac_config_reg lcac_tahiti[] = 109 { 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198 }; 199 200 static const struct si_cac_config_reg cac_override_tahiti[] = 201 { 202 { 0xFFFFFFFF } 203 }; 204 205 static const struct si_powertune_data powertune_data_tahiti = 206 { 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234 }; 235 236 static const struct si_dte_data dte_data_tahiti = 237 { 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252 }; 253 254 static const struct si_dte_data dte_data_tahiti_le = 255 { 256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 258 0x5, 259 0xAFC8, 260 0x64, 261 0x32, 262 1, 263 0, 264 0x10, 265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 268 85, 269 true 270 }; 271 272 static const struct si_dte_data dte_data_tahiti_pro = 273 { 274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 275 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 276 5, 277 45000, 278 100, 279 0xA, 280 1, 281 0, 282 0x10, 283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 286 90, 287 true 288 }; 289 290 static const struct si_dte_data dte_data_new_zealand = 291 { 292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 294 0x5, 295 0xAFC8, 296 0x69, 297 0x32, 298 1, 299 0, 300 0x10, 301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 304 85, 305 true 306 }; 307 308 static const struct si_dte_data dte_data_aruba_pro = 309 { 310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 311 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 312 5, 313 45000, 314 100, 315 0xA, 316 1, 317 0, 318 0x10, 319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 322 90, 323 true 324 }; 325 326 static const struct si_dte_data dte_data_malta = 327 { 328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 329 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 330 5, 331 45000, 332 100, 333 0xA, 334 1, 335 0, 336 0x10, 337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 340 90, 341 true 342 }; 343 344 struct si_cac_config_reg cac_weights_pitcairn[] = 345 { 346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 406 { 0xFFFFFFFF } 407 }; 408 409 static const struct si_cac_config_reg lcac_pitcairn[] = 410 { 411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0xFFFFFFFF } 498 }; 499 500 static const struct si_cac_config_reg cac_override_pitcairn[] = 501 { 502 { 0xFFFFFFFF } 503 }; 504 505 static const struct si_powertune_data powertune_data_pitcairn = 506 { 507 ((1 << 16) | 27027), 508 5, 509 0, 510 6, 511 100, 512 { 513 51600000UL, 514 1800000UL, 515 7194395UL, 516 309631529UL, 517 -1270850L, 518 4513710L, 519 100 520 }, 521 117830498UL, 522 12, 523 { 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0 532 }, 533 true 534 }; 535 536 static const struct si_dte_data dte_data_pitcairn = 537 { 538 { 0, 0, 0, 0, 0 }, 539 { 0, 0, 0, 0, 0 }, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 0, 551 false 552 }; 553 554 static const struct si_dte_data dte_data_curacao_xt = 555 { 556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 557 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 558 5, 559 45000, 560 100, 561 0xA, 562 1, 563 0, 564 0x10, 565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 568 90, 569 true 570 }; 571 572 static const struct si_dte_data dte_data_curacao_pro = 573 { 574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 575 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 576 5, 577 45000, 578 100, 579 0xA, 580 1, 581 0, 582 0x10, 583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 586 90, 587 true 588 }; 589 590 static const struct si_dte_data dte_data_neptune_xt = 591 { 592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 593 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 594 5, 595 45000, 596 100, 597 0xA, 598 1, 599 0, 600 0x10, 601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 604 90, 605 true 606 }; 607 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 609 { 610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 670 { 0xFFFFFFFF } 671 }; 672 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 674 { 675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 735 { 0xFFFFFFFF } 736 }; 737 738 static const struct si_cac_config_reg cac_weights_heathrow[] = 739 { 740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 800 { 0xFFFFFFFF } 801 }; 802 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 804 { 805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 865 { 0xFFFFFFFF } 866 }; 867 868 static const struct si_cac_config_reg cac_weights_cape_verde[] = 869 { 870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 930 { 0xFFFFFFFF } 931 }; 932 933 static const struct si_cac_config_reg lcac_cape_verde[] = 934 { 935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0xFFFFFFFF } 990 }; 991 992 static const struct si_cac_config_reg cac_override_cape_verde[] = 993 { 994 { 0xFFFFFFFF } 995 }; 996 997 static const struct si_powertune_data powertune_data_cape_verde = 998 { 999 ((1 << 16) | 0x6993), 1000 5, 1001 0, 1002 7, 1003 105, 1004 { 1005 0UL, 1006 0UL, 1007 7194395UL, 1008 309631529UL, 1009 -1270850L, 1010 4513710L, 1011 100 1012 }, 1013 117830498UL, 1014 12, 1015 { 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0 1024 }, 1025 true 1026 }; 1027 1028 static const struct si_dte_data dte_data_cape_verde = 1029 { 1030 { 0, 0, 0, 0, 0 }, 1031 { 0, 0, 0, 0, 0 }, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 0, 1043 false 1044 }; 1045 1046 static const struct si_dte_data dte_data_venus_xtx = 1047 { 1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1050 5, 1051 55000, 1052 0x69, 1053 0xA, 1054 1, 1055 0, 1056 0x3, 1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 90, 1061 true 1062 }; 1063 1064 static const struct si_dte_data dte_data_venus_xt = 1065 { 1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1068 5, 1069 55000, 1070 0x69, 1071 0xA, 1072 1, 1073 0, 1074 0x3, 1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 90, 1079 true 1080 }; 1081 1082 static const struct si_dte_data dte_data_venus_pro = 1083 { 1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1086 5, 1087 55000, 1088 0x69, 1089 0xA, 1090 1, 1091 0, 1092 0x3, 1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 90, 1097 true 1098 }; 1099 1100 struct si_cac_config_reg cac_weights_oland[] = 1101 { 1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1162 { 0xFFFFFFFF } 1163 }; 1164 1165 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1166 { 1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1227 { 0xFFFFFFFF } 1228 }; 1229 1230 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1231 { 1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1292 { 0xFFFFFFFF } 1293 }; 1294 1295 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1296 { 1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1357 { 0xFFFFFFFF } 1358 }; 1359 1360 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1361 { 1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1422 { 0xFFFFFFFF } 1423 }; 1424 1425 static const struct si_cac_config_reg lcac_oland[] = 1426 { 1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0xFFFFFFFF } 1470 }; 1471 1472 static const struct si_cac_config_reg lcac_mars_pro[] = 1473 { 1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0xFFFFFFFF } 1517 }; 1518 1519 static const struct si_cac_config_reg cac_override_oland[] = 1520 { 1521 { 0xFFFFFFFF } 1522 }; 1523 1524 static const struct si_powertune_data powertune_data_oland = 1525 { 1526 ((1 << 16) | 0x6993), 1527 5, 1528 0, 1529 7, 1530 105, 1531 { 1532 0UL, 1533 0UL, 1534 7194395UL, 1535 309631529UL, 1536 -1270850L, 1537 4513710L, 1538 100 1539 }, 1540 117830498UL, 1541 12, 1542 { 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0 1551 }, 1552 true 1553 }; 1554 1555 static const struct si_powertune_data powertune_data_mars_pro = 1556 { 1557 ((1 << 16) | 0x6993), 1558 5, 1559 0, 1560 7, 1561 105, 1562 { 1563 0UL, 1564 0UL, 1565 7194395UL, 1566 309631529UL, 1567 -1270850L, 1568 4513710L, 1569 100 1570 }, 1571 117830498UL, 1572 12, 1573 { 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0 1582 }, 1583 true 1584 }; 1585 1586 static const struct si_dte_data dte_data_oland = 1587 { 1588 { 0, 0, 0, 0, 0 }, 1589 { 0, 0, 0, 0, 0 }, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 0, 1601 false 1602 }; 1603 1604 static const struct si_dte_data dte_data_mars_pro = 1605 { 1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1607 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1608 5, 1609 55000, 1610 105, 1611 0xA, 1612 1, 1613 0, 1614 0x10, 1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1618 90, 1619 true 1620 }; 1621 1622 static const struct si_dte_data dte_data_sun_xt = 1623 { 1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1625 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1626 5, 1627 55000, 1628 105, 1629 0xA, 1630 1, 1631 0, 1632 0x10, 1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1636 90, 1637 true 1638 }; 1639 1640 1641 static const struct si_cac_config_reg cac_weights_hainan[] = 1642 { 1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1703 { 0xFFFFFFFF } 1704 }; 1705 1706 static const struct si_powertune_data powertune_data_hainan = 1707 { 1708 ((1 << 16) | 0x6993), 1709 5, 1710 0, 1711 9, 1712 105, 1713 { 1714 0UL, 1715 0UL, 1716 7194395UL, 1717 309631529UL, 1718 -1270850L, 1719 4513710L, 1720 100 1721 }, 1722 117830498UL, 1723 12, 1724 { 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0 1733 }, 1734 true 1735 }; 1736 1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1741 1742 extern int si_mc_load_microcode(struct radeon_device *rdev); 1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1744 1745 static int si_populate_voltage_value(struct radeon_device *rdev, 1746 const struct atom_voltage_table *table, 1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1748 static int si_get_std_voltage_value(struct radeon_device *rdev, 1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1750 u16 *std_voltage); 1751 static int si_write_smc_soft_register(struct radeon_device *rdev, 1752 u16 reg_offset, u32 value); 1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1754 struct rv7xx_pl *pl, 1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1756 static int si_calculate_sclk_params(struct radeon_device *rdev, 1757 u32 engine_clock, 1758 SISLANDS_SMC_SCLK_VALUE *sclk); 1759 1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1762 1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1764 { 1765 struct si_power_info *pi = rdev->pm.dpm.priv; 1766 1767 return pi; 1768 } 1769 1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1771 u16 v, s32 t, u32 ileakage, u32 *leakage) 1772 { 1773 s64 kt, kv, leakage_w, i_leakage, vddc; 1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1775 s64 tmp; 1776 1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1778 vddc = div64_s64(drm_int2fixp(v), 1000); 1779 temperature = div64_s64(drm_int2fixp(t), 1000); 1780 1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1785 t_ref = drm_int2fixp(coeff->t_ref); 1786 1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1791 1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1793 1794 *leakage = drm_fixp2int(leakage_w * 1000); 1795 } 1796 1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1798 const struct ni_leakage_coeffients *coeff, 1799 u16 v, 1800 s32 t, 1801 u32 i_leakage, 1802 u32 *leakage) 1803 { 1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1805 } 1806 1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1808 const u32 fixed_kt, u16 v, 1809 u32 ileakage, u32 *leakage) 1810 { 1811 s64 kt, kv, leakage_w, i_leakage, vddc; 1812 1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1814 vddc = div64_s64(drm_int2fixp(v), 1000); 1815 1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1819 1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1821 1822 *leakage = drm_fixp2int(leakage_w * 1000); 1823 } 1824 1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1826 const struct ni_leakage_coeffients *coeff, 1827 const u32 fixed_kt, 1828 u16 v, 1829 u32 i_leakage, 1830 u32 *leakage) 1831 { 1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1833 } 1834 1835 1836 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1837 struct si_dte_data *dte_data) 1838 { 1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1841 u32 k = dte_data->k; 1842 u32 t_max = dte_data->max_t; 1843 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1844 u32 t_0 = dte_data->t0; 1845 u32 i; 1846 1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1848 dte_data->tdep_count = 3; 1849 1850 for (i = 0; i < k; i++) { 1851 dte_data->r[i] = 1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1853 (p_limit2 * (u32)100); 1854 } 1855 1856 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1857 1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1859 dte_data->tdep_r[i] = dte_data->r[4]; 1860 } 1861 } else { 1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1863 } 1864 } 1865 1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1867 { 1868 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1869 struct si_power_info *si_pi = si_get_pi(rdev); 1870 bool update_dte_from_pl2 = false; 1871 1872 if (rdev->family == CHIP_TAHITI) { 1873 si_pi->cac_weights = cac_weights_tahiti; 1874 si_pi->lcac_config = lcac_tahiti; 1875 si_pi->cac_override = cac_override_tahiti; 1876 si_pi->powertune_data = &powertune_data_tahiti; 1877 si_pi->dte_data = dte_data_tahiti; 1878 1879 switch (rdev->pdev->device) { 1880 case 0x6798: 1881 si_pi->dte_data.enable_dte_by_default = true; 1882 break; 1883 case 0x6799: 1884 si_pi->dte_data = dte_data_new_zealand; 1885 break; 1886 case 0x6790: 1887 case 0x6791: 1888 case 0x6792: 1889 case 0x679E: 1890 si_pi->dte_data = dte_data_aruba_pro; 1891 update_dte_from_pl2 = true; 1892 break; 1893 case 0x679B: 1894 si_pi->dte_data = dte_data_malta; 1895 update_dte_from_pl2 = true; 1896 break; 1897 case 0x679A: 1898 si_pi->dte_data = dte_data_tahiti_pro; 1899 update_dte_from_pl2 = true; 1900 break; 1901 default: 1902 if (si_pi->dte_data.enable_dte_by_default == true) 1903 DRM_ERROR("DTE is not enabled!\n"); 1904 break; 1905 } 1906 } else if (rdev->family == CHIP_PITCAIRN) { 1907 switch (rdev->pdev->device) { 1908 case 0x6810: 1909 case 0x6818: 1910 si_pi->cac_weights = cac_weights_pitcairn; 1911 si_pi->lcac_config = lcac_pitcairn; 1912 si_pi->cac_override = cac_override_pitcairn; 1913 si_pi->powertune_data = &powertune_data_pitcairn; 1914 si_pi->dte_data = dte_data_curacao_xt; 1915 update_dte_from_pl2 = true; 1916 break; 1917 case 0x6819: 1918 case 0x6811: 1919 si_pi->cac_weights = cac_weights_pitcairn; 1920 si_pi->lcac_config = lcac_pitcairn; 1921 si_pi->cac_override = cac_override_pitcairn; 1922 si_pi->powertune_data = &powertune_data_pitcairn; 1923 si_pi->dte_data = dte_data_curacao_pro; 1924 update_dte_from_pl2 = true; 1925 break; 1926 case 0x6800: 1927 case 0x6806: 1928 si_pi->cac_weights = cac_weights_pitcairn; 1929 si_pi->lcac_config = lcac_pitcairn; 1930 si_pi->cac_override = cac_override_pitcairn; 1931 si_pi->powertune_data = &powertune_data_pitcairn; 1932 si_pi->dte_data = dte_data_neptune_xt; 1933 update_dte_from_pl2 = true; 1934 break; 1935 default: 1936 si_pi->cac_weights = cac_weights_pitcairn; 1937 si_pi->lcac_config = lcac_pitcairn; 1938 si_pi->cac_override = cac_override_pitcairn; 1939 si_pi->powertune_data = &powertune_data_pitcairn; 1940 si_pi->dte_data = dte_data_pitcairn; 1941 break; 1942 } 1943 } else if (rdev->family == CHIP_VERDE) { 1944 si_pi->lcac_config = lcac_cape_verde; 1945 si_pi->cac_override = cac_override_cape_verde; 1946 si_pi->powertune_data = &powertune_data_cape_verde; 1947 1948 switch (rdev->pdev->device) { 1949 case 0x683B: 1950 case 0x683F: 1951 case 0x6829: 1952 case 0x6835: 1953 si_pi->cac_weights = cac_weights_cape_verde_pro; 1954 si_pi->dte_data = dte_data_cape_verde; 1955 break; 1956 case 0x682C: 1957 si_pi->cac_weights = cac_weights_cape_verde_pro; 1958 si_pi->dte_data = dte_data_sun_xt; 1959 break; 1960 case 0x6825: 1961 case 0x6827: 1962 si_pi->cac_weights = cac_weights_heathrow; 1963 si_pi->dte_data = dte_data_cape_verde; 1964 break; 1965 case 0x6824: 1966 case 0x682D: 1967 si_pi->cac_weights = cac_weights_chelsea_xt; 1968 si_pi->dte_data = dte_data_cape_verde; 1969 break; 1970 case 0x682F: 1971 si_pi->cac_weights = cac_weights_chelsea_pro; 1972 si_pi->dte_data = dte_data_cape_verde; 1973 break; 1974 case 0x6820: 1975 si_pi->cac_weights = cac_weights_heathrow; 1976 si_pi->dte_data = dte_data_venus_xtx; 1977 break; 1978 case 0x6821: 1979 si_pi->cac_weights = cac_weights_heathrow; 1980 si_pi->dte_data = dte_data_venus_xt; 1981 break; 1982 case 0x6823: 1983 case 0x682B: 1984 case 0x6822: 1985 case 0x682A: 1986 si_pi->cac_weights = cac_weights_chelsea_pro; 1987 si_pi->dte_data = dte_data_venus_pro; 1988 break; 1989 default: 1990 si_pi->cac_weights = cac_weights_cape_verde; 1991 si_pi->dte_data = dte_data_cape_verde; 1992 break; 1993 } 1994 } else if (rdev->family == CHIP_OLAND) { 1995 switch (rdev->pdev->device) { 1996 case 0x6601: 1997 case 0x6621: 1998 case 0x6603: 1999 case 0x6605: 2000 si_pi->cac_weights = cac_weights_mars_pro; 2001 si_pi->lcac_config = lcac_mars_pro; 2002 si_pi->cac_override = cac_override_oland; 2003 si_pi->powertune_data = &powertune_data_mars_pro; 2004 si_pi->dte_data = dte_data_mars_pro; 2005 update_dte_from_pl2 = true; 2006 break; 2007 case 0x6600: 2008 case 0x6606: 2009 case 0x6620: 2010 case 0x6604: 2011 si_pi->cac_weights = cac_weights_mars_xt; 2012 si_pi->lcac_config = lcac_mars_pro; 2013 si_pi->cac_override = cac_override_oland; 2014 si_pi->powertune_data = &powertune_data_mars_pro; 2015 si_pi->dte_data = dte_data_mars_pro; 2016 update_dte_from_pl2 = true; 2017 break; 2018 case 0x6611: 2019 case 0x6613: 2020 case 0x6608: 2021 si_pi->cac_weights = cac_weights_oland_pro; 2022 si_pi->lcac_config = lcac_mars_pro; 2023 si_pi->cac_override = cac_override_oland; 2024 si_pi->powertune_data = &powertune_data_mars_pro; 2025 si_pi->dte_data = dte_data_mars_pro; 2026 update_dte_from_pl2 = true; 2027 break; 2028 case 0x6610: 2029 si_pi->cac_weights = cac_weights_oland_xt; 2030 si_pi->lcac_config = lcac_mars_pro; 2031 si_pi->cac_override = cac_override_oland; 2032 si_pi->powertune_data = &powertune_data_mars_pro; 2033 si_pi->dte_data = dte_data_mars_pro; 2034 update_dte_from_pl2 = true; 2035 break; 2036 default: 2037 si_pi->cac_weights = cac_weights_oland; 2038 si_pi->lcac_config = lcac_oland; 2039 si_pi->cac_override = cac_override_oland; 2040 si_pi->powertune_data = &powertune_data_oland; 2041 si_pi->dte_data = dte_data_oland; 2042 break; 2043 } 2044 } else if (rdev->family == CHIP_HAINAN) { 2045 si_pi->cac_weights = cac_weights_hainan; 2046 si_pi->lcac_config = lcac_oland; 2047 si_pi->cac_override = cac_override_oland; 2048 si_pi->powertune_data = &powertune_data_hainan; 2049 si_pi->dte_data = dte_data_sun_xt; 2050 update_dte_from_pl2 = true; 2051 } else { 2052 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2053 return; 2054 } 2055 2056 ni_pi->enable_power_containment = false; 2057 ni_pi->enable_cac = false; 2058 ni_pi->enable_sq_ramping = false; 2059 si_pi->enable_dte = false; 2060 2061 if (si_pi->powertune_data->enable_powertune_by_default) { 2062 ni_pi->enable_power_containment= true; 2063 ni_pi->enable_cac = true; 2064 if (si_pi->dte_data.enable_dte_by_default) { 2065 si_pi->enable_dte = true; 2066 if (update_dte_from_pl2) 2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2068 2069 } 2070 ni_pi->enable_sq_ramping = true; 2071 } 2072 2073 ni_pi->driver_calculate_cac_leakage = true; 2074 ni_pi->cac_configuration_required = true; 2075 2076 if (ni_pi->cac_configuration_required) { 2077 ni_pi->support_cac_long_term_average = true; 2078 si_pi->dyn_powertune_data.l2_lta_window_size = 2079 si_pi->powertune_data->l2_lta_window_size_default; 2080 si_pi->dyn_powertune_data.lts_truncate = 2081 si_pi->powertune_data->lts_truncate_default; 2082 } else { 2083 ni_pi->support_cac_long_term_average = false; 2084 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2085 si_pi->dyn_powertune_data.lts_truncate = 0; 2086 } 2087 2088 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2089 } 2090 2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2092 { 2093 return 1; 2094 } 2095 2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2097 { 2098 u32 xclk; 2099 u32 wintime; 2100 u32 cac_window; 2101 u32 cac_window_size; 2102 2103 xclk = radeon_get_xclk(rdev); 2104 2105 if (xclk == 0) 2106 return 0; 2107 2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2109 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2110 2111 wintime = (cac_window_size * 100) / xclk; 2112 2113 return wintime; 2114 } 2115 2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2117 { 2118 return power_in_watts; 2119 } 2120 2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2122 bool adjust_polarity, 2123 u32 tdp_adjustment, 2124 u32 *tdp_limit, 2125 u32 *near_tdp_limit) 2126 { 2127 u32 adjustment_delta, max_tdp_limit; 2128 2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2130 return -EINVAL; 2131 2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2133 2134 if (adjust_polarity) { 2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2137 } else { 2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2142 else 2143 *near_tdp_limit = 0; 2144 } 2145 2146 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2147 return -EINVAL; 2148 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2149 return -EINVAL; 2150 2151 return 0; 2152 } 2153 2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2155 struct radeon_ps *radeon_state) 2156 { 2157 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2158 struct si_power_info *si_pi = si_get_pi(rdev); 2159 2160 if (ni_pi->enable_power_containment) { 2161 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2162 PP_SIslands_PAPMParameters *papm_parm; 2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2165 u32 tdp_limit; 2166 u32 near_tdp_limit; 2167 int ret; 2168 2169 if (scaling_factor == 0) 2170 return -EINVAL; 2171 2172 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2173 2174 ret = si_calculate_adjusted_tdp_limits(rdev, 2175 false, /* ??? */ 2176 rdev->pm.dpm.tdp_adjustment, 2177 &tdp_limit, 2178 &near_tdp_limit); 2179 if (ret) 2180 return ret; 2181 2182 smc_table->dpm2Params.TDPLimit = 2183 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2184 smc_table->dpm2Params.NearTDPLimit = 2185 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2186 smc_table->dpm2Params.SafePowerLimit = 2187 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2188 2189 ret = si_copy_bytes_to_smc(rdev, 2190 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2191 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2192 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2193 sizeof(u32) * 3, 2194 si_pi->sram_end); 2195 if (ret) 2196 return ret; 2197 2198 if (si_pi->enable_ppm) { 2199 papm_parm = &si_pi->papm_parm; 2200 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2201 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2202 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2203 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2204 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2205 papm_parm->PlatformPowerLimit = 0xffffffff; 2206 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2207 2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2209 (u8 *)papm_parm, 2210 sizeof(PP_SIslands_PAPMParameters), 2211 si_pi->sram_end); 2212 if (ret) 2213 return ret; 2214 } 2215 } 2216 return 0; 2217 } 2218 2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2220 struct radeon_ps *radeon_state) 2221 { 2222 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2223 struct si_power_info *si_pi = si_get_pi(rdev); 2224 2225 if (ni_pi->enable_power_containment) { 2226 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2228 int ret; 2229 2230 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2231 2232 smc_table->dpm2Params.NearTDPLimit = 2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2234 smc_table->dpm2Params.SafePowerLimit = 2235 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2236 2237 ret = si_copy_bytes_to_smc(rdev, 2238 (si_pi->state_table_start + 2239 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2240 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2241 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2242 sizeof(u32) * 2, 2243 si_pi->sram_end); 2244 if (ret) 2245 return ret; 2246 } 2247 2248 return 0; 2249 } 2250 2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2252 const u16 prev_std_vddc, 2253 const u16 curr_std_vddc) 2254 { 2255 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2256 u64 prev_vddc = (u64)prev_std_vddc; 2257 u64 curr_vddc = (u64)curr_std_vddc; 2258 u64 pwr_efficiency_ratio, n, d; 2259 2260 if ((prev_vddc == 0) || (curr_vddc == 0)) 2261 return 0; 2262 2263 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2264 d = prev_vddc * prev_vddc; 2265 pwr_efficiency_ratio = div64_u64(n, d); 2266 2267 if (pwr_efficiency_ratio > (u64)0xFFFF) 2268 return 0; 2269 2270 return (u16)pwr_efficiency_ratio; 2271 } 2272 2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2274 struct radeon_ps *radeon_state) 2275 { 2276 struct si_power_info *si_pi = si_get_pi(rdev); 2277 2278 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2279 radeon_state->vclk && radeon_state->dclk) 2280 return true; 2281 2282 return false; 2283 } 2284 2285 static int si_populate_power_containment_values(struct radeon_device *rdev, 2286 struct radeon_ps *radeon_state, 2287 SISLANDS_SMC_SWSTATE *smc_state) 2288 { 2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2290 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2291 struct ni_ps *state = ni_get_ps(radeon_state); 2292 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2293 u32 prev_sclk; 2294 u32 max_sclk; 2295 u32 min_sclk; 2296 u16 prev_std_vddc; 2297 u16 curr_std_vddc; 2298 int i; 2299 u16 pwr_efficiency_ratio; 2300 u8 max_ps_percent; 2301 bool disable_uvd_power_tune; 2302 int ret; 2303 2304 if (ni_pi->enable_power_containment == false) 2305 return 0; 2306 2307 if (state->performance_level_count == 0) 2308 return -EINVAL; 2309 2310 if (smc_state->levelCount != state->performance_level_count) 2311 return -EINVAL; 2312 2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2314 2315 smc_state->levels[0].dpm2.MaxPS = 0; 2316 smc_state->levels[0].dpm2.NearTDPDec = 0; 2317 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2318 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2319 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2320 2321 for (i = 1; i < state->performance_level_count; i++) { 2322 prev_sclk = state->performance_levels[i-1].sclk; 2323 max_sclk = state->performance_levels[i].sclk; 2324 if (i == 1) 2325 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2326 else 2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2328 2329 if (prev_sclk > max_sclk) 2330 return -EINVAL; 2331 2332 if ((max_ps_percent == 0) || 2333 (prev_sclk == max_sclk) || 2334 disable_uvd_power_tune) { 2335 min_sclk = max_sclk; 2336 } else if (i == 1) { 2337 min_sclk = prev_sclk; 2338 } else { 2339 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2340 } 2341 2342 if (min_sclk < state->performance_levels[0].sclk) 2343 min_sclk = state->performance_levels[0].sclk; 2344 2345 if (min_sclk == 0) 2346 return -EINVAL; 2347 2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2349 state->performance_levels[i-1].vddc, &vddc); 2350 if (ret) 2351 return ret; 2352 2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2354 if (ret) 2355 return ret; 2356 2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2358 state->performance_levels[i].vddc, &vddc); 2359 if (ret) 2360 return ret; 2361 2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2363 if (ret) 2364 return ret; 2365 2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2367 prev_std_vddc, curr_std_vddc); 2368 2369 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2370 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2371 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2372 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2373 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2374 } 2375 2376 return 0; 2377 } 2378 2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2380 struct radeon_ps *radeon_state, 2381 SISLANDS_SMC_SWSTATE *smc_state) 2382 { 2383 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2384 struct ni_ps *state = ni_get_ps(radeon_state); 2385 u32 sq_power_throttle, sq_power_throttle2; 2386 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2387 int i; 2388 2389 if (state->performance_level_count == 0) 2390 return -EINVAL; 2391 2392 if (smc_state->levelCount != state->performance_level_count) 2393 return -EINVAL; 2394 2395 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2396 return -EINVAL; 2397 2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2399 enable_sq_ramping = false; 2400 2401 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2402 enable_sq_ramping = false; 2403 2404 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2405 enable_sq_ramping = false; 2406 2407 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2408 enable_sq_ramping = false; 2409 2410 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2411 enable_sq_ramping = false; 2412 2413 for (i = 0; i < state->performance_level_count; i++) { 2414 sq_power_throttle = 0; 2415 sq_power_throttle2 = 0; 2416 2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2418 enable_sq_ramping) { 2419 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2420 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2421 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2422 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2423 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2424 } else { 2425 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2426 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2427 } 2428 2429 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2430 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2431 } 2432 2433 return 0; 2434 } 2435 2436 static int si_enable_power_containment(struct radeon_device *rdev, 2437 struct radeon_ps *radeon_new_state, 2438 bool enable) 2439 { 2440 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2441 PPSMC_Result smc_result; 2442 int ret = 0; 2443 2444 if (ni_pi->enable_power_containment) { 2445 if (enable) { 2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2448 if (smc_result != PPSMC_Result_OK) { 2449 ret = -EINVAL; 2450 ni_pi->pc_enabled = false; 2451 } else { 2452 ni_pi->pc_enabled = true; 2453 } 2454 } 2455 } else { 2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2457 if (smc_result != PPSMC_Result_OK) 2458 ret = -EINVAL; 2459 ni_pi->pc_enabled = false; 2460 } 2461 } 2462 2463 return ret; 2464 } 2465 2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2467 { 2468 struct si_power_info *si_pi = si_get_pi(rdev); 2469 int ret = 0; 2470 struct si_dte_data *dte_data = &si_pi->dte_data; 2471 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2472 u32 table_size; 2473 u8 tdep_count; 2474 u32 i; 2475 2476 if (dte_data == NULL) 2477 si_pi->enable_dte = false; 2478 2479 if (si_pi->enable_dte == false) 2480 return 0; 2481 2482 if (dte_data->k <= 0) 2483 return -EINVAL; 2484 2485 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2486 if (dte_tables == NULL) { 2487 si_pi->enable_dte = false; 2488 return -ENOMEM; 2489 } 2490 2491 table_size = dte_data->k; 2492 2493 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2494 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2495 2496 tdep_count = dte_data->tdep_count; 2497 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2498 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2499 2500 dte_tables->K = cpu_to_be32(table_size); 2501 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2502 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2503 dte_tables->WindowSize = dte_data->window_size; 2504 dte_tables->temp_select = dte_data->temp_select; 2505 dte_tables->DTE_mode = dte_data->dte_mode; 2506 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2507 2508 if (tdep_count > 0) 2509 table_size--; 2510 2511 for (i = 0; i < table_size; i++) { 2512 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2513 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2514 } 2515 2516 dte_tables->Tdep_count = tdep_count; 2517 2518 for (i = 0; i < (u32)tdep_count; i++) { 2519 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2520 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2521 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2522 } 2523 2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2525 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2526 kfree(dte_tables); 2527 2528 return ret; 2529 } 2530 2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2532 u16 *max, u16 *min) 2533 { 2534 struct si_power_info *si_pi = si_get_pi(rdev); 2535 struct radeon_cac_leakage_table *table = 2536 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2537 u32 i; 2538 u32 v0_loadline; 2539 2540 2541 if (table == NULL) 2542 return -EINVAL; 2543 2544 *max = 0; 2545 *min = 0xFFFF; 2546 2547 for (i = 0; i < table->count; i++) { 2548 if (table->entries[i].vddc > *max) 2549 *max = table->entries[i].vddc; 2550 if (table->entries[i].vddc < *min) 2551 *min = table->entries[i].vddc; 2552 } 2553 2554 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2555 return -EINVAL; 2556 2557 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2558 2559 if (v0_loadline > 0xFFFFUL) 2560 return -EINVAL; 2561 2562 *min = (u16)v0_loadline; 2563 2564 if ((*min > *max) || (*max == 0) || (*min == 0)) 2565 return -EINVAL; 2566 2567 return 0; 2568 } 2569 2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2571 { 2572 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2573 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2574 } 2575 2576 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2577 PP_SIslands_CacConfig *cac_tables, 2578 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2579 u16 t0, u16 t_step) 2580 { 2581 struct si_power_info *si_pi = si_get_pi(rdev); 2582 u32 leakage; 2583 unsigned int i, j; 2584 s32 t; 2585 u32 smc_leakage; 2586 u32 scaling_factor; 2587 u16 voltage; 2588 2589 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2590 2591 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2592 t = (1000 * (i * t_step + t0)); 2593 2594 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2595 voltage = vddc_max - (vddc_step * j); 2596 2597 si_calculate_leakage_for_v_and_t(rdev, 2598 &si_pi->powertune_data->leakage_coefficients, 2599 voltage, 2600 t, 2601 si_pi->dyn_powertune_data.cac_leakage, 2602 &leakage); 2603 2604 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2605 2606 if (smc_leakage > 0xFFFF) 2607 smc_leakage = 0xFFFF; 2608 2609 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2610 cpu_to_be16((u16)smc_leakage); 2611 } 2612 } 2613 return 0; 2614 } 2615 2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2617 PP_SIslands_CacConfig *cac_tables, 2618 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2619 { 2620 struct si_power_info *si_pi = si_get_pi(rdev); 2621 u32 leakage; 2622 unsigned int i, j; 2623 u32 smc_leakage; 2624 u32 scaling_factor; 2625 u16 voltage; 2626 2627 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2628 2629 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2630 voltage = vddc_max - (vddc_step * j); 2631 2632 si_calculate_leakage_for_v(rdev, 2633 &si_pi->powertune_data->leakage_coefficients, 2634 si_pi->powertune_data->fixed_kt, 2635 voltage, 2636 si_pi->dyn_powertune_data.cac_leakage, 2637 &leakage); 2638 2639 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2640 2641 if (smc_leakage > 0xFFFF) 2642 smc_leakage = 0xFFFF; 2643 2644 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2645 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2646 cpu_to_be16((u16)smc_leakage); 2647 } 2648 return 0; 2649 } 2650 2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2652 { 2653 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2654 struct si_power_info *si_pi = si_get_pi(rdev); 2655 PP_SIslands_CacConfig *cac_tables = NULL; 2656 u16 vddc_max, vddc_min, vddc_step; 2657 u16 t0, t_step; 2658 u32 load_line_slope, reg; 2659 int ret = 0; 2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2661 2662 if (ni_pi->enable_cac == false) 2663 return 0; 2664 2665 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2666 if (!cac_tables) 2667 return -ENOMEM; 2668 2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2670 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2671 WREG32(CG_CAC_CTRL, reg); 2672 2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2674 si_pi->dyn_powertune_data.dc_pwr_value = 2675 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2677 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2678 2679 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2680 2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2682 if (ret) 2683 goto done_free; 2684 2685 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2686 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2687 t_step = 4; 2688 t0 = 60; 2689 2690 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2691 ret = si_init_dte_leakage_table(rdev, cac_tables, 2692 vddc_max, vddc_min, vddc_step, 2693 t0, t_step); 2694 else 2695 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2696 vddc_max, vddc_min, vddc_step); 2697 if (ret) 2698 goto done_free; 2699 2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2701 2702 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2703 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2704 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2705 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2706 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2707 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2708 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2709 cac_tables->calculation_repeats = cpu_to_be32(2); 2710 cac_tables->dc_cac = cpu_to_be32(0); 2711 cac_tables->log2_PG_LKG_SCALE = 12; 2712 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2713 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2714 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2715 2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2717 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2718 2719 if (ret) 2720 goto done_free; 2721 2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2723 2724 done_free: 2725 if (ret) { 2726 ni_pi->enable_cac = false; 2727 ni_pi->enable_power_containment = false; 2728 } 2729 2730 kfree(cac_tables); 2731 2732 return 0; 2733 } 2734 2735 static int si_program_cac_config_registers(struct radeon_device *rdev, 2736 const struct si_cac_config_reg *cac_config_regs) 2737 { 2738 const struct si_cac_config_reg *config_regs = cac_config_regs; 2739 u32 data = 0, offset; 2740 2741 if (!config_regs) 2742 return -EINVAL; 2743 2744 while (config_regs->offset != 0xFFFFFFFF) { 2745 switch (config_regs->type) { 2746 case SISLANDS_CACCONFIG_CGIND: 2747 offset = SMC_CG_IND_START + config_regs->offset; 2748 if (offset < SMC_CG_IND_END) 2749 data = RREG32_SMC(offset); 2750 break; 2751 default: 2752 data = RREG32(config_regs->offset << 2); 2753 break; 2754 } 2755 2756 data &= ~config_regs->mask; 2757 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2758 2759 switch (config_regs->type) { 2760 case SISLANDS_CACCONFIG_CGIND: 2761 offset = SMC_CG_IND_START + config_regs->offset; 2762 if (offset < SMC_CG_IND_END) 2763 WREG32_SMC(offset, data); 2764 break; 2765 default: 2766 WREG32(config_regs->offset << 2, data); 2767 break; 2768 } 2769 config_regs++; 2770 } 2771 return 0; 2772 } 2773 2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2775 { 2776 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2777 struct si_power_info *si_pi = si_get_pi(rdev); 2778 int ret; 2779 2780 if ((ni_pi->enable_cac == false) || 2781 (ni_pi->cac_configuration_required == false)) 2782 return 0; 2783 2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2785 if (ret) 2786 return ret; 2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2788 if (ret) 2789 return ret; 2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2791 if (ret) 2792 return ret; 2793 2794 return 0; 2795 } 2796 2797 static int si_enable_smc_cac(struct radeon_device *rdev, 2798 struct radeon_ps *radeon_new_state, 2799 bool enable) 2800 { 2801 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2802 struct si_power_info *si_pi = si_get_pi(rdev); 2803 PPSMC_Result smc_result; 2804 int ret = 0; 2805 2806 if (ni_pi->enable_cac) { 2807 if (enable) { 2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2809 if (ni_pi->support_cac_long_term_average) { 2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2811 if (smc_result != PPSMC_Result_OK) 2812 ni_pi->support_cac_long_term_average = false; 2813 } 2814 2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2816 if (smc_result != PPSMC_Result_OK) { 2817 ret = -EINVAL; 2818 ni_pi->cac_enabled = false; 2819 } else { 2820 ni_pi->cac_enabled = true; 2821 } 2822 2823 if (si_pi->enable_dte) { 2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2825 if (smc_result != PPSMC_Result_OK) 2826 ret = -EINVAL; 2827 } 2828 } 2829 } else if (ni_pi->cac_enabled) { 2830 if (si_pi->enable_dte) 2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2832 2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2834 2835 ni_pi->cac_enabled = false; 2836 2837 if (ni_pi->support_cac_long_term_average) 2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2839 } 2840 } 2841 return ret; 2842 } 2843 2844 static int si_init_smc_spll_table(struct radeon_device *rdev) 2845 { 2846 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2847 struct si_power_info *si_pi = si_get_pi(rdev); 2848 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2849 SISLANDS_SMC_SCLK_VALUE sclk_params; 2850 u32 fb_div, p_div; 2851 u32 clk_s, clk_v; 2852 u32 sclk = 0; 2853 int ret = 0; 2854 u32 tmp; 2855 int i; 2856 2857 if (si_pi->spll_table_start == 0) 2858 return -EINVAL; 2859 2860 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2861 if (spll_table == NULL) 2862 return -ENOMEM; 2863 2864 for (i = 0; i < 256; i++) { 2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2866 if (ret) 2867 break; 2868 2869 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2870 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2872 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2873 2874 fb_div &= ~0x00001FFF; 2875 fb_div >>= 1; 2876 clk_v >>= 6; 2877 2878 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2879 ret = -EINVAL; 2880 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2881 ret = -EINVAL; 2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2883 ret = -EINVAL; 2884 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2885 ret = -EINVAL; 2886 2887 if (ret) 2888 break; 2889 2890 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2891 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2892 spll_table->freq[i] = cpu_to_be32(tmp); 2893 2894 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2896 spll_table->ss[i] = cpu_to_be32(tmp); 2897 2898 sclk += 512; 2899 } 2900 2901 2902 if (!ret) 2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2904 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2905 si_pi->sram_end); 2906 2907 if (ret) 2908 ni_pi->enable_power_containment = false; 2909 2910 kfree(spll_table); 2911 2912 return ret; 2913 } 2914 2915 struct si_dpm_quirk { 2916 u32 chip_vendor; 2917 u32 chip_device; 2918 u32 subsys_vendor; 2919 u32 subsys_device; 2920 u32 max_sclk; 2921 u32 max_mclk; 2922 }; 2923 2924 /* cards with dpm stability problems */ 2925 static struct si_dpm_quirk si_dpm_quirk_list[] = { 2926 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 2927 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 2929 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 2930 { PCI_VENDOR_ID_ATI, 0x6811, 0x1762, 0x2015, 0, 120000 }, 2931 { 0, 0, 0, 0 }, 2932 }; 2933 2934 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2935 u16 vce_voltage) 2936 { 2937 u16 highest_leakage = 0; 2938 struct si_power_info *si_pi = si_get_pi(rdev); 2939 int i; 2940 2941 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2942 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2943 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2944 } 2945 2946 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2947 return highest_leakage; 2948 2949 return vce_voltage; 2950 } 2951 2952 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2953 u32 evclk, u32 ecclk, u16 *voltage) 2954 { 2955 u32 i; 2956 int ret = -EINVAL; 2957 struct radeon_vce_clock_voltage_dependency_table *table = 2958 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2959 2960 if (((evclk == 0) && (ecclk == 0)) || 2961 (table && (table->count == 0))) { 2962 *voltage = 0; 2963 return 0; 2964 } 2965 2966 for (i = 0; i < table->count; i++) { 2967 if ((evclk <= table->entries[i].evclk) && 2968 (ecclk <= table->entries[i].ecclk)) { 2969 *voltage = table->entries[i].v; 2970 ret = 0; 2971 break; 2972 } 2973 } 2974 2975 /* if no match return the highest voltage */ 2976 if (ret) 2977 *voltage = table->entries[table->count - 1].v; 2978 2979 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2980 2981 return ret; 2982 } 2983 2984 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2985 struct radeon_ps *rps) 2986 { 2987 struct ni_ps *ps = ni_get_ps(rps); 2988 struct radeon_clock_and_voltage_limits *max_limits; 2989 bool disable_mclk_switching = false; 2990 bool disable_sclk_switching = false; 2991 u32 mclk, sclk; 2992 u16 vddc, vddci, min_vce_voltage = 0; 2993 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2994 u32 max_sclk = 0, max_mclk = 0; 2995 int i; 2996 struct si_dpm_quirk *p = si_dpm_quirk_list; 2997 2998 /* Apply dpm quirks */ 2999 while (p && p->chip_device != 0) { 3000 if (rdev->pdev->vendor == p->chip_vendor && 3001 rdev->pdev->device == p->chip_device && 3002 rdev->pdev->subsystem_vendor == p->subsys_vendor && 3003 rdev->pdev->subsystem_device == p->subsys_device) { 3004 max_sclk = p->max_sclk; 3005 max_mclk = p->max_mclk; 3006 break; 3007 } 3008 ++p; 3009 } 3010 3011 if (rps->vce_active) { 3012 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3013 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3014 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3015 &min_vce_voltage); 3016 } else { 3017 rps->evclk = 0; 3018 rps->ecclk = 0; 3019 } 3020 3021 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3022 ni_dpm_vblank_too_short(rdev)) 3023 disable_mclk_switching = true; 3024 3025 if (rps->vclk || rps->dclk) { 3026 disable_mclk_switching = true; 3027 disable_sclk_switching = true; 3028 } 3029 3030 if (rdev->pm.dpm.ac_power) 3031 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3032 else 3033 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3034 3035 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3036 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3037 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3038 } 3039 if (rdev->pm.dpm.ac_power == false) { 3040 for (i = 0; i < ps->performance_level_count; i++) { 3041 if (ps->performance_levels[i].mclk > max_limits->mclk) 3042 ps->performance_levels[i].mclk = max_limits->mclk; 3043 if (ps->performance_levels[i].sclk > max_limits->sclk) 3044 ps->performance_levels[i].sclk = max_limits->sclk; 3045 if (ps->performance_levels[i].vddc > max_limits->vddc) 3046 ps->performance_levels[i].vddc = max_limits->vddc; 3047 if (ps->performance_levels[i].vddci > max_limits->vddci) 3048 ps->performance_levels[i].vddci = max_limits->vddci; 3049 } 3050 } 3051 3052 /* limit clocks to max supported clocks based on voltage dependency tables */ 3053 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3054 &max_sclk_vddc); 3055 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3056 &max_mclk_vddci); 3057 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3058 &max_mclk_vddc); 3059 3060 for (i = 0; i < ps->performance_level_count; i++) { 3061 if (max_sclk_vddc) { 3062 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3063 ps->performance_levels[i].sclk = max_sclk_vddc; 3064 } 3065 if (max_mclk_vddci) { 3066 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3067 ps->performance_levels[i].mclk = max_mclk_vddci; 3068 } 3069 if (max_mclk_vddc) { 3070 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3071 ps->performance_levels[i].mclk = max_mclk_vddc; 3072 } 3073 if (max_mclk) { 3074 if (ps->performance_levels[i].mclk > max_mclk) 3075 ps->performance_levels[i].mclk = max_mclk; 3076 } 3077 if (max_sclk) { 3078 if (ps->performance_levels[i].sclk > max_sclk) 3079 ps->performance_levels[i].sclk = max_sclk; 3080 } 3081 } 3082 3083 /* XXX validate the min clocks required for display */ 3084 3085 if (disable_mclk_switching) { 3086 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3087 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3088 } else { 3089 mclk = ps->performance_levels[0].mclk; 3090 vddci = ps->performance_levels[0].vddci; 3091 } 3092 3093 if (disable_sclk_switching) { 3094 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3095 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3096 } else { 3097 sclk = ps->performance_levels[0].sclk; 3098 vddc = ps->performance_levels[0].vddc; 3099 } 3100 3101 if (rps->vce_active) { 3102 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3103 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3104 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3105 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3106 } 3107 3108 /* adjusted low state */ 3109 ps->performance_levels[0].sclk = sclk; 3110 ps->performance_levels[0].mclk = mclk; 3111 ps->performance_levels[0].vddc = vddc; 3112 ps->performance_levels[0].vddci = vddci; 3113 3114 if (disable_sclk_switching) { 3115 sclk = ps->performance_levels[0].sclk; 3116 for (i = 1; i < ps->performance_level_count; i++) { 3117 if (sclk < ps->performance_levels[i].sclk) 3118 sclk = ps->performance_levels[i].sclk; 3119 } 3120 for (i = 0; i < ps->performance_level_count; i++) { 3121 ps->performance_levels[i].sclk = sclk; 3122 ps->performance_levels[i].vddc = vddc; 3123 } 3124 } else { 3125 for (i = 1; i < ps->performance_level_count; i++) { 3126 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3127 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3128 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3129 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3130 } 3131 } 3132 3133 if (disable_mclk_switching) { 3134 mclk = ps->performance_levels[0].mclk; 3135 for (i = 1; i < ps->performance_level_count; i++) { 3136 if (mclk < ps->performance_levels[i].mclk) 3137 mclk = ps->performance_levels[i].mclk; 3138 } 3139 for (i = 0; i < ps->performance_level_count; i++) { 3140 ps->performance_levels[i].mclk = mclk; 3141 ps->performance_levels[i].vddci = vddci; 3142 } 3143 } else { 3144 for (i = 1; i < ps->performance_level_count; i++) { 3145 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3146 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3147 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3148 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3149 } 3150 } 3151 3152 for (i = 0; i < ps->performance_level_count; i++) 3153 btc_adjust_clock_combinations(rdev, max_limits, 3154 &ps->performance_levels[i]); 3155 3156 for (i = 0; i < ps->performance_level_count; i++) { 3157 if (ps->performance_levels[i].vddc < min_vce_voltage) 3158 ps->performance_levels[i].vddc = min_vce_voltage; 3159 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3160 ps->performance_levels[i].sclk, 3161 max_limits->vddc, &ps->performance_levels[i].vddc); 3162 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3163 ps->performance_levels[i].mclk, 3164 max_limits->vddci, &ps->performance_levels[i].vddci); 3165 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3166 ps->performance_levels[i].mclk, 3167 max_limits->vddc, &ps->performance_levels[i].vddc); 3168 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3169 rdev->clock.current_dispclk, 3170 max_limits->vddc, &ps->performance_levels[i].vddc); 3171 } 3172 3173 for (i = 0; i < ps->performance_level_count; i++) { 3174 btc_apply_voltage_delta_rules(rdev, 3175 max_limits->vddc, max_limits->vddci, 3176 &ps->performance_levels[i].vddc, 3177 &ps->performance_levels[i].vddci); 3178 } 3179 3180 ps->dc_compatible = true; 3181 for (i = 0; i < ps->performance_level_count; i++) { 3182 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3183 ps->dc_compatible = false; 3184 } 3185 } 3186 3187 #if 0 3188 static int si_read_smc_soft_register(struct radeon_device *rdev, 3189 u16 reg_offset, u32 *value) 3190 { 3191 struct si_power_info *si_pi = si_get_pi(rdev); 3192 3193 return si_read_smc_sram_dword(rdev, 3194 si_pi->soft_regs_start + reg_offset, value, 3195 si_pi->sram_end); 3196 } 3197 #endif 3198 3199 static int si_write_smc_soft_register(struct radeon_device *rdev, 3200 u16 reg_offset, u32 value) 3201 { 3202 struct si_power_info *si_pi = si_get_pi(rdev); 3203 3204 return si_write_smc_sram_dword(rdev, 3205 si_pi->soft_regs_start + reg_offset, 3206 value, si_pi->sram_end); 3207 } 3208 3209 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3210 { 3211 bool ret = false; 3212 u32 tmp, width, row, column, bank, density; 3213 bool is_memory_gddr5, is_special; 3214 3215 tmp = RREG32(MC_SEQ_MISC0); 3216 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3217 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3218 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3219 3220 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3221 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3222 3223 tmp = RREG32(MC_ARB_RAMCFG); 3224 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3225 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3226 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3227 3228 density = (1 << (row + column - 20 + bank)) * width; 3229 3230 if ((rdev->pdev->device == 0x6819) && 3231 is_memory_gddr5 && is_special && (density == 0x400)) 3232 ret = true; 3233 3234 return ret; 3235 } 3236 3237 static void si_get_leakage_vddc(struct radeon_device *rdev) 3238 { 3239 struct si_power_info *si_pi = si_get_pi(rdev); 3240 u16 vddc, count = 0; 3241 int i, ret; 3242 3243 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3244 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3245 3246 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3247 si_pi->leakage_voltage.entries[count].voltage = vddc; 3248 si_pi->leakage_voltage.entries[count].leakage_index = 3249 SISLANDS_LEAKAGE_INDEX0 + i; 3250 count++; 3251 } 3252 } 3253 si_pi->leakage_voltage.count = count; 3254 } 3255 3256 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3257 u32 index, u16 *leakage_voltage) 3258 { 3259 struct si_power_info *si_pi = si_get_pi(rdev); 3260 int i; 3261 3262 if (leakage_voltage == NULL) 3263 return -EINVAL; 3264 3265 if ((index & 0xff00) != 0xff00) 3266 return -EINVAL; 3267 3268 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3269 return -EINVAL; 3270 3271 if (index < SISLANDS_LEAKAGE_INDEX0) 3272 return -EINVAL; 3273 3274 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3275 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3276 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3277 return 0; 3278 } 3279 } 3280 return -EAGAIN; 3281 } 3282 3283 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3284 { 3285 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3286 bool want_thermal_protection; 3287 enum radeon_dpm_event_src dpm_event_src; 3288 3289 switch (sources) { 3290 case 0: 3291 default: 3292 want_thermal_protection = false; 3293 break; 3294 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3295 want_thermal_protection = true; 3296 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3297 break; 3298 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3299 want_thermal_protection = true; 3300 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3301 break; 3302 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3303 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3304 want_thermal_protection = true; 3305 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3306 break; 3307 } 3308 3309 if (want_thermal_protection) { 3310 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3311 if (pi->thermal_protection) 3312 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3313 } else { 3314 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3315 } 3316 } 3317 3318 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3319 enum radeon_dpm_auto_throttle_src source, 3320 bool enable) 3321 { 3322 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3323 3324 if (enable) { 3325 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3326 pi->active_auto_throttle_sources |= 1 << source; 3327 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3328 } 3329 } else { 3330 if (pi->active_auto_throttle_sources & (1 << source)) { 3331 pi->active_auto_throttle_sources &= ~(1 << source); 3332 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3333 } 3334 } 3335 } 3336 3337 static void si_start_dpm(struct radeon_device *rdev) 3338 { 3339 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3340 } 3341 3342 static void si_stop_dpm(struct radeon_device *rdev) 3343 { 3344 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3345 } 3346 3347 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3348 { 3349 if (enable) 3350 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3351 else 3352 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3353 3354 } 3355 3356 #if 0 3357 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3358 u32 thermal_level) 3359 { 3360 PPSMC_Result ret; 3361 3362 if (thermal_level == 0) { 3363 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3364 if (ret == PPSMC_Result_OK) 3365 return 0; 3366 else 3367 return -EINVAL; 3368 } 3369 return 0; 3370 } 3371 3372 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3373 { 3374 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3375 } 3376 #endif 3377 3378 #if 0 3379 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3380 { 3381 if (ac_power) 3382 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3383 0 : -EINVAL; 3384 3385 return 0; 3386 } 3387 #endif 3388 3389 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3390 PPSMC_Msg msg, u32 parameter) 3391 { 3392 WREG32(SMC_SCRATCH0, parameter); 3393 return si_send_msg_to_smc(rdev, msg); 3394 } 3395 3396 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3397 { 3398 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3399 return -EINVAL; 3400 3401 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3402 0 : -EINVAL; 3403 } 3404 3405 int si_dpm_force_performance_level(struct radeon_device *rdev, 3406 enum radeon_dpm_forced_level level) 3407 { 3408 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3409 struct ni_ps *ps = ni_get_ps(rps); 3410 u32 levels = ps->performance_level_count; 3411 3412 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3413 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3414 return -EINVAL; 3415 3416 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3417 return -EINVAL; 3418 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3419 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3420 return -EINVAL; 3421 3422 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3423 return -EINVAL; 3424 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3425 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3426 return -EINVAL; 3427 3428 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3429 return -EINVAL; 3430 } 3431 3432 rdev->pm.dpm.forced_level = level; 3433 3434 return 0; 3435 } 3436 3437 #if 0 3438 static int si_set_boot_state(struct radeon_device *rdev) 3439 { 3440 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3441 0 : -EINVAL; 3442 } 3443 #endif 3444 3445 static int si_set_sw_state(struct radeon_device *rdev) 3446 { 3447 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3448 0 : -EINVAL; 3449 } 3450 3451 static int si_halt_smc(struct radeon_device *rdev) 3452 { 3453 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3454 return -EINVAL; 3455 3456 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3457 0 : -EINVAL; 3458 } 3459 3460 static int si_resume_smc(struct radeon_device *rdev) 3461 { 3462 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3463 return -EINVAL; 3464 3465 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3466 0 : -EINVAL; 3467 } 3468 3469 static void si_dpm_start_smc(struct radeon_device *rdev) 3470 { 3471 si_program_jump_on_start(rdev); 3472 si_start_smc(rdev); 3473 si_start_smc_clock(rdev); 3474 } 3475 3476 static void si_dpm_stop_smc(struct radeon_device *rdev) 3477 { 3478 si_reset_smc(rdev); 3479 si_stop_smc_clock(rdev); 3480 } 3481 3482 static int si_process_firmware_header(struct radeon_device *rdev) 3483 { 3484 struct si_power_info *si_pi = si_get_pi(rdev); 3485 u32 tmp; 3486 int ret; 3487 3488 ret = si_read_smc_sram_dword(rdev, 3489 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3490 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3491 &tmp, si_pi->sram_end); 3492 if (ret) 3493 return ret; 3494 3495 si_pi->state_table_start = tmp; 3496 3497 ret = si_read_smc_sram_dword(rdev, 3498 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3499 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3500 &tmp, si_pi->sram_end); 3501 if (ret) 3502 return ret; 3503 3504 si_pi->soft_regs_start = tmp; 3505 3506 ret = si_read_smc_sram_dword(rdev, 3507 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3508 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3509 &tmp, si_pi->sram_end); 3510 if (ret) 3511 return ret; 3512 3513 si_pi->mc_reg_table_start = tmp; 3514 3515 ret = si_read_smc_sram_dword(rdev, 3516 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3517 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3518 &tmp, si_pi->sram_end); 3519 if (ret) 3520 return ret; 3521 3522 si_pi->fan_table_start = tmp; 3523 3524 ret = si_read_smc_sram_dword(rdev, 3525 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3526 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3527 &tmp, si_pi->sram_end); 3528 if (ret) 3529 return ret; 3530 3531 si_pi->arb_table_start = tmp; 3532 3533 ret = si_read_smc_sram_dword(rdev, 3534 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3535 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3536 &tmp, si_pi->sram_end); 3537 if (ret) 3538 return ret; 3539 3540 si_pi->cac_table_start = tmp; 3541 3542 ret = si_read_smc_sram_dword(rdev, 3543 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3544 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3545 &tmp, si_pi->sram_end); 3546 if (ret) 3547 return ret; 3548 3549 si_pi->dte_table_start = tmp; 3550 3551 ret = si_read_smc_sram_dword(rdev, 3552 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3553 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3554 &tmp, si_pi->sram_end); 3555 if (ret) 3556 return ret; 3557 3558 si_pi->spll_table_start = tmp; 3559 3560 ret = si_read_smc_sram_dword(rdev, 3561 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3562 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3563 &tmp, si_pi->sram_end); 3564 if (ret) 3565 return ret; 3566 3567 si_pi->papm_cfg_table_start = tmp; 3568 3569 return ret; 3570 } 3571 3572 static void si_read_clock_registers(struct radeon_device *rdev) 3573 { 3574 struct si_power_info *si_pi = si_get_pi(rdev); 3575 3576 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3577 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3578 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3579 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3580 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3581 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3582 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3583 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3584 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3585 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3586 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3587 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3588 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3589 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3590 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3591 } 3592 3593 static void si_enable_thermal_protection(struct radeon_device *rdev, 3594 bool enable) 3595 { 3596 if (enable) 3597 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3598 else 3599 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3600 } 3601 3602 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3603 { 3604 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3605 } 3606 3607 #if 0 3608 static int si_enter_ulp_state(struct radeon_device *rdev) 3609 { 3610 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3611 3612 udelay(25000); 3613 3614 return 0; 3615 } 3616 3617 static int si_exit_ulp_state(struct radeon_device *rdev) 3618 { 3619 int i; 3620 3621 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3622 3623 udelay(7000); 3624 3625 for (i = 0; i < rdev->usec_timeout; i++) { 3626 if (RREG32(SMC_RESP_0) == 1) 3627 break; 3628 udelay(1000); 3629 } 3630 3631 return 0; 3632 } 3633 #endif 3634 3635 static int si_notify_smc_display_change(struct radeon_device *rdev, 3636 bool has_display) 3637 { 3638 PPSMC_Msg msg = has_display ? 3639 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3640 3641 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3642 0 : -EINVAL; 3643 } 3644 3645 static void si_program_response_times(struct radeon_device *rdev) 3646 { 3647 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3648 u32 vddc_dly, acpi_dly, vbi_dly; 3649 u32 reference_clock; 3650 3651 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3652 3653 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3654 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3655 3656 if (voltage_response_time == 0) 3657 voltage_response_time = 1000; 3658 3659 acpi_delay_time = 15000; 3660 vbi_time_out = 100000; 3661 3662 reference_clock = radeon_get_xclk(rdev); 3663 3664 vddc_dly = (voltage_response_time * reference_clock) / 100; 3665 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3666 vbi_dly = (vbi_time_out * reference_clock) / 100; 3667 3668 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3669 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3670 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3671 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3672 } 3673 3674 static void si_program_ds_registers(struct radeon_device *rdev) 3675 { 3676 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3677 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3678 3679 if (eg_pi->sclk_deep_sleep) { 3680 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3681 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3682 ~AUTOSCALE_ON_SS_CLEAR); 3683 } 3684 } 3685 3686 static void si_program_display_gap(struct radeon_device *rdev) 3687 { 3688 u32 tmp, pipe; 3689 int i; 3690 3691 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3692 if (rdev->pm.dpm.new_active_crtc_count > 0) 3693 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3694 else 3695 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3696 3697 if (rdev->pm.dpm.new_active_crtc_count > 1) 3698 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3699 else 3700 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3701 3702 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3703 3704 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3705 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3706 3707 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3708 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3709 /* find the first active crtc */ 3710 for (i = 0; i < rdev->num_crtc; i++) { 3711 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3712 break; 3713 } 3714 if (i == rdev->num_crtc) 3715 pipe = 0; 3716 else 3717 pipe = i; 3718 3719 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3720 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3721 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3722 } 3723 3724 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3725 * This can be a problem on PowerXpress systems or if you want to use the card 3726 * for offscreen rendering or compute if there are no crtcs enabled. 3727 */ 3728 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3729 } 3730 3731 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3732 { 3733 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3734 3735 if (enable) { 3736 if (pi->sclk_ss) 3737 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3738 } else { 3739 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3740 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3741 } 3742 } 3743 3744 static void si_setup_bsp(struct radeon_device *rdev) 3745 { 3746 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3747 u32 xclk = radeon_get_xclk(rdev); 3748 3749 r600_calculate_u_and_p(pi->asi, 3750 xclk, 3751 16, 3752 &pi->bsp, 3753 &pi->bsu); 3754 3755 r600_calculate_u_and_p(pi->pasi, 3756 xclk, 3757 16, 3758 &pi->pbsp, 3759 &pi->pbsu); 3760 3761 3762 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3763 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3764 3765 WREG32(CG_BSP, pi->dsp); 3766 } 3767 3768 static void si_program_git(struct radeon_device *rdev) 3769 { 3770 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3771 } 3772 3773 static void si_program_tp(struct radeon_device *rdev) 3774 { 3775 int i; 3776 enum r600_td td = R600_TD_DFLT; 3777 3778 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3779 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3780 3781 if (td == R600_TD_AUTO) 3782 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3783 else 3784 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3785 3786 if (td == R600_TD_UP) 3787 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3788 3789 if (td == R600_TD_DOWN) 3790 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3791 } 3792 3793 static void si_program_tpp(struct radeon_device *rdev) 3794 { 3795 WREG32(CG_TPC, R600_TPC_DFLT); 3796 } 3797 3798 static void si_program_sstp(struct radeon_device *rdev) 3799 { 3800 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3801 } 3802 3803 static void si_enable_display_gap(struct radeon_device *rdev) 3804 { 3805 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3806 3807 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3808 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3809 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3810 3811 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3812 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3813 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3814 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3815 } 3816 3817 static void si_program_vc(struct radeon_device *rdev) 3818 { 3819 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3820 3821 WREG32(CG_FTV, pi->vrc); 3822 } 3823 3824 static void si_clear_vc(struct radeon_device *rdev) 3825 { 3826 WREG32(CG_FTV, 0); 3827 } 3828 3829 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3830 { 3831 u8 mc_para_index; 3832 3833 if (memory_clock < 10000) 3834 mc_para_index = 0; 3835 else if (memory_clock >= 80000) 3836 mc_para_index = 0x0f; 3837 else 3838 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3839 return mc_para_index; 3840 } 3841 3842 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3843 { 3844 u8 mc_para_index; 3845 3846 if (strobe_mode) { 3847 if (memory_clock < 12500) 3848 mc_para_index = 0x00; 3849 else if (memory_clock > 47500) 3850 mc_para_index = 0x0f; 3851 else 3852 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3853 } else { 3854 if (memory_clock < 65000) 3855 mc_para_index = 0x00; 3856 else if (memory_clock > 135000) 3857 mc_para_index = 0x0f; 3858 else 3859 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3860 } 3861 return mc_para_index; 3862 } 3863 3864 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3865 { 3866 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3867 bool strobe_mode = false; 3868 u8 result = 0; 3869 3870 if (mclk <= pi->mclk_strobe_mode_threshold) 3871 strobe_mode = true; 3872 3873 if (pi->mem_gddr5) 3874 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3875 else 3876 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3877 3878 if (strobe_mode) 3879 result |= SISLANDS_SMC_STROBE_ENABLE; 3880 3881 return result; 3882 } 3883 3884 static int si_upload_firmware(struct radeon_device *rdev) 3885 { 3886 struct si_power_info *si_pi = si_get_pi(rdev); 3887 int ret; 3888 3889 si_reset_smc(rdev); 3890 si_stop_smc_clock(rdev); 3891 3892 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3893 3894 return ret; 3895 } 3896 3897 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3898 const struct atom_voltage_table *table, 3899 const struct radeon_phase_shedding_limits_table *limits) 3900 { 3901 u32 data, num_bits, num_levels; 3902 3903 if ((table == NULL) || (limits == NULL)) 3904 return false; 3905 3906 data = table->mask_low; 3907 3908 num_bits = hweight32(data); 3909 3910 if (num_bits == 0) 3911 return false; 3912 3913 num_levels = (1 << num_bits); 3914 3915 if (table->count != num_levels) 3916 return false; 3917 3918 if (limits->count != (num_levels - 1)) 3919 return false; 3920 3921 return true; 3922 } 3923 3924 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3925 u32 max_voltage_steps, 3926 struct atom_voltage_table *voltage_table) 3927 { 3928 unsigned int i, diff; 3929 3930 if (voltage_table->count <= max_voltage_steps) 3931 return; 3932 3933 diff = voltage_table->count - max_voltage_steps; 3934 3935 for (i= 0; i < max_voltage_steps; i++) 3936 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3937 3938 voltage_table->count = max_voltage_steps; 3939 } 3940 3941 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3942 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3943 struct atom_voltage_table *voltage_table) 3944 { 3945 u32 i; 3946 3947 if (voltage_dependency_table == NULL) 3948 return -EINVAL; 3949 3950 voltage_table->mask_low = 0; 3951 voltage_table->phase_delay = 0; 3952 3953 voltage_table->count = voltage_dependency_table->count; 3954 for (i = 0; i < voltage_table->count; i++) { 3955 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3956 voltage_table->entries[i].smio_low = 0; 3957 } 3958 3959 return 0; 3960 } 3961 3962 static int si_construct_voltage_tables(struct radeon_device *rdev) 3963 { 3964 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3965 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3966 struct si_power_info *si_pi = si_get_pi(rdev); 3967 int ret; 3968 3969 if (pi->voltage_control) { 3970 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3971 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3972 if (ret) 3973 return ret; 3974 3975 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3976 si_trim_voltage_table_to_fit_state_table(rdev, 3977 SISLANDS_MAX_NO_VREG_STEPS, 3978 &eg_pi->vddc_voltage_table); 3979 } else if (si_pi->voltage_control_svi2) { 3980 ret = si_get_svi2_voltage_table(rdev, 3981 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3982 &eg_pi->vddc_voltage_table); 3983 if (ret) 3984 return ret; 3985 } else { 3986 return -EINVAL; 3987 } 3988 3989 if (eg_pi->vddci_control) { 3990 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3991 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3992 if (ret) 3993 return ret; 3994 3995 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3996 si_trim_voltage_table_to_fit_state_table(rdev, 3997 SISLANDS_MAX_NO_VREG_STEPS, 3998 &eg_pi->vddci_voltage_table); 3999 } 4000 if (si_pi->vddci_control_svi2) { 4001 ret = si_get_svi2_voltage_table(rdev, 4002 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4003 &eg_pi->vddci_voltage_table); 4004 if (ret) 4005 return ret; 4006 } 4007 4008 if (pi->mvdd_control) { 4009 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4010 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4011 4012 if (ret) { 4013 pi->mvdd_control = false; 4014 return ret; 4015 } 4016 4017 if (si_pi->mvdd_voltage_table.count == 0) { 4018 pi->mvdd_control = false; 4019 return -EINVAL; 4020 } 4021 4022 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4023 si_trim_voltage_table_to_fit_state_table(rdev, 4024 SISLANDS_MAX_NO_VREG_STEPS, 4025 &si_pi->mvdd_voltage_table); 4026 } 4027 4028 if (si_pi->vddc_phase_shed_control) { 4029 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4030 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4031 if (ret) 4032 si_pi->vddc_phase_shed_control = false; 4033 4034 if ((si_pi->vddc_phase_shed_table.count == 0) || 4035 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4036 si_pi->vddc_phase_shed_control = false; 4037 } 4038 4039 return 0; 4040 } 4041 4042 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4043 const struct atom_voltage_table *voltage_table, 4044 SISLANDS_SMC_STATETABLE *table) 4045 { 4046 unsigned int i; 4047 4048 for (i = 0; i < voltage_table->count; i++) 4049 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4050 } 4051 4052 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4053 SISLANDS_SMC_STATETABLE *table) 4054 { 4055 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4056 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4057 struct si_power_info *si_pi = si_get_pi(rdev); 4058 u8 i; 4059 4060 if (si_pi->voltage_control_svi2) { 4061 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4062 si_pi->svc_gpio_id); 4063 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4064 si_pi->svd_gpio_id); 4065 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4066 2); 4067 } else { 4068 if (eg_pi->vddc_voltage_table.count) { 4069 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4070 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4071 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4072 4073 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4074 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4075 table->maxVDDCIndexInPPTable = i; 4076 break; 4077 } 4078 } 4079 } 4080 4081 if (eg_pi->vddci_voltage_table.count) { 4082 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4083 4084 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4085 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4086 } 4087 4088 4089 if (si_pi->mvdd_voltage_table.count) { 4090 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4091 4092 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4093 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4094 } 4095 4096 if (si_pi->vddc_phase_shed_control) { 4097 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4098 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4099 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4100 4101 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4102 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4103 4104 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4105 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4106 } else { 4107 si_pi->vddc_phase_shed_control = false; 4108 } 4109 } 4110 } 4111 4112 return 0; 4113 } 4114 4115 static int si_populate_voltage_value(struct radeon_device *rdev, 4116 const struct atom_voltage_table *table, 4117 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4118 { 4119 unsigned int i; 4120 4121 for (i = 0; i < table->count; i++) { 4122 if (value <= table->entries[i].value) { 4123 voltage->index = (u8)i; 4124 voltage->value = cpu_to_be16(table->entries[i].value); 4125 break; 4126 } 4127 } 4128 4129 if (i >= table->count) 4130 return -EINVAL; 4131 4132 return 0; 4133 } 4134 4135 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4136 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4137 { 4138 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4139 struct si_power_info *si_pi = si_get_pi(rdev); 4140 4141 if (pi->mvdd_control) { 4142 if (mclk <= pi->mvdd_split_frequency) 4143 voltage->index = 0; 4144 else 4145 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4146 4147 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4148 } 4149 return 0; 4150 } 4151 4152 static int si_get_std_voltage_value(struct radeon_device *rdev, 4153 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4154 u16 *std_voltage) 4155 { 4156 u16 v_index; 4157 bool voltage_found = false; 4158 *std_voltage = be16_to_cpu(voltage->value); 4159 4160 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4161 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4162 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4163 return -EINVAL; 4164 4165 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4166 if (be16_to_cpu(voltage->value) == 4167 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4168 voltage_found = true; 4169 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4170 *std_voltage = 4171 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4172 else 4173 *std_voltage = 4174 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4175 break; 4176 } 4177 } 4178 4179 if (!voltage_found) { 4180 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4181 if (be16_to_cpu(voltage->value) <= 4182 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4183 voltage_found = true; 4184 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4185 *std_voltage = 4186 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4187 else 4188 *std_voltage = 4189 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4190 break; 4191 } 4192 } 4193 } 4194 } else { 4195 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4196 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4197 } 4198 } 4199 4200 return 0; 4201 } 4202 4203 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4204 u16 value, u8 index, 4205 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4206 { 4207 voltage->index = index; 4208 voltage->value = cpu_to_be16(value); 4209 4210 return 0; 4211 } 4212 4213 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4214 const struct radeon_phase_shedding_limits_table *limits, 4215 u16 voltage, u32 sclk, u32 mclk, 4216 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4217 { 4218 unsigned int i; 4219 4220 for (i = 0; i < limits->count; i++) { 4221 if ((voltage <= limits->entries[i].voltage) && 4222 (sclk <= limits->entries[i].sclk) && 4223 (mclk <= limits->entries[i].mclk)) 4224 break; 4225 } 4226 4227 smc_voltage->phase_settings = (u8)i; 4228 4229 return 0; 4230 } 4231 4232 static int si_init_arb_table_index(struct radeon_device *rdev) 4233 { 4234 struct si_power_info *si_pi = si_get_pi(rdev); 4235 u32 tmp; 4236 int ret; 4237 4238 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4239 if (ret) 4240 return ret; 4241 4242 tmp &= 0x00FFFFFF; 4243 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4244 4245 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4246 } 4247 4248 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4249 { 4250 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4251 } 4252 4253 static int si_reset_to_default(struct radeon_device *rdev) 4254 { 4255 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4256 0 : -EINVAL; 4257 } 4258 4259 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4260 { 4261 struct si_power_info *si_pi = si_get_pi(rdev); 4262 u32 tmp; 4263 int ret; 4264 4265 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4266 &tmp, si_pi->sram_end); 4267 if (ret) 4268 return ret; 4269 4270 tmp = (tmp >> 24) & 0xff; 4271 4272 if (tmp == MC_CG_ARB_FREQ_F0) 4273 return 0; 4274 4275 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4276 } 4277 4278 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4279 u32 engine_clock) 4280 { 4281 u32 dram_rows; 4282 u32 dram_refresh_rate; 4283 u32 mc_arb_rfsh_rate; 4284 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4285 4286 if (tmp >= 4) 4287 dram_rows = 16384; 4288 else 4289 dram_rows = 1 << (tmp + 10); 4290 4291 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4292 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4293 4294 return mc_arb_rfsh_rate; 4295 } 4296 4297 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4298 struct rv7xx_pl *pl, 4299 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4300 { 4301 u32 dram_timing; 4302 u32 dram_timing2; 4303 u32 burst_time; 4304 4305 arb_regs->mc_arb_rfsh_rate = 4306 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4307 4308 radeon_atom_set_engine_dram_timings(rdev, 4309 pl->sclk, 4310 pl->mclk); 4311 4312 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4313 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4314 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4315 4316 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4317 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4318 arb_regs->mc_arb_burst_time = (u8)burst_time; 4319 4320 return 0; 4321 } 4322 4323 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4324 struct radeon_ps *radeon_state, 4325 unsigned int first_arb_set) 4326 { 4327 struct si_power_info *si_pi = si_get_pi(rdev); 4328 struct ni_ps *state = ni_get_ps(radeon_state); 4329 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4330 int i, ret = 0; 4331 4332 for (i = 0; i < state->performance_level_count; i++) { 4333 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4334 if (ret) 4335 break; 4336 ret = si_copy_bytes_to_smc(rdev, 4337 si_pi->arb_table_start + 4338 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4339 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4340 (u8 *)&arb_regs, 4341 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4342 si_pi->sram_end); 4343 if (ret) 4344 break; 4345 } 4346 4347 return ret; 4348 } 4349 4350 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4351 struct radeon_ps *radeon_new_state) 4352 { 4353 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4354 SISLANDS_DRIVER_STATE_ARB_INDEX); 4355 } 4356 4357 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4358 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4359 { 4360 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4361 struct si_power_info *si_pi = si_get_pi(rdev); 4362 4363 if (pi->mvdd_control) 4364 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4365 si_pi->mvdd_bootup_value, voltage); 4366 4367 return 0; 4368 } 4369 4370 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4371 struct radeon_ps *radeon_initial_state, 4372 SISLANDS_SMC_STATETABLE *table) 4373 { 4374 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4375 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4376 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4377 struct si_power_info *si_pi = si_get_pi(rdev); 4378 u32 reg; 4379 int ret; 4380 4381 table->initialState.levels[0].mclk.vDLL_CNTL = 4382 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4383 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4384 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4385 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4386 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4387 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4388 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4389 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4390 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4391 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4392 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4393 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4394 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4395 table->initialState.levels[0].mclk.vMPLL_SS = 4396 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4397 table->initialState.levels[0].mclk.vMPLL_SS2 = 4398 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4399 4400 table->initialState.levels[0].mclk.mclk_value = 4401 cpu_to_be32(initial_state->performance_levels[0].mclk); 4402 4403 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4404 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4405 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4406 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4407 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4408 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4409 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4410 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4411 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4412 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4413 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4414 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4415 4416 table->initialState.levels[0].sclk.sclk_value = 4417 cpu_to_be32(initial_state->performance_levels[0].sclk); 4418 4419 table->initialState.levels[0].arbRefreshState = 4420 SISLANDS_INITIAL_STATE_ARB_INDEX; 4421 4422 table->initialState.levels[0].ACIndex = 0; 4423 4424 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4425 initial_state->performance_levels[0].vddc, 4426 &table->initialState.levels[0].vddc); 4427 4428 if (!ret) { 4429 u16 std_vddc; 4430 4431 ret = si_get_std_voltage_value(rdev, 4432 &table->initialState.levels[0].vddc, 4433 &std_vddc); 4434 if (!ret) 4435 si_populate_std_voltage_value(rdev, std_vddc, 4436 table->initialState.levels[0].vddc.index, 4437 &table->initialState.levels[0].std_vddc); 4438 } 4439 4440 if (eg_pi->vddci_control) 4441 si_populate_voltage_value(rdev, 4442 &eg_pi->vddci_voltage_table, 4443 initial_state->performance_levels[0].vddci, 4444 &table->initialState.levels[0].vddci); 4445 4446 if (si_pi->vddc_phase_shed_control) 4447 si_populate_phase_shedding_value(rdev, 4448 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4449 initial_state->performance_levels[0].vddc, 4450 initial_state->performance_levels[0].sclk, 4451 initial_state->performance_levels[0].mclk, 4452 &table->initialState.levels[0].vddc); 4453 4454 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4455 4456 reg = CG_R(0xffff) | CG_L(0); 4457 table->initialState.levels[0].aT = cpu_to_be32(reg); 4458 4459 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4460 4461 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4462 4463 if (pi->mem_gddr5) { 4464 table->initialState.levels[0].strobeMode = 4465 si_get_strobe_mode_settings(rdev, 4466 initial_state->performance_levels[0].mclk); 4467 4468 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4469 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4470 else 4471 table->initialState.levels[0].mcFlags = 0; 4472 } 4473 4474 table->initialState.levelCount = 1; 4475 4476 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4477 4478 table->initialState.levels[0].dpm2.MaxPS = 0; 4479 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4480 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4481 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4482 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4483 4484 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4485 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4486 4487 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4488 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4489 4490 return 0; 4491 } 4492 4493 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4494 SISLANDS_SMC_STATETABLE *table) 4495 { 4496 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4497 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4498 struct si_power_info *si_pi = si_get_pi(rdev); 4499 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4500 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4501 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4502 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4503 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4504 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4505 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4506 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4507 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4508 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4509 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4510 u32 reg; 4511 int ret; 4512 4513 table->ACPIState = table->initialState; 4514 4515 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4516 4517 if (pi->acpi_vddc) { 4518 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4519 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4520 if (!ret) { 4521 u16 std_vddc; 4522 4523 ret = si_get_std_voltage_value(rdev, 4524 &table->ACPIState.levels[0].vddc, &std_vddc); 4525 if (!ret) 4526 si_populate_std_voltage_value(rdev, std_vddc, 4527 table->ACPIState.levels[0].vddc.index, 4528 &table->ACPIState.levels[0].std_vddc); 4529 } 4530 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4531 4532 if (si_pi->vddc_phase_shed_control) { 4533 si_populate_phase_shedding_value(rdev, 4534 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4535 pi->acpi_vddc, 4536 0, 4537 0, 4538 &table->ACPIState.levels[0].vddc); 4539 } 4540 } else { 4541 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4542 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4543 if (!ret) { 4544 u16 std_vddc; 4545 4546 ret = si_get_std_voltage_value(rdev, 4547 &table->ACPIState.levels[0].vddc, &std_vddc); 4548 4549 if (!ret) 4550 si_populate_std_voltage_value(rdev, std_vddc, 4551 table->ACPIState.levels[0].vddc.index, 4552 &table->ACPIState.levels[0].std_vddc); 4553 } 4554 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4555 si_pi->sys_pcie_mask, 4556 si_pi->boot_pcie_gen, 4557 RADEON_PCIE_GEN1); 4558 4559 if (si_pi->vddc_phase_shed_control) 4560 si_populate_phase_shedding_value(rdev, 4561 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4562 pi->min_vddc_in_table, 4563 0, 4564 0, 4565 &table->ACPIState.levels[0].vddc); 4566 } 4567 4568 if (pi->acpi_vddc) { 4569 if (eg_pi->acpi_vddci) 4570 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4571 eg_pi->acpi_vddci, 4572 &table->ACPIState.levels[0].vddci); 4573 } 4574 4575 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4576 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4577 4578 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4579 4580 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4581 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4582 4583 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4584 cpu_to_be32(dll_cntl); 4585 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4586 cpu_to_be32(mclk_pwrmgt_cntl); 4587 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4588 cpu_to_be32(mpll_ad_func_cntl); 4589 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4590 cpu_to_be32(mpll_dq_func_cntl); 4591 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4592 cpu_to_be32(mpll_func_cntl); 4593 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4594 cpu_to_be32(mpll_func_cntl_1); 4595 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4596 cpu_to_be32(mpll_func_cntl_2); 4597 table->ACPIState.levels[0].mclk.vMPLL_SS = 4598 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4599 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4600 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4601 4602 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4603 cpu_to_be32(spll_func_cntl); 4604 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4605 cpu_to_be32(spll_func_cntl_2); 4606 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4607 cpu_to_be32(spll_func_cntl_3); 4608 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4609 cpu_to_be32(spll_func_cntl_4); 4610 4611 table->ACPIState.levels[0].mclk.mclk_value = 0; 4612 table->ACPIState.levels[0].sclk.sclk_value = 0; 4613 4614 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4615 4616 if (eg_pi->dynamic_ac_timing) 4617 table->ACPIState.levels[0].ACIndex = 0; 4618 4619 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4620 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4621 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4622 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4623 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4624 4625 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4626 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4627 4628 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4629 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4630 4631 return 0; 4632 } 4633 4634 static int si_populate_ulv_state(struct radeon_device *rdev, 4635 SISLANDS_SMC_SWSTATE *state) 4636 { 4637 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4638 struct si_power_info *si_pi = si_get_pi(rdev); 4639 struct si_ulv_param *ulv = &si_pi->ulv; 4640 u32 sclk_in_sr = 1350; /* ??? */ 4641 int ret; 4642 4643 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4644 &state->levels[0]); 4645 if (!ret) { 4646 if (eg_pi->sclk_deep_sleep) { 4647 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4648 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4649 else 4650 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4651 } 4652 if (ulv->one_pcie_lane_in_ulv) 4653 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4654 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4655 state->levels[0].ACIndex = 1; 4656 state->levels[0].std_vddc = state->levels[0].vddc; 4657 state->levelCount = 1; 4658 4659 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4660 } 4661 4662 return ret; 4663 } 4664 4665 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4666 { 4667 struct si_power_info *si_pi = si_get_pi(rdev); 4668 struct si_ulv_param *ulv = &si_pi->ulv; 4669 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4670 int ret; 4671 4672 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4673 &arb_regs); 4674 if (ret) 4675 return ret; 4676 4677 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4678 ulv->volt_change_delay); 4679 4680 ret = si_copy_bytes_to_smc(rdev, 4681 si_pi->arb_table_start + 4682 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4683 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4684 (u8 *)&arb_regs, 4685 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4686 si_pi->sram_end); 4687 4688 return ret; 4689 } 4690 4691 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4692 { 4693 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4694 4695 pi->mvdd_split_frequency = 30000; 4696 } 4697 4698 static int si_init_smc_table(struct radeon_device *rdev) 4699 { 4700 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4701 struct si_power_info *si_pi = si_get_pi(rdev); 4702 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4703 const struct si_ulv_param *ulv = &si_pi->ulv; 4704 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4705 int ret; 4706 u32 lane_width; 4707 u32 vr_hot_gpio; 4708 4709 si_populate_smc_voltage_tables(rdev, table); 4710 4711 switch (rdev->pm.int_thermal_type) { 4712 case THERMAL_TYPE_SI: 4713 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4714 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4715 break; 4716 case THERMAL_TYPE_NONE: 4717 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4718 break; 4719 default: 4720 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4721 break; 4722 } 4723 4724 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4725 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4726 4727 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4728 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4729 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4730 } 4731 4732 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4733 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4734 4735 if (pi->mem_gddr5) 4736 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4737 4738 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4739 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4740 4741 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4742 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4743 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4744 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4745 vr_hot_gpio); 4746 } 4747 4748 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4749 if (ret) 4750 return ret; 4751 4752 ret = si_populate_smc_acpi_state(rdev, table); 4753 if (ret) 4754 return ret; 4755 4756 table->driverState = table->initialState; 4757 4758 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4759 SISLANDS_INITIAL_STATE_ARB_INDEX); 4760 if (ret) 4761 return ret; 4762 4763 if (ulv->supported && ulv->pl.vddc) { 4764 ret = si_populate_ulv_state(rdev, &table->ULVState); 4765 if (ret) 4766 return ret; 4767 4768 ret = si_program_ulv_memory_timing_parameters(rdev); 4769 if (ret) 4770 return ret; 4771 4772 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4773 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4774 4775 lane_width = radeon_get_pcie_lanes(rdev); 4776 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4777 } else { 4778 table->ULVState = table->initialState; 4779 } 4780 4781 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4782 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4783 si_pi->sram_end); 4784 } 4785 4786 static int si_calculate_sclk_params(struct radeon_device *rdev, 4787 u32 engine_clock, 4788 SISLANDS_SMC_SCLK_VALUE *sclk) 4789 { 4790 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4791 struct si_power_info *si_pi = si_get_pi(rdev); 4792 struct atom_clock_dividers dividers; 4793 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4794 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4795 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4796 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4797 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4798 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4799 u64 tmp; 4800 u32 reference_clock = rdev->clock.spll.reference_freq; 4801 u32 reference_divider; 4802 u32 fbdiv; 4803 int ret; 4804 4805 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4806 engine_clock, false, ÷rs); 4807 if (ret) 4808 return ret; 4809 4810 reference_divider = 1 + dividers.ref_div; 4811 4812 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4813 do_div(tmp, reference_clock); 4814 fbdiv = (u32) tmp; 4815 4816 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4817 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4818 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4819 4820 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4821 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4822 4823 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4824 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4825 spll_func_cntl_3 |= SPLL_DITHEN; 4826 4827 if (pi->sclk_ss) { 4828 struct radeon_atom_ss ss; 4829 u32 vco_freq = engine_clock * dividers.post_div; 4830 4831 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4832 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4833 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4834 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4835 4836 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4837 cg_spll_spread_spectrum |= CLK_S(clk_s); 4838 cg_spll_spread_spectrum |= SSEN; 4839 4840 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4841 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4842 } 4843 } 4844 4845 sclk->sclk_value = engine_clock; 4846 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4847 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4848 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4849 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4850 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4851 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4852 4853 return 0; 4854 } 4855 4856 static int si_populate_sclk_value(struct radeon_device *rdev, 4857 u32 engine_clock, 4858 SISLANDS_SMC_SCLK_VALUE *sclk) 4859 { 4860 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4861 int ret; 4862 4863 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4864 if (!ret) { 4865 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4866 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4867 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4868 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4869 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4870 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4871 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4872 } 4873 4874 return ret; 4875 } 4876 4877 static int si_populate_mclk_value(struct radeon_device *rdev, 4878 u32 engine_clock, 4879 u32 memory_clock, 4880 SISLANDS_SMC_MCLK_VALUE *mclk, 4881 bool strobe_mode, 4882 bool dll_state_on) 4883 { 4884 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4885 struct si_power_info *si_pi = si_get_pi(rdev); 4886 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4887 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4888 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4889 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4890 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4891 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4892 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4893 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4894 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4895 struct atom_mpll_param mpll_param; 4896 int ret; 4897 4898 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4899 if (ret) 4900 return ret; 4901 4902 mpll_func_cntl &= ~BWCTRL_MASK; 4903 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4904 4905 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4906 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4907 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4908 4909 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4910 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4911 4912 if (pi->mem_gddr5) { 4913 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4914 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4915 YCLK_POST_DIV(mpll_param.post_div); 4916 } 4917 4918 if (pi->mclk_ss) { 4919 struct radeon_atom_ss ss; 4920 u32 freq_nom; 4921 u32 tmp; 4922 u32 reference_clock = rdev->clock.mpll.reference_freq; 4923 4924 if (pi->mem_gddr5) 4925 freq_nom = memory_clock * 4; 4926 else 4927 freq_nom = memory_clock * 2; 4928 4929 tmp = freq_nom / reference_clock; 4930 tmp = tmp * tmp; 4931 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4932 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4933 u32 clks = reference_clock * 5 / ss.rate; 4934 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4935 4936 mpll_ss1 &= ~CLKV_MASK; 4937 mpll_ss1 |= CLKV(clkv); 4938 4939 mpll_ss2 &= ~CLKS_MASK; 4940 mpll_ss2 |= CLKS(clks); 4941 } 4942 } 4943 4944 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4945 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4946 4947 if (dll_state_on) 4948 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4949 else 4950 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4951 4952 mclk->mclk_value = cpu_to_be32(memory_clock); 4953 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4954 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4955 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4956 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4957 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4958 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4959 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4960 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4961 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4962 4963 return 0; 4964 } 4965 4966 static void si_populate_smc_sp(struct radeon_device *rdev, 4967 struct radeon_ps *radeon_state, 4968 SISLANDS_SMC_SWSTATE *smc_state) 4969 { 4970 struct ni_ps *ps = ni_get_ps(radeon_state); 4971 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4972 int i; 4973 4974 for (i = 0; i < ps->performance_level_count - 1; i++) 4975 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4976 4977 smc_state->levels[ps->performance_level_count - 1].bSP = 4978 cpu_to_be32(pi->psp); 4979 } 4980 4981 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4982 struct rv7xx_pl *pl, 4983 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4984 { 4985 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4986 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4987 struct si_power_info *si_pi = si_get_pi(rdev); 4988 int ret; 4989 bool dll_state_on; 4990 u16 std_vddc; 4991 bool gmc_pg = false; 4992 4993 if (eg_pi->pcie_performance_request && 4994 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4995 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4996 else 4997 level->gen2PCIE = (u8)pl->pcie_gen; 4998 4999 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 5000 if (ret) 5001 return ret; 5002 5003 level->mcFlags = 0; 5004 5005 if (pi->mclk_stutter_mode_threshold && 5006 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5007 !eg_pi->uvd_enabled && 5008 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5009 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5010 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5011 5012 if (gmc_pg) 5013 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5014 } 5015 5016 if (pi->mem_gddr5) { 5017 if (pl->mclk > pi->mclk_edc_enable_threshold) 5018 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5019 5020 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5021 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5022 5023 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5024 5025 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5026 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5027 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5028 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5029 else 5030 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5031 } else { 5032 dll_state_on = false; 5033 } 5034 } else { 5035 level->strobeMode = si_get_strobe_mode_settings(rdev, 5036 pl->mclk); 5037 5038 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5039 } 5040 5041 ret = si_populate_mclk_value(rdev, 5042 pl->sclk, 5043 pl->mclk, 5044 &level->mclk, 5045 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5046 if (ret) 5047 return ret; 5048 5049 ret = si_populate_voltage_value(rdev, 5050 &eg_pi->vddc_voltage_table, 5051 pl->vddc, &level->vddc); 5052 if (ret) 5053 return ret; 5054 5055 5056 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5057 if (ret) 5058 return ret; 5059 5060 ret = si_populate_std_voltage_value(rdev, std_vddc, 5061 level->vddc.index, &level->std_vddc); 5062 if (ret) 5063 return ret; 5064 5065 if (eg_pi->vddci_control) { 5066 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5067 pl->vddci, &level->vddci); 5068 if (ret) 5069 return ret; 5070 } 5071 5072 if (si_pi->vddc_phase_shed_control) { 5073 ret = si_populate_phase_shedding_value(rdev, 5074 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5075 pl->vddc, 5076 pl->sclk, 5077 pl->mclk, 5078 &level->vddc); 5079 if (ret) 5080 return ret; 5081 } 5082 5083 level->MaxPoweredUpCU = si_pi->max_cu; 5084 5085 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5086 5087 return ret; 5088 } 5089 5090 static int si_populate_smc_t(struct radeon_device *rdev, 5091 struct radeon_ps *radeon_state, 5092 SISLANDS_SMC_SWSTATE *smc_state) 5093 { 5094 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5095 struct ni_ps *state = ni_get_ps(radeon_state); 5096 u32 a_t; 5097 u32 t_l, t_h; 5098 u32 high_bsp; 5099 int i, ret; 5100 5101 if (state->performance_level_count >= 9) 5102 return -EINVAL; 5103 5104 if (state->performance_level_count < 2) { 5105 a_t = CG_R(0xffff) | CG_L(0); 5106 smc_state->levels[0].aT = cpu_to_be32(a_t); 5107 return 0; 5108 } 5109 5110 smc_state->levels[0].aT = cpu_to_be32(0); 5111 5112 for (i = 0; i <= state->performance_level_count - 2; i++) { 5113 ret = r600_calculate_at( 5114 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5115 100 * R600_AH_DFLT, 5116 state->performance_levels[i + 1].sclk, 5117 state->performance_levels[i].sclk, 5118 &t_l, 5119 &t_h); 5120 5121 if (ret) { 5122 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5123 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5124 } 5125 5126 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5127 a_t |= CG_R(t_l * pi->bsp / 20000); 5128 smc_state->levels[i].aT = cpu_to_be32(a_t); 5129 5130 high_bsp = (i == state->performance_level_count - 2) ? 5131 pi->pbsp : pi->bsp; 5132 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5133 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5134 } 5135 5136 return 0; 5137 } 5138 5139 static int si_disable_ulv(struct radeon_device *rdev) 5140 { 5141 struct si_power_info *si_pi = si_get_pi(rdev); 5142 struct si_ulv_param *ulv = &si_pi->ulv; 5143 5144 if (ulv->supported) 5145 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5146 0 : -EINVAL; 5147 5148 return 0; 5149 } 5150 5151 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5152 struct radeon_ps *radeon_state) 5153 { 5154 const struct si_power_info *si_pi = si_get_pi(rdev); 5155 const struct si_ulv_param *ulv = &si_pi->ulv; 5156 const struct ni_ps *state = ni_get_ps(radeon_state); 5157 int i; 5158 5159 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5160 return false; 5161 5162 /* XXX validate against display requirements! */ 5163 5164 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5165 if (rdev->clock.current_dispclk <= 5166 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5167 if (ulv->pl.vddc < 5168 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5169 return false; 5170 } 5171 } 5172 5173 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5174 return false; 5175 5176 return true; 5177 } 5178 5179 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5180 struct radeon_ps *radeon_new_state) 5181 { 5182 const struct si_power_info *si_pi = si_get_pi(rdev); 5183 const struct si_ulv_param *ulv = &si_pi->ulv; 5184 5185 if (ulv->supported) { 5186 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5187 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5188 0 : -EINVAL; 5189 } 5190 return 0; 5191 } 5192 5193 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5194 struct radeon_ps *radeon_state, 5195 SISLANDS_SMC_SWSTATE *smc_state) 5196 { 5197 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5198 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5199 struct si_power_info *si_pi = si_get_pi(rdev); 5200 struct ni_ps *state = ni_get_ps(radeon_state); 5201 int i, ret; 5202 u32 threshold; 5203 u32 sclk_in_sr = 1350; /* ??? */ 5204 5205 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5206 return -EINVAL; 5207 5208 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5209 5210 if (radeon_state->vclk && radeon_state->dclk) { 5211 eg_pi->uvd_enabled = true; 5212 if (eg_pi->smu_uvd_hs) 5213 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5214 } else { 5215 eg_pi->uvd_enabled = false; 5216 } 5217 5218 if (state->dc_compatible) 5219 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5220 5221 smc_state->levelCount = 0; 5222 for (i = 0; i < state->performance_level_count; i++) { 5223 if (eg_pi->sclk_deep_sleep) { 5224 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5225 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5226 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5227 else 5228 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5229 } 5230 } 5231 5232 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5233 &smc_state->levels[i]); 5234 smc_state->levels[i].arbRefreshState = 5235 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5236 5237 if (ret) 5238 return ret; 5239 5240 if (ni_pi->enable_power_containment) 5241 smc_state->levels[i].displayWatermark = 5242 (state->performance_levels[i].sclk < threshold) ? 5243 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5244 else 5245 smc_state->levels[i].displayWatermark = (i < 2) ? 5246 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5247 5248 if (eg_pi->dynamic_ac_timing) 5249 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5250 else 5251 smc_state->levels[i].ACIndex = 0; 5252 5253 smc_state->levelCount++; 5254 } 5255 5256 si_write_smc_soft_register(rdev, 5257 SI_SMC_SOFT_REGISTER_watermark_threshold, 5258 threshold / 512); 5259 5260 si_populate_smc_sp(rdev, radeon_state, smc_state); 5261 5262 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5263 if (ret) 5264 ni_pi->enable_power_containment = false; 5265 5266 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5267 if (ret) 5268 ni_pi->enable_sq_ramping = false; 5269 5270 return si_populate_smc_t(rdev, radeon_state, smc_state); 5271 } 5272 5273 static int si_upload_sw_state(struct radeon_device *rdev, 5274 struct radeon_ps *radeon_new_state) 5275 { 5276 struct si_power_info *si_pi = si_get_pi(rdev); 5277 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5278 int ret; 5279 u32 address = si_pi->state_table_start + 5280 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5281 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5282 ((new_state->performance_level_count - 1) * 5283 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5284 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5285 5286 memset(smc_state, 0, state_size); 5287 5288 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5289 if (ret) 5290 return ret; 5291 5292 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5293 state_size, si_pi->sram_end); 5294 5295 return ret; 5296 } 5297 5298 static int si_upload_ulv_state(struct radeon_device *rdev) 5299 { 5300 struct si_power_info *si_pi = si_get_pi(rdev); 5301 struct si_ulv_param *ulv = &si_pi->ulv; 5302 int ret = 0; 5303 5304 if (ulv->supported && ulv->pl.vddc) { 5305 u32 address = si_pi->state_table_start + 5306 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5307 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5308 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5309 5310 memset(smc_state, 0, state_size); 5311 5312 ret = si_populate_ulv_state(rdev, smc_state); 5313 if (!ret) 5314 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5315 state_size, si_pi->sram_end); 5316 } 5317 5318 return ret; 5319 } 5320 5321 static int si_upload_smc_data(struct radeon_device *rdev) 5322 { 5323 struct radeon_crtc *radeon_crtc = NULL; 5324 int i; 5325 5326 if (rdev->pm.dpm.new_active_crtc_count == 0) 5327 return 0; 5328 5329 for (i = 0; i < rdev->num_crtc; i++) { 5330 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5331 radeon_crtc = rdev->mode_info.crtcs[i]; 5332 break; 5333 } 5334 } 5335 5336 if (radeon_crtc == NULL) 5337 return 0; 5338 5339 if (radeon_crtc->line_time <= 0) 5340 return 0; 5341 5342 if (si_write_smc_soft_register(rdev, 5343 SI_SMC_SOFT_REGISTER_crtc_index, 5344 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5345 return 0; 5346 5347 if (si_write_smc_soft_register(rdev, 5348 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5349 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5350 return 0; 5351 5352 if (si_write_smc_soft_register(rdev, 5353 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5354 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5355 return 0; 5356 5357 return 0; 5358 } 5359 5360 static int si_set_mc_special_registers(struct radeon_device *rdev, 5361 struct si_mc_reg_table *table) 5362 { 5363 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5364 u8 i, j, k; 5365 u32 temp_reg; 5366 5367 for (i = 0, j = table->last; i < table->last; i++) { 5368 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5369 return -EINVAL; 5370 switch (table->mc_reg_address[i].s1 << 2) { 5371 case MC_SEQ_MISC1: 5372 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5373 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5374 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5375 for (k = 0; k < table->num_entries; k++) 5376 table->mc_reg_table_entry[k].mc_data[j] = 5377 ((temp_reg & 0xffff0000)) | 5378 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5379 j++; 5380 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5381 return -EINVAL; 5382 5383 temp_reg = RREG32(MC_PMG_CMD_MRS); 5384 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5385 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5386 for (k = 0; k < table->num_entries; k++) { 5387 table->mc_reg_table_entry[k].mc_data[j] = 5388 (temp_reg & 0xffff0000) | 5389 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5390 if (!pi->mem_gddr5) 5391 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5392 } 5393 j++; 5394 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5395 return -EINVAL; 5396 5397 if (!pi->mem_gddr5) { 5398 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5399 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5400 for (k = 0; k < table->num_entries; k++) 5401 table->mc_reg_table_entry[k].mc_data[j] = 5402 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5403 j++; 5404 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5405 return -EINVAL; 5406 } 5407 break; 5408 case MC_SEQ_RESERVE_M: 5409 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5410 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5411 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5412 for(k = 0; k < table->num_entries; k++) 5413 table->mc_reg_table_entry[k].mc_data[j] = 5414 (temp_reg & 0xffff0000) | 5415 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5416 j++; 5417 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5418 return -EINVAL; 5419 break; 5420 default: 5421 break; 5422 } 5423 } 5424 5425 table->last = j; 5426 5427 return 0; 5428 } 5429 5430 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5431 { 5432 bool result = true; 5433 5434 switch (in_reg) { 5435 case MC_SEQ_RAS_TIMING >> 2: 5436 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5437 break; 5438 case MC_SEQ_CAS_TIMING >> 2: 5439 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5440 break; 5441 case MC_SEQ_MISC_TIMING >> 2: 5442 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5443 break; 5444 case MC_SEQ_MISC_TIMING2 >> 2: 5445 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5446 break; 5447 case MC_SEQ_RD_CTL_D0 >> 2: 5448 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5449 break; 5450 case MC_SEQ_RD_CTL_D1 >> 2: 5451 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5452 break; 5453 case MC_SEQ_WR_CTL_D0 >> 2: 5454 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5455 break; 5456 case MC_SEQ_WR_CTL_D1 >> 2: 5457 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5458 break; 5459 case MC_PMG_CMD_EMRS >> 2: 5460 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5461 break; 5462 case MC_PMG_CMD_MRS >> 2: 5463 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5464 break; 5465 case MC_PMG_CMD_MRS1 >> 2: 5466 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5467 break; 5468 case MC_SEQ_PMG_TIMING >> 2: 5469 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5470 break; 5471 case MC_PMG_CMD_MRS2 >> 2: 5472 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5473 break; 5474 case MC_SEQ_WR_CTL_2 >> 2: 5475 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5476 break; 5477 default: 5478 result = false; 5479 break; 5480 } 5481 5482 return result; 5483 } 5484 5485 static void si_set_valid_flag(struct si_mc_reg_table *table) 5486 { 5487 u8 i, j; 5488 5489 for (i = 0; i < table->last; i++) { 5490 for (j = 1; j < table->num_entries; j++) { 5491 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5492 table->valid_flag |= 1 << i; 5493 break; 5494 } 5495 } 5496 } 5497 } 5498 5499 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5500 { 5501 u32 i; 5502 u16 address; 5503 5504 for (i = 0; i < table->last; i++) 5505 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5506 address : table->mc_reg_address[i].s1; 5507 5508 } 5509 5510 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5511 struct si_mc_reg_table *si_table) 5512 { 5513 u8 i, j; 5514 5515 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5516 return -EINVAL; 5517 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5518 return -EINVAL; 5519 5520 for (i = 0; i < table->last; i++) 5521 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5522 si_table->last = table->last; 5523 5524 for (i = 0; i < table->num_entries; i++) { 5525 si_table->mc_reg_table_entry[i].mclk_max = 5526 table->mc_reg_table_entry[i].mclk_max; 5527 for (j = 0; j < table->last; j++) { 5528 si_table->mc_reg_table_entry[i].mc_data[j] = 5529 table->mc_reg_table_entry[i].mc_data[j]; 5530 } 5531 } 5532 si_table->num_entries = table->num_entries; 5533 5534 return 0; 5535 } 5536 5537 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5538 { 5539 struct si_power_info *si_pi = si_get_pi(rdev); 5540 struct atom_mc_reg_table *table; 5541 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5542 u8 module_index = rv770_get_memory_module_index(rdev); 5543 int ret; 5544 5545 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5546 if (!table) 5547 return -ENOMEM; 5548 5549 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5550 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5551 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5552 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5553 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5554 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5555 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5556 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5557 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5558 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5559 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5560 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5561 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5562 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5563 5564 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5565 if (ret) 5566 goto init_mc_done; 5567 5568 ret = si_copy_vbios_mc_reg_table(table, si_table); 5569 if (ret) 5570 goto init_mc_done; 5571 5572 si_set_s0_mc_reg_index(si_table); 5573 5574 ret = si_set_mc_special_registers(rdev, si_table); 5575 if (ret) 5576 goto init_mc_done; 5577 5578 si_set_valid_flag(si_table); 5579 5580 init_mc_done: 5581 kfree(table); 5582 5583 return ret; 5584 5585 } 5586 5587 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5588 SMC_SIslands_MCRegisters *mc_reg_table) 5589 { 5590 struct si_power_info *si_pi = si_get_pi(rdev); 5591 u32 i, j; 5592 5593 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5594 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5595 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5596 break; 5597 mc_reg_table->address[i].s0 = 5598 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5599 mc_reg_table->address[i].s1 = 5600 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5601 i++; 5602 } 5603 } 5604 mc_reg_table->last = (u8)i; 5605 } 5606 5607 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5608 SMC_SIslands_MCRegisterSet *data, 5609 u32 num_entries, u32 valid_flag) 5610 { 5611 u32 i, j; 5612 5613 for(i = 0, j = 0; j < num_entries; j++) { 5614 if (valid_flag & (1 << j)) { 5615 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5616 i++; 5617 } 5618 } 5619 } 5620 5621 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5622 struct rv7xx_pl *pl, 5623 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5624 { 5625 struct si_power_info *si_pi = si_get_pi(rdev); 5626 u32 i = 0; 5627 5628 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5629 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5630 break; 5631 } 5632 5633 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5634 --i; 5635 5636 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5637 mc_reg_table_data, si_pi->mc_reg_table.last, 5638 si_pi->mc_reg_table.valid_flag); 5639 } 5640 5641 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5642 struct radeon_ps *radeon_state, 5643 SMC_SIslands_MCRegisters *mc_reg_table) 5644 { 5645 struct ni_ps *state = ni_get_ps(radeon_state); 5646 int i; 5647 5648 for (i = 0; i < state->performance_level_count; i++) { 5649 si_convert_mc_reg_table_entry_to_smc(rdev, 5650 &state->performance_levels[i], 5651 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5652 } 5653 } 5654 5655 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5656 struct radeon_ps *radeon_boot_state) 5657 { 5658 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5659 struct si_power_info *si_pi = si_get_pi(rdev); 5660 struct si_ulv_param *ulv = &si_pi->ulv; 5661 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5662 5663 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5664 5665 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5666 5667 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5668 5669 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5670 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5671 5672 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5673 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5674 si_pi->mc_reg_table.last, 5675 si_pi->mc_reg_table.valid_flag); 5676 5677 if (ulv->supported && ulv->pl.vddc != 0) 5678 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5679 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5680 else 5681 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5682 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5683 si_pi->mc_reg_table.last, 5684 si_pi->mc_reg_table.valid_flag); 5685 5686 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5687 5688 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5689 (u8 *)smc_mc_reg_table, 5690 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5691 } 5692 5693 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5694 struct radeon_ps *radeon_new_state) 5695 { 5696 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5697 struct si_power_info *si_pi = si_get_pi(rdev); 5698 u32 address = si_pi->mc_reg_table_start + 5699 offsetof(SMC_SIslands_MCRegisters, 5700 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5701 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5702 5703 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5704 5705 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5706 5707 5708 return si_copy_bytes_to_smc(rdev, address, 5709 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5710 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5711 si_pi->sram_end); 5712 5713 } 5714 5715 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5716 { 5717 if (enable) 5718 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5719 else 5720 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5721 } 5722 5723 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5724 struct radeon_ps *radeon_state) 5725 { 5726 struct ni_ps *state = ni_get_ps(radeon_state); 5727 int i; 5728 u16 pcie_speed, max_speed = 0; 5729 5730 for (i = 0; i < state->performance_level_count; i++) { 5731 pcie_speed = state->performance_levels[i].pcie_gen; 5732 if (max_speed < pcie_speed) 5733 max_speed = pcie_speed; 5734 } 5735 return max_speed; 5736 } 5737 5738 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5739 { 5740 u32 speed_cntl; 5741 5742 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5743 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5744 5745 return (u16)speed_cntl; 5746 } 5747 5748 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5749 struct radeon_ps *radeon_new_state, 5750 struct radeon_ps *radeon_current_state) 5751 { 5752 struct si_power_info *si_pi = si_get_pi(rdev); 5753 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5754 enum radeon_pcie_gen current_link_speed; 5755 5756 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5757 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5758 else 5759 current_link_speed = si_pi->force_pcie_gen; 5760 5761 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5762 si_pi->pspp_notify_required = false; 5763 if (target_link_speed > current_link_speed) { 5764 switch (target_link_speed) { 5765 #if defined(CONFIG_ACPI) 5766 case RADEON_PCIE_GEN3: 5767 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5768 break; 5769 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5770 if (current_link_speed == RADEON_PCIE_GEN2) 5771 break; 5772 case RADEON_PCIE_GEN2: 5773 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5774 break; 5775 #endif 5776 default: 5777 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5778 break; 5779 } 5780 } else { 5781 if (target_link_speed < current_link_speed) 5782 si_pi->pspp_notify_required = true; 5783 } 5784 } 5785 5786 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5787 struct radeon_ps *radeon_new_state, 5788 struct radeon_ps *radeon_current_state) 5789 { 5790 struct si_power_info *si_pi = si_get_pi(rdev); 5791 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5792 u8 request; 5793 5794 if (si_pi->pspp_notify_required) { 5795 if (target_link_speed == RADEON_PCIE_GEN3) 5796 request = PCIE_PERF_REQ_PECI_GEN3; 5797 else if (target_link_speed == RADEON_PCIE_GEN2) 5798 request = PCIE_PERF_REQ_PECI_GEN2; 5799 else 5800 request = PCIE_PERF_REQ_PECI_GEN1; 5801 5802 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5803 (si_get_current_pcie_speed(rdev) > 0)) 5804 return; 5805 5806 #if defined(CONFIG_ACPI) 5807 radeon_acpi_pcie_performance_request(rdev, request, false); 5808 #endif 5809 } 5810 } 5811 5812 #if 0 5813 static int si_ds_request(struct radeon_device *rdev, 5814 bool ds_status_on, u32 count_write) 5815 { 5816 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5817 5818 if (eg_pi->sclk_deep_sleep) { 5819 if (ds_status_on) 5820 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5821 PPSMC_Result_OK) ? 5822 0 : -EINVAL; 5823 else 5824 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5825 PPSMC_Result_OK) ? 0 : -EINVAL; 5826 } 5827 return 0; 5828 } 5829 #endif 5830 5831 static void si_set_max_cu_value(struct radeon_device *rdev) 5832 { 5833 struct si_power_info *si_pi = si_get_pi(rdev); 5834 5835 if (rdev->family == CHIP_VERDE) { 5836 switch (rdev->pdev->device) { 5837 case 0x6820: 5838 case 0x6825: 5839 case 0x6821: 5840 case 0x6823: 5841 case 0x6827: 5842 si_pi->max_cu = 10; 5843 break; 5844 case 0x682D: 5845 case 0x6824: 5846 case 0x682F: 5847 case 0x6826: 5848 si_pi->max_cu = 8; 5849 break; 5850 case 0x6828: 5851 case 0x6830: 5852 case 0x6831: 5853 case 0x6838: 5854 case 0x6839: 5855 case 0x683D: 5856 si_pi->max_cu = 10; 5857 break; 5858 case 0x683B: 5859 case 0x683F: 5860 case 0x6829: 5861 si_pi->max_cu = 8; 5862 break; 5863 default: 5864 si_pi->max_cu = 0; 5865 break; 5866 } 5867 } else { 5868 si_pi->max_cu = 0; 5869 } 5870 } 5871 5872 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5873 struct radeon_clock_voltage_dependency_table *table) 5874 { 5875 u32 i; 5876 int j; 5877 u16 leakage_voltage; 5878 5879 if (table) { 5880 for (i = 0; i < table->count; i++) { 5881 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5882 table->entries[i].v, 5883 &leakage_voltage)) { 5884 case 0: 5885 table->entries[i].v = leakage_voltage; 5886 break; 5887 case -EAGAIN: 5888 return -EINVAL; 5889 case -EINVAL: 5890 default: 5891 break; 5892 } 5893 } 5894 5895 for (j = (table->count - 2); j >= 0; j--) { 5896 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5897 table->entries[j].v : table->entries[j + 1].v; 5898 } 5899 } 5900 return 0; 5901 } 5902 5903 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5904 { 5905 int ret = 0; 5906 5907 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5908 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5909 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5910 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5911 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5912 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5913 return ret; 5914 } 5915 5916 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5917 struct radeon_ps *radeon_new_state, 5918 struct radeon_ps *radeon_current_state) 5919 { 5920 u32 lane_width; 5921 u32 new_lane_width = 5922 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5923 u32 current_lane_width = 5924 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5925 5926 if (new_lane_width != current_lane_width) { 5927 radeon_set_pcie_lanes(rdev, new_lane_width); 5928 lane_width = radeon_get_pcie_lanes(rdev); 5929 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5930 } 5931 } 5932 5933 static void si_set_vce_clock(struct radeon_device *rdev, 5934 struct radeon_ps *new_rps, 5935 struct radeon_ps *old_rps) 5936 { 5937 if ((old_rps->evclk != new_rps->evclk) || 5938 (old_rps->ecclk != new_rps->ecclk)) { 5939 /* turn the clocks on when encoding, off otherwise */ 5940 if (new_rps->evclk || new_rps->ecclk) 5941 vce_v1_0_enable_mgcg(rdev, false); 5942 else 5943 vce_v1_0_enable_mgcg(rdev, true); 5944 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5945 } 5946 } 5947 5948 void si_dpm_setup_asic(struct radeon_device *rdev) 5949 { 5950 int r; 5951 5952 r = si_mc_load_microcode(rdev); 5953 if (r) 5954 DRM_ERROR("Failed to load MC firmware!\n"); 5955 rv770_get_memory_type(rdev); 5956 si_read_clock_registers(rdev); 5957 si_enable_acpi_power_management(rdev); 5958 } 5959 5960 static int si_thermal_enable_alert(struct radeon_device *rdev, 5961 bool enable) 5962 { 5963 u32 thermal_int = RREG32(CG_THERMAL_INT); 5964 5965 if (enable) { 5966 PPSMC_Result result; 5967 5968 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5969 WREG32(CG_THERMAL_INT, thermal_int); 5970 rdev->irq.dpm_thermal = false; 5971 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5972 if (result != PPSMC_Result_OK) { 5973 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5974 return -EINVAL; 5975 } 5976 } else { 5977 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5978 WREG32(CG_THERMAL_INT, thermal_int); 5979 rdev->irq.dpm_thermal = true; 5980 } 5981 5982 return 0; 5983 } 5984 5985 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5986 int min_temp, int max_temp) 5987 { 5988 int low_temp = 0 * 1000; 5989 int high_temp = 255 * 1000; 5990 5991 if (low_temp < min_temp) 5992 low_temp = min_temp; 5993 if (high_temp > max_temp) 5994 high_temp = max_temp; 5995 if (high_temp < low_temp) { 5996 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5997 return -EINVAL; 5998 } 5999 6000 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6001 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6002 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6003 6004 rdev->pm.dpm.thermal.min_temp = low_temp; 6005 rdev->pm.dpm.thermal.max_temp = high_temp; 6006 6007 return 0; 6008 } 6009 6010 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6011 { 6012 struct si_power_info *si_pi = si_get_pi(rdev); 6013 u32 tmp; 6014 6015 if (si_pi->fan_ctrl_is_in_default_mode) { 6016 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6017 si_pi->fan_ctrl_default_mode = tmp; 6018 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6019 si_pi->t_min = tmp; 6020 si_pi->fan_ctrl_is_in_default_mode = false; 6021 } 6022 6023 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6024 tmp |= TMIN(0); 6025 WREG32(CG_FDO_CTRL2, tmp); 6026 6027 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6028 tmp |= FDO_PWM_MODE(mode); 6029 WREG32(CG_FDO_CTRL2, tmp); 6030 } 6031 6032 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6033 { 6034 struct si_power_info *si_pi = si_get_pi(rdev); 6035 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6036 u32 duty100; 6037 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6038 u16 fdo_min, slope1, slope2; 6039 u32 reference_clock, tmp; 6040 int ret; 6041 u64 tmp64; 6042 6043 if (!si_pi->fan_table_start) { 6044 rdev->pm.dpm.fan.ucode_fan_control = false; 6045 return 0; 6046 } 6047 6048 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6049 6050 if (duty100 == 0) { 6051 rdev->pm.dpm.fan.ucode_fan_control = false; 6052 return 0; 6053 } 6054 6055 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6056 do_div(tmp64, 10000); 6057 fdo_min = (u16)tmp64; 6058 6059 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6060 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6061 6062 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6063 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6064 6065 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6066 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6067 6068 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6069 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6070 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6071 6072 fan_table.slope1 = cpu_to_be16(slope1); 6073 fan_table.slope2 = cpu_to_be16(slope2); 6074 6075 fan_table.fdo_min = cpu_to_be16(fdo_min); 6076 6077 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6078 6079 fan_table.hys_up = cpu_to_be16(1); 6080 6081 fan_table.hys_slope = cpu_to_be16(1); 6082 6083 fan_table.temp_resp_lim = cpu_to_be16(5); 6084 6085 reference_clock = radeon_get_xclk(rdev); 6086 6087 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6088 reference_clock) / 1600); 6089 6090 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6091 6092 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6093 fan_table.temp_src = (uint8_t)tmp; 6094 6095 ret = si_copy_bytes_to_smc(rdev, 6096 si_pi->fan_table_start, 6097 (u8 *)(&fan_table), 6098 sizeof(fan_table), 6099 si_pi->sram_end); 6100 6101 if (ret) { 6102 DRM_ERROR("Failed to load fan table to the SMC."); 6103 rdev->pm.dpm.fan.ucode_fan_control = false; 6104 } 6105 6106 return 0; 6107 } 6108 6109 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6110 { 6111 struct si_power_info *si_pi = si_get_pi(rdev); 6112 PPSMC_Result ret; 6113 6114 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6115 if (ret == PPSMC_Result_OK) { 6116 si_pi->fan_is_controlled_by_smc = true; 6117 return 0; 6118 } else { 6119 return -EINVAL; 6120 } 6121 } 6122 6123 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6124 { 6125 struct si_power_info *si_pi = si_get_pi(rdev); 6126 PPSMC_Result ret; 6127 6128 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6129 6130 if (ret == PPSMC_Result_OK) { 6131 si_pi->fan_is_controlled_by_smc = false; 6132 return 0; 6133 } else { 6134 return -EINVAL; 6135 } 6136 } 6137 6138 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6139 u32 *speed) 6140 { 6141 u32 duty, duty100; 6142 u64 tmp64; 6143 6144 if (rdev->pm.no_fan) 6145 return -ENOENT; 6146 6147 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6148 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6149 6150 if (duty100 == 0) 6151 return -EINVAL; 6152 6153 tmp64 = (u64)duty * 100; 6154 do_div(tmp64, duty100); 6155 *speed = (u32)tmp64; 6156 6157 if (*speed > 100) 6158 *speed = 100; 6159 6160 return 0; 6161 } 6162 6163 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6164 u32 speed) 6165 { 6166 struct si_power_info *si_pi = si_get_pi(rdev); 6167 u32 tmp; 6168 u32 duty, duty100; 6169 u64 tmp64; 6170 6171 if (rdev->pm.no_fan) 6172 return -ENOENT; 6173 6174 if (si_pi->fan_is_controlled_by_smc) 6175 return -EINVAL; 6176 6177 if (speed > 100) 6178 return -EINVAL; 6179 6180 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6181 6182 if (duty100 == 0) 6183 return -EINVAL; 6184 6185 tmp64 = (u64)speed * duty100; 6186 do_div(tmp64, 100); 6187 duty = (u32)tmp64; 6188 6189 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6190 tmp |= FDO_STATIC_DUTY(duty); 6191 WREG32(CG_FDO_CTRL0, tmp); 6192 6193 return 0; 6194 } 6195 6196 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6197 { 6198 if (mode) { 6199 /* stop auto-manage */ 6200 if (rdev->pm.dpm.fan.ucode_fan_control) 6201 si_fan_ctrl_stop_smc_fan_control(rdev); 6202 si_fan_ctrl_set_static_mode(rdev, mode); 6203 } else { 6204 /* restart auto-manage */ 6205 if (rdev->pm.dpm.fan.ucode_fan_control) 6206 si_thermal_start_smc_fan_control(rdev); 6207 else 6208 si_fan_ctrl_set_default_mode(rdev); 6209 } 6210 } 6211 6212 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6213 { 6214 struct si_power_info *si_pi = si_get_pi(rdev); 6215 u32 tmp; 6216 6217 if (si_pi->fan_is_controlled_by_smc) 6218 return 0; 6219 6220 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6221 return (tmp >> FDO_PWM_MODE_SHIFT); 6222 } 6223 6224 #if 0 6225 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6226 u32 *speed) 6227 { 6228 u32 tach_period; 6229 u32 xclk = radeon_get_xclk(rdev); 6230 6231 if (rdev->pm.no_fan) 6232 return -ENOENT; 6233 6234 if (rdev->pm.fan_pulses_per_revolution == 0) 6235 return -ENOENT; 6236 6237 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6238 if (tach_period == 0) 6239 return -ENOENT; 6240 6241 *speed = 60 * xclk * 10000 / tach_period; 6242 6243 return 0; 6244 } 6245 6246 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6247 u32 speed) 6248 { 6249 u32 tach_period, tmp; 6250 u32 xclk = radeon_get_xclk(rdev); 6251 6252 if (rdev->pm.no_fan) 6253 return -ENOENT; 6254 6255 if (rdev->pm.fan_pulses_per_revolution == 0) 6256 return -ENOENT; 6257 6258 if ((speed < rdev->pm.fan_min_rpm) || 6259 (speed > rdev->pm.fan_max_rpm)) 6260 return -EINVAL; 6261 6262 if (rdev->pm.dpm.fan.ucode_fan_control) 6263 si_fan_ctrl_stop_smc_fan_control(rdev); 6264 6265 tach_period = 60 * xclk * 10000 / (8 * speed); 6266 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6267 tmp |= TARGET_PERIOD(tach_period); 6268 WREG32(CG_TACH_CTRL, tmp); 6269 6270 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6271 6272 return 0; 6273 } 6274 #endif 6275 6276 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6277 { 6278 struct si_power_info *si_pi = si_get_pi(rdev); 6279 u32 tmp; 6280 6281 if (!si_pi->fan_ctrl_is_in_default_mode) { 6282 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6283 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6284 WREG32(CG_FDO_CTRL2, tmp); 6285 6286 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6287 tmp |= TMIN(si_pi->t_min); 6288 WREG32(CG_FDO_CTRL2, tmp); 6289 si_pi->fan_ctrl_is_in_default_mode = true; 6290 } 6291 } 6292 6293 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6294 { 6295 if (rdev->pm.dpm.fan.ucode_fan_control) { 6296 si_fan_ctrl_start_smc_fan_control(rdev); 6297 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6298 } 6299 } 6300 6301 static void si_thermal_initialize(struct radeon_device *rdev) 6302 { 6303 u32 tmp; 6304 6305 if (rdev->pm.fan_pulses_per_revolution) { 6306 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6307 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6308 WREG32(CG_TACH_CTRL, tmp); 6309 } 6310 6311 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6312 tmp |= TACH_PWM_RESP_RATE(0x28); 6313 WREG32(CG_FDO_CTRL2, tmp); 6314 } 6315 6316 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6317 { 6318 int ret; 6319 6320 si_thermal_initialize(rdev); 6321 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6322 if (ret) 6323 return ret; 6324 ret = si_thermal_enable_alert(rdev, true); 6325 if (ret) 6326 return ret; 6327 if (rdev->pm.dpm.fan.ucode_fan_control) { 6328 ret = si_halt_smc(rdev); 6329 if (ret) 6330 return ret; 6331 ret = si_thermal_setup_fan_table(rdev); 6332 if (ret) 6333 return ret; 6334 ret = si_resume_smc(rdev); 6335 if (ret) 6336 return ret; 6337 si_thermal_start_smc_fan_control(rdev); 6338 } 6339 6340 return 0; 6341 } 6342 6343 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6344 { 6345 if (!rdev->pm.no_fan) { 6346 si_fan_ctrl_set_default_mode(rdev); 6347 si_fan_ctrl_stop_smc_fan_control(rdev); 6348 } 6349 } 6350 6351 int si_dpm_enable(struct radeon_device *rdev) 6352 { 6353 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6354 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6355 struct si_power_info *si_pi = si_get_pi(rdev); 6356 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6357 int ret; 6358 6359 if (si_is_smc_running(rdev)) 6360 return -EINVAL; 6361 if (pi->voltage_control || si_pi->voltage_control_svi2) 6362 si_enable_voltage_control(rdev, true); 6363 if (pi->mvdd_control) 6364 si_get_mvdd_configuration(rdev); 6365 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6366 ret = si_construct_voltage_tables(rdev); 6367 if (ret) { 6368 DRM_ERROR("si_construct_voltage_tables failed\n"); 6369 return ret; 6370 } 6371 } 6372 if (eg_pi->dynamic_ac_timing) { 6373 ret = si_initialize_mc_reg_table(rdev); 6374 if (ret) 6375 eg_pi->dynamic_ac_timing = false; 6376 } 6377 if (pi->dynamic_ss) 6378 si_enable_spread_spectrum(rdev, true); 6379 if (pi->thermal_protection) 6380 si_enable_thermal_protection(rdev, true); 6381 si_setup_bsp(rdev); 6382 si_program_git(rdev); 6383 si_program_tp(rdev); 6384 si_program_tpp(rdev); 6385 si_program_sstp(rdev); 6386 si_enable_display_gap(rdev); 6387 si_program_vc(rdev); 6388 ret = si_upload_firmware(rdev); 6389 if (ret) { 6390 DRM_ERROR("si_upload_firmware failed\n"); 6391 return ret; 6392 } 6393 ret = si_process_firmware_header(rdev); 6394 if (ret) { 6395 DRM_ERROR("si_process_firmware_header failed\n"); 6396 return ret; 6397 } 6398 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6399 if (ret) { 6400 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6401 return ret; 6402 } 6403 ret = si_init_smc_table(rdev); 6404 if (ret) { 6405 DRM_ERROR("si_init_smc_table failed\n"); 6406 return ret; 6407 } 6408 ret = si_init_smc_spll_table(rdev); 6409 if (ret) { 6410 DRM_ERROR("si_init_smc_spll_table failed\n"); 6411 return ret; 6412 } 6413 ret = si_init_arb_table_index(rdev); 6414 if (ret) { 6415 DRM_ERROR("si_init_arb_table_index failed\n"); 6416 return ret; 6417 } 6418 if (eg_pi->dynamic_ac_timing) { 6419 ret = si_populate_mc_reg_table(rdev, boot_ps); 6420 if (ret) { 6421 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6422 return ret; 6423 } 6424 } 6425 ret = si_initialize_smc_cac_tables(rdev); 6426 if (ret) { 6427 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6428 return ret; 6429 } 6430 ret = si_initialize_hardware_cac_manager(rdev); 6431 if (ret) { 6432 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6433 return ret; 6434 } 6435 ret = si_initialize_smc_dte_tables(rdev); 6436 if (ret) { 6437 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6438 return ret; 6439 } 6440 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6441 if (ret) { 6442 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6443 return ret; 6444 } 6445 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6446 if (ret) { 6447 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6448 return ret; 6449 } 6450 si_program_response_times(rdev); 6451 si_program_ds_registers(rdev); 6452 si_dpm_start_smc(rdev); 6453 ret = si_notify_smc_display_change(rdev, false); 6454 if (ret) { 6455 DRM_ERROR("si_notify_smc_display_change failed\n"); 6456 return ret; 6457 } 6458 si_enable_sclk_control(rdev, true); 6459 si_start_dpm(rdev); 6460 6461 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6462 6463 si_thermal_start_thermal_controller(rdev); 6464 6465 ni_update_current_ps(rdev, boot_ps); 6466 6467 return 0; 6468 } 6469 6470 static int si_set_temperature_range(struct radeon_device *rdev) 6471 { 6472 int ret; 6473 6474 ret = si_thermal_enable_alert(rdev, false); 6475 if (ret) 6476 return ret; 6477 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6478 if (ret) 6479 return ret; 6480 ret = si_thermal_enable_alert(rdev, true); 6481 if (ret) 6482 return ret; 6483 6484 return ret; 6485 } 6486 6487 int si_dpm_late_enable(struct radeon_device *rdev) 6488 { 6489 int ret; 6490 6491 ret = si_set_temperature_range(rdev); 6492 if (ret) 6493 return ret; 6494 6495 return ret; 6496 } 6497 6498 void si_dpm_disable(struct radeon_device *rdev) 6499 { 6500 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6501 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6502 6503 if (!si_is_smc_running(rdev)) 6504 return; 6505 si_thermal_stop_thermal_controller(rdev); 6506 si_disable_ulv(rdev); 6507 si_clear_vc(rdev); 6508 if (pi->thermal_protection) 6509 si_enable_thermal_protection(rdev, false); 6510 si_enable_power_containment(rdev, boot_ps, false); 6511 si_enable_smc_cac(rdev, boot_ps, false); 6512 si_enable_spread_spectrum(rdev, false); 6513 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6514 si_stop_dpm(rdev); 6515 si_reset_to_default(rdev); 6516 si_dpm_stop_smc(rdev); 6517 si_force_switch_to_arb_f0(rdev); 6518 6519 ni_update_current_ps(rdev, boot_ps); 6520 } 6521 6522 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6523 { 6524 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6525 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6526 struct radeon_ps *new_ps = &requested_ps; 6527 6528 ni_update_requested_ps(rdev, new_ps); 6529 6530 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6531 6532 return 0; 6533 } 6534 6535 static int si_power_control_set_level(struct radeon_device *rdev) 6536 { 6537 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6538 int ret; 6539 6540 ret = si_restrict_performance_levels_before_switch(rdev); 6541 if (ret) 6542 return ret; 6543 ret = si_halt_smc(rdev); 6544 if (ret) 6545 return ret; 6546 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6547 if (ret) 6548 return ret; 6549 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6550 if (ret) 6551 return ret; 6552 ret = si_resume_smc(rdev); 6553 if (ret) 6554 return ret; 6555 ret = si_set_sw_state(rdev); 6556 if (ret) 6557 return ret; 6558 return 0; 6559 } 6560 6561 int si_dpm_set_power_state(struct radeon_device *rdev) 6562 { 6563 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6564 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6565 struct radeon_ps *old_ps = &eg_pi->current_rps; 6566 int ret; 6567 6568 ret = si_disable_ulv(rdev); 6569 if (ret) { 6570 DRM_ERROR("si_disable_ulv failed\n"); 6571 return ret; 6572 } 6573 ret = si_restrict_performance_levels_before_switch(rdev); 6574 if (ret) { 6575 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6576 return ret; 6577 } 6578 if (eg_pi->pcie_performance_request) 6579 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6580 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6581 ret = si_enable_power_containment(rdev, new_ps, false); 6582 if (ret) { 6583 DRM_ERROR("si_enable_power_containment failed\n"); 6584 return ret; 6585 } 6586 ret = si_enable_smc_cac(rdev, new_ps, false); 6587 if (ret) { 6588 DRM_ERROR("si_enable_smc_cac failed\n"); 6589 return ret; 6590 } 6591 ret = si_halt_smc(rdev); 6592 if (ret) { 6593 DRM_ERROR("si_halt_smc failed\n"); 6594 return ret; 6595 } 6596 ret = si_upload_sw_state(rdev, new_ps); 6597 if (ret) { 6598 DRM_ERROR("si_upload_sw_state failed\n"); 6599 return ret; 6600 } 6601 ret = si_upload_smc_data(rdev); 6602 if (ret) { 6603 DRM_ERROR("si_upload_smc_data failed\n"); 6604 return ret; 6605 } 6606 ret = si_upload_ulv_state(rdev); 6607 if (ret) { 6608 DRM_ERROR("si_upload_ulv_state failed\n"); 6609 return ret; 6610 } 6611 if (eg_pi->dynamic_ac_timing) { 6612 ret = si_upload_mc_reg_table(rdev, new_ps); 6613 if (ret) { 6614 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6615 return ret; 6616 } 6617 } 6618 ret = si_program_memory_timing_parameters(rdev, new_ps); 6619 if (ret) { 6620 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6621 return ret; 6622 } 6623 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6624 6625 ret = si_resume_smc(rdev); 6626 if (ret) { 6627 DRM_ERROR("si_resume_smc failed\n"); 6628 return ret; 6629 } 6630 ret = si_set_sw_state(rdev); 6631 if (ret) { 6632 DRM_ERROR("si_set_sw_state failed\n"); 6633 return ret; 6634 } 6635 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6636 si_set_vce_clock(rdev, new_ps, old_ps); 6637 if (eg_pi->pcie_performance_request) 6638 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6639 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6640 if (ret) { 6641 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6642 return ret; 6643 } 6644 ret = si_enable_smc_cac(rdev, new_ps, true); 6645 if (ret) { 6646 DRM_ERROR("si_enable_smc_cac failed\n"); 6647 return ret; 6648 } 6649 ret = si_enable_power_containment(rdev, new_ps, true); 6650 if (ret) { 6651 DRM_ERROR("si_enable_power_containment failed\n"); 6652 return ret; 6653 } 6654 6655 ret = si_power_control_set_level(rdev); 6656 if (ret) { 6657 DRM_ERROR("si_power_control_set_level failed\n"); 6658 return ret; 6659 } 6660 6661 return 0; 6662 } 6663 6664 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6665 { 6666 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6667 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6668 6669 ni_update_current_ps(rdev, new_ps); 6670 } 6671 6672 #if 0 6673 void si_dpm_reset_asic(struct radeon_device *rdev) 6674 { 6675 si_restrict_performance_levels_before_switch(rdev); 6676 si_disable_ulv(rdev); 6677 si_set_boot_state(rdev); 6678 } 6679 #endif 6680 6681 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6682 { 6683 si_program_display_gap(rdev); 6684 } 6685 6686 union power_info { 6687 struct _ATOM_POWERPLAY_INFO info; 6688 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6689 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6690 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6691 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6692 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6693 }; 6694 6695 union pplib_clock_info { 6696 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6697 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6698 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6699 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6700 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6701 }; 6702 6703 union pplib_power_state { 6704 struct _ATOM_PPLIB_STATE v1; 6705 struct _ATOM_PPLIB_STATE_V2 v2; 6706 }; 6707 6708 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6709 struct radeon_ps *rps, 6710 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6711 u8 table_rev) 6712 { 6713 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6714 rps->class = le16_to_cpu(non_clock_info->usClassification); 6715 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6716 6717 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6718 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6719 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6720 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6721 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6722 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6723 } else { 6724 rps->vclk = 0; 6725 rps->dclk = 0; 6726 } 6727 6728 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6729 rdev->pm.dpm.boot_ps = rps; 6730 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6731 rdev->pm.dpm.uvd_ps = rps; 6732 } 6733 6734 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6735 struct radeon_ps *rps, int index, 6736 union pplib_clock_info *clock_info) 6737 { 6738 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6739 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6740 struct si_power_info *si_pi = si_get_pi(rdev); 6741 struct ni_ps *ps = ni_get_ps(rps); 6742 u16 leakage_voltage; 6743 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6744 int ret; 6745 6746 ps->performance_level_count = index + 1; 6747 6748 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6749 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6750 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6751 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6752 6753 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6754 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6755 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6756 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6757 si_pi->sys_pcie_mask, 6758 si_pi->boot_pcie_gen, 6759 clock_info->si.ucPCIEGen); 6760 6761 /* patch up vddc if necessary */ 6762 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6763 &leakage_voltage); 6764 if (ret == 0) 6765 pl->vddc = leakage_voltage; 6766 6767 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6768 pi->acpi_vddc = pl->vddc; 6769 eg_pi->acpi_vddci = pl->vddci; 6770 si_pi->acpi_pcie_gen = pl->pcie_gen; 6771 } 6772 6773 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6774 index == 0) { 6775 /* XXX disable for A0 tahiti */ 6776 si_pi->ulv.supported = false; 6777 si_pi->ulv.pl = *pl; 6778 si_pi->ulv.one_pcie_lane_in_ulv = false; 6779 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6780 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6781 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6782 } 6783 6784 if (pi->min_vddc_in_table > pl->vddc) 6785 pi->min_vddc_in_table = pl->vddc; 6786 6787 if (pi->max_vddc_in_table < pl->vddc) 6788 pi->max_vddc_in_table = pl->vddc; 6789 6790 /* patch up boot state */ 6791 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6792 u16 vddc, vddci, mvdd; 6793 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6794 pl->mclk = rdev->clock.default_mclk; 6795 pl->sclk = rdev->clock.default_sclk; 6796 pl->vddc = vddc; 6797 pl->vddci = vddci; 6798 si_pi->mvdd_bootup_value = mvdd; 6799 } 6800 6801 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6802 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6803 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6804 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6805 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6806 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6807 } 6808 } 6809 6810 static int si_parse_power_table(struct radeon_device *rdev) 6811 { 6812 struct radeon_mode_info *mode_info = &rdev->mode_info; 6813 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6814 union pplib_power_state *power_state; 6815 int i, j, k, non_clock_array_index, clock_array_index; 6816 union pplib_clock_info *clock_info; 6817 struct _StateArray *state_array; 6818 struct _ClockInfoArray *clock_info_array; 6819 struct _NonClockInfoArray *non_clock_info_array; 6820 union power_info *power_info; 6821 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6822 u16 data_offset; 6823 u8 frev, crev; 6824 u8 *power_state_offset; 6825 struct ni_ps *ps; 6826 6827 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6828 &frev, &crev, &data_offset)) 6829 return -EINVAL; 6830 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6831 6832 state_array = (struct _StateArray *) 6833 (mode_info->atom_context->bios + data_offset + 6834 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6835 clock_info_array = (struct _ClockInfoArray *) 6836 (mode_info->atom_context->bios + data_offset + 6837 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6838 non_clock_info_array = (struct _NonClockInfoArray *) 6839 (mode_info->atom_context->bios + data_offset + 6840 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6841 6842 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6843 state_array->ucNumEntries, GFP_KERNEL); 6844 if (!rdev->pm.dpm.ps) 6845 return -ENOMEM; 6846 power_state_offset = (u8 *)state_array->states; 6847 for (i = 0; i < state_array->ucNumEntries; i++) { 6848 u8 *idx; 6849 power_state = (union pplib_power_state *)power_state_offset; 6850 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6851 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6852 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6853 if (!rdev->pm.power_state[i].clock_info) 6854 return -EINVAL; 6855 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6856 if (ps == NULL) { 6857 kfree(rdev->pm.dpm.ps); 6858 return -ENOMEM; 6859 } 6860 rdev->pm.dpm.ps[i].ps_priv = ps; 6861 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6862 non_clock_info, 6863 non_clock_info_array->ucEntrySize); 6864 k = 0; 6865 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6866 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6867 clock_array_index = idx[j]; 6868 if (clock_array_index >= clock_info_array->ucNumEntries) 6869 continue; 6870 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6871 break; 6872 clock_info = (union pplib_clock_info *) 6873 ((u8 *)&clock_info_array->clockInfo[0] + 6874 (clock_array_index * clock_info_array->ucEntrySize)); 6875 si_parse_pplib_clock_info(rdev, 6876 &rdev->pm.dpm.ps[i], k, 6877 clock_info); 6878 k++; 6879 } 6880 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6881 } 6882 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6883 6884 /* fill in the vce power states */ 6885 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6886 u32 sclk, mclk; 6887 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6888 clock_info = (union pplib_clock_info *) 6889 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6890 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6891 sclk |= clock_info->si.ucEngineClockHigh << 16; 6892 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6893 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6894 rdev->pm.dpm.vce_states[i].sclk = sclk; 6895 rdev->pm.dpm.vce_states[i].mclk = mclk; 6896 } 6897 6898 return 0; 6899 } 6900 6901 int si_dpm_init(struct radeon_device *rdev) 6902 { 6903 struct rv7xx_power_info *pi; 6904 struct evergreen_power_info *eg_pi; 6905 struct ni_power_info *ni_pi; 6906 struct si_power_info *si_pi; 6907 struct atom_clock_dividers dividers; 6908 int ret; 6909 u32 mask; 6910 6911 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6912 if (si_pi == NULL) 6913 return -ENOMEM; 6914 rdev->pm.dpm.priv = si_pi; 6915 ni_pi = &si_pi->ni; 6916 eg_pi = &ni_pi->eg; 6917 pi = &eg_pi->rv7xx; 6918 6919 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6920 if (ret) 6921 si_pi->sys_pcie_mask = 0; 6922 else 6923 si_pi->sys_pcie_mask = mask; 6924 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6925 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6926 6927 si_set_max_cu_value(rdev); 6928 6929 rv770_get_max_vddc(rdev); 6930 si_get_leakage_vddc(rdev); 6931 si_patch_dependency_tables_based_on_leakage(rdev); 6932 6933 pi->acpi_vddc = 0; 6934 eg_pi->acpi_vddci = 0; 6935 pi->min_vddc_in_table = 0; 6936 pi->max_vddc_in_table = 0; 6937 6938 ret = r600_get_platform_caps(rdev); 6939 if (ret) 6940 return ret; 6941 6942 ret = r600_parse_extended_power_table(rdev); 6943 if (ret) 6944 return ret; 6945 6946 ret = si_parse_power_table(rdev); 6947 if (ret) 6948 return ret; 6949 6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6951 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6952 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6953 r600_free_extended_power_table(rdev); 6954 return -ENOMEM; 6955 } 6956 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6957 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6958 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6959 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6960 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6961 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6962 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6963 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6964 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6965 6966 if (rdev->pm.dpm.voltage_response_time == 0) 6967 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6968 if (rdev->pm.dpm.backbias_response_time == 0) 6969 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6970 6971 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6972 0, false, ÷rs); 6973 if (ret) 6974 pi->ref_div = dividers.ref_div + 1; 6975 else 6976 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6977 6978 eg_pi->smu_uvd_hs = false; 6979 6980 pi->mclk_strobe_mode_threshold = 40000; 6981 if (si_is_special_1gb_platform(rdev)) 6982 pi->mclk_stutter_mode_threshold = 0; 6983 else 6984 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6985 pi->mclk_edc_enable_threshold = 40000; 6986 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6987 6988 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6989 6990 pi->voltage_control = 6991 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6992 VOLTAGE_OBJ_GPIO_LUT); 6993 if (!pi->voltage_control) { 6994 si_pi->voltage_control_svi2 = 6995 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6996 VOLTAGE_OBJ_SVID2); 6997 if (si_pi->voltage_control_svi2) 6998 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6999 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7000 } 7001 7002 pi->mvdd_control = 7003 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7004 VOLTAGE_OBJ_GPIO_LUT); 7005 7006 eg_pi->vddci_control = 7007 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7008 VOLTAGE_OBJ_GPIO_LUT); 7009 if (!eg_pi->vddci_control) 7010 si_pi->vddci_control_svi2 = 7011 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7012 VOLTAGE_OBJ_SVID2); 7013 7014 si_pi->vddc_phase_shed_control = 7015 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7016 VOLTAGE_OBJ_PHASE_LUT); 7017 7018 rv770_get_engine_memory_ss(rdev); 7019 7020 pi->asi = RV770_ASI_DFLT; 7021 pi->pasi = CYPRESS_HASI_DFLT; 7022 pi->vrc = SISLANDS_VRC_DFLT; 7023 7024 pi->gfx_clock_gating = true; 7025 7026 eg_pi->sclk_deep_sleep = true; 7027 si_pi->sclk_deep_sleep_above_low = false; 7028 7029 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7030 pi->thermal_protection = true; 7031 else 7032 pi->thermal_protection = false; 7033 7034 eg_pi->dynamic_ac_timing = true; 7035 7036 eg_pi->light_sleep = true; 7037 #if defined(CONFIG_ACPI) 7038 eg_pi->pcie_performance_request = 7039 radeon_acpi_is_pcie_performance_request_supported(rdev); 7040 #else 7041 eg_pi->pcie_performance_request = false; 7042 #endif 7043 7044 si_pi->sram_end = SMC_RAM_END; 7045 7046 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7047 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7048 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7049 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7050 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7051 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7052 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7053 7054 si_initialize_powertune_defaults(rdev); 7055 7056 /* make sure dc limits are valid */ 7057 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7058 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7059 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7060 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7061 7062 si_pi->fan_ctrl_is_in_default_mode = true; 7063 7064 return 0; 7065 } 7066 7067 void si_dpm_fini(struct radeon_device *rdev) 7068 { 7069 int i; 7070 7071 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7072 kfree(rdev->pm.dpm.ps[i].ps_priv); 7073 } 7074 kfree(rdev->pm.dpm.ps); 7075 kfree(rdev->pm.dpm.priv); 7076 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7077 r600_free_extended_power_table(rdev); 7078 } 7079 7080 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7081 struct seq_file *m) 7082 { 7083 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7084 struct radeon_ps *rps = &eg_pi->current_rps; 7085 struct ni_ps *ps = ni_get_ps(rps); 7086 struct rv7xx_pl *pl; 7087 u32 current_index = 7088 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7089 CURRENT_STATE_INDEX_SHIFT; 7090 7091 if (current_index >= ps->performance_level_count) { 7092 seq_printf(m, "invalid dpm profile %d\n", current_index); 7093 } else { 7094 pl = &ps->performance_levels[current_index]; 7095 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7096 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7097 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7098 } 7099 } 7100 7101 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7102 { 7103 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7104 struct radeon_ps *rps = &eg_pi->current_rps; 7105 struct ni_ps *ps = ni_get_ps(rps); 7106 struct rv7xx_pl *pl; 7107 u32 current_index = 7108 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7109 CURRENT_STATE_INDEX_SHIFT; 7110 7111 if (current_index >= ps->performance_level_count) { 7112 return 0; 7113 } else { 7114 pl = &ps->performance_levels[current_index]; 7115 return pl->sclk; 7116 } 7117 } 7118 7119 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7120 { 7121 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7122 struct radeon_ps *rps = &eg_pi->current_rps; 7123 struct ni_ps *ps = ni_get_ps(rps); 7124 struct rv7xx_pl *pl; 7125 u32 current_index = 7126 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7127 CURRENT_STATE_INDEX_SHIFT; 7128 7129 if (current_index >= ps->performance_level_count) { 7130 return 0; 7131 } else { 7132 pl = &ps->performance_levels[current_index]; 7133 return pl->mclk; 7134 } 7135 } 7136